JP4994022B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device including transistors. In addition, the present invention relates to a display device including a semiconductor device and an electronic device including the display device.

  Note that the semiconductor device here refers to all devices that can function by utilizing semiconductor characteristics.

  In recent years, so-called self-luminous display devices in which pixels are formed by light-emitting elements such as light-emitting diodes (LEDs) have attracted attention. As a light-emitting element used in such a self-luminous display device, an organic light-emitting diode (also referred to as an OLED (Organic Light Emitting Diode), an organic EL element, or an electroluminescence (EL) element) attracts attention. It has been used for EL displays and the like. Since light-emitting elements such as OLEDs are self-luminous, there are advantages such as higher pixel visibility than a liquid crystal display, no need for a backlight, and high response speed.

  A self-luminous display device includes a display and a peripheral circuit that inputs a signal to the display. The display arranges light emitting elements for each pixel and controls the light emission of these light emitting elements to display an image.

  A thin film transistor (hereinafter referred to as TFT) is arranged in each pixel of the display. Here, a pixel configuration in which two TFTs are arranged for each pixel and light emission of a light emitting element of each pixel is controlled will be described (for example, see Patent Document 1).

  FIG. 15 shows a pixel configuration of the display. In the pixel portion 2100, data lines (also referred to as source signal lines) S1 to Sx, scanning lines (also referred to as gate signal lines) G1 to Gy, power supply lines (also referred to as power supply lines) V1 to Vx are arranged, and x (x Is a natural number) pixels in columns y (y is a natural number). Each pixel includes a selection transistor (also referred to as a switching TFT, a switch transistor, or a SWTFT) 2101, a driving transistor (also referred to as a driving TFT) 2102, a storage capacitor 2103, and a light emitting element 2104.

  A method for driving the pixel portion 2100 will be briefly described. In the selection period, when a scanning line is selected, the selection transistor 2101 is turned on, and the potential of the data line at that time is written to the gate terminal of the driving transistor 2102 via the selection transistor 2101. From the end of the selection period to the next selection period, the storage capacitor 2103 holds the potential of the gate terminal of the driving transistor 2102.

  Here, in the configuration of FIG. 15, the relationship between the absolute value (| Vgs |) of the voltage between the gate and the source of the driving transistor and the threshold voltage (| Vth |) of the driving transistor 2102 is | Vgs |> | When Vth |, the driving transistor 2102 is turned on. Then, a current flows due to a voltage between the power supply line and the counter electrode connected to the light emitting element 2104, so that the light emitting element 2104 enters a light emitting state. When | Vgs | <| Vth |, the driving transistor 2102 is turned off, and no voltage is applied to both ends of the light-emitting element 2104. Then, the light emitting element 2104 enters a non-light emitting state (light-off state).

  In the pixel having the configuration shown in FIG. 15, there are roughly two methods for expressing gradations: an analog gradation method and a digital gradation method.

  Here, the analog gradation method refers to a method of expressing gradation by changing luminance of a light emitting element with an analog value for a signal input to a pixel. The digital gradation method is a method for expressing gradation by controlling light emission or extinction of a light-emitting element only by turning on or off the switching element by a signal input to a pixel.

  Compared to the analog gray scale method, the digital gray scale method is advantageous in that it is more resistant to variations between TFTs, and that it is easier to make the gradation expression more accurate.

  A time gradation method is known as an example of a digital gradation method gradation expression method. This type of driving method is a method of expressing gradation by controlling a period during which each pixel of a display device emits light. Further, as disclosed in Patent Document 1, high-precision multi-gradation display is achieved by using an erasing transistor (also referred to as erasing TFT) in addition to a driving transistor and a selection transistor for each pixel in a digital time gray scale method. Can be realized. Hereinafter, in the present specification, this driving method is referred to as SES (Simultaneous Erase Scan) driving.

In recent years, in order to reduce power consumption of display devices, display devices having a pixel configuration in which a memory is incorporated in each pixel in a display unit are known (see Patent Document 2 and Patent Document 3).
JP 2001-343933 A Japanese Patent Laid-Open No. 2002-140034 Japanese Patent Laying-Open No. 2005-049402

  For example, as disclosed in Patent Document 1, in the conventional pixel configuration, the power consumption of the data line driving circuit greatly depends on the charge / discharge of the final buffer. When the frequency is F, the capacity is C, and the voltage is V, the power consumption P is generally obtained by the equation (1).

P = FCV ² (F: frequency C: capacity V: voltage) (1)

  Therefore, from the equation (1), it is desirable to set the amplitude of the voltage of the data line as small as possible in the data line driving circuit. For this reason, the amplitude of the voltage of the data line is set to the amplitude of the smallest voltage at which the driving transistor can be turned on or off. In other words, it is desirable to set the absolute value of the voltage (hereinafter referred to as Vgs) applied between the gate and the source of the driving transistor to such an extent that the on / off operation of the driving transistor can be reliably performed.

  The potential of the data line input to the pixel is held by the storage capacitor until the selection period in which the selection transistor is turned on after the selection period in which the selection transistor is turned on ends.

  However, the potential applied to the gate terminal of the drive transistor stored in the storage capacitor fluctuates due to the influence of noise, leakage from the selection transistor, etc., and the drive transistor cannot maintain normal on or off, and may malfunction. There is a problem of having sex.

  In addition, in order to prevent a malfunction due to a change in the gate potential of the driving transistor, there is a problem that increasing the amplitude of the voltage of the data line causes an increase in power consumption. From equation (1), the power consumption of the data line driving circuit increases with the square of the voltage, and therefore the increase in the amplitude of the data line voltage has a large effect.

  More specifically, the problems of the conventional technique will be described in detail with reference to FIG. In the pixel configuration illustrated in FIG. 16A, the pixel 2200 includes a selection transistor 2201, a driving transistor 2202, a storage capacitor 2203, and a light-emitting element 2204. At this time, the light emitting element is digitally driven. Further, it is assumed that the selection transistor is an N-channel type and the driving transistor is a P-channel type.

  A specific potential of each wiring is described with reference to FIG. The potential of the counter electrode 2208 of the light-emitting element 2204 is GND (hereinafter referred to as 0V), the potential of the power supply line 2207 is 7V, and the high potential level of the data line 2206 (hereinafter referred to as High level, High potential, or High) is 7V. A low potential level (hereinafter referred to as low level, low potential, or low) is set to 0V, a high potential of the scanning line 2205 is set to 10V, and a low potential is set to 0V.

  Of course, it is noted that the potential of each wiring, the polarity of each transistor, etc. are examples and not limited thereto.

  FIG. 16B shows a timing chart of potentials of the scanning line, the data line, and the node G in a state where the light-emitting element emits light and is turned off. In the period where the scanning line 2205 is 10 V, the selection transistor 2201 is turned on, and the potential of the data line 2206 is taken into the node G. Then, the potential of the data line 2206 is held in the holding capacitor 2203. When the held potential is a high potential, that is, 7 V or more, the voltage between the gate and the source of the driving transistor 2202 is lower than the absolute value of the threshold voltage of the driving transistor 2202, the driving transistor 2202 is turned off, and the light emitting element 2204 Is turned off. When the held potential is a low potential, that is, 0 V or less, the voltage between the gate and the source of the driving transistor 2202 exceeds the absolute value of the threshold voltage of the driving transistor 2202, the driving transistor 2202 is turned on, and the light emitting element 2204 is turned on. Becomes a light emitting state.

  In the pixel structure described here, the potential of the data line 2206 is written to the node G as it is. Since the on / off state of the driving transistor 2202 is controlled by the potential of the node G, which is the potential of the data line 2206 to be captured, at least the High potential of the data line 2206 is equal to or higher than that of the power supply line 2207 and the Low potential is the driving transistor. A potential at which 2202 is sufficiently turned on is required. In other words, the relationship between the voltage (Vel) applied to the light emitting element 2204 and the voltage (Vds) applied between the source and drain of the driving transistor 2202 is Vel >> Vds, that is, a condition for operating the driving transistor 2202 in the linear region. It is necessary to satisfy.

  However, due to variations in threshold voltage of the driving transistor 2202, fluctuations in the threshold voltage, external noise during the holding period, potential leakage from the selection transistor 2201 as shown in FIG. As the potential of the node G varies, the voltage between the gate and the source of the driving transistor 2202 varies. In that case, the driving transistor 2202 cannot maintain normal on or off, and may malfunction.

  As described above, in the semiconductor device having the conventional pixel configuration, there is a problem in that the potential applied to the gate terminal of the driving transistor varies due to noise or leakage from the selection transistor, causing the driving transistor to malfunction. In addition, supplying a data line signal with a large potential amplitude enough to guarantee a stable operation of the driving transistor causes a problem that the power consumption of the data line driving circuit is greatly affected.

  The present invention has been devised in view of the above problems, and provides a semiconductor device that solves the above problems, a display device including the semiconductor device, and an electronic apparatus including the display device.

  In one embodiment of the present invention, a first transistor in which a gate terminal is connected to a data line, a first terminal is connected to a first power supply line, a gate terminal is connected to a first scanning line, and a first terminal is connected A second transistor connected to the second terminal of the first transistor, a memory circuit, a switching circuit, a third transistor having a gate terminal connected to the switching circuit, and a second terminal connected to the light emitting element; The memory circuit is connected to the second terminal of the second transistor and the second scan line, and the switching circuit is connected to the second terminal of the second transistor, the memory circuit, and the third scan line. The switching circuit switches the connection between the third transistor, the switching circuit, the memory circuit, and the second power supply line, and applies the input potential to the gate terminal of the third transistor. Semiconductor device characterized by A.

  In the present invention, the first transistor and the second transistor may be N-channel transistors, and the third transistor may be a P-channel transistor.

  According to one aspect of the present invention, a first N-channel transistor in which a gate terminal is connected to a data line, a first terminal is connected to a first power supply line, a gate terminal is connected to a first scan line, A second N-channel transistor having one terminal connected to the second terminal of the first N-channel transistor, a memory circuit, a switching circuit, a first terminal connected to the second power supply line, and a second A first P-channel transistor having a terminal connected to the light-emitting element, and the memory circuit includes a first input terminal connected to a second terminal of the second N-channel transistor, and a second input A NOR circuit having a terminal connected to the second scan line; a third N-channel transistor having a gate terminal connected to the output terminal of the NOR circuit; a first terminal connected to the first power supply line; The terminal is connected to the first scanning line, and the first A second P-channel transistor whose child is connected to the second power supply line, a gate terminal is connected to the output terminal of the NOR circuit, and a first terminal is connected to the second terminal of the second P-channel transistor. And a third P-channel transistor having a second terminal connected to the second terminal of the third N-channel transistor, and the switching circuit has a gate terminal connected to the third scanning line, One terminal is connected to the second terminal of the second N-channel transistor, the second terminal of the third N-channel transistor, and the second terminal of the third P-channel transistor, and the second terminal is connected to the first terminal A fourth N-channel transistor connected to the gate terminal of the P-channel transistor, a gate terminal connected to the third scanning line, a first terminal connected to the second power supply line, and a second terminal connected to the second 4 N channels A fourth P-channel transistor connected to the second terminal of the transistor and the gate terminal of the first P-channel transistor, and the memory circuit includes a first P-channel transistor that is turned on. 1 or a second potential that is turned off is input, a third potential at which the third P-channel transistor is turned off is input to the second power supply line, and the switching circuit has the first potential Alternatively, any one of the second potential and the third potential is applied to the gate terminal of the third P-channel transistor.

  In the present invention, the potential of the first power supply line may be lower than the potential of the second power supply line.

  In the present invention, the light emitting element may be an electroluminescent element.

  One embodiment of the present invention is a display device including a display portion having a plurality of pixels and a driver circuit. The pixel has a gate terminal connected to a data line and a first terminal connected to a first power supply line. A first transistor, a second transistor having a gate terminal connected to the first scan line, a first terminal connected to the second terminal of the first transistor, a memory circuit, a switching circuit, a gate And a third transistor having a terminal connected to the switching circuit and a second terminal connected to the light emitting element, and the memory circuit is connected to the second terminal of the second transistor and the second scan line. The switching circuit is connected to the second terminal of the second transistor, the memory circuit, and the third scanning line, and the switching circuit switches the connection between the third transistor, the memory circuit, and the second power supply line. The input potential is A display device having a semiconductor device characterized in that it applied to the gate terminal of the register.

  In the present invention, the first transistor and the second transistor may be N-channel transistors, and the third transistor may be a P-channel transistor.

  One embodiment of the present invention is a display device including a display portion having a plurality of pixels and a driver circuit. The pixel has a gate terminal connected to a data line and a first terminal connected to a first power supply line. A first N-channel transistor having a gate terminal connected to the first scan line and a first terminal connected to a second terminal of the first N-channel transistor; A memory circuit; a switching circuit; and a first P-channel transistor having a first terminal connected to the second power supply line and a second terminal connected to the light-emitting element. A NOR circuit connected to the second terminal of the second N-channel transistor, a second input terminal connected to the second scanning line, and a gate terminal connected to the output terminal of the NOR circuit, The first terminal is connected to the first power line. N-channel transistor, a second P-channel transistor having a gate terminal connected to the first scanning line, a first terminal connected to the second power supply line, and a gate terminal serving as an output terminal of the NOR circuit A third P-channel transistor connected, having a first terminal connected to the second terminal of the second P-channel transistor, and a second terminal connected to the second terminal of the third N-channel transistor; The switching circuit includes a gate terminal connected to the third scan line, a first terminal connected to the second terminal of the second N-channel transistor, a second terminal of the third N-channel transistor, and a second terminal A fourth N-channel transistor connected to the second terminal of the third P-channel transistor, the second terminal connected to the gate terminal of the first P-channel transistor, and a gate terminal connected to the third scanning line. A fourth P connected to the second power supply line, and connected to the second terminal of the fourth N-channel transistor and the gate terminal of the first P-channel transistor. A first potential at which the first P-channel transistor is turned on or a second potential at which the first P-channel transistor is turned off is input to the memory circuit. The third potential at which the three P-channel transistors are turned off is input, and the switching circuit supplies either the first potential, the second potential, or the third potential to the third P-channel transistor. A display device having a semiconductor device, which is applied to a gate terminal of a transistor.

  In the present invention, the potential of the first power supply line may be lower than the potential of the second power supply line.

  In the present invention, the light emitting element may be an electroluminescent element.

  One embodiment of the present invention is an electronic device including a display panel, and the display panel includes a display portion having a plurality of pixels and a driver circuit. The pixels have gate terminals connected to data lines. A first transistor having a first terminal connected to the first power line, a second terminal having a gate terminal connected to the first scan line, and a first terminal connected to the second terminal of the first transistor; A third circuit having a transistor, a memory circuit, a switching circuit, a gate terminal connected to the switching circuit, and a second terminal connected to the light-emitting element; The switching circuit is connected to the second terminal of the second transistor, the memory circuit, and the third scanning line, and the switching circuit is connected to the second transistor and the second scanning line. Switching of connection with memory circuit and second power supply line Performed, the input potential is an electronic device including a display panel having a semiconductor device characterized in that it applied to the gate terminal of the third transistor.

  In the present invention, the first transistor and the second transistor may be N-channel transistors, and the third transistor may be a P-channel transistor.

  One embodiment of the present invention is an electronic device including a display panel, and the display panel includes a display portion having a plurality of pixels and a driver circuit. The pixels have gate terminals connected to data lines. A first N-channel transistor having a first terminal connected to the first power supply line, a gate terminal connected to the first scanning line, and a first terminal connected to the second terminal of the first N-channel transistor. A connected second N-channel transistor, a memory circuit, a switching circuit, and a first P-channel transistor having a first terminal connected to a second power supply line and a second terminal connected to a light emitting element A NOR circuit having a first input terminal connected to the second terminal of the second N-channel transistor and a second input terminal connected to the second scan line; The gate terminal is connected to the output terminal of the NOR circuit, A third N-channel transistor having a terminal connected to the first power supply line, a second P-channel having a gate terminal connected to the first scanning line, and a first terminal connected to the second power supply line Transistor, the gate terminal is connected to the output terminal of the NOR circuit, the first terminal is connected to the second terminal of the second P-channel transistor, and the second terminal is the second terminal of the third N-channel transistor A switching circuit including a gate terminal connected to the third scan line, a first terminal connected to the second terminal of the second N-channel transistor, A fourth N-channel transistor connected to the second terminal of the third N-channel transistor and the second terminal of the third P-channel transistor, the second terminal being connected to the gate terminal of the first P-channel transistor. Type Tran And the gate terminal is connected to the third scanning line, the first terminal is connected to the second power supply line, the second terminal is the second terminal of the fourth N-channel transistor and the first P-channel type. A fourth P-channel transistor connected to a gate terminal of the transistor, and the memory circuit has a first potential at which the first P-channel transistor is turned on or a second potential at which the first P-channel transistor is turned off. The third potential at which the third P-channel transistor is turned off is input to the second power supply line, and the switching circuit has the first potential or the second potential and the third potential. Any one of them is applied to the gate terminal of the third P-channel transistor, which is an electronic device including a display panel having a semiconductor device.

  In the present invention, the potential of the first power supply line may be lower than the potential of the second power supply line.

  In the present invention, the light emitting element may be an electroluminescent element.

  In the present invention, the second scanning line may be the first scanning line in the scanning order before the second scanning line.

  In the present invention, a structure in which one electrode is connected to the gate terminal of the third P-channel transistor and the other electrode is connected to the first power supply line may be used.

  In the present invention, the electronic device includes a television receiver, a camera such as a video camera, a digital camera, a goggle type display, a navigation system, a sound reproduction device, a computer, a game device, a mobile computer, a mobile phone, a portable game machine, An electronic book or an image playback device.

  According to the present invention, in a semiconductor device having a light-emitting element, a constant potential is continuously supplied to the gate terminal of the driving transistor regardless of whether the light-emitting state or the light-off state. Therefore, stable operation can be performed as compared with the conventional pixel configuration in which the potential is held by the holding capacitor.

  Further, in the semiconductor device of the present invention, the potential to be turned on or off applied to the gate terminal of the driving transistor and the potential of the data line can be set separately. Therefore, the amplitude of the potential of the data line can be set to a low amplitude, and a semiconductor device with significantly reduced power consumption can be provided.

  Further, the semiconductor device of the present invention can prevent the signal even if the supply of the signal from the scanning line driving circuit or the data line driving circuit arranged around the pixel portion to the memory circuit arranged in each pixel of the pixel portion is stopped. The data of the signal immediately before the supply is stopped can be held, and the light emitting or light emitting state of the light emitting element can be held.

  Furthermore, the semiconductor device of the present invention can display data of RGB 1-bit (8 colors) still images without supplying data to the pixels again even after erasing.

  Furthermore, the semiconductor device of the present invention can easily determine the brightness by the length of the light emission period in the case of a RGB still image of 1 bit (8 colors).

  In addition, by applying the present invention to a display device, a potential for making a light-emitting state or a potential for making a light-off state continue to be stably supplied to the gate terminal of the driving transistor. Therefore, display can be performed with stable operation as compared with the conventional pixel configuration in which the potential is held by the holding capacitor.

  Furthermore, in the display device of the present invention, the on / off potential applied to the gate terminal of the driving transistor and the potential of the data line can be set separately. Accordingly, the amplitude of the potential of the data line can be set to a low amplitude, and a display device with significantly reduced power consumption can be provided.

  Further, the display device of the present invention can prevent the signal even if the supply of the signal from the scanning line driving circuit or the data line driving circuit arranged around the pixel portion to the memory circuit arranged in each pixel of the pixel portion is stopped. By holding the data of the signal immediately before the supply is stopped, it is possible to provide a display device that can hold the light emitting or emitting state of the light emitting element and display an image.

  Further, in an electronic device using the semiconductor device of the present invention, a constant potential is continuously supplied to the gate terminal of the driving transistor regardless of whether the light emitting state or the light-off state. Therefore, display can be performed with stable operation as compared with the conventional pixel configuration in which the potential is held by the holding capacitor. In addition, a product that performs display with stable operation can be manufactured, and a product with fewer defects can be provided to the customer.

  Further, in the electronic device of the present invention, the potential to be turned on or off applied to the gate terminal of the driving transistor and the potential of the data line can be set separately. Therefore, the amplitude of the potential of the data line can be set to a low amplitude, and an electronic device with greatly reduced power consumption can be provided.

  Further, an electronic device having the display device of the present invention can receive a signal from a scanning line driving circuit or a data line driving circuit arranged around a pixel portion provided in the display portion to a memory circuit arranged in each pixel of the pixel portion. To provide an electronic device capable of displaying an image while maintaining the light emission or extinction state of a light emitting element by retaining the signal data immediately before the signal supply is stopped even if the supply of the signal is stopped it can.

  In the electronic device of the present invention, in the case of an RGB 1-bit (8 colors) still image, each of the pixel units is arranged from a scanning line driving circuit or a data line driving circuit arranged around the pixel unit provided in the display unit. Even if the supply of signals to the memory circuit arranged in the pixel is stopped, it is possible to return from the light-off state to the light-emitting state using the data of the signal immediately before the signal supply is stopped.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in the drawings described below, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

  First, a pixel configuration and an operation principle of the semiconductor device of the present invention will be described.

  FIG. 1 shows a pixel configuration of the present invention. Although only one pixel is shown here, a plurality of pixels are actually arranged in a matrix in the row direction and the column direction in the pixel portion of the semiconductor device.

  The pixel includes a data transistor 101 (also referred to as a first transistor), a switch transistor 102 (also referred to as a second transistor), a memory circuit 103, a driving transistor 105 (also referred to as a third transistor), and a data line 108. The first power line 112, the second power line 113, the first scanning line 109, the second scanning line 110, the third scanning line 111, the light emitting element 106, and the counter electrode 107. And a switching circuit 104.

  The data transistor 101 has a first terminal (source terminal or drain terminal) connected to the first power supply line 112, a gate terminal connected to the data line 108, and a second terminal (source terminal or drain terminal) connected to the switch transistor 102. The first terminal (source terminal or drain terminal) is connected. The gate terminal of the switch transistor 102 is connected to the first scanning line 109, and the second terminal (source terminal or drain terminal) is connected to the input terminal and output terminal of the memory circuit 103 and the first input terminal of the switching circuit 104. ing. The memory circuit 103 is connected to the first input terminal of the switching circuit 104, the second terminal of the switch transistor 102, and the second scanning line 110. The switching circuit 104 has a second input terminal connected to the second power supply line 113, a third input terminal connected to the third scanning line 111, and an output terminal connected to the gate terminal of the driving transistor 105. Has been. The first terminal (source terminal or drain terminal) of the driving transistor 105 is connected to the second power supply line 113, the gate terminal is connected to the input terminal and the output terminal of the memory circuit 103, and the second terminal of the switch transistor 102, The second terminal (source terminal or drain terminal) is connected to one electrode of the light emitting element 106. The other electrode of the light emitting element 106 is connected to the counter electrode 107.

  Note that the potential of the first power supply line 112 is set to a potential Vc lower than the potential of the second power supply line 113. That is, Vc is a potential that satisfies Vc <Vdd with reference to the potential Vdd set in the second power supply line 113 during the light emission period of the pixel. That is, the absolute value (| Vgs |) of the voltage applied between the gate and source of the driving transistor 105 is | Vth | <| Vgs with respect to the absolute value (| Vth |) of the threshold voltage of the driving transistor 105. Is a potential satisfying |. For example, Vc = GND (ground potential) may be used.

  Note that the first terminal of the data transistor 101 may be connected anywhere as long as it is connected to a wiring set with a potential Vc lower than that of the second power supply line 113 in a period in which the data transistor 101 is turned on. For example, in a period in which the data transistor 101 is on, a potential of Vc may be set to the second scanning line 110 provided in the adjacent pixel, and the potential of Vc may be supplied to the pixel from there. .

  Note that a potential Vss lower than that of the second power supply line 113 is set for the counter electrode (cathode) 107 of the light-emitting element 106. That is, Vss is a potential that satisfies Vss <Vdd with reference to the potential Vdd set in the second power supply line 113 during the light emission period of the pixel. For example, Vss = GND (ground potential) may be used. Further, the potential of the first power supply line 112 and the counter electrode 107 may be set to the same GND.

  Note that in this specification, a signal input to the driving transistor to turn on the light-emitting element is a first signal, and a signal input to the driving transistor to turn off the light-emitting element is a second signal. It is called a signal.

  Next, FIG. 2 shows an operation method for the pixel configuration of FIG.

  For the sake of explanation, an N-channel transistor is used as the data transistor 101, an N-channel transistor is used as the switch transistor 102, and a P-channel transistor is used as the driving transistor 105 in FIG. However, the polarity of the transistor is not particularly limited as long as the potential of the wiring connected to the terminal of each transistor is appropriately changed and the same operation as that of each transistor of the present invention is performed. In addition, when changing the direction of the current flowing through the light-emitting element, the potentials of the second power supply line 113 and the counter electrode 107 may be set as appropriate as in the case of changing the polarity of each transistor described above.

  First, FIG. 2 shows a timing chart of potentials of the first scanning line 109, the second scanning line 110, and the third scanning line 111 in the pixel structure of the present invention. In the pixel configuration of the present invention, the light emission state and the light-off state of each pixel are selected by the reset period, the selection period, the sustain period 1, the sustain period 2, and the sustain period 3.

  In the pixel configuration of the present invention, conventionally, a signal for controlling on / off of the driving transistor 105 input from the data line 108 is not input. Therefore, it is necessary to input a reset signal (light-out signal) to the memory circuit 103 in the pixel in advance. This period in which the reset signal is input to the memory circuit 103 in the pixel in advance is referred to as a reset period in this specification.

  Further, FIG. 2 shows a state in which the reset period and the selection period operate continuously, but it is preferable to provide a time margin between the reset period and the selection period. By providing a time margin between the reset period and the selection period, the potential input from the data line can be input to the pixel without malfunction.

  In the reset period, unlit data, that is, a potential at which the driving transistor 105 is turned off is input to the memory circuit 103 regardless of what data is stored before the reset period.

  In the reset period, the switching circuit 104 controlled by the potential of the third scanning line 111 applies a potential at which the driving transistor 105 is turned off to the gate terminal of the driving transistor 105.

  In the selection period, the switch transistor 102 is turned on by the first scanning line 109, and whether or not the data transistor 101 is turned on is determined by the potential of the data line 108 in the data transistor 101. When the data line 108 is at a high potential, the data transistor 101 is turned on, and light emission data, that is, a potential at which the driving transistor 105 is turned on is input to the memory circuit 103. On the other hand, when the data line 108 is at a low potential, the data transistor 101 is turned off, and unlit data, that is, a potential at which the driving transistor 105 is turned off is input to the memory circuit 103.

  In the selection period, the data stored in the memory circuit 103, that is, the potential at which the driving transistor 105 is turned on or off is applied to the gate terminal of the driving transistor 105 by the switching circuit 104 controlled by the potential of the third scanning line 111. Is applied.

  In the sustain period 1 and the sustain period 3, the switching circuit 104 controlled by the potential of the third scanning line 111 does not depend on the data stored in the memory circuit 103, and the driving transistor 105 has a gate terminal connected to the driving transistor 105. A potential at which 105 is turned off is applied, and the light-emitting element 106 is turned off.

  In the sustain period 2, according to the data stored in the memory circuit 103 by the switching circuit 104, a potential at which the driving transistor 105 is turned on or off is applied to the gate terminal of the driving transistor 105, and the light emitting element 106 emits light or turns off. It becomes a state.

  Note that the potential of the gate terminal of the driving transistor 105 in the holding period is held by the memory circuit 103. Therefore, as compared with a pixel configuration using a storage capacitor, the potential applied to the gate terminal of the driving transistor 105 fluctuates due to noise, leakage from the switch transistor 102, and the like, and there is less problem of malfunction.

  Note that with respect to holding the light emitting state and the off state described above, during the holding period, the scanning line driving circuit and the data line driving circuit arranged around the pixel portion are transferred to the memory circuit 103 arranged in each pixel of the pixel portion. Even when the signal supply is stopped, the memory circuit 103 holds the data of the signal immediately before the signal supply is stopped, and the light emitting state of the light emitting element can be held. Therefore, when a still image or the like is displayed using the semiconductor device of the present invention, it is not necessary to operate the scanning line driving circuit or the data line driving circuit, so that a significant reduction in power consumption can be expected.

  Further, since the pixel can be turned off while the data is held in the memory circuit by the switching circuit 104, even if the still image of 1 bit for RGB (8 colors) is turned off, the data line driver circuit can change the pixel portion. The display can be performed again without supplying a signal to the data line, and it is not necessary to operate the data line driver circuit, so that a significant reduction in power consumption can be expected.

  In this embodiment, a specific pixel structure and an operation principle of a semiconductor device of the present invention will be described.

  First, the pixel configuration of the semiconductor device of the present invention will be described in detail with reference to FIG. Although only one pixel is shown here, a plurality of pixels are actually arranged in a matrix in the row direction and the column direction in the pixel portion of the semiconductor device.

  The pixel includes a data transistor 501, a switch transistor 502, a NOR circuit including a transistor 503, a transistor 504, a transistor 505, and a transistor 506, a transistor 507, a transistor 508, a transistor 509, a transistor 510, and a transistor 511. Transistor 512, data line 520, first power line 518, second power line 519, first scan line 515, second scan line 516, third scan line 517, and light emission An element 513 and a counter electrode 514 are provided. In this embodiment, the NOR circuit, the transistor 507, the transistor 508, and the transistor 509 are collectively referred to as a memory circuit 521. The transistor 510 and the transistor 511 are collectively referred to as a switching circuit 522. Note that the data transistor 501 is an N-channel transistor, the switch transistor 502 is an N-channel transistor, the transistors 503 and 504 are P-channel transistors, the transistors 505 and 506 are N-channel transistors, and the transistor 510 is An N-channel transistor, a P-channel transistor as the transistor 511, and a P-channel transistor as the driving transistor 512 are used. However, the polarity of the transistor is not particularly limited as long as the potential of the wiring connected to the terminal of each transistor is appropriately changed and the same operation as that of each transistor of the present invention is performed.

  The data transistor 501 has a first terminal (source terminal or drain terminal) connected to the first power supply line 518, a gate terminal connected to the data line 520, and a second terminal (source terminal or drain terminal) connected to the switch transistor 502. The first terminal (source terminal or drain terminal) is connected. The NOR circuit is composed of a transistor 503, a transistor 504, a transistor 505, and a transistor 506. A gate input terminal of the transistor 504 and the transistor 505 is connected as a first input terminal, and a gate terminal of the transistor 503 and the transistor 506 is connected. The second input terminal is used as a second input terminal, and the second terminal (source terminal or drain terminal) of the transistor 504 and the second terminal (source terminal or drain terminal) of the transistor 505 are connected as output terminals. The gate terminal of the switch transistor 502 is connected to the first scanning line 515, and the second terminal (source terminal or drain terminal) is the first input terminal of the NOR circuit, the transistor 504 and the gate terminal of the transistor 505 and the transistor A second terminal (source terminal or drain terminal) 508, a second terminal (source terminal or drain terminal) of the transistor 509, and a first terminal (source terminal or drain terminal) of the transistor 510 are connected. The first terminal (source terminal or drain terminal) of the transistor 503 is connected to the second power supply line 519. The first terminal (source terminal or drain terminal) of the transistor 505 is connected to the first power supply line 518. A first terminal (source terminal or drain terminal) of the transistor 506 is connected to the first power supply line 518. The other input terminal of the NOR circuit is connected to the second scanning line 516, and the output terminal is connected to the gate terminal of the transistor 508 and the gate terminal of the transistor 509. A first terminal (source terminal or drain terminal) of the transistor 507 is connected to the second power supply line 519, a gate terminal is connected to the first scanning line 515, and a second terminal (source terminal or drain terminal) is the transistor. It is connected to a first terminal (source terminal or drain terminal) 508. The first terminal (source terminal or drain terminal) of the transistor 509 is connected to the first power supply line 518. The gate terminal of the transistor 510 is connected to the third scanning line 517, and the second terminal (source terminal or drain terminal) is connected to the gate terminal of the driving transistor 512 and the second terminal (source terminal or drain terminal) of the transistor 511. It is connected. In addition, a first terminal (a source terminal or a drain terminal) of the transistor 511 is connected to the second power supply line 519, and a gate terminal is connected to the third scanning line 517. The first terminal (source terminal or drain terminal) of the driving transistor 512 is connected to the second power supply line 519, and the second terminal (source terminal or drain terminal) is connected to one electrode of the light-emitting element 513. . The other electrode of the light emitting element 513 is connected to the counter electrode 514.

  Note that the first power supply line 518 is set to a potential Vc lower than that of the second power supply line 519. Note that Vc is a potential that satisfies Vc <Vdd with reference to the potential Vdd set in the second power supply line 519 during the light emission period of the pixel. That is, the absolute value (| Vgs |) of the voltage applied between the gate and the source of the driving transistor 512 is | Vth | <| Vgs with respect to the absolute value (| Vth |) of the threshold voltage of the driving transistor 512. Is a potential satisfying |. For example, Vc = GND (ground potential) may be used.

  Note that a potential Vss lower than that of the second power supply line 519 is set for the counter electrode (cathode) 514 of the light-emitting element 513. Note that Vss is a potential that satisfies Vss <Vdd with reference to the potential Vdd set in the second power supply line 519 during the light emission period of the pixel. For example, Vss = GND (ground potential) may be used. Further, the potential of the first power supply line 518 and the counter electrode may be set to the same GND.

  Note that the timing chart of the potentials of the first scanning line 515, the second scanning line 516, and the third scanning line 517 in the pixel structure of the present invention is the same as that in the above-described first embodiment. Therefore, the description is omitted.

  In the pixel configuration of the present invention, conventionally, a signal for controlling on / off of the driving transistor 512 input from the data line 520 is not input. Therefore, it is necessary to input a reset signal (light-out signal) to the memory circuit 521 in the pixel in advance. This period in which the reset signal is input to the memory circuit 521 in the pixel in advance is referred to as a reset period in this specification.

  Further, FIG. 2 shows a state in which the reset period and the selection period operate continuously, but it is preferable to provide a time margin between the reset period and the selection period. By providing a time margin between the reset period and the selection period, the potential input from the data line can be input to the pixel without malfunction.

  In the reset period, light-off data, that is, a potential at which the driving transistor 512 is turned off is applied to the memory circuit 521 regardless of what data is stored before the reset period.

  In the reset period, the switching circuit 522 controlled by the potential of the second scanning line 516 applies a potential at which the driving transistor 512 is turned off to the gate terminal of the driving transistor 512.

  In the selection period, the switch transistor 502 is turned on by the first scanning line 515. In the data transistor 501, whether or not the data transistor 501 is turned on is determined by the potential of the data line 520 input to the gate terminal. When the data line 520 is at a high potential, the data transistor 501 is turned on, and light emission data, that is, a potential at which the driving transistor 512 is turned off is input to the memory circuit 521. In addition, when the data line 520 is at a low potential, the data transistor 501 is turned off, and unlit data, that is, a potential at which the driving transistor 512 is turned off is input to the memory circuit 521.

  In the selection period, the transistor 511 of the switching circuit 522 controlled by the potential of the third scanning line 517 is turned on, so that a potential at which the driving transistor 512 is turned off is applied to the gate terminal of the driving transistor 512.

  In the sustain period 1 and the sustain period 3, the transistor 511 of the switching circuit 522 controlled by the potential of the third scanning line 517 is turned on, so that the driving transistor 512 does not depend on the data stored in the memory circuit 521. Since a potential at which the driving transistor 512 is turned off is applied to the gate terminal and no current flows through the light-emitting element 513, the light-emitting element 513 is turned off.

  In the sustain period 2, the transistor 510 of the switching circuit 522 controlled by the potential of the third scanning line 517 is turned on, so that the potential at which the driving transistor 512 is turned on or off according to the data stored in the memory circuit 521. Applied to the gate terminal of the driving transistor 512, the light-emitting element 513 is turned on or off.

  Note that the potential of the gate terminal of the driving transistor 512 in the holding period is held by the memory circuit 521. Therefore, as compared with a pixel configuration using a storage capacitor, the potential applied to the gate terminal of the driving transistor 512 is less likely to fluctuate due to noise or leakage from the switch transistor 502 and malfunction.

  Note that with respect to holding the light emitting state and the off state described above, in the holding period, the scanning line driving circuit and the data line driving circuit arranged around the pixel portion are transferred to the memory circuit 521 arranged in each pixel of the pixel portion. Even when the signal supply is stopped, data of the signal immediately before the signal supply is stopped is held in the memory circuit 521 and the light emitting state of the light emitting element 513 can be held. Therefore, when a still image or the like is displayed using the semiconductor device of the present invention, it is not necessary to operate the scanning line driving circuit or the data line driving circuit, so that a significant reduction in power consumption can be expected.

  Further, the pixel can be turned off while the data is held in the memory circuit 521 by the switching circuit 522. Therefore, in the case of a still image of 1 bit for each RGB (8 colors), the pixel from the data line driver circuit can be turned off. Since it is possible to display again without supplying a signal to the unit and it is not necessary to operate the data line driver circuit, a significant reduction in power consumption can be expected.

  This embodiment can be freely combined with the above embodiment modes.

  This embodiment will explain that the semiconductor device of the present invention in Embodiment 1 expresses gradation by a time gradation method.

  The semiconductor device of the present invention operates by SES driving. Conventionally, it has been necessary to use an erasing TFT in order to realize multiple gradations by the time gradation method. In the present invention, since a reset period is provided before each selection period, it is not necessary to newly provide an erasing transistor.

  FIG. 4 shows an example of performing gradation expression by the time gradation method. FIG. 4 is a timing chart for obtaining a 3-bit gradation. Each bit reset period Tr1 to Tr3, selection address (writing) periods Ta1 to Ta3, sustain (light emission) periods Ts1 to Ts3, and an erasing period. Te1.

  The erasing period in this embodiment operates in the reset period in the first embodiment. That is, this is an operation of rewriting a signal for holding the light emission state held in the memory circuit to a signal for holding the light-off state.

Since the reset period and the selection address (writing) period are periods required for the operation of inputting the video signal to the pixels for one screen, they have the same length for each bit. On the other hand, the length of the sustain (light emission) period is, for example, a ratio of 1: 2: 4:... 2 ^(n-1) to a power of 2, and the gradation is expressed by the sum of the light emission periods. To do. In the example of FIG. 4, since it is 3 bits, the length of the sustain (light emission) period is 1: 2: 4.

  Regarding the erasing period, originally, when the sustain (light emission) period is short, the selected address (writing) period in the subframe overlaps with the address period in the next subframe, and different gate signal lines are selected simultaneously. It shall be provided so that it will not occur.

  This embodiment can be freely combined with the above embodiment modes and embodiments.

  A top view and a cross-sectional structure of a light-emitting device of the present invention will be described with reference to the drawings. More specifically, a top view and a cross-sectional structure of a light-emitting device including a data transistor, a drive transistor, and a light-emitting element will be described with reference to FIGS.

  5A is a top view of the semiconductor device of the present invention, and FIG. 5B is a circuit diagram of the top view of FIG. 5A. As shown in FIGS. 5A and 5B, a storage capacitor may be provided at the gate terminal of the driving transistor as necessary. Note that in FIGS. 5A and 5B, numerals 1 to 12 indicate correspondence of the transistors in FIGS. 5A and 5B. In this example, the second scanning line is connected to the first scanning line in the immediately preceding row.

  FIG. 6 is a cross-sectional view of the data transistor from GND in the top view in FIG. 5A, and a cross-sectional view of the light emitting element from the drive transistor. Next, the laminated structure will be described in order.

  In FIG. 6, a glass substrate, a quartz substrate, a stainless steel substrate, or the like can be used as the substrate 1201 having an insulating surface. In addition, a substrate made of a plastic such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN) or a flexible synthetic resin such as acrylic can be used as long as it can withstand the processing temperature in the manufacturing process.

  First, a base film is formed over the substrate 1201. As the base film, an insulating film such as silicon oxide, silicon nitride, or silicon nitride oxide can be used. Next, an amorphous semiconductor film is formed over the base film. The thickness of the amorphous semiconductor film is 25 to 100 nm. For the amorphous semiconductor film, not only silicon but also silicon germanium can be used. Subsequently, the amorphous semiconductor film is crystallized as necessary to form a crystalline semiconductor film 1202. As a method for crystallization, a heating furnace, laser irradiation, irradiation of light emitted from a lamp, or a combination thereof can be used. For example, a crystalline semiconductor film is formed by adding a metal element to an amorphous semiconductor film and performing heat treatment using a heating furnace. Thus, the addition of a metal element is preferable because crystallization can be performed at a low temperature.

  Note that a thin film transistor (TFT) formed using a crystalline semiconductor film has higher field-effect mobility and higher on-current than a TFT formed using an amorphous semiconductor film, and thus is more suitable as a transistor used in a semiconductor device. ing.

  Next, the crystalline semiconductor film 1202 is patterned into a predetermined shape. Next, an insulating film functioning as a gate insulating film is formed. The insulating film is formed with a thickness of 10 to 150 nm so as to cover the semiconductor film. For example, a silicon oxynitride film, a silicon oxide film, or the like can be used, and a single layer structure or a stacked structure may be used.

  Next, a conductive film functioning as a gate electrode is formed over the gate insulating film. Although the gate electrode may be a single layer or a stacked layer, it is formed by stacking conductive films here. The conductive films 1203A and 1203B each include an element selected from tantalum (Ta), aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), and copper (Cu), or any of these elements as a main component. It is made of alloy material or compound material. In this embodiment, a tantalum nitride film with a thickness of 10 to 50 nm is formed as the conductive film 1203A, and a tungsten film with a thickness of 200 to 400 nm is formed as the conductive film 1203B.

  Next, an impurity element is added using the gate electrode as a mask to form an impurity region. At this time, a low concentration impurity region may be formed in addition to the high concentration impurity region. The low concentration impurity region is called an LDD (Lightly Doped Drain) region.

  Next, insulating films 1204 and 1205 functioning as the interlayer insulating film 1206 are formed. The insulating film 1204 is preferably an insulating film containing nitrogen. Here, the insulating film 1204 is formed using a 100 nm silicon nitride film by a plasma CVD method. The insulating film 1205 is preferably formed using an organic material or an inorganic material. As the organic material, polyimide, acrylic, polyamide, polyimide amide, benzocyclobutene, or siloxane can be used. Siloxane has a skeletal structure with a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Examples of the inorganic material include oxygen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y) (x and y are natural numbers), and the like. Alternatively, an insulating film containing nitrogen can be used. Note that a film formed using an organic material has good flatness, but moisture and oxygen are absorbed by the organic material. In order to prevent this, an insulating film containing an inorganic material is preferably formed over the insulating film formed using an organic material.

  Next, after a contact hole is formed in the interlayer insulating film 1206, a conductive film 1207 functioning as a source wiring and a drain wiring of the transistor is formed. As the conductive film 1207, a film formed of an element of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), or silicon (Si) or an alloy film using these elements can be used. In this embodiment, a titanium film, a titanium nitride film, an alloy film of titanium and aluminum, and a stacked film of a titanium film are formed.

  Next, an insulating film 1208 is formed so as to cover the conductive film 1207. The material shown for the interlayer insulating film 1206 can be used for the insulating film 1208. Next, a pixel electrode (also referred to as a first electrode) 1209 is formed in the opening provided in the insulating film 1208. In order to improve the step coverage of the pixel electrode 1209 in the opening, the end surface of the opening may be rounded so as to have a plurality of radii of curvature.

  As a material of the pixel electrode 1209, it is preferable to use a conductive material such as a metal, an alloy, an electrically conductive compound, or a mixture thereof having a high work function (work function of 4.0 eV or more). Specific examples of the conductive material include indium oxide containing tungsten oxide (IWO), indium zinc oxide containing tungsten oxide (IWZO), indium oxide containing titanium oxide (ITO), and indium tin oxide containing titanium oxide. A thing (ITTiO) etc. can be used. Needless to say, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide added with silicon oxide (ITSO), or the like can also be used.

  The composition proportion of the conductive material is as follows. The composition ratio of indium oxide containing tungsten oxide may be 1 wt% tungsten oxide and 99 wt% indium oxide. The composition ratio of indium zinc oxide containing tungsten oxide may be 1 wt% tungsten oxide, 0.5 wt% zinc oxide, and 98.5 wt% indium oxide. The indium oxide containing titanium oxide may be titanium oxide 1 wt% to 5 wt% and indium oxide 99 wt% to 95 wt%. The composition ratio of indium tin oxide (ITO) may be 10 wt% tin oxide and 90 wt% indium oxide. The composition ratio of indium zinc oxide (IZO) may be 10 wt% zinc oxide and 89 wt% indium oxide. The composition ratio of indium tin oxide containing titanium oxide may be 5 wt% titanium oxide, 10 wt% tin oxide, and 85 wt% indium oxide. The above composition ratio is an example, and the ratio of the composition ratio may be set as appropriate.

  Next, an electroluminescent layer 1210 is formed by an evaporation method or an inkjet method. The electroluminescent layer 1210 includes an organic material or an inorganic material, and includes an electron injection layer (EIL), an electron transport layer (ETL), a light emitting layer (EML), a hole transport layer (HTL), and a hole injection layer (HIL). ) And the like. Note that the boundaries between the layers are not necessarily clear, and there are cases where the materials constituting the layers are partially mixed and the interface is unclear.

  Note that the electroluminescent layer is preferably formed using a plurality of layers having different functions such as a hole injecting and transporting layer, a light emitting layer, and an electron injecting and transporting layer.

  Note that the hole injecting and transporting layer is preferably formed using a composite material including a hole transporting organic compound material and an inorganic compound material that exhibits an electron accepting property with respect to the organic compound material. By adopting such a configuration, many hole carriers are generated in an organic compound that has essentially no intrinsic carrier, and extremely excellent hole injection and transport properties can be obtained. Due to this effect, the drive voltage can be made lower than in the prior art. In addition, since the hole injecting and transporting layer can be thickened without causing an increase in driving voltage, a short circuit of the light emitting element due to dust or the like can be suppressed.

  Examples of hole transporting organic compound materials include copper phthalocyanine (abbreviation: CuPc), vanadyl phthalocyanine (abbreviation: VOPc), 4,4 ′, 4 ″ -tris (N, N-diphenylamino) triphenyl. Amine (abbreviation: TDATA), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenylamino] triphenylamine (abbreviation: MTDATA), 1,3,5-tris [N , N-di (m-tolyl) amino] benzene (abbreviation: m-MTDAB), N, N′-diphenyl-N, N′-bis (3-methylphenyl) -1,1′-biphenyl-4,4 '-Diamine (abbreviation: TPD), 4,4'-bis [N- (1-naphthyl) -N-phenylamino] biphenyl (abbreviation: NPB), 4,4'-bis {N- [4-di ( m-tri ) Amino] phenyl-N-phenylamino} biphenyl (abbreviation: DNTPD), 4,4 ′, 4 ″ -tris (N-carbazolyl) triphenylamine (abbreviation: TCTA), and the like. Never happen.

  Note that examples of the inorganic compound material exhibiting electron acceptability include titanium oxide, zirconium oxide, vanadium oxide, molybdenum oxide, tungsten oxide, rhenium oxide, ruthenium oxide, and zinc oxide. Vanadium oxide, molybdenum oxide, tungsten oxide, and rhenium oxide are particularly preferable because they can be vacuum-deposited and are easy to handle.

Note that the electron injecting and transporting layer is formed using an electron transporting organic compound material. Specifically, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), bis (10-hydroxybenzo [h] -quinolinato) beryllium (Abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) (4-phenylphenolato) aluminum (abbreviation: BAlq), bis [2- (2′-hydroxyphenyl) benzoxazolate] zinc (abbreviation) : Zn (BOX) ₂ ), bis [2- (2′-hydroxyphenyl) benzothiazolate] zinc (abbreviation: Zn (BTZ) ₂ ), bathophenanthroline (abbreviation: BPhen), bathocuproine (abbreviation: BCP), 2- ( 4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole Abbreviation: PBD), 1,3-bis [5- (4-tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 2,2 ′, 2 ″-(1,3,5-benzenetriyl) -tris (1-phenyl-1H-benzimidazole) (abbreviation: TPBI), 3- (4-biphenylyl) -4-phenyl-5- (4- tert-butylphenyl) -1,2,4-triazole (abbreviation: TAZ), 3- (4-biphenylyl) -4- (4-ethylphenyl) -5- (4-tert-butylphenyl) -1,2 , 4-triazole (abbreviation: p-EtTAZ) and the like, but is not limited thereto.

Note that the light-emitting layer includes 9,10-di (2-naphthyl) anthracene (abbreviation: DNA), 9,10-di (2-naphthyl) -2-tert-butylanthracene (abbreviation: t-BuDNA), 4 , 4′-bis (2,2-diphenylvinyl) biphenyl (abbreviation: DPVBi), coumarin 30, coumarin 6, coumarin 545, coumarin 545T, perylene, rubrene, periflanthene, 2,5,8,11-tetra (tert-) (Butyl) perylene (abbreviation: TBP), 9,10-diphenylanthracene (abbreviation: DPA), 5,12-diphenyltetracene (abbreviation: DPT), 4- (dicyanomethylene) -2-methyl-6- [p- ( Dimethylamino) styryl] -4H-pyran (abbreviation: DCM1), 4- (dicyanomethylene) -2-methyl-6- [2- (juro Lysine-9-yl) ethenyl] -4H-pyran (abbreviation: DCM2), 4- (dicyanomethylene) -2,6-bis [p- (dimethylamino) styryl] -4H-pyran (abbreviation: BisDCM) and the like. Can be mentioned. In addition, bis [2- (4 ′, 6′-difluorophenyl) pyridinato-N, C ^{2 ′} ] iridium (picolinato) (abbreviation: FIr (pic)), bis {2- [3 ′, 5′-bis ( Trifluoromethyl) phenyl] pyridinato-N, C ^{2 ′} } iridium (picolinate) (abbreviation: Ir (CF ₃ ppy) ₂ (pic)), tris (2-phenylpyridinato-N, C ^{2 ′} ) iridium ( Abbreviations: Ir (ppy) ₃ ), bis (2-phenylpyridinato-N, C ^{2 ′} ) iridium (acetylacetonate) (abbreviation: Ir (ppy) ₂ (acac)), bis [2- (2 ′ - thienyl) pyridinato -N, C ^{3 ']} iridium (acetylacetonate) _{(abbreviation: Ir (thp) 2 (acac} )), bis (2-phenylquinolinato--N, C ^2') iridium (acetyl Acetonate) _{(abbreviation: Ir (pq) 2 (acac} )), bis [2- (2'-benzothienyl) pyridinato -N, C ^{3 ']} iridium (acetylacetonato) (abbreviation: Ir _(btp) 2 (acac A compound capable of emitting phosphorescence such as)) can also be used.

  In addition to the singlet excited light emitting material, a triplet excited material containing a metal complex or the like may be used for the light emitting layer. For example, among red light emitting pixels, green light emitting pixels, and blue light emitting pixels, a red light emitting pixel having a relatively short luminance half time is formed of a triplet excitation light emitting material, and the other A singlet excited luminescent material is used. The triplet excited luminescent material has a feature that the light emission efficiency is good, so that less power is required to obtain the same luminance. That is, when applied to a red pixel, the amount of current flowing through the light emitting element can be reduced, so that reliability can be improved. As a reduction in power consumption, a red light-emitting pixel and a green light-emitting pixel may be formed using a triplet excitation light-emitting material, and a blue light-emitting pixel may be formed using a singlet excitation light-emitting material. By forming a green light-emitting element having high human visibility with a triplet excited light-emitting material, power consumption can be further reduced.

  The light emitting layer may be configured to perform color display by forming light emitting layers having different emission wavelength bands for each pixel. Typically, a light emitting layer corresponding to each color of R (red), G (green), and B (blue) is formed. In this case as well, it is possible to improve color purity and prevent mirror reflection (reflection) of the pixel portion by providing a filter that transmits light in the emission wavelength band on the light emission side of the pixel. Can do. By providing the filter, it is possible to omit a circularly polarizing plate that has been conventionally required, and it is possible to eliminate the loss of light emitted from the light emitting layer. Furthermore, a change in color tone that occurs when the pixel portion (display screen) is viewed obliquely can be reduced.

  In addition, examples of the polymer electroluminescent material that can be used for forming the light emitting layer include polyparaphenylene vinylene, polyparaphenylene, polythiophene, and polyfluorene.

In addition, an inorganic material may be used for the light emitting layer. As the inorganic material, a compound semiconductor such as zinc sulfide (ZnS) added with manganese (Mn) or rare earth (Eu, Ce, etc.) as impurities can be applied. These impurities are called luminescent center ions, and light emission is obtained by electronic transition in the ions. In addition, a compound semiconductor such as zinc sulfide (ZnS) is added with Cu, Ag, Au, or the like as an acceptor element and F, Cl, Br, or the like as a donor element, and emits light by transition between the acceptor and the donor. Can be applied. Further, GaAs may be added in order to further improve the light emission efficiency. The light emitting layer may be provided with a thickness of 100 to 1000 nm (preferably 300 to 600 nm). A dielectric layer is provided between such a light emitting layer and the electrodes (anode and cathode) in order to increase the light emission efficiency. As the dielectric layer, barium titanate (BaTiO ₃ ) or the like can be used. The dielectric layer is provided with a thickness of 50 to 500 nm (preferably 100 to 200 nm).

  In any case, the layer structure of the electroluminescent layer can be changed, and instead of having a specific hole or electron injecting and transporting layer or a light emitting layer, an electrode layer for this purpose can be provided, or a light emitting property can be obtained. Such a modification that the material is dispersed is acceptable as long as the object as the light emitting element can be achieved.

  Further, a color filter (colored layer) may be formed on the sealing substrate. The color filter (colored layer) can be formed by an evaporation method or a droplet discharge method. When the color filter (colored layer) is used, high-definition display can be performed. This is because the color filter (colored layer) can correct a broad peak to be sharp in the emission spectrum of each RGB.

  Further, full color display can be performed by forming a material exhibiting monochromatic light emission and combining a color filter and a color conversion layer. The color filter (colored layer) and the color conversion layer may be formed, for example, on the second substrate (sealing substrate) and attached to the substrate.

  Then, a counter electrode (also referred to as a second electrode) 1211 is formed by a sputtering method or an evaporation method. One of the pixel electrode 1209 and the counter electrode 1211 serves as an anode and the other serves as a cathode.

As the cathode material, it is preferable to use a metal, an alloy, an electrically conductive compound, a mixture thereof, or the like having a low work function (work function of 3.8 eV or less). Specific examples of the cathode material include elements belonging to Group 1 or Group 2 of the periodic table of elements, that is, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr, and alloys containing these (Mg : Ag, Al: Li) and compounds (LiF, CsF, CaF ₂ ), as well as transition metals including rare earth metals. However, since the cathode needs to have translucency, these metals or an alloy containing these metals are formed very thinly, and are formed by lamination with a metal (including an alloy) such as ITO.

After that, a protective film made of a silicon nitride film or a DLC (Diamond Like Carbon) film may be provided so as to cover the counter electrode 1211. The light emitting device of the present invention is completed through the above steps.

  This embodiment can be freely combined with the above embodiment modes and embodiments.

  In this embodiment, the structure of the display device will be described with reference to FIG.

  In FIG. 7A, a pixel portion 1302 in which a plurality of pixels 1301 are arranged in a matrix is provided over a substrate 1307. A signal line driver circuit 1303 and a first scan line driver are provided around the pixel portion 1302. A circuit 1304 and a second scan line driver circuit 1305 are included. These drive circuits are supplied with signals from the outside via the FPC 1306.

  FIG. 7B illustrates a structure of the first scan line driver circuit 1304 and the second scan line driver circuit 1305. The first scan line driver circuit 1304 and the second scan line driver circuit 1305 each include a shift register 1314 and a buffer 1315. FIG. 7C illustrates a structure of the signal line driver circuit 1303. The signal line driver circuit 1303 includes a shift register 1311, a first latch circuit 1312, a second latch circuit 1313, and a buffer 1317.

  Note that the structures of the scan line driver circuit and the signal line driver circuit are not limited to the above description, and may include a sampling circuit, a level shifter, or the like, for example. In addition to the driving circuit, a circuit such as a CPU or a controller may be integrally formed on the substrate 1307. Then, the number of external circuits (IC) to be connected is reduced, and the weight and thickness can be further increased.

  Note that in this specification, a panel in which the display device illustrated in FIG. 7A is attached to the FPC as illustrated in FIG. 7A and an EL element is used as a light-emitting element is referred to as an EL element in this specification. This is called a module.

  This embodiment can be freely combined with the above embodiment modes and embodiments.

  In this embodiment, correction of the potential of the second power supply line and suppression of the influence due to the change in the current value of the light emitting element due to the change in the environmental temperature and the change over time will be described.

  The light-emitting element has a property that its resistance value (internal resistance value) changes depending on the ambient temperature. Specifically, when the room temperature is a normal temperature, the resistance value decreases when the temperature is higher than normal, and the resistance value increases when the temperature is lower than normal. Therefore, when the temperature increases, the current value increases and becomes higher than the desired luminance. When the same voltage is applied when the temperature decreases, the current value decreases and the luminance becomes lower than the desired luminance. Further, the light emitting element has a property that its current value decreases with time due to deterioration. Specifically, when the light emission time and the light extinction time are accumulated, the resistance value increases with the deterioration of the light emitting element. Therefore, when the light emission time and the light extinction time are accumulated, when the same voltage as that of the first light emission period or the light extinction period is applied, the current value is reduced to a luminance lower than a desired luminance.

  Due to the properties of the above-described light emitting element, when the environmental temperature changes or changes with time, the luminance varies. In this embodiment, correction by using the potential of the second power supply line of the present invention can suppress the influence due to the change in the current value of the light emitting element due to the change in environmental temperature and the change with time.

  FIG. 8 shows a circuit configuration. The same pixel shown in FIG. 3 is arranged in the pixel, and the description similar to that in FIG. 3 is omitted. In FIG. 8, a driving transistor 1403 and a light emitting element 1404 are connected between the second power supply line 1401 and the counter electrode 1402 shown in FIG. Then, a current flows from the second power supply line 1401 to the counter electrode 1402. The light emitting element 1404 emits light according to the magnitude of current flowing therethrough.

  In the case of such a pixel structure, if the potentials of the second power supply line 1401 and the counter electrode 1402 are fixed, the characteristics deteriorate if current continues to flow through the light emitting element 1404. The characteristics of the light emitting element 1404 vary depending on the temperature.

  Specifically, when a current continues to flow through the light emitting element 1404, the voltage-current characteristic shifts. That is, the resistance value of the light emitting element 1404 increases, and the flowing current value decreases even when the same voltage is applied. Moreover, even if the same magnitude | size electric current flows, luminous efficiency will fall and a brightness | luminance will fall. As the temperature characteristics, when the temperature decreases, the voltage-current characteristics of the light-emitting element 1404 shift, and the resistance value of the light-emitting element 1404 increases.

  Therefore, the influence of deterioration and fluctuation as described above is corrected using a monitoring circuit. In this embodiment, by adjusting the potential of the second power supply line 1401, deterioration of the light-emitting element 1404 and fluctuation due to temperature are corrected.

  Therefore, the configuration of the monitor circuit will be described. A monitor current source 1408 and a monitor light emitting element 1409 are connected between the first monitor power line 1406 and the second monitor power line 1407. An input terminal of a sampling circuit 1410 for outputting the voltage of the monitor light emitting element is connected between the monitor current source 1408 and the monitor light emitting element 1409. A power supply circuit 1411 is connected to the output terminal of the sampling circuit 1410, and a second power supply line 1401 is connected to the power supply circuit 1411. Therefore, the potential of the second power supply line 1401 is controlled by the output of the sampling circuit 1410.

  Next, the operation of the monitor circuit will be described. First, when the light emitting element 1404 emits light with the brightest number of gradations, the monitoring current source 1408 passes a current having a magnitude desired to flow through the light emitting element 1404. The current value at this time is Imax.

  Then, a voltage having a magnitude necessary for flowing a current having a magnitude Imax is added to the voltage across the monitor light emitting element 1409. Even if the voltage-current characteristic of the monitor light emitting element 1409 changes due to deterioration, temperature, or the like, the voltage across the monitor light emitting element 1409 also changes accordingly and becomes an optimum magnitude. Therefore, the influence of fluctuations (deterioration, temperature change, etc.) of the monitor light emitting element 1409 can be corrected.

  The voltage applied to the monitor light emitting element 1409 is input to the input terminal of the sampling circuit 1410. The output potential of the sampling circuit 1410 is input to the power supply circuit 1411 connected to the power supply circuit power supply line 1412.

  The power supply circuit 1411 supplies a potential corresponding to the potential from the output terminal of the sampling circuit 1410 to the second power supply line 1401. That is, the potential of the second power supply line 1401 is corrected by the monitoring circuit, and the light-emitting element 1404 is corrected for deterioration and fluctuation due to temperature.

  Note that the sampling circuit 1410 may be any circuit as long as it samples and holds a voltage corresponding to the current input to the monitor light emitting element. For example, a switching element such as a MOS transistor and a capacitor element may be used to sample the input voltage.

  The power supply circuit 1411 may be a circuit that outputs an input voltage. For example, a circuit may be configured by combining any one or more of an operational amplifier, a bipolar transistor, and a MOS transistor.

  Note that the monitor light emitting element 1409 is preferably formed on the same substrate by the same manufacturing method as the pixel light emitting element 1404. This is because the correction is shifted if the characteristics are different between the monitor and the pixel.

  Note that the light-emitting element 1404 arranged in the pixel has a period in which current is not frequently supplied. Therefore, if the monitor light-emitting element 1409 is continuously supplied with current, the monitor light-emitting element 1409 has more time. Deterioration greatly progresses. Therefore, the potential output from the sampling circuit 1410 is a potential as if the correction has been strengthened. Therefore, the light emitting element deterioration degree in an actual pixel may be matched. For example, on average, if the lighting rate of the entire screen is 30%, a current may be supplied to the monitor light emitting element 1409 only during a period corresponding to a luminance of 30%. At that time, a period in which no current flows in the monitor light emitting element 1409 occurs. However, it is necessary to keep the voltage supplied from the output terminal of the sampling circuit 1410 unchanged. In order to realize this, a capacitor element is provided at the input terminal of the sampling circuit 1410, and the potential when a current is supplied to the monitor light emitting element 1409 may be held there.

  Note that when the monitor circuit is operated in accordance with the brightest number of gradations, a strongly corrected potential is output, which causes burn-in in pixels (due to variations in the degree of deterioration for each pixel). Since the luminance unevenness becomes inconspicuous, it is desirable to operate the monitor circuit in accordance with the brightest number of gradations.

  In this embodiment, it is more preferable that the driving transistor 1403 is operated in a linear region. By operating in the linear region, the driving transistor 1403 operates as a switch. Therefore, it is possible to make it difficult for the drive transistor 1403 to be affected by the characteristic variation due to deterioration or temperature. When operating only in the linear region, it is often digitally controlled whether or not current flows through the light emitting element 1404. In that case, in order to increase the number of gradations, it is preferable to combine a time gradation method, an area gradation method, or the like.

  This embodiment can be freely combined with the above embodiment modes and embodiments.

  Electronic devices including the semiconductor device of the present invention include television receivers, video cameras, digital cameras and other cameras, goggle-type displays, navigation systems, sound playback devices (car audio components, etc.), computers, game devices, and portable information terminals. (Mobile computer, mobile phone, portable game machine, electronic book, or the like), an image playback apparatus (specifically, a digital versatile disc (DVD)) provided with a recording medium, and can display the image And a device equipped with a display). Specific examples of these electronic devices are shown in FIGS. 9, 10, 11 (A) to 11 (B), 12 (A) to 12 (B), 13, 14 (A) to 14 ( E).

  FIG. 9 shows an EL module in which a display panel 5001 and a circuit board 5011 are combined. A circuit board 5011 is provided with a control circuit 5012, a signal dividing circuit 5013, and the like, and is electrically connected to the display panel 5001 through a connection wiring 5014.

  The display panel 5001 includes a pixel portion 5002 provided with a plurality of pixels, a scanning line driver circuit 5003, and a signal line driver circuit 5004 for supplying a video signal to the selected pixel. Note that in the case of manufacturing an EL module, a semiconductor device which forms a pixel in the pixel portion 5002 may be manufactured using the above embodiment. In addition, a control driver circuit portion such as the scan line driver circuit 5003 or the signal line driver circuit 5004 can be manufactured using the TFT formed in the above embodiment. As described above, the EL module television shown in FIG. 9 can be completed.

  FIG. 10 is a block diagram illustrating a main configuration of the EL television receiver. A tuner 5101 receives a video signal and an audio signal. The video signal includes a video signal amplifying circuit 5102, a video signal processing circuit 5103 that converts a signal output from the video signal into a color signal corresponding to each color of red, green, and blue, and the video signal as input specifications of the driver IC. Processing is performed by a control circuit 5012 for conversion. The control circuit 5012 outputs a signal to each of the scanning line side and the signal line side. In the case of digital driving, a signal dividing circuit 5013 may be provided on the signal line side so that an input digital signal is divided into m pieces and supplied.

  Of the signals received by the tuner 5101, the audio signal is sent to the audio signal amplifier circuit 5105, and the output is supplied to the speaker 5107 through the audio signal processing circuit 5106. The control circuit 5108 receives control information on the receiving station (reception frequency) and volume from the input unit 5109 and sends a signal to the tuner 5101 and the audio signal processing circuit 5106.

  As shown in FIG. 11A, a television receiver can be completed by incorporating an EL module into a housing 5201. A display screen 5202 is formed by the EL module. In addition, a speaker 5203, an operation switch 5204, and the like are provided as appropriate.

  FIG. 11B illustrates a television receiver that can carry only a display wirelessly. A housing and a signal receiver are incorporated in the housing 5212, and the display portion 5213 and the speaker portion 5217 are driven by the battery. The battery can be repeatedly charged by a charger 5210. The charger 5210 can transmit and receive a video signal, and can transmit the video signal to a signal receiver of the display. The housing 5212 is controlled by operation keys 5216. The device illustrated in FIG. 11B can also be referred to as a video / audio two-way communication device because a signal can be sent from the housing 5212 to the charger 5210 by operating the operation key 5216. In addition, by operating the operation key 5216, a signal is transmitted from the housing 5212 to the charger 5210, and further, a signal that can be transmitted by the charger 5210 is received by another electronic device, thereby controlling communication of the other electronic device. It can be said to be a general-purpose remote control device. The present invention can be applied to the display portion 5213.

  The semiconductor device of the present invention is driven by using the television receiver shown in FIGS. 9, 10, 11 A to 11 B, regardless of whether the light emitting element in the display portion is in a light emitting state or in an off state. A constant potential is continuously supplied to the gate terminal of the transistor. Therefore, compared to the conventional pixel configuration in which the potential is held by the holding capacitor, a product that displays with stable operation can be manufactured, and a product with fewer defects can be provided to the customer.

  Further, the semiconductor device of the present invention is applied to the gate terminal of the driving transistor in the pixel of the display portion by using it in the television receiver shown in FIGS. 9, 10, and 11A to 11B. The potential for turning on or off and the potential of the data line can be set separately. Therefore, it is possible to set the amplitude of the potential of the data line to a low amplitude, and it is possible to provide a semiconductor device with significantly reduced power consumption, and to provide customers with products with greatly reduced power consumption. Can do.

  Of course, the present invention is not limited to a television receiver, and is applied to various uses as a display medium of a particularly large area such as a monitor of a personal computer, an information display board in a railway station or airport, an advertisement display board in a street, etc. can do.

  FIG. 12A shows a module in which a display panel 5301 and a printed wiring board 5302 are combined. The display panel 5301 includes a pixel portion 5303 provided with a plurality of pixels, a first scan line driver circuit 5304, a second scan line driver circuit 5305, and a signal line driver circuit that supplies a video signal to the selected pixel. 5306 is provided.

  The printed wiring board 5302 is provided with a controller 5307, a central processing unit (CPU) 5308, a memory 5309, a power supply circuit 5310, an audio processing circuit 5311, a transmission / reception circuit 5312, and the like. The printed wiring board 5302 and the display panel 5301 are connected by a flexible printed wiring board (FPC) 5313. The FPC 5313 may be provided with a capacitor, a buffer circuit, or the like so that noise is added to the power supply voltage or the signal or the rise of the signal is not slowed. The controller 5307, the audio processing circuit 5311, the memory 5309, the CPU 5308, the power supply circuit 5310, and the like can be mounted on the display panel 5301 using a COG (Chip On Glass) method. The scale of the printed wiring board 5302 can be reduced by the COG method.

  Various control signals are input and output through an interface unit 5314 provided in the printed wiring board 5302. An antenna port 5315 for transmitting and receiving signals to and from the antenna is provided on the printed wiring board 5302.

  FIG. 12B shows a block diagram of the module shown in FIG. This module includes a VRAM 5316, a DRAM 5317, a flash memory 5318, and the like as the memory 5309. The VRAM 5316 stores image data to be displayed on the panel, the DRAM 5317 stores image data or audio data, and the flash memory 5318 stores various programs.

  The power supply circuit 5310 supplies power for operating the display panel 5301, the controller 5307, the CPU 5308, the sound processing circuit 5311, the memory 5309, and the transmission / reception circuit 5312. Depending on the specifications of the panel, the power supply circuit 5310 may be provided with a current source.

  The CPU 5308 includes a control signal generation circuit 5320, a decoder 5321, a register 5322, an arithmetic circuit 5323, a RAM 5324, an I / F 5319 for the CPU 5308, and the like. Various signals input to the CPU 5308 via the I / F 5319 are temporarily held in the register 5322 and then input to the arithmetic circuit 5323, the decoder 5321, and the like. The arithmetic circuit 5323 performs an operation based on the input signal and designates a place to send various commands. On the other hand, the signal input to the decoder 5321 is decoded and input to the control signal generation circuit 5320. The control signal generation circuit 5320 generates a signal including various instructions based on the input signal, and a location designated by the arithmetic circuit 5323, specifically, a memory 5309, a transmission / reception circuit 5312, an audio processing circuit 5311, a controller 5307, and the like. Send to.

  The memory 5309, the transmission / reception circuit 5312, the sound processing circuit 5311, and the controller 5307 operate according to the received commands. The operation will be briefly described below.

  A signal input from the input unit 5325 is sent to the CPU 5308 mounted on the printed wiring board 5302 via the interface unit 5314. The control signal generation circuit 5320 converts the image data stored in the VRAM 5316 into a predetermined format according to a signal sent from the input unit 5325 such as a pointing device or a keyboard, and sends the image data to the controller 5307.

  The controller 5307 performs data processing on a signal including image data sent from the CPU 5308 in accordance with the specifications of the panel, and supplies the processed signal to the display panel 5301. Further, the controller 5307 generates an Hsync signal, a Vsync signal, a clock signal CLK, an AC voltage (AC Cont), and a switching signal L / R based on the power supply voltage input from the power supply circuit 5310 and various signals input from the CPU 5308. Generated and supplied to the display panel 5301.

  In the transmission / reception circuit 5312, signals transmitted / received as radio waves in the antenna 5328 are processed. Specifically, high-frequency signals such as an isolator, a band-pass filter, a VCO (Voltage Controlled Oscillator), an LPF (Low Pass Filter), a coupler, and a balun. Includes circuitry. A signal including audio information among signals transmitted and received in the transmission / reception circuit 5312 is sent to the audio processing circuit 5311 in accordance with a command from the CPU 5308.

  A signal including audio information sent in accordance with a command from the CPU 5308 is demodulated into an audio signal by the audio processing circuit 5311 and sent to the speaker 5327. An audio signal sent from the microphone 5326 is modulated in the audio processing circuit 5311 and sent to the transmission / reception circuit 5312 in accordance with a command from the CPU 5308.

  The controller 5307, the CPU 5308, the power supply circuit 5310, the sound processing circuit 5311, and the memory 5309 can be mounted as a package of this embodiment. This embodiment can be applied to any circuit other than a high-frequency circuit such as an isolator, a band pass filter, a VCO (Voltage Controlled Oscillator), an LPF (Low Pass Filter), a coupler, and a balun.

  FIG. 13 illustrates one mode of a mobile phone including the module illustrated in FIGS. 12 (A) to 12 (B). The display panel 5301 is incorporated in a housing 5330 so as to be detachable. The shape and size of the housing 5330 can be changed as appropriate in accordance with the size of the display panel 5301. The housing 5330 to which the display panel 5301 is fixed is fitted to the printed board 5331 and assembled as a module.

  The display panel 5301 is connected to the printed board 5331 through the FPC 5313. A signal processing circuit 5335 including a speaker 5332, a microphone 5333, a transmission / reception circuit 5334, a CPU, a controller, and the like is formed over the printed circuit board 5331. Such a module is combined with the input means 5336, the battery 5337, and the antenna 5340 and stored in the housing 5339. The pixel portion of the display panel 5301 is arranged so that it can be seen from an opening window formed in the housing 5339.

  The mobile phone according to the present embodiment can be transformed into various modes according to the function and application. For example, a configuration may be adopted in which a plurality of display panels are provided, or the housing is divided into a plurality of parts as appropriate and can be opened and closed by a hinge.

  In the mobile phone in FIG. 13, the display panel 5301 is formed by arranging semiconductor devices similar to those described in the embodiment in a matrix. In the semiconductor device, the potential to be turned on or off applied to the gate terminal of the driving transistor in the pixel and the potential of the data line are set separately, and the light-emitting element in the pixel is in a light-emitting state or a light-off state. A constant potential can be continuously supplied to the gate terminal of the driving transistor. Therefore, it is possible to set the data line amplitude to a low amplitude to reduce power consumption, and to operate stably compared to the conventional pixel configuration in which the potential is held by the holding capacitor. Have. Since the display panel 5301 including the semiconductor device has similar features, this mobile phone can reduce power consumption and display stable operation. With such a feature, in the mobile phone, the power supply circuit can be significantly reduced or reduced, and display defects can be reduced. Therefore, the housing 5339 can be reduced in size and weight. Since the mobile phone according to the present invention has low power consumption and reduced size and weight, a product with improved portability can be provided to customers.

  FIG. 14A illustrates a television device, which includes a housing 6001, a support base 6002, a display portion 6003, and the like. In this television device, the display portion 6003 is formed by arranging semiconductor devices similar to those described in the embodiment in a matrix. In the semiconductor device, the potential to be turned on or off applied to the gate terminal of the driving transistor in the pixel and the potential of the data line are set separately, and the light-emitting element in the pixel is in a light-emitting state or a light-off state. A constant potential can be continuously supplied to the gate terminal of the driving transistor. Accordingly, it is possible to set the amplitude of the potential of the data line to a low amplitude to reduce power consumption, and to perform a stable operation as compared with the conventional pixel configuration in which the potential is held by the holding capacitor. It has characteristics. Since the display portion 6003 including the semiconductor device has similar features, the television device can reduce power consumption and display stable operation. With such a feature, in the television device, the power supply circuit can be significantly reduced or reduced, and display defects can be reduced. Therefore, the housing 6001 can be reduced in size and weight. In the television device according to the present invention, low power consumption and reduction in size and weight are achieved, so that a product with improved portability can be provided to a customer.

  FIG. 14B illustrates a computer, which includes a main body 6101, a housing 6102, a display portion 6103, a keyboard 6104, an external connection port 6105, a pointing mouse 6106, and the like. In this computer, the display portion 6103 is formed by arranging semiconductor devices similar to those described in the embodiment in a matrix. In the semiconductor device, the potential to be turned on or off applied to the gate terminal of the driving transistor in the pixel and the potential of the data line are set separately, and the light-emitting element in the pixel is in a light-emitting state or a light-off state. A constant potential can be continuously supplied to the gate terminal of the driving transistor. Accordingly, it is possible to set the amplitude of the potential of the data line to a low amplitude to reduce power consumption, and to perform a stable operation as compared with the conventional pixel configuration in which the potential is held by the holding capacitor. It has characteristics. Since the display portion 6103 which includes the semiconductor device has similar characteristics, this computer can reduce power consumption and display stable operation. With such a feature, a power supply circuit can be significantly reduced or reduced or display defects can be reduced in a computer; thus, the main body 6101 and the housing 6102 can be reduced in size and weight. In the computer according to the present invention, low power consumption and reduction in size and weight are achieved, so that a product with improved portability can be provided to a customer.

  FIG. 14C illustrates a portable computer, which includes a main body 6201, a display portion 6202, a switch 6203, operation keys 6204, an infrared port 6205, and the like. In this portable computer, the display portion 6202 is formed by arranging semiconductor devices similar to those described in the embodiment in a matrix. In the semiconductor device, the on / off potential applied to the gate terminal of the driving transistor in the pixel and the potential of the data line are set separately, and driving is performed regardless of whether the light-emitting element is in a light-emitting state or a light-off state in the pixel. A constant potential can be continuously supplied to the gate terminal of the transistor. Therefore, the characteristic is that the amplitude of the potential of the data line is set to a low amplitude to reduce the power consumption, and the stable operation is possible as compared with the conventional pixel configuration in which the potential is held by the holding capacitor. Have. Since the display portion 6202 which includes the semiconductor device has similar features, this portable computer can reduce power consumption and display stable operation. With such a feature, in a portable computer, the power supply circuit can be significantly reduced or reduced, or display defects can be reduced. Therefore, the main body 6201 can be reduced in size and weight. In the portable computer according to the present invention, low power consumption and reduction in size and weight are achieved, so that a product with improved portability can be provided to a customer.

  FIG. 14D illustrates a portable game machine including a housing 6301, a display portion 6302, speaker portions 6303, operation keys 6304, a recording medium insertion portion 6305, and the like. In this portable game machine, the display portion 6302 is formed by arranging semiconductor devices similar to those described in the embodiment in a matrix. In the semiconductor device, the on / off potential applied to the gate terminal of the driving transistor in the pixel and the potential of the data line are set separately, and driving is performed regardless of whether the light-emitting element is in a light-emitting state or a light-off state in the pixel. A constant potential can be continuously supplied to the gate terminal of the transistor. Therefore, the characteristic is that the amplitude of the potential of the data line is set to a low amplitude to reduce the power consumption, and the stable operation is possible as compared with the conventional pixel configuration in which the potential is held by the holding capacitor. Have. Since the display portion 6302 which includes the semiconductor device has similar characteristics, this portable game machine can reduce power consumption and display stable operation. With such a feature, in a portable game machine, the power supply circuit can be significantly reduced or reduced, or display defects can be reduced. Therefore, the housing 6301 can be reduced in size and weight. In the portable game machine according to the present invention, low power consumption and reduction in size and weight are achieved, so that a product with improved portability can be provided to a customer.

  FIG. 14E illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 6401, a housing 6402, a display portion A 6403, a display portion B 6404, and a recording medium (such as a DVD). A reading unit 6405, operation keys 6406, a speaker unit 6407, and the like are included. The display portion A 6403 mainly displays image information, and the display portion B 6404 mainly displays character information. In this image reproduction device, the display portion A 6403 and the display portion B 6404 are configured by arranging semiconductor devices similar to those described in the embodiment in a matrix. In the semiconductor device, the on / off potential applied to the gate terminal of the driving transistor in the pixel and the potential of the data line are set separately, and driving is performed regardless of whether the light-emitting element is in a light-emitting state or in a light-off state. A constant potential can be continuously supplied to the gate terminal of the transistor. Therefore, the characteristic is that the amplitude of the potential of the data line is set to a low amplitude to reduce the power consumption, and the stable operation is possible as compared with the conventional pixel configuration in which the potential is held by the holding capacitor. Have. Since the display portion A 6403 and the display portion B 6404 which are formed using the semiconductor device have similar characteristics, this image reproduction device can reduce power consumption and display stable operation. With such a feature, in the image reproducing device, the power supply circuit can be significantly reduced or reduced, or display defects can be reduced. Therefore, the display portion A 6403 and the display portion B 6404 can be reduced in size and weight. Since the image reproducing apparatus according to the present invention achieves low power consumption and small size and weight, a product with improved portability can be provided to customers.

  Display devices used in these electronic devices can use not only a glass substrate but also a heat-resistant plastic substrate depending on the size, strength, or purpose of use. As a result, the weight can be further reduced.

  Note that the display portion used in these electronic devices includes the semiconductor device described in any of the above embodiments, and is included in each pixel of the pixel portion from a scan line driver circuit or a data line driver circuit arranged around the pixel portion. Even when signal supply to the arranged memory circuit is stopped, data of the signal immediately before the signal supply is stopped is held in the memory circuit, and the light emitting state and the light-off state of the light emitting element can be held. Therefore, when a still image or the like is displayed using the semiconductor device of the present invention, it is not necessary to operate the scanning line driving circuit or the data line driving circuit. In addition, a product with reduced power consumption can be provided to a customer even when a still image is displayed.

  It should be noted that the examples shown in the present embodiment are only examples and are not limited to these applications.

  This embodiment can be implemented by being freely combined with any description of the above embodiment modes and embodiments.

The circuit diagram of an embodiment of the invention. FIG. 3 is a diagram illustrating an embodiment of the present invention. 1 is a circuit diagram of Embodiment 1 of the present invention. The timing chart figure of Example 2 of this invention. The circuit diagram and top view of Example 3 of this invention. Sectional drawing of Example 3 of this invention. The top view and block diagram which show the structure of Example 4 of this invention. The circuit diagram of Example 5 of the present invention. The figure of the electronic device of Example 6 of this invention. The figure of the electronic device of Example 6 of this invention. The figure of the electronic device of Example 6 of this invention. The figure of the electronic device of Example 6 of this invention. The figure of the electronic device of Example 6 of this invention. The figure of the electronic device of Example 6 of this invention. The figure which shows the conventional pixel structure. The figure which shows the problem of the conventional pixel structure.

Explanation of symbols

101 data transistor 102 switch transistor 103 memory circuit 104 switching circuit 105 drive transistor 106 light emitting element 107 counter electrode 108 data line 109 first scanning line 110 second scanning line 111 third scanning line 112 first power supply line 113 first 2 power line 501 data transistor 502 switch transistor 503 transistor 504 transistor 505 transistor 506 transistor 507 transistor 508 transistor 509 transistor 510 transistor 511 transistor 512 drive transistor 513 light emitting element 514 counter electrode 515 first scan line 516 second scan line 517 Third scanning line 518 First power line 519 Second power line 520 Data line 521 Memory circuit 522 Switching circuit 1201 Substrate 202 crystalline semiconductor film 1203A conductive film 1203B conductive film 1204 insulating film 1205 insulating film 1206 interlayer insulating film 1207 conductive film 1208 insulating film 1209 pixel electrode 1210 electroluminescent layer 1211 counter electrode 1301 pixel 1302 pixel portion 1303 signal line driver circuit 1304 first Scan line driver circuit 1305 Second scan line driver circuit 1306 FPC
1307 Substrate 1311 Shift register 1312 Latch circuit 1313 Latch circuit 1314 Shift register 1315 Buffer 1317 Buffer 1401 Second power supply line 1402 Counter electrode 1403 Drive transistor 1404 Light emitting element 1406 Monitor power supply line 1407 Monitor power supply line 1408 Monitor light source 1409 Monitor light emission Element 1410 Sampling circuit 1411 Power supply circuit 1412 Power supply line for power supply circuit 2100 Pixel portion 2101 Selection transistor 2102 Drive transistor 2103 Holding capacitor 2104 Light emitting element 2200 Pixel 2201 Selection transistor 2202 Drive transistor 2203 Holding capacitor 2204 Light emitting element 2205 Scanning line 2206 Data line 2207 Power supply Line 2208 Counter electrode 5001 Display panel 5002 Pixel portion 5003 Scan line Moving circuit 5004 signal line driving circuit 5011 circuit board 5012 control circuit 5013 signal dividing circuit 5014 connection wiring 5101 tuner 5102 video signal amplifier circuit 5103 video signal processing circuit 5105 audio signal amplifier circuit 5106 audio signal processing circuit 5107 speaker 5108 control circuit 5109 input unit 5201 Case 5202 Display screen 5203 Speaker 5204 Operation switch 5210 Battery charger 5212 Case 5213 Display portion 5216 Operation key 5217 Speaker portion 5301 Display panel 5302 Printed wiring board 5303 Pixel portion 5304 First scan line driver circuit 5305 Second scan line Drive circuit 5306 Signal line drive circuit 5307 Controller 5308 CPU
5309 Memory 5310 Power supply circuit 5311 Audio processing circuit 5312 Transmission / reception circuit 5313 FPC
5314 Interface Port 5315 Antenna Port 5316 VRAM
5317 DRAM
5318 Flash memory 5320 Control signal generation circuit 5321 Decoder 5322 Register 5323 Arithmetic circuit 5324 RAM
5325 Input means 5326 Microphone 5327 Speaker 5328 Antenna 5330 Housing 5331 Printed circuit board 5332 Speaker 5333 Microphone 5334 Transmission / reception circuit 5335 Signal processing circuit 5336 Input means 5337 Battery 5339 Case 5340 Antenna 6001 Case 6002 Support base 6003 Display portion 6101 Main body 6102 Case 6103 Display unit 6104 Keyboard 6105 External connection port 6106 Pointing mouse 6201 Main body 6202 Display unit 6203 Switch 6204 Operation key 6205 Infrared port 6301 Case 6302 Display unit 6303 Speaker unit 6304 Operation key 6305 Recording medium insertion unit 6401 Main unit 6402 Case 6403 Display unit A
6404 Display portion B
6405 Recording medium (DVD etc.) reading unit 6406 Operation key 6407 Speaker unit

Claims (5)

Data lines,
First to third scanning lines;
First and second power lines;
A light emitting element;
A first transistor having a gate terminal electrically connected to the data line and a first terminal electrically connected to the first power line ;
A second transistor having a gate terminal electrically connected to the first scan line and a first terminal electrically connected to a second terminal of the first transistor;
A memory circuit;
A switching circuit;
A third transistor having a gate terminal electrically connected to the switching circuit and a second terminal electrically connected to the light emitting element;
The memory circuit is electrically connected to a second terminal of the second transistor and the second scan line ;
The switching circuit is electrically connected to a second terminal of the second transistor, the memory circuit, and the third scanning line ;
The switching circuit switches the connection between the third transistor and the memory circuit or the connection between the third transistor and the second power supply line, and the input potential is changed to the third transistor. A semiconductor device characterized by being applied to the gate terminal of the semiconductor device. In claim 1,
The semiconductor device, wherein the first transistor and the second transistor are N-channel transistors, and the third transistor is a P-channel transistor. Data lines,
First to third scanning lines;
First and second power lines;
A light emitting element;
A first N-channel transistor having a gate terminal electrically connected to the data line and a first terminal electrically connected to the first power line;
A second N-channel transistor having a gate terminal electrically connected to the first scan line and a first terminal electrically connected to a second terminal of the first N-channel transistor;
A memory circuit;
A switching circuit;
A first P-channel transistor having a first terminal electrically connected to the second power supply line and a second terminal electrically connected to the light emitting element;
The memory circuit includes a NOR having a first input terminal electrically connected to a second terminal of the second N-channel transistor and a second input terminal electrically connected to the second scan line. Circuit,
A third N-channel transistor having a gate terminal electrically connected to the output terminal of the NOR circuit and a first terminal electrically connected to the first power supply line;
A second P-channel transistor having a gate terminal electrically connected to the first scan line and a first terminal electrically connected to the second power supply line;
The gate terminal is electrically connected to the output terminal of the NOR circuit, the first terminal is electrically connected to the second terminal of the second P-channel transistor, and the second terminal is the third N-channel transistor. A third P-channel transistor electrically connected to the second terminal of
In the switching circuit, a gate terminal is electrically connected to the third scanning line, a first terminal is a second terminal of the second N-channel transistor, and a second terminal of the third N-channel transistor. And a fourth N-channel transistor electrically connected to the second terminal of the third P-channel transistor, and the second terminal electrically connected to the gate terminal of the first P-channel transistor. When,
A gate terminal is electrically connected to the third scanning line, a first terminal is electrically connected to the second power supply line, a second terminal is a second terminal of the fourth N-channel transistor, and A fourth P-channel transistor electrically connected to a gate terminal of the first P-channel transistor;
A first potential at which the first P-channel transistor is turned on or a second potential at which the first P-channel transistor is turned off is input to the memory circuit,
Wherein the second power supply line, the second potential to which the first P-channel transistor is turned off is input,
The switching circuit, a semiconductor device, characterized in that the first potential or the second conductive position, is applied to the gate terminal of the first P-channel transistor. In claim 3,
The semiconductor device according to claim 1, wherein a potential of the first power supply line is lower than a second potential of the second power supply line. In any one of Claims 1 thru | or 4,
The semiconductor device, wherein the light emitting element is an electroluminescence element.

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