JP5364235B2 - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device in which by making a bias current, ample for insulating a short-circuited point, to flow in the reverse direction and applying a transistor with the use of amorphous silicon. <P>SOLUTION: The display device includes a switching transistor for controlling the input of a video signal; a drive transistor for controlling the current flowing in the forward direction to that of a light-emitting device; and an AC transistor for controlling the current flowing in the direction reverse to that of the light-emitting device, and a reverse bias current can be made to flow in the light-emitting device. Also, the transistor is constituted of an N-channel transistor. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

  The present invention relates to a display device using a light emitting element. The present invention also relates to an electronic device having the display device in a display portion.

  In recent years, a technology for forming a transistor, for example, a TFT (Thin Film Transistor) on a substrate has greatly advanced, and an active matrix display device has been developed.

  In addition, a so-called self-luminous display device in which a pixel is formed of a light emitting element such as a light emitting diode (LED) has attracted attention. As a light-emitting element used in such a self-luminous display device, an organic light-emitting diode (also referred to as an OLED (Organic Light Emitting Diode), an organic EL element, or an electroluminescence (EL) element) attracts attention. It has been used for organic EL displays and the like. Since the light emitting element is a self-luminous type, a light source such as a backlight is not required unlike a liquid crystal display device. For this reason, it is considered promising as a means for realizing a lighter and thinner display device, and in recent years, a large screen EL display has been developed following the liquid crystal television.

  A problem in putting an EL display into practical use is a short lifetime of a light emitting element due to deterioration of an EL layer. Factors that influence the length of the life of the EL layer include the structure of the device that drives the EL display, the characteristics of the organic EL material that constitutes the EL layer, the material of the electrode, the conditions in the production process, and the like.

  In addition to the above-described factors, the EL display driving method has recently attracted attention as a factor that affects the length of the EL layer lifetime. In order to emit light from an EL element, a method of applying a direct current to two electrodes, an anode and a cathode, sandwiching an EL layer has been conventionally used. That is, the EL display is DC driven, and the EL drive voltage applied to the EL layer always has the same polarity.

However, when a forward drive voltage and a reverse drive voltage are applied to the light-emitting element and a reverse drive voltage is applied to the light-emitting element, a current sufficient to insulate the short-circuited part is passed through the short-circuited part. Therefore, there has been proposed a driving method capable of extending the lifetime of the light emitting element (see Patent Document 1).
JP-A-2005-202371

  In addition, there is an initial failure in which a pixel electrode and a counter electrode are short-circuited and a region that does not emit light is formed in the pixel region. A short circuit occurs when foreign matter (dust) adheres before the light emitting element is formed, or when a pinhole is generated in the electroluminescent layer because a fine protrusion is formed on the anode when forming the anode. In addition, since the electroluminescent layer is thin, the electroluminescent layer may not be uniformly formed and pinholes may occur. In a pixel in which such an initial failure has occurred, lighting and non-lighting according to the signal are not performed, and almost all of the current flows through the short-circuited part, causing a phenomenon that the entire element is extinguished, or a specific pixel is turned on or off. A phenomenon that does not light up occurs, and the image is not displayed well.

  In addition to the initial failure described above, progressive failure (also referred to as deterioration with time) may occur with the passage of time due to a newly generated anode-cathode short circuit. The short circuit between the anode and the cathode newly generated with the passage of time is caused by fine protrusions generated when the anode is formed. That is, in the laminate in which the electroluminescent layer is sandwiched between the pair of electrodes, there is a potential short-circuit portion, and the short-circuit portion is exposed as time passes. In addition to the short circuit between the anode and the cathode, the progressive defect may also be caused by causing a minute gap between the electroluminescent layer and the cathode to spread over time, thereby causing poor contact between the electroluminescent layer and the cathode. It is said.

  By applying a drive voltage in the reverse direction, the initial failure can be insulated by carbonizing or oxidizing the short-circuited portion, and further progress can be suppressed. With regard to progressive defects, it is possible to suppress the generation and progression by insulating the short-circuited portion by carbonizing or oxidizing, or suppressing the spread of the gap between the electroluminescent layer and the cathode. .

  In order to suppress the progress of defects, it is necessary to drive the light emitting element with an alternating current. Driving the light emitting element with an alternating current means that voltages having different polarities are alternately applied to the light emitting element. In other words, in addition to the forward voltage necessary for light emission, the reverse voltage is applied. The forward voltage and the reverse voltage may not necessarily be equal in strength and application time. Even if only a slight reverse voltage is applied, it will be referred to as alternating current. In the present invention, a reverse voltage is applied to the light emitting element and a reverse bias current is supplied to perform AC driving, thereby suppressing defects in the light emitting element.

  In order to insulate the short-circuited part, it is necessary to pass a large current sufficient to insulate the short-circuited part. Usually, it is desirable that the current value sufficient to insulate the short-circuited portion is much larger than the current value flowing in the forward direction in order to cause the light emitting element to emit light.

  On the other hand, a display device and a driving method using amorphous silicon have been problems as an inexpensive manufacturing technique that has already been established. For example, when polysilicon is used for the semiconductor film, a crystallization process is required, but it is difficult to irradiate a large area substrate with a uniform laser beam, so a uniform crystal can be obtained over a wide area. It becomes difficult. In view of this, development of a high-quality display device using amorphous silicon and development of a driving method, which can increase the area, simplify the manufacturing process, and do not require crystallization, are in progress. However, when amorphous silicon is used, a P-channel transistor cannot realize sufficient operation characteristics and functions, and thus the display device needs to be configured with an N-channel transistor.

  Accordingly, an object of the present invention is to apply a pixel including an N-channel transistor to a display device and a driving method thereof. It is another object of the present invention to provide a display device capable of applying a reverse voltage to a light emitting element in order to provide good light emission characteristics and extend the life of the light emitting element.

  One of the structures of the present invention includes a first wiring, a second wiring, a third wiring, a fourth wiring, a light emitting element having a pixel electrode and a counter electrode, and an input of a video signal. The pixel includes a first transistor to be controlled, a second transistor for controlling a current flowing in the forward direction in the light emitting element, and a third transistor for controlling a current flowing in the reverse direction in the light emitting element. The gate electrode of the first transistor is electrically connected to the first wiring, one of the source electrode and the drain electrode of the first transistor is electrically connected to the second wiring through which the video signal flows, and the other Are electrically connected to the gate electrode of the second transistor. One of the source electrode and the drain electrode of the second transistor is electrically connected to the third wiring, and the other is electrically connected to the pixel electrode. One of the source electrode and the drain electrode of the third transistor is electrically connected to the pixel electrode and the gate electrode of the third transistor, and the other is electrically connected to the fourth wiring. Further, the first transistor, the second transistor, and the third transistor are N-channel transistors. Note that the first transistor, the second transistor, and the third transistor are preferably operated in a linear region.

  In other words, in other words, the light-emitting element having a scanning line, a signal line, a power supply line, a potential control line, a pixel electrode and a counter electrode, a switching transistor for controlling input of a video signal, and the light-emitting element The pixel has a driving transistor for controlling the current flowing in the forward direction and an AC transistor for controlling the current flowing in the reverse direction in the light emitting element. The gate electrode of the switching transistor is electrically connected to the scanning line, one of the source electrode and the drain electrode of the switching transistor is electrically connected to the signal line through which the video signal flows, and the other is the gate of the driving transistor. It is electrically connected to the electrode. One of the source electrode and the drain electrode of the driving transistor is electrically connected to the power supply line, and the other is electrically connected to the pixel electrode. One of the source electrode and the drain electrode of the AC transistor is electrically connected to the pixel electrode and the gate electrode of the AC transistor, and the other is electrically connected to the potential control line. The switching transistor, the driving transistor, and the AC transistor are N-channel transistors. Note that the switching transistor, the driving transistor, and the AC transistor may operate in a linear region.

  One of the structures of the present invention includes a first wiring, a second wiring, a third wiring, a fourth wiring, a light emitting element having a pixel electrode and a counter electrode, and an input of a video signal. The pixel includes a first transistor to be controlled, a second transistor for controlling a current flowing in the forward direction in the light emitting element, and a third transistor for controlling a current flowing in the reverse direction in the light emitting element. The gate electrode of the first transistor is electrically connected to the first wiring, one of the source electrode and the drain electrode of the first transistor is electrically connected to the second wiring through which the video signal flows, and the other Are electrically connected to the gate electrode of the second transistor. One of the source electrode and the drain electrode of the second transistor is electrically connected to the third wiring, and the other is electrically connected to the pixel electrode. One of the source electrode and the drain electrode of the third transistor is electrically connected to the pixel electrode, the other is electrically connected to the third wiring, and the gate electrode of the third transistor is connected to the fourth wiring. The Further, the first transistor, the second transistor, and the third transistor are N-channel transistors. Note that the first transistor, the second transistor, and the third transistor may operate in a linear region. Further, the fourth wiring and the counter electrode may be connected.

  In other words, the above structure is applied in the order of a scanning line, a signal line, a power line, a wiring, a pixel electrode and a counter electrode, a switching transistor for controlling input of a video signal, and a light emitting element. The pixel includes a driving transistor that controls current flowing in the direction and an AC transistor that controls current flowing in the reverse direction in the light emitting element. The gate electrode of the switching transistor is electrically connected to the scanning line, one of the source electrode and the drain electrode of the switching transistor is electrically connected to the signal line through which the video signal flows, and the other is the gate of the driving transistor. It is electrically connected to the electrode. One of the source electrode and the drain electrode of the driving transistor is electrically connected to the power supply line, and the other is electrically connected to the pixel electrode. One of the source electrode and the drain electrode of the AC transistor is electrically connected to the pixel electrode, the other is electrically connected to the power supply line, and the gate electrode of the AC transistor is connected to the wiring. The switching transistor, the driving transistor, and the AC transistor are N-channel transistors. Note that the switching transistor, the driving transistor, and the AC transistor are preferably operated in a linear region. Further, the wiring and the counter electrode may be connected.

  In the above structure, the ratio (L1 / W1) between the channel length L1 and the channel width W1 of the second transistor is larger than the ratio (L2 / W2) between the channel length L2 and the channel width W2 of the third transistor. preferable. More specifically, the channel length of the third transistor is preferably equal to or shorter than the channel width.

  One of the structures of the present invention is a light-emitting element including a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, a pixel electrode, and a counter electrode. A first transistor that controls input of a video signal, a second transistor that controls a forward current flowing through the light emitting element, a third transistor that controls a current flowing backward through the light emitting element, and a fourth transistor A pixel includes a transistor. The gate electrode of the first transistor is electrically connected to the first wiring, one of the source electrode or the drain electrode of the first transistor is electrically connected to the second wiring through which the video signal flows, and the other is connected to the first wiring. It is electrically connected to the gate electrodes of the two transistors. One of the source electrode and the drain electrode of the second transistor is electrically connected to the third wiring, and the other is electrically connected to the pixel electrode. One of the source electrode and the drain electrode of the third transistor is connected to the gate electrode of the second transistor, the other electrode is connected to the pixel electrode, and the gate electrode of the third transistor is connected to the fourth wiring. . One of the source electrode and the drain electrode of the fourth transistor is electrically connected to the pixel electrode and the gate electrode of the fourth transistor, and the other is electrically connected to the fifth wiring. Further, the first transistor, the second transistor, the third transistor, and the fourth transistor are N-channel transistors. Note that the first transistor, the second transistor, the third transistor, and the fourth transistor are preferably operated in a linear region.

  In other words, in other words, the scan line, the signal line, the power supply line, the first potential control line, the second potential control line, the light-emitting element including the pixel electrode and the counter electrode, and the video signal A switching transistor for controlling an input; a driving transistor for controlling a current flowing in a forward direction in the light emitting element; a first AC transistor and a second AC transistor for controlling a current flowing in a reverse direction in the light emitting element; It has in the pixel. The gate electrode of the switching transistor is electrically connected to the scanning line, one of the source electrode or drain electrode of the switching transistor is electrically connected to the signal line through which the video signal flows, and the other is connected to the gate electrode of the driving transistor. Electrically connected. One of the source electrode and the drain electrode of the driving transistor is electrically connected to the power supply line, and the other is electrically connected to the pixel electrode. One of the source electrode and the drain electrode of the first AC transistor is connected to the gate electrode of the driving transistor, the other electrode is connected to the pixel electrode, and the gate electrode of the first AC transistor has the first potential control. Connected with the line. One of the source electrode and the drain electrode of the second AC transistor is electrically connected to the pixel electrode and the gate electrode of the second AC transistor, and the other is electrically connected to the second potential control line. . The switching transistor, the driving transistor, the first AC transistor, and the second AC transistor are N-channel transistors. Note that the switching transistor, the driving transistor, the first AC transistor, and the second AC transistor are preferably operated in a linear region.

  In the above structure, the ratio (L1 / W1) between the channel length L1 and the channel width W1 of the second transistor is larger than the ratio (L2 / W2) between the channel length L2 and the channel width W2 of the fourth transistor. preferable. More specifically, the channel length of the fourth transistor is preferably equal to or shorter than the channel width.

  In the above structure, the ratio of the channel length to the channel width of the second transistor is preferably 5 or more.

  One of the structures of the present invention includes a first wiring, a second wiring, a third wiring, a light-emitting element having a pixel electrode and a counter electrode, a capacitor having two electrodes, and a video signal. A first transistor and a second transistor for controlling the input, a third transistor for controlling a current flowing in the forward direction in the light emitting element, and a fourth transistor for controlling a current flowing in the reverse direction in the light emitting element. It has in the pixel. Gate electrodes of the first transistor and the second transistor are electrically connected to the first wiring. One of the source electrode and the drain electrode of the first transistor is electrically connected to the second wiring through which the video signal flows, and the other is electrically connected to the pixel electrode. One of a source electrode and a drain electrode of the second transistor is electrically connected to the third wiring, and the other is electrically connected to a gate electrode of the third transistor and one electrode of the capacitor. One of a source electrode and a drain electrode of the third transistor is electrically connected to the third wiring, and the other is electrically connected to the pixel electrode and the other electrode of the capacitor. One of a source electrode and a drain electrode of the fourth transistor is electrically connected to the third wiring, and the other is electrically connected to the pixel electrode and the gate electrode of the fourth transistor. Further, the first transistor, the second transistor, the third transistor, and the fourth transistor are N-channel transistors. Note that the third transistor preferably operates in a saturation region, and the first transistor, the second transistor, and the fourth transistor preferably operate in a linear region.

  In other words, in other words, the scanning line, the signal line, the power supply line, the light emitting element having the pixel electrode and the counter electrode, the capacitive element having two electrodes, and the first that controls the input of the video signal. The pixel includes a switching transistor, a second switching transistor, a driving transistor for controlling a current flowing in the forward direction in the light emitting element, and an AC transistor for controlling a current flowing in the reverse direction in the light emitting element. Gate electrodes of the first switching transistor and the second switching transistor are electrically connected to the scan line. One of the source electrode and the drain electrode of the first switching transistor is electrically connected to a signal line through which a video signal flows, and the other is electrically connected to the pixel electrode. One of the source electrode and the drain electrode of the second switching transistor is electrically connected to the power supply line, and the other is electrically connected to the gate electrode of the driving transistor and one electrode of the capacitor. One of a source electrode and a drain electrode of the driving transistor is electrically connected to the power supply line, and the other is electrically connected to the pixel electrode and the other electrode of the capacitor. One of the source electrode and the drain electrode of the AC transistor is electrically connected to the power supply line, and the other is electrically connected to the pixel electrode and the gate electrode of the AC transistor. Further, the first switching transistor, the second switching transistor, the driving transistor, and the AC transistor are N-channel transistors. Note that the driving transistor is preferably operated in a saturation region, and the first switching transistor, the second switching transistor, and the AC transistor are preferably operated in a linear region.

  One structure of the present invention includes a first wiring, a second wiring, a third wiring, a fourth wiring, a light-emitting element having a pixel electrode and a counter electrode, and two electrodes. A capacitor element, a first transistor and a second transistor that control input of a video signal, a third transistor that controls a forward current flowing through the light emitting element, and a current that flows backward through the light emitting element The pixel includes a fourth transistor. Gate electrodes of the first transistor and the second transistor are electrically connected to the first wiring. One of the source electrode and the drain electrode of the first transistor is electrically connected to the second wiring through which the video signal flows, and the other is electrically connected to the pixel electrode. One of a source electrode and a drain electrode of the second transistor is electrically connected to the third wiring, and the other is electrically connected to a gate electrode of the third transistor and one electrode of the capacitor. One of a source electrode and a drain electrode of the third transistor is electrically connected to the third wiring, and the other is electrically connected to the pixel electrode and the other electrode of the capacitor. One of a source electrode and a drain electrode of the fourth transistor is electrically connected to the fourth wiring, and the other is electrically connected to the pixel electrode and the gate electrode of the fourth transistor. Further, the first transistor, the second transistor, the third transistor, and the fourth transistor are N-channel transistors. Note that the third transistor preferably operates in a saturation region, and the first transistor, the second transistor, and the fourth transistor preferably operate in a linear region.

  In other words, in other words, a scanning line, a signal line, a power supply line, a potential control line, a light emitting element having a pixel electrode and a counter electrode, a capacitive element having two electrodes, and an input of a video signal are input. A first switching transistor and a second switching transistor to be controlled, a driving transistor for controlling a current flowing in the forward direction in the light emitting element, and an AC transistor for controlling a current flowing in the reverse direction in the light emitting element Have. Gate electrodes of the first switching transistor and the second switching transistor are electrically connected to the scan line. One of the source electrode and the drain electrode of the first switching transistor is electrically connected to a signal line through which a video signal flows, and the other is electrically connected to the pixel electrode. One of the source electrode and the drain electrode of the second switching transistor is electrically connected to the power supply line, and the other is electrically connected to the gate electrode of the driving transistor and one electrode of the capacitor. One of a source electrode and a drain electrode of the driving transistor is electrically connected to the power supply line, and the other is electrically connected to the pixel electrode and the other electrode of the capacitor. One of the source electrode and the drain electrode of the AC transistor is electrically connected to the potential control line, and the other is electrically connected to the pixel electrode and the gate electrode of the AC transistor. Further, the first switching transistor, the second switching transistor, the driving transistor, and the AC transistor are N-channel transistors. Note that the driving transistor is preferably operated in a saturation region, and the first switching transistor, the second switching transistor, and the AC transistor are preferably operated in a linear region.

  In the above structure, the ratio (L1 / W1) between the channel length L1 and the channel width W1 of the third transistor is larger than the ratio (L2 / W2) between the channel length L2 and the channel width W2 of the fourth transistor. Preferably. More specifically, the channel length of the fourth transistor is preferably equal to or shorter than the channel width, and the ratio of the channel length to the channel width of the third transistor is preferably 5 or more.

  In the above structure, the current that flows in the reverse direction to the light emitting element is preferably larger than the current that flows in the forward direction to the light emitting element, the potential of the counter electrode is a fixed potential, and the potential of the third wiring is the light emitting element. You may change according to the direction of the electric current sent through.

  In the above structure, the N-channel transistor may be a transistor using amorphous silicon.

  The above structure may be applied to an electronic device using a display device.

  The present invention is characterized in that a light-emitting element is provided on a large-area substrate provided with a pixel portion (or a drive circuit) including an N-channel TFT having an active layer of amorphous silicon.

  With the above configuration, when a forward voltage is applied to the light emitting element, a constant current can be supplied to the light emitting element, and when a reverse voltage is applied to the light emitting element, a short-circuited portion is provided. A current sufficient to insulate can be supplied to the short-circuit portion, and the lifetime of the light-emitting element can be extended. That is, by applying a voltage in the reverse direction to the light emitting element, initial failure and progressive failure of the light emitting element can be suppressed, and a reduction in luminance due to deterioration of the electroluminescent layer can be prevented.

  In addition, since the present invention uses a driving method composed of N-channel transistors, it can be composed of amorphous silicon. Since amorphous silicon suitable for a mass production process is used for an active layer of a transistor, a transistor can be formed over a large-area substrate, and a semiconductor film crystallization step after film formation can be omitted. Manufacturing costs can be reduced. Furthermore, if amorphous silicon is used for the active layer of the transistor, an amorphous silicon transistor substrate can be manufactured using a conventional existing production line, and the equipment cost can be reduced.

  Furthermore, by configuring with an N-channel transistor, the circuit configuration can be configured with a unipolar transistor. Thereby, the manufacturing process can be simplified, the manufacturing cost can be reduced, and the yield can be improved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, it should be understood by those skilled in the art that the present invention can be implemented in many different modes, and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Understood. Therefore, the present invention should not be construed as being limited to the description of the embodiment modes. Note that in the structures of the present invention described below, reference numerals indicating the same elements are used in common in different drawings, and repetitive description in that case may be omitted.

(Embodiment 1)
(Circuit configuration 1)
FIG. 1 shows an embodiment of a circuit constituting a pixel as a circuit configuration (also referred to as a pixel configuration) diagram according to the present invention.

  1 controls a light-emitting element 104, a transistor used as a switching element for controlling input of a video signal to the pixel (switching transistor 101), and a current value flowing through the light-emitting element 104. And a transistor (alternating current transistor 103) that applies a reverse bias current to the light emitting element 104 when a reverse voltage is applied to the light emitting element 104. The switching transistor 101, the driving transistor 102, and the AC transistor 103 have the same polarity. As a feature of the present invention, N-type transistors are used as these transistors. Further, although a capacitor is not provided in this embodiment, it may be provided as a capacitor for holding the potential of a video signal.

  As shown in FIG. 1, the gate electrode of the switching transistor 101 is connected to the scanning line G. One of the source electrode and the drain electrode of the switching transistor 101 is connected to the signal line S, and the other is connected to the gate electrode of the driving transistor 102. One of the source electrode and the drain electrode of the driving transistor 102 is connected to the power supply line V, and the other is connected to the pixel electrode of the light emitting element 104.

  In this embodiment mode, one of the source electrode and the drain electrode of the AC transistor 103 is connected to the potential control line W, and the other is connected to the pixel electrode of the light-emitting element 104. The gate electrode of the AC transistor 103 is connected to the source electrode or the drain electrode of the AC transistor 103 connected to the pixel electrode of the light emitting element 104.

  Note that in this specification, “connected” means electrical connection unless there is a particular limitation.

  In this specification, a potential control line is a wiring that changes a potential in order to control an AC transistor.

  Further, when the switching transistor 101 is in a non-selected state (off state), the gate potential of the driving transistor 102 is held by the gate capacitance of the driving transistor 102. Note that FIG. 1 illustrates a structure in which the gate potential is held by the gate capacitance of the driving transistor 102 without providing the capacitor element; however, the present invention is not limited to this structure, and a capacitor element may be provided. .

  Further, in this embodiment, the ratio L / W between the channel length L and the channel width W of the driving transistor 102 is set larger than that of the AC transistor 103. Specifically, in the driving transistor 102, L is set larger than W, and more desirably 5/1 or more. Further, in the AC transistor 103, L is equal to or shorter than W. Accordingly, the current value flowing in the reverse direction when a reverse voltage is applied to the light emitting element 104 is made larger than the current value flowing in the forward direction when a forward voltage is applied to the light emitting element 104 in the pixel. Can do.

  The light-emitting element 104 has an anode and a cathode. In this specification, when the anode is used as a pixel electrode, the cathode is called a counter electrode, and when the cathode is used as a pixel electrode, the anode is called a counter electrode.

  Here, it can be said that the switching transistor preferably has a configuration with little leakage current (off-state current and gate leakage current). Note that the off-current is a current that flows between the source and the drain when the transistor is off, and the gate leakage current is a current that flows between the gate and the source or drain via the gate insulating film. Current.

  Therefore, the N-channel transistor used for the switching transistor 101 is preferably provided with a low concentration impurity region (also referred to as a lightly doped drain (LDD region)). This is because a transistor having a structure provided with an LDD region can reduce off-state current. In addition, the switching transistor 101 needs to have a large on-current when a current flows through the light-emitting element 104.

  In a more preferable mode, the switching transistor 101 is provided with an LDD region, and the LDD region is provided with a region overlapping with the gate electrode. Then, the switching transistor 101 can increase the on-current and further reduce the generation of hot electrons. Therefore, the reliability of the switching transistor 101 is improved.

  Further, the driving transistor 102 is also provided with an LDD region, and the LDD region overlaps with the gate electrode, whereby reliability is improved.

  The off-state current can also be reduced by reducing the thickness of the gate insulating film. Therefore, the thickness of the switching transistor 101 is preferably smaller than the thickness of the driving transistor 102.

  Further, when the switching transistor 101 has a double gate structure or other multi-gate structure, gate leakage current can be reduced. Further, by adopting a double gate structure or other multi-gate structure in the driving transistor 102, the gate leakage current can be reduced and the reliability can be improved.

  In particular, when an off-state current flows through the switching transistor 101, the gate capacitance of the driving transistor 102 cannot hold the voltage written during the writing period. Therefore, the switching transistor 101 is preferably provided with an LDD region, a thin gate insulating film, or a multi-gate structure to reduce off-state current.

  Note that in this specification, a light-emitting element (EL element) is described as an element having a structure in which an electroluminescent layer (EL layer) that emits light when an electric field is generated is sandwiched between an anode and a cathode. It is not limited to.

  In this specification, a light-emitting element means light emission (fluorescence) at the time of transition from a singlet exciton to a ground state and light emission (phosphorescence at the time of transition from a triplet exciton to a ground state). ) Will be described as indicating both.

  Examples of the electroluminescent layer include a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer. The light emitting element is basically shown in a structure in which an anode, a light emitting layer, and a cathode are stacked in this order. In addition to this, a structure in which an anode, a hole injection layer, a light emitting layer, an electron injection layer, and a cathode are stacked in this order, Examples include a structure in which an anode, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer, and a cathode are stacked in this order.

  Note that the electroluminescent layer is not limited to a layer in which a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer, and the like are clearly distinguished. In other words, the electroluminescent layer may have a structure in which materials constituting the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, the electron injection layer, and the like are mixed. Moreover, the inorganic substance may be mixed.

  Further, the electroluminescent layer of the light emitting element may be any material of a low molecular material, a high molecular material, and a medium molecular material.

  Note that in this specification, the term “middle molecular material” means that the number of molecules is 20 or less or the length of a chained molecule is 10 μm or less and has no sublimation property.

  Next, the operation in the circuit configuration of FIG. 1 will be described with reference to FIG.

  First, in the writing period of FIG. 2A, when the scanning line G is selected, the switching transistor 101 whose gate electrode is connected to the scanning line G is turned on. Then, the potential Vsig of the video signal input to the signal line S is input to the gate electrode of the driving transistor 102 via the switching transistor 101, and the gate potential of the driving transistor 102 is driven by the gate capacitance of the driving transistor 102. Is retained. In addition, since the driving transistor 102 is turned on by the potential Vsig of the video signal, a forward bias current flows through the light emitting element 104 and the light emitting element 104 emits light.

  Specifically, the potential Vdd is supplied to the power supply line V and the potential Vss is supplied to the counter electrode of the light emitting element 104, so that the light emitting element 104 emits light. At this time, the potential Vss and the potential Vdd applied to the power supply line V are potentials that satisfy Vss <Vdd. For example, GND (ground potential), 0 V, or the like may be applied as the potential Vss.

  On the other hand, in this writing period, the potential Vdd2 of the potential control line W is set higher than the potential Vss of the counter electrode of the light-emitting element 104 (that is, Vdd2> Vss is satisfied). The electrode of the AC transistor 103 to be connected serves as a drain electrode, and the electrode of the AC transistor 103 connected to the pixel electrode of the light emitting element 104 serves as a source electrode. Further, since the source electrode and the gate electrode of the AC transistor 103 are connected, the AC transistor 103 is turned off.

  Note that the case where the driving transistor 102 is turned on by the potential Vsig of the video signal in the writing period has been described; however, when the driving transistor 102 is turned off by the potential Vsig of the video signal, the current to the light-emitting element 104 is Therefore, the light emitting element 104 does not emit light.

  In this specification, a transistor in an on state indicates that a gate voltage causes a conductive state between a source electrode and a drain electrode. In addition, the transistor is in an off state indicates that the gate voltage causes a non-conduction state between the source electrode and the drain electrode.

  In the present specification, applying a reverse voltage to the light emitting element means applying a reverse voltage to the forward voltage, and a reverse bias current flows through the light emitting element, Does not emit light.

  Next, in the display period of FIG. 2B, the switching transistor 101 is turned off by controlling the potential of the scanning line G. In addition, since the potential Vsig of the video signal written in the writing period is held by the gate capacitance of the driving transistor 102, the driving transistor 102 is turned on. Accordingly, a forward bias current flows to the light emitting element 104, and the light emitting element 104 emits light.

  Specifically, as in the writing period, the potential Vdd is supplied to the power supply line V, the potential Vss is supplied to the counter electrode of the light-emitting element 104, and the light-emitting element 104 emits light. At this time, the potential Vss and the potential Vdd applied to the power supply line V are potentials that satisfy Vss <Vdd. For example, GND (ground potential), 0 V, or the like may be applied as the potential Vss.

  On the other hand, as in the writing period, the potential Vdd2 of the potential control line W is set to a potential higher than the potential Vss of the counter electrode of the light emitting element 104 (that is, Vdd2> Vss is satisfied). It is turned off.

  In the writing period, the case where the driving transistor 102 is turned on by the potential Vsig of the video signal has been described; however, when the driving transistor 102 is turned off by the potential Vsig of the video signal, the current to the light-emitting element 104 is Therefore, no current is supplied to the light-emitting element 104 even during the display period.

  Next, in the reverse bias period (non-lighting period) in FIG. 2C, the switching transistor 101 is turned off by controlling the potential of the scanning line G.

  On the other hand, the AC transistor 103 connected to the potential control line W is set by setting the potential Vss2 of the potential control line W to a potential lower than the potential Vss of the counter electrode of the light emitting element 104 (that is, satisfying Vss> Vss2). The electrode is a source electrode, and the electrode connected to the pixel electrode of the light-emitting element 104 is a drain electrode. Further, since the drain electrode and the gate electrode of the AC transistor 103 are connected, the AC transistor 103 is turned on. Thus, a reverse voltage is applied to the light emitting element 104, and a reverse bias current flows in the light emitting element 104 and the AC transistor 103.

  Note that in the case where the driving transistor 102 is turned on by the potential Vsig of the video signal in the writing period and the display period, the gate transistor holds the potential of the video signal even in the reverse bias period. Is turned on. As a result, a forward bias current flows through the driving transistor 102 (not shown), but most of the current flows into the AC transistor 103, so that the operation is not particularly affected. In addition, as described above, when the L / W of the driving transistor 102 is made larger than the L / W of the AC transistor 103, the channel width W of the AC transistor 103 is increased. The bias current flowing in the direction tends to flow to the AC transistor 103. Needless to say, current is not supplied to the driving transistor 102 when the driving transistor 102 is turned off in the writing period and the display period.

  As described above, by making the L / W of the driving transistor 102 larger than the L / W of the AC transistor 103, the current flowing through the AC transistor 103 is made larger than the current flowing through the driving transistor 102. can do. That is, the current value of the reverse bias current is larger than the current value of the forward bias current, and a large current can flow through the light emitting element 104 during the reverse bias period.

  Further, the potential difference between Vss2 and Vss in the reverse bias period may be larger than the potential difference between Vdd and Vss in the display period. As a result, the current value of the reverse bias current becomes larger than the current value of the forward bias current, and a larger current can further flow through the light emitting element 104 during the reverse bias period.

  Note that although the potential of the counter electrode of the light-emitting element 104 and the potential of the power supply line V are fixed potentials in this embodiment mode, the present invention is not limited to this. For example, the potential of the counter electrode of the light emitting element 104 may be changed, or both the potential of the power supply line V and the potential of the counter electrode of the light emitting element 104 may be changed.

  Next, a method for expressing gradation in a pixel having such a configuration will be described.

  Gradation expression methods can be broadly divided into analog methods and digital methods. Compared with the analog method, the digital method has advantages such as being resistant to variations in transistors and suitable for multi-gradation. Whereas the analog method is limited by the variation of transistors, the digital method can display very uniform gradation even if there is a slight variation in TFT.

  As an example of a digital gradation expression method, a time gradation method is known. This type of driving method is a method of expressing gradation by controlling a period during which each pixel of a display device emits light.

  When a period for displaying one image is one frame period, one frame period is divided into a plurality of subframe periods.

  Each subframe period is turned on or off, that is, the light emitting element of each pixel is turned on or off to control the period during which the light emitting element emits light per frame period. Expressed.

  A method of driving by the digital time gray scale method using the pixel shown in FIG. 1 will be described with reference to a timing chart of FIG. In FIG. 3, a reverse voltage is applied to the light emitting element 104 as the reverse bias period (non-lighting period) BF at the fourth bit.

  When an image is displayed using the display device of the present invention, the screen rewriting operation and the display operation are repeatedly performed during the display period. The number of rewrites is not particularly limited, but is preferably at least about 60 times per second so that a person viewing the image does not feel flicker. Here, a period for performing a rewriting operation and a display operation for one screen (one frame) and a reverse bias period are referred to as one frame period F1.

As shown in FIG. 3, one frame period F1 includes four subframe periods SF1, SF2, including a writing period Ta1, Ta2, Ta3, Ta4, a display period Ts1, Ts2, Ts3, Ts4, and a reverse bias period BF. Time-divided into SF3 and SF4. A light emitting element to which a signal for emitting light is given is in a light emitting state during a display period. The ratio of the length of the display period in each subframe period is as follows: first subframe period Ta1: second subframe period Ta2: third subframe period Ta3: fourth subframe period Ta4 = 2 ³ : 2 ² : 2 ¹ : 2 ⁰ = 8: 4: 2: 1 As a result, 4-bit gradation can be expressed. However, the number of bits and the number of gradations are not limited to those described here. For example, eight subframe periods may be provided to enable 8-bit gradation.

  The writing period and the display period of the above operation are repeated for all the subframe periods SF1 to SF4. In SF4, the reverse bias period BF is added to complete one frame period F1. Here, the lengths of the display periods Ts1 to Ts4 of the subframe periods SF1 to SF4 are set as appropriate, and the gray scale is determined by the total display period of the subframe periods SF1 to SF4 in which the light emitting element 104 emits light per frame period F1. Express. That is, the gradation is expressed by the total lighting time in one frame period F1.

  Note that the subframe periods SF1 to SF4 may be arranged without being consecutive in one frame. Further, one subframe period may be composed of a plurality of subframe periods, or the plurality of subframe periods may be arranged without being consecutive in one frame. Note that in the case of expressing gradation using the time gradation method, the number of subframes is not particularly limited. Further, the length of the lighting period of each subframe period and which subframe is lit, that is, the selection method of the subframe is not particularly limited.

  When the pixel of FIG. 1 is driven in an analog manner, as shown in FIG. 4, a period in which a forward polarity voltage is applied to the light emitting element in one frame period F1, that is, a forward bias period FF and a reverse direction. It is sufficient to provide a period for applying a voltage having the polarity, that is, a reverse bias period BF. Note that an analog video signal may be written to each pixel in the forward bias period FF (Ta: writing period) and the light-emitting element 104 may emit light or not emit light (Ts: display period).

  As described above, in the structure of the present invention, when a reverse voltage is applied, a current sufficient to insulate a short-circuited portion can be passed, and the lifetime of the light-emitting element can be extended. In addition, since the circuit configuration can be constituted by a unipolar transistor, it can be manufactured at low cost.

  In addition, an amorphous silicon transistor can be used by manufacturing a transistor having a circuit structure as an N-type transistor. Therefore, since a transistor manufacturing technique using amorphous silicon that has already been established can be applied, a display device with favorable and stable operation characteristics can be obtained with a simple and inexpensive manufacturing process.

(Embodiment 2)
In this embodiment, a structure of a display included in the display device will be described with respect to the display device manufactured using Embodiment 1.

  The display device includes a display and a peripheral circuit that inputs a signal to the display.

  FIG. 5 is a block diagram showing the configuration of the display. In FIG. 5, the display 300 includes a signal line driver circuit 301, a scanning line driver circuit 302, and a pixel portion 303. The pixel portion 303 has a configuration in which pixels are arranged in a matrix.

  A thin film transistor (hereinafter referred to as TFT) is arranged in each pixel of the pixel portion 303. Here, a display in which three TFTs are arranged for each pixel using the circuit configuration shown in Embodiment Mode 1 and a light emitting element is provided for each pixel will be described.

  FIG. 6 shows a configuration of a pixel portion of the display. In the pixel portion 310, signal lines S1 to Sx, scanning lines G1 to Gy, power supply lines V1 to Vx, and potential control lines W1 to Wy are arranged, and x (x is a natural number) columns y (y is a natural number) rows. Pixels are arranged. Each pixel 311 includes a switching transistor 101, a driving transistor 102, an AC transistor 103, and a light emitting element 104.

  The pixel 311 shown in FIG. 6 corresponds to FIG. 1, and one of the signal lines S1 to Sx, one of the scanning lines G1 to Gy, and one of the power supply lines V1 to Vx. One line V1, one line W1 among potential control lines W1 to Wx, a switching transistor 101, a driving transistor 102, an AC transistor 103, and a light emitting element 104 are included.

  By combining the above structure and the present invention, the lifetime of the light emitting element can be extended, and by using a pixel formed of an N-type transistor, an inexpensive display device and display can be manufactured.

  Note that although the circuit configuration in FIG. 1 described in Embodiment 1 is used in this embodiment, the present invention is not limited to this and can be implemented in combination with other embodiments and examples.

(Embodiment 3)
(Circuit configuration 2)
In this embodiment mode, a configuration different from the circuit configuration in FIG. 1 described in Embodiment Mode 1 will be described.

  7 controls the light emitting element 104, a transistor used as a switching element for controlling input of a video signal to the pixel (switching transistor 101), and a current value flowing through the light emitting element 104. And a transistor (alternating current transistor 103) that applies a reverse bias current to the light emitting element 104 when a reverse voltage is applied to the light emitting element 104. The switching transistor 101, the driving transistor 102, and the AC transistor 103 have the same polarity. As a feature of the present invention, N-type transistors are used as these transistors. Further, although a capacitor is not provided in this embodiment, it may be provided as a capacitor for holding the potential of a video signal.

  As shown in FIG. 7, the gate electrode of the switching transistor 101 is connected to the scanning line G. One of the source electrode and the drain electrode of the switching transistor 101 is connected to the signal line S, and the other is connected to the gate electrode of the driving transistor 102. One of the source electrode and the drain electrode of the driving transistor 102 is connected to the power supply line V, and the other is connected to the pixel electrode of the light emitting element 104.

  In this embodiment mode, one of the source electrode and the drain electrode of the AC transistor 103 is connected to the gate electrode of the driving transistor 102, and the other is connected to the pixel electrode of the light-emitting element 104 and the source of the driving transistor 102. Connected to electrode or drain electrode. The gate electrode of the AC transistor 103 is connected to the potential control line W.

  Further, when the switching transistor 101 is in a non-selected state (off state), the gate potential of the driving transistor 102 is held by the gate capacitance of the driving transistor 102. Note that FIG. 7 illustrates a structure in which a gate potential is held by the gate capacitance of the driving transistor 102 without providing a capacitor element; however, the present invention is not limited to this structure, and a capacitor element may be provided. .

  Here, it can be said that the switching transistor preferably has a configuration with little leakage current (off-state current and gate leakage current). Note that the off-current is a current that flows between the source and the drain when the transistor is off, and the gate leakage current is a current that flows between the gate and the source or drain via the gate insulating film. Current.

  Therefore, the N-channel transistor used for the switching transistor 101 is preferably provided with a low concentration impurity region (also referred to as a lightly doped drain (LDD region)). This is because a transistor having a structure provided with an LDD region can reduce off-state current. In addition, the switching transistor 101 needs to have a large on-current when a current flows through the light-emitting element 104.

  In a more preferable mode, the switching transistor 101 is provided with an LDD region, and the LDD region is provided with a region overlapping with the gate electrode. Then, the switching transistor 101 can increase the on-current and further reduce the generation of hot electrons. Therefore, the reliability of the switching transistor 101 is improved.

  Further, the driving transistor 102 is also provided with an LDD region, and the LDD region overlaps with the gate electrode, whereby reliability is improved.

  The off-state current can also be reduced by reducing the thickness of the gate insulating film. Therefore, the thickness of the switching transistor 101 is preferably smaller than the thickness of the driving transistor 102.

  Further, when the switching transistor 101 has a double gate structure or other multi-gate structure, gate leakage current can be reduced. Further, by adopting a double gate structure or other multi-gate structure in the driving transistor 102, the gate leakage current can be reduced and the reliability can be improved.

  In particular, when an off-state current flows through the switching transistor 101, the gate capacitance of the driving transistor 102 cannot hold the voltage written during the writing period. Therefore, the switching transistor 101 is preferably provided with an LDD region, a thin gate insulating film, or a multi-gate structure to reduce off-state current.

  Next, the operation in the circuit configuration of FIG. 7 will be described with reference to FIG.

  First, in the writing period in FIG. 8A, when the scanning line G is selected, the switching transistor 101 whose gate electrode is connected to the scanning line G is turned on. Then, the potential Vsig of the video signal input to the signal line S is input to the gate electrode of the driving transistor 102 via the switching transistor 101, and the gate potential is held by the gate capacitance of the driving transistor 102.

  Further, since the potential Vss1 of the power supply line V is set to a potential that is the same as or lower than the potential Vss of the counter electrode of the light emitting element 104 (that is, Vss ≧ Vss1 is satisfied), the light emitting element 104 does not emit light. As the potential Vss, for example, GND (ground potential), 0 V, or the like may be applied. Further, a reverse bias current flows through the light emitting element 104 due to the potential difference between Vss1 and Vss that is set. (However, it does not flow when Vss1 and Vss are at the same potential.)

  On the other hand, in this writing period, the potential Vss2 of the potential control line W is set low so that the AC transistor 103 is turned off.

  Note that the case where the driving transistor 102 is turned on by the potential Vsig of the video signal in the writing period has been described; however, the current to the light-emitting element 104 is also applied when the driving transistor 102 is turned off by the potential Vsig of the video signal. Therefore, the light emitting element 104 does not emit light.

  Next, in the display period of FIG. 8B, the switching transistor 101 is turned off by controlling the potential of the scanning line G. In addition, since the potential Vsig of the video signal written in the writing period is held by the gate capacitance of the driving transistor 102, the driving transistor 102 is turned on.

  In addition, since the potential Vdd1 of the power supply line V is set to a potential higher than the potential Vss of the counter electrode of the light emitting element 104 (that is, Vdd1> Vss is satisfied), a forward bias current flows to the light emitting element 104 and light emission occurs. The element 104 emits light.

  On the other hand, as in the writing period, the potential Vss2 of the potential control line W is set low so that the AC transistor 103 is turned off.

  In the writing period, the case where the driving transistor 102 is turned on by the potential Vsig of the video signal has been described; however, when the driving transistor 102 is turned off by the potential Vsig of the video signal, the current to the light-emitting element 104 is Therefore, no current is supplied to the light-emitting element 104 even during the display period.

  Next, in the reverse bias period (non-lighting period) in FIG. 8C, the switching transistor 101 is turned off by controlling the potential of the scanning line G.

  Further, the potential Vss3 of the power supply line V is set lower than the potential Vss of the counter electrode of the light emitting element 104. That is, by setting the potential to satisfy Vss> Vss3, when the driving transistor 102 is turned on, the electrode of the driving transistor 102 connected to the power supply line V becomes a source electrode, and the pixel of the light emitting element 104 The electrode of the driving transistor 102 connected to the electrode serves as a drain electrode.

  Note that in order to make the current value of the reverse bias current in the reverse bias period larger than the current value of the forward bias current in the display period, the potential difference between Vss3 and Vss is larger than the potential difference between Vdd1 and Vss in the display period. It should be larger. Accordingly, the current value of the reverse bias current can be increased, and a large current can flow through the light emitting element 104 during the reverse bias period.

  Further, the potential Vdd2 of the potential control line W is set high so that the AC transistor 103 is turned on. Accordingly, the gate electrode and the drain electrode of the driving transistor 102 have the same potential, and the driving transistor 102 is turned on. Therefore, a reverse bias current flows through the driving transistor 102, and a reverse bias current also flows through the light emitting element 104. That is, a reverse voltage is applied to the light emitting element 104.

  Note that although the potential of the counter electrode of the light-emitting element 104 is a fixed potential in this embodiment mode, the present invention is not limited to this. For example, the potential of the counter electrode of the light emitting element 104 may be changed, or both the potential of the power supply line V and the potential of the counter electrode of the light emitting element 104 may be changed.

  Next, a method of driving by the digital time gray scale method using the pixel shown in FIG. 7 will be described with reference to a timing chart of FIG.

As shown in FIG. 9, one frame period F1 includes four subframe periods SF1, SF2, SF3, SF4 including a writing period Ta1, Ta2, Ta3, Ta4 and a display period Ts1, Ts2, Ts3, Ts4, and a reverse direction. It is time-divided into a bias period (non-lighting period) BF. A light emitting element to which a signal for emitting light is given is in a light emitting state during a display period. The ratio of the length of the display period in each subframe period is as follows: first subframe period Ta1: second subframe period Ta2: third subframe period Ta3: fourth subframe period Ta4 = 2 ³ : 2 ² : 2 ¹ : 2 ⁰ = 8: 4: 2: 1 As a result, 4-bit gradation can be expressed. However, the number of bits and the number of gradations are not limited to those described here. For example, eight subframe periods may be provided to enable 8-bit gradation.

  The writing period and the display period of the above operation are repeated for all the subframe periods SF1 to SF4, and a period for applying a reverse voltage (reverse bias period BF) is provided to complete one frame period F1. Here, the lengths of the display periods Ts1 to Ts4 of the subframe periods SF1 to SF4 are set as appropriate, and the gray scale is determined by the total display period of the subframe periods SF1 to SF4 in which the light emitting element 104 emits light per frame period F1. Express. That is, the gradation is expressed by the total lighting time in one frame period F1.

  Note that the subframe periods SF1 to SF4 may be arranged without being consecutive in one frame. Further, one subframe period may be composed of a plurality of subframe periods, or the plurality of subframe periods may be arranged without being consecutive in one frame. Note that in the case of expressing gradation using the time gradation method, the number of subframes is not particularly limited. Further, the length of the lighting period of each subframe period and which subframe is lit, that is, the selection method of the subframe is not particularly limited.

  Further, as shown in FIG. 23, in each subframe period SF1 to SF4 in one frame period F1, an operation of applying a reverse voltage simultaneously with each writing period Ta1 to Ta4 may be performed. That is, in FIG. 23, the writing periods Ta1 to Ta4 are also reverse bias periods in which an operation of applying a reverse voltage is performed simultaneously with the writing operation. FIG. 23 shows an example in which gradation is expressed using a 4-bit digital video signal.

  When the pixel of FIG. 7 is driven in an analog manner, as shown in FIG. 10, a period in which a voltage having a forward polarity is applied to the light emitting element in one frame period F1, that is, a forward bias period FF and a reverse direction. It is sufficient to provide a period for applying a voltage having the polarity, that is, a reverse bias period BF. Note that the forward bias period FF is time-divided into a writing period Ta and a display period Ts, and an analog video signal may be written to each pixel in the forward bias period FF so that the light emitting element 104 emits light or does not emit light.

  As described above, in the structure of the present invention, when a reverse voltage is applied, a current sufficient to insulate a short-circuited portion can be passed, and the lifetime of the light-emitting element can be extended. In addition, since the circuit configuration can be constituted by a unipolar transistor, it can be manufactured at low cost.

  In addition, an amorphous silicon transistor can be used by manufacturing a transistor having a circuit structure as an N-type transistor. Therefore, since a transistor manufacturing technique using amorphous silicon that has already been established can be applied, a display device with favorable and stable operation characteristics can be obtained with a simple and inexpensive manufacturing process.

(Embodiment 4)
(Circuit configuration 3)
In this embodiment mode, a configuration different from the circuit configuration in FIG. 1 described in Embodiment Mode 1 will be described.

  A circuit included in the pixel illustrated in FIG. 11 includes a light-emitting element 104 and a transistor used as a switching element for controlling input of a video signal to the pixel (a first switching transistor 105 and a second switching transistor 106). A transistor for controlling the current value flowing through the light emitting element 104 (driving transistor 102), and a transistor for supplying a reverse bias current to the light emitting element 104 when applying a reverse voltage to the light emitting element 104 (AC transistor) 103). In this embodiment, the capacitor 112 having two electrodes is provided to hold the potential of the video signal. However, the gate potential of the driving transistor 102 is set using the gate capacitance of the driving transistor 102 or the like. If it can be held, the capacitor 112 may be omitted. The first switching transistor 105, the second switching transistor 106, the driving transistor 102, and the AC transistor 103 have the same polarity. As a feature of the present invention, N-type transistors are used as these transistors. To do.

  As shown in FIG. 11, the gate electrode of the first switching transistor 105 is connected to the second scanning line GL2, and one of the source electrode and the drain electrode of the first switching transistor 105 is connected to the signal line S. The other is connected to the source electrode or drain electrode of the driving transistor 102. The gate electrode of the second switching transistor 106 is connected to the first scanning line GL1, and one of the source electrode and the drain electrode of the second switching transistor 106 is for the power supply line V and the other is for driving. The gate electrode of the transistor 102 and the capacitor 112 are connected. The signal line S is connected to the current source 113.

  Further, one of the source electrode and the drain electrode of the driving transistor 102 is connected to the power supply line V, and the other is connected to the pixel electrode of the light emitting element 104 and the capacitor 112. One of the two electrodes of the capacitor 112 is connected to the gate electrode of the driving transistor 102 and the other is connected to the source electrode or the drain electrode of the driving transistor 102 connected to the pixel electrode of the light emitting element 104. . Note that the driving transistor 102 is set to operate in a saturation region.

  In this embodiment mode, one of the source electrode and the drain electrode of the AC transistor 103 is connected to the power supply line V and the other is connected to the pixel electrode of the light-emitting element 104. The gate electrode of the AC transistor 103 is connected to the source electrode or the drain electrode of the AC transistor 103 connected to the pixel electrode of the light emitting element 104.

  In addition, when the first switching transistor 105 and the second switching transistor 106 are in a non-selected state (off state), the capacitor 112 is provided to hold a potential difference between the electrodes of the capacitor 112. Yes. Note that although the capacitor 112 is provided in FIG. 11, the present invention is not limited to this structure when the gate potential can be held by the gate capacitance of the driving transistor 102, and the capacitor 112 is omitted. Also good.

  Further, in this embodiment, the ratio L / W between the channel length L and the channel width W of the driving transistor 102 is set larger than that of the AC transistor 103. Specifically, in the driving transistor 102, L is set larger than W, and more desirably 5/1 or more. Further, in the AC transistor 103, L is equal to or shorter than W. Accordingly, the current value flowing in the reverse direction when a reverse voltage is applied to the light emitting element 104 is made larger than the current value flowing in the forward direction when a forward voltage is applied to the light emitting element 104 in the pixel. Can do.

  Here, it can be said that the first switching transistor 105 and the second switching transistor 106 are preferably configured to have a small leakage current (off-state current and gate leakage current). Note that the off-current is a current that flows between the source and the drain when the transistor is off, and the gate leakage current is a current that flows between the gate and the source or drain via the gate insulating film. Current.

  Therefore, the n-channel transistor used for the first switching transistor 105 and the second switching transistor 106 is preferably provided with a low-concentration impurity region (also referred to as a lightly doped drain (LDD region)). . This is because a transistor having a structure provided with an LDD region can reduce off-state current. In addition, the first switching transistor 105 and the second switching transistor 106 need to increase the on-state current when a current flows through the light-emitting element 104.

  In a more preferable mode, LDD regions are provided in the first switching transistor 105 and the second switching transistor 106, and the LDD region is provided with a region overlapping with the gate electrode. Then, the first switching transistor 105 and the second switching transistor 106 can increase the on-current and further reduce the generation of hot electrons. Therefore, the reliability of the first switching transistor 105 and the second switching transistor 106 is improved.

  Further, the driving transistor 102 is also provided with an LDD region, and the LDD region overlaps with the gate electrode, whereby reliability is improved.

  The off-state current can also be reduced by reducing the thickness of the gate insulating film. Therefore, the film thickness of the first switching transistor 105 and the second switching transistor 106 may be smaller than the film thickness of the driving transistor 102.

  Further, gate leakage current can be reduced by using the first switching transistor 105 and the second switching transistor 106 as transistors having a double gate structure or other multi-gate structures. Further, by adopting a double gate structure or other multi-gate structure in the driving transistor 102, the gate leakage current can be reduced and the reliability can be improved.

  In particular, when an off-state current flows through the second switching transistor 106, the capacitor 112 cannot hold the voltage written in the writing period. Therefore, the off-state current can be reduced by providing the second switching transistor 106 with an LDD region, a thin gate insulating film, or a multi-gate structure.

  Next, the operation in the circuit configuration of FIG. 11 will be described with reference to FIG.

  First, in the writing period of FIG. 12A, when the first scanning line GL1 and the second scanning line GL2 are selected, the first switching transistor whose gate electrode is connected to the second scanning line GL2. 105, and the second switching transistor 106 whose gate electrode is connected to the first scanning line GL1 is turned on. At this time, a predetermined gradation current Idata necessary for causing the light emitting element 104 to emit light with a predetermined luminance gradation is supplied from the current source 113 to the signal line S. Here, the current source 113 has a potential lower than the potential Vss of the counter electrode of the light emitting element 104 and the potential Vss1 of the power supply line V as the gradation potential Vdata for supplying the gradation current Idata to the signal line S (that is, Vss). , Vss1> Vdata). For example, GND (ground potential), 0 V, or the like may be applied as the potential Vss.

  In addition, the potential Vss1 of the power supply line V is set to be equal to or lower than the potential Vss of the counter electrode of the light emitting element 104 (that is, Vss ≧ Vss1), and the second switching transistor 106 is used. The potential Vss1 of the power supply line V is input to the capacitor 112 and the gate electrode of the driving transistor 102. Accordingly, electric charge is accumulated in the capacitor 112, and when the capacitor 112 is charged, a voltage component (holding voltage) is held, and the driving transistor 102 is turned on. Further, the electrode of the driving transistor 102 connected to the power supply line V serves as a drain electrode, and the other electrode serves as a source electrode. Accordingly, the write current Idt based on the gradation current Idata is supplied through the driving transistor 102.

  As described above, Idt flows as the drain currents of the driving transistor 102 and the first switching transistor 105 based on the gradation current Idata set by the current source 113, and corresponds to the potential difference between the two electrodes in the capacitor 112. Charge is accumulated, and the voltage component (holding voltage) is held. Note that at this time, the write current Idt flows based on the grayscale potential Vdata lower than the potential Vss of the counter electrode of the light-emitting element 104, so that the potential of the node N1 is lowered. Bias current flows. Therefore, the light-emitting element 104 does not emit light during the writing period.

  Further, in this writing period, the potential of the node N1 is lowered by the writing current Idt, so that the potential Vss1 of the power supply line V becomes higher than the potential applied to the node N1. Therefore, the electrode of the AC transistor 103 connected to the power supply line V is a drain electrode, and the other electrode is a source electrode. Therefore, since the source electrode and the gate electrode of the AC transistor 103 are connected, the AC transistor 103 is turned off.

  Note that the case where the driving transistor 102 is turned on by the grayscale potential Vdata in the writing period has been described; however, the case where the driving transistor 102 is turned off by the grayscale potential Vdata is also a forward direction to the light-emitting element 104. Since the bias current is not supplied, the light emitting element 104 does not emit light.

  Next, in the display period in FIG. 12B, the first switching transistor 105 and the second switching transistor 106 are turned off by controlling the potentials of the first scan line GL1 and the second scan line GL2. Since the charge (holding voltage) accumulated in the writing period, that is, the potential difference between both electrodes of the capacitor 112 is held, the driving transistor 102 is turned on. Further, since the potential Vdd1 of the power supply line V is set to a potential higher than the potential Vss of the counter electrode of the light emitting element 104 (Vdd1> Vss), a forward bias current flows to the light emitting element 104, and the light emitting element 104 emits light. To do.

  On the other hand, since the potential Vdd1 of the power supply line V is set higher than the potential Vss of the counter electrode of the light emitting element 104, the electrode of the AC transistor 103 connected to the power supply line V serves as a drain electrode, and the other electrode serves as a source. It becomes an electrode. Therefore, since the source electrode and the gate electrode of the AC transistor 103 are connected, the AC transistor 103 is turned off.

  Although the case where the driving transistor 102 is turned on by the grayscale potential Vdata in the writing period has been described, when the driving transistor 102 is turned off by the grayscale potential Vdata, the forward direction to the light emitting element 104 is increased. Since no bias current is supplied, no current is supplied to the light-emitting element 104 even during the display period.

  Next, in the reverse bias period (non-lighting period) in FIG. 12C, the first switching transistor 105 and the second switching transistor 105 are controlled by controlling the potentials of the first scanning line GL1 and the second scanning line GL2. The switching transistor 106 is turned off.

  Further, by setting the potential Vss2 of the power supply line V to a potential lower than the potential Vss of the counter electrode of the light emitting element 104 (that is, Vss> Vss2), the electrode of the AC transistor 103 connected to the power supply line V is the source. The other electrode is the drain electrode. Accordingly, since the drain electrode and the gate electrode of the AC transistor 103 are connected, the AC transistor 103 is turned on. Accordingly, a reverse voltage is applied to the light emitting element 104, and a reverse bias current flows in the light emitting element 104 and the AC transistor 103.

  Note that in the case where the driving transistor 102 is turned on in the writing period and the display period, the potential difference between both electrodes of the capacitor 112 is held based on the writing current Idt even in the reverse bias period, so that driving is performed. The transistor is turned on. As a result, a reverse bias current flows through the driving transistor 102. However, as described above, the current flowing in the driving transistor 102 is made larger than the current value flowing in the AC transistor 103 by making the L / W of the driving transistor 102 larger than the L / W of the AC transistor 103. The value becomes smaller. Needless to say, current is not supplied to the driving transistor 102 when the driving transistor 102 is turned off in the writing period and the display period.

  Further, the potential difference between Vss2 and Vss in the reverse bias period may be larger than the potential difference between Vdd1 and Vss in the display period. As a result, the current value of the reverse bias current becomes larger than the current value of the forward bias current, and a larger current can further flow through the light emitting element 104 during the reverse bias period.

  In addition to the above circuit configuration, the second scanning line GL2 may not be provided, and the gate electrodes of the first switching transistor 105 and the second switching transistor 106 may be connected to the scanning line G. FIG. 13 shows the configuration. By configuring the single scanning line G, the number of wirings can be reduced and the aperture ratio of the pixel can be increased. The operation is the same as the operation of the first scanning line GL1 and the second scanning line GL2 in the operation of the above-described circuit configuration except that the operation is performed on the scanning line G, and is therefore omitted here.

  Next, a gray scale method of driving by an analog time gray scale method using the pixel shown in FIG. 11 will be described with reference to a timing chart of FIG.

  As shown in FIG. 14A, during one frame period F1, a period in which a forward polarity voltage is applied to the light emitting element, that is, a forward bias period FF, and a period in which a reverse polarity voltage is applied, A reverse bias period BF is provided. Note that the forward bias period FF is time-divided into a writing period Ta and a display period Ts, and an analog video signal may be written to each pixel in the forward bias period FF so that the light emitting element 104 emits light or does not emit light.

  FIG. 14B shows a timing chart in an arbitrary row (i-th row).

  In the signal writing period Ta (i) to the pixel, the potential of the analog signal, that is, the gradation potential Vdata is set in the current source 113 connected to the signal line S. This gradation potential Vdata corresponds to a video signal. When a video signal is written to the pixel, a high-level potential is applied to the first scan line GL1 and the second scan line GL2, and the second switching transistor 106 and the first switching transistor 105 are connected. Turn it on. Further, the low-level potential Vss1 is applied to the potential of the power supply line V. Here, the potential Vss1 of the power supply line V is set to be equal to or lower than the potential Vss of the counter electrode of the light emitting element 104 (that is, Vss ≧ Vss1).

  Next, in the display period Ts (i), a low-level potential is applied to the first scanning line GL1 and the second scanning line GL2, and a high-level potential Vdd1 is applied to the potential of the power supply line V. . Here, the potential Vdd1 of the power supply line V is set to be higher than the potential Vss of the counter electrode of the light emitting element 104 (that is, Vdd1> Vss), and the light emitting element 104 emits light.

  In the reverse bias period BF, the low-level potential is maintained in the first scanning line GL1 and the second scanning line GL2, and the low-level potential Vss2 is applied to the power supply line V. Here, the potential Vss2 of the power supply line V is set to a potential lower than the potential Vss of the counter electrode of the light emitting element 104 (that is, Vss> Vss2). By providing such a reverse bias period, a voltage in the reverse direction is applied to the light emitting element, thereby suppressing initial failure and progressive failure of the light emitting element and preventing reduction in luminance due to degradation of the electroluminescent layer. it can.

  When the pixel of FIG. 11 is driven by the digital time gray scale method, as shown in FIG. 15, one frame period F1 includes writing periods Ta1, Ta2, Ta3, Ta4 and display periods Ts1, Ts2, Ts3, Ts4. It is time-divided into four subframe periods SF1, SF2, SF3, SF4 and a reverse bias period (non-lighting period) BF. In the writing period, the light-emitting element to which a signal for emitting light is given is in a light-emitting state in the display period. After the writing period and the display period are alternately performed, the reverse bias period is performed.

  In this embodiment, 4-bit gradation is expressed, but the number of bits and the number of gradations are not limited to those described here. For example, eight subframe periods are provided so that 8-bit gradation can be performed. May be. Furthermore, one subframe period may be further composed of a plurality of subframe periods, and they may be arranged without being continuous in one frame. Note that in the case of expressing gradation using the time gradation method, the number of subframes is not particularly limited. Further, the length of the lighting period of each subframe period and which subframe is lit, that is, the selection method of the subframe is not particularly limited.

  As described above, when a reverse voltage is applied, a current sufficient to insulate a short-circuited portion can be supplied, and the life of the light-emitting element can be extended. In addition, since the circuit configuration can be constituted by a unipolar transistor, it can be manufactured at low cost.

  In addition, an amorphous silicon transistor can be used by manufacturing a transistor having a circuit structure as an N-type transistor. Therefore, since a transistor manufacturing technique using amorphous silicon that has already been established can be applied, a display device with favorable and stable operation characteristics can be obtained with a simple and inexpensive manufacturing process.

(Embodiment 5)
(Circuit configuration 4)
In this embodiment mode, a configuration different from the circuit configuration in FIG. 1 described in Embodiment Mode 1 will be described.

  16 includes a light-emitting element 104 and transistors used as switching elements for controlling input of video signals to the pixel (first switching transistor 105 and second switching transistor 106). A transistor for controlling the current value flowing through the light emitting element 104 (driving transistor 102), and a transistor for supplying a reverse bias current to the light emitting element 104 when applying a reverse voltage to the light emitting element 104 (AC transistor) 103). In this embodiment, the capacitor 112 having two electrodes is provided to hold the potential of the video signal. However, the gate potential of the driving transistor 102 is set using the gate capacitance of the driving transistor 102 or the like. If it can be held, the capacitor 112 may be omitted. The first switching transistor 105, the second switching transistor 106, the driving transistor 102, and the AC transistor 103 have the same polarity. As a feature of the present invention, N-type transistors are used as these transistors. To do.

  As shown in FIG. 16, the gate electrode of the first switching transistor 105 is connected to the second scanning line GL2, and one of the source electrode or the drain electrode of the first switching transistor 105 is connected to the signal line S, The other is connected to the source electrode or drain electrode of the driving transistor 102. The gate electrode of the second switching transistor 106 is connected to the first scanning line GL1, and one of the source electrode and the drain electrode of the second switching transistor 106 is for the power supply line V and the other is for driving. The gate electrode of the transistor 102 and the capacitor 112 are connected. The signal line S is connected to the current source 113.

  Further, one of the source electrode and the drain electrode of the driving transistor 102 is connected to the power supply line V, and the other is connected to the pixel electrode of the light emitting element 104 and the capacitor 112. One of the two electrodes of the capacitor 112 is connected to the gate electrode of the driving transistor 102 and the other is connected to the source electrode or the drain electrode of the driving transistor 102 connected to the pixel electrode of the light emitting element 104. . Note that the driving transistor 102 is set to operate in a saturation region.

  In this embodiment mode, one of the source electrode and the drain electrode of the AC transistor 103 is connected to the pixel electrode of the light-emitting element 104 and the other is connected to the potential control line W. The gate electrode of the AC transistor 103 is connected to the source electrode or drain electrode of the AC transistor 103 connected to the potential control line W.

  In addition, when the first switching transistor 105 and the second switching transistor 106 are in a non-selected state (off state), the capacitor 112 is provided to hold a potential difference between the electrodes of the capacitor 112. Yes. 16A and 16B, the capacitor 112 is provided; however, in the case where the gate potential can be held by the gate capacitance of the driving transistor 102, the present invention is not limited to this structure, and the capacitor is omitted. good.

  Further, in this embodiment, the ratio L / W between the channel length L and the channel width W of the driving transistor 102 is set larger than that of the AC transistor 103. Specifically, in the driving transistor 102, L is set larger than W, and more desirably 5/1 or more. Further, in the AC transistor 103, L is equal to or shorter than W. Accordingly, the current value flowing in the reverse direction when a reverse voltage is applied to the light emitting element 104 is made larger than the current value flowing in the forward direction when a forward voltage is applied to the light emitting element 104 in the pixel. Can do.

  Here, it can be said that the first switching transistor 105 and the second switching transistor 106 are preferably configured to have a small leakage current (off-state current and gate leakage current). Note that the off-current is a current that flows between the source and the drain when the transistor is off, and the gate leakage current is a current that flows between the gate and the source or drain via the gate insulating film. Current.

  Therefore, the n-channel transistor used for the first switching transistor 105 and the second switching transistor 106 is preferably provided with a low-concentration impurity region (also referred to as a lightly doped drain (LDD region)). . This is because a transistor having a structure provided with an LDD region can reduce off-state current. In addition, the first switching transistor 105 and the second switching transistor 106 need to increase the on-state current when a current flows through the light-emitting element 104.

  In a more preferable mode, LDD regions are provided in the first switching transistor 105 and the second switching transistor 106, and the LDD region is provided with a region overlapping with the gate electrode. Then, the first switching transistor 105 and the second switching transistor 106 can increase the on-current and further reduce the generation of hot electrons. Therefore, the reliability of the first switching transistor 105 and the second switching transistor 106 is improved.

  Further, the driving transistor 102 is also provided with an LDD region, and the LDD region overlaps with the gate electrode, whereby reliability is improved.

  The off-state current can also be reduced by reducing the thickness of the gate insulating film. Therefore, the film thickness of the first switching transistor 105 and the second switching transistor 106 may be smaller than the film thickness of the driving transistor 102.

  Further, gate leakage current can be reduced by using the first switching transistor 105 and the second switching transistor 106 as transistors having a double gate structure or other multi-gate structures. Further, by adopting a double gate structure or other multi-gate structure in the driving transistor 102, the gate leakage current can be reduced and the reliability can be improved.

  In particular, when an off-state current flows through the second switching transistor 106, the capacitor 112 cannot hold the voltage written in the writing period. Therefore, the off-state current can be reduced by providing the second switching transistor 106 with an LDD region, a thin gate insulating film, or a multi-gate structure.

  Next, the operation in the circuit configuration of FIG. 16 will be described with reference to FIG.

  First, in the writing period of FIG. 17A, when the first scan line GL1 and the second scan line GL2 are selected, the first switching transistor whose gate electrode is connected to the second scan line GL2. 105 and the second switching transistor 106 whose gate electrode is connected to the first scanning line GL1 are turned on. At this time, a predetermined gradation current Idata necessary for causing the light emitting element 104 to emit light with a predetermined luminance gradation is supplied from the current source 113 to the signal line S. Here, the current source 113 has a potential lower than the potential Vss of the counter electrode of the light emitting element 104 and the potential Vss1 of the power supply line V as the gradation potential Vdata for supplying the gradation current Idata to the signal line S (that is, Vss). , Vss1> Vdata). For example, GND (ground potential), 0 V, or the like may be applied as the potential Vss.

  In addition, the potential Vss1 of the power supply line V is set to be equal to or lower than the potential Vss of the counter electrode of the light emitting element 104 (that is, Vss ≧ Vss1), and the second switching transistor 106 is used. The potential Vss1 of the power supply line V is input to the capacitor 112 and the gate electrode of the driving transistor 102. Accordingly, electric charge is accumulated in the capacitor 112, and when the capacitor 112 is charged, a voltage component (holding voltage) is held, and the driving transistor 102 is turned on. Further, the electrode of the driving transistor 102 connected to the power supply line V serves as a drain electrode, and the other electrode serves as a source electrode. Accordingly, the write current Idt based on the gradation current Idata is supplied through the driving transistor 102.

  Thus, Idt flows as the drain current of the driving transistor 102 and the first switching transistor 105 due to the gradation current Idata set by the current source 113, and the charge corresponding to the potential difference between the two electrodes is passed through the capacitor 112. Are stored, and the voltage component (holding voltage) is held. Note that at this time, the write current Idt flows based on the grayscale potential Vdata lower than the potential Vss of the counter electrode of the light-emitting element 104, so that the potential of the node N1 is lowered. Bias current flows. Therefore, the light-emitting element 104 does not emit light during the writing period.

  On the other hand, in this writing period, the potential Vdd3 of the potential control line W is set to be higher than the potential Vss of the counter electrode of the light emitting element 104 (that is, Vdd3> Vss). Therefore, the electrode of the AC transistor 103 connected to the potential control line W is a drain electrode, and the other electrode is a source electrode. Therefore, since the source electrode and the gate electrode of the AC transistor 103 are connected, the AC transistor 103 is turned off.

Note that the case where the driving transistor 102 is turned on by the grayscale potential Vdata in the writing period has been described; however, the case where the driving transistor 102 is turned off by the grayscale potential Vdata is also a forward direction to the light-emitting element 104. Since the bias current is not supplied, the light emitting element 104 does not emit light.

  Next, in the display period in FIG. 17B, the first switching transistor 105 and the second switching transistor 106 are turned off by controlling the potentials of the first scan line GL1 and the second scan line GL2. Since the charge (holding voltage) accumulated in the writing period, that is, the potential difference between both electrodes of the capacitor 112 is held, the driving transistor 102 is turned on. Further, since the potential Vdd1 of the power supply line V is set to a potential higher than the potential Vss of the counter electrode of the light emitting element 104 (Vdd1> Vss), a forward bias current flows to the light emitting element 104, and the light emitting element 104 emits light. To do.

  On the other hand, as in the writing period, the potential Vdd3 of the potential control line W is set to be higher than the potential Vss of the counter electrode of the light emitting element 104. Therefore, the electrode of the AC transistor 103 connected to the potential control line W is a drain electrode, and the other electrode is a source electrode. Therefore, since the source electrode and the gate electrode of the AC transistor 103 are connected, the AC transistor 103 is turned off.

  Although the case where the driving transistor 102 is turned on by the grayscale potential Vdata in the writing period has been described, when the driving transistor 102 is turned off by the grayscale potential Vdata, the forward direction to the light emitting element 104 is increased. Since no bias current is supplied, no current is supplied to the light-emitting element 104 even during the display period.

  Next, in the reverse bias period (non-lighting period) in FIG. 17C, the first switching transistor 105 and the second switching transistor 105 are controlled by controlling the potentials of the first scanning line GL1 and the second scanning line GL2. The switching transistor 106 is turned off.

  Further, by setting the potential Vss3 of the potential control line W to a potential lower than the potential Vss of the counter electrode of the light emitting element 104 (that is, Vss> Vss3), the electrode of the AC transistor 103 connected to the potential control line W Becomes a source electrode, and the other electrode becomes a drain electrode. Accordingly, since the drain electrode and the gate electrode of the AC transistor 103 are connected, the AC transistor 103 is turned on. Accordingly, a reverse voltage is applied to the light emitting element 104, and a reverse bias current flows in the light emitting element 104 and the AC transistor 103.

  On the other hand, the potential Vss2 of the power supply line V is set to be equal to or lower than the potential Vss of the counter electrode of the light emitting element 104 (that is, Vss ≧ Vss2). In addition, when the driving transistor 102 is turned on in the writing period and the display period, the potential difference between both electrodes of the capacitor 112 is held based on the writing current Idt even in the reverse bias period. The transistor is turned on.

  As a result, a reverse bias current flows through the driving transistor 102 by the potential set to the potential Vss2 of the power supply line V. (It does not flow when the potential Vss2 to be set is the same as Vss). However, as described above, the current flowing in the driving transistor 102 is made larger than the current value flowing in the AC transistor 103 by making the L / W of the driving transistor 102 larger than the L / W of the AC transistor 103. The value becomes smaller. Needless to say, current is not supplied to the driving transistor 102 when the driving transistor 102 is turned off in the writing period and the display period.

  In addition, the potential difference between the potential Vss3 of the potential control line W and the potential Vss of the counter electrode of the light emitting element 104 in the reverse bias period is expressed as the potential Vdd1 of the power supply line V and the potential Vss of the counter electrode of the light emitting element 104 in the display period. It may be larger than the potential difference. As a result, the current value of the reverse bias current becomes larger than the current value of the forward bias current, and a larger current can further flow through the light emitting element 104 during the reverse bias period.

  In addition to the above circuit configuration, the second scanning line GL2 may not be provided, and the gate electrodes of the first switching transistor 105 and the second switching transistor 106 may be connected to the scanning line G. FIG. 18 shows the configuration. By configuring the single scanning line G, the number of wirings can be reduced and the aperture ratio of the pixel can be increased. The operation is the same as the operation of the first scanning line GL1 and the second scanning line GL2 in the operation of the above-described circuit configuration except that the operation is performed on the scanning line G, and is therefore omitted here.

  Next, a gray scale method of driving by the analog time gray scale method using the pixel shown in FIG. 16 will be described with reference to a timing chart of FIG.

  As shown in FIG. 19A, a period in which a forward polarity voltage is applied to the light emitting element in one frame period F1, that is, a forward bias period FF, and a period in which a reverse polarity voltage is applied, A reverse bias period BF is provided. Note that the forward bias period FF is time-divided into a writing period Ta and a display period Ts, and an analog video signal may be written to each pixel in the forward bias period FF so that the light emitting element 104 emits light or does not emit light.

  FIG. 19B shows a timing chart in an arbitrary row (i-th row).

  In the signal writing period Ta (i) to the pixel, the potential of the analog signal, that is, the gradation potential Vdata is set in the current source 113 connected to the signal line S. This gradation potential Vdata corresponds to a video signal. When a video signal is written to the pixel, a high-level potential is applied to the first scan line GL1 and the second scan line GL2, and the second switching transistor 106 and the first switching transistor 105 are connected. Turn it on. Further, the low-level potential Vss1 is applied to the potential of the power supply line V, and the high-level potential Vdd3 is applied to the potential of the potential control line W. Here, the potential Vss1 of the power supply line V is set to be equal to or lower than the potential Vss of the counter electrode of the light emitting element 104 (that is, Vss ≧ Vss1). Further, the potential Vdd3 of the potential control line W is set to a potential higher than the potential Vss of the counter electrode of the light emitting element 104 (that is, Vdd3> Vss).

  Next, in the display period Ts (i), a low-level potential is applied to the first scanning line GL1 and the second scanning line GL2, and a high-level potential Vdd1 is applied to the potential of the power supply line V. . Further, the potential of the potential control line W is maintained at the high level potential Vdd3. Here, the potential Vdd1 of the power supply line V is set to be higher than the potential Vss of the counter electrode of the light emitting element 104 (that is, Vdd1> Vss), and the light emitting element 104 emits light. Further, the potential Vdd3 of the potential control line W is set to a potential higher than the potential Vss of the counter electrode of the light emitting element 104 (that is, Vdd3> Vss).

  In the reverse bias period BF, the low-level potential is maintained in the first scanning line GL1 and the second scanning line GL2, the low-level potential Vss2 is applied to the power supply line V, and the potential control line W A low level potential Vss3 is applied to the potential. Here, the potential Vss2 of the power supply line V is set to be equal to or lower than the potential Vss of the counter electrode of the light emitting element 104 (that is, Vss ≧ Vss2). The potential Vss3 of the potential control line W is set to a potential lower than the potential Vss of the counter electrode of the light emitting element 104 (that is, Vss> Vss3). By providing such a reverse bias period, a voltage in the reverse direction is applied to the light emitting element, thereby suppressing initial failure and progressive failure of the light emitting element and preventing reduction in luminance due to degradation of the electroluminescent layer. it can.

  Note that in the potential of the power supply line V, the potential Vss1 in the writing period and the potential Vss2 in the reverse bias period are the same as or lower than the potential Vss of the counter electrode of the light-emitting element 104, or different potentials. It is good.

  When the pixel of FIG. 16 is driven by the digital time gray scale method, as shown in FIG. 20, one frame period F1 includes writing periods Ta1, Ta2, Ta3, Ta4 and display periods Ts1, Ts2, Ts3, Ts4. It is time-divided into four subframe periods SF1, SF2, SF3, SF4 and a reverse bias period (non-lighting period) BF. In the writing period, the light-emitting element to which a signal for emitting light is given is in a light-emitting state in the display period. After the writing period and the display period are alternately performed, the reverse bias period is performed.

  In this embodiment, 4-bit gradation is expressed, but the number of bits and the number of gradations are not limited to those described here. For example, eight subframe periods are provided so that 8-bit gradation can be performed. May be. Furthermore, one subframe period may be further composed of a plurality of subframe periods, and they may be arranged without being continuous in one frame. Note that in the case of expressing gradation using the time gradation method, the number of subframes is not particularly limited. Further, the length of the lighting period of each subframe period and which subframe is lit, that is, the selection method of the subframe is not particularly limited.

  As described above, in the structure of the present invention, when a reverse voltage is applied, a current sufficient to insulate a short-circuited portion can be passed, and the lifetime of the light-emitting element can be extended. In addition, since the circuit configuration can be constituted by a unipolar transistor, it can be manufactured at low cost.

  In addition, an amorphous silicon transistor can be used by manufacturing a transistor having a circuit structure as an N-type transistor. Therefore, since a transistor manufacturing technique using amorphous silicon that has already been established can be applied, a display device with favorable and stable operation characteristics can be obtained with a simple and inexpensive manufacturing process.

(Embodiment 6)
(Circuit configuration 5)
In this embodiment mode, a configuration different from the circuit configuration in FIG. 1 described in Embodiment Mode 1 will be described.

  A circuit included in the pixel illustrated in FIG. 21 controls the light-emitting element 104, a transistor used as a switching element for controlling input of a video signal to the pixel (switching transistor 101), and a current value flowing through the light-emitting element 104. And a transistor (alternating current transistor 103) that applies a reverse bias current to the light emitting element 104 when a reverse voltage is applied to the light emitting element 104. The switching transistor 101, the driving transistor 102, and the AC transistor 103 have the same polarity. As a feature of the present invention, N-type transistors are used as these transistors. Further, although a capacitor is not provided in this embodiment, it may be provided as a capacitor for holding the potential of a video signal.

  As shown in FIG. 21, the gate electrode of the switching transistor 101 is connected to the scanning line G. One of the source electrode and the drain electrode of the switching transistor 101 is connected to the signal line S, and the other is connected to the gate electrode of the driving transistor 102. One of the source electrode and the drain electrode of the driving transistor 102 is connected to the power supply line V, and the other is connected to the pixel electrode of the light emitting element 104.

  In this embodiment mode, one of the source electrode and the drain electrode of the AC transistor 103 is connected to the power supply line V and the other is connected to the pixel electrode of the light-emitting element 104. The gate electrode of the AC transistor 103 is connected to the wiring 110.

  Note that in this embodiment, operation in the case where the wiring 110 and the counter electrode of the light-emitting element 104 are connected is described. By connecting the wiring 110 and the counter electrode of the light-emitting element 104, power consumption can be reduced. In addition, when the counter electrode of the light-emitting element 104 and the wiring 110 are in contact with each other, the wiring 110 functions as an auxiliary electrode of the counter electrode of the light-emitting element 104, and the resistance of the counter electrode of the light-emitting element 104 is reduced. In addition, the thickness of the counter electrode of the light emitting element 104 can be reduced, and the transmittance of the counter electrode of the light emitting element 104 and the wiring 110 can be increased. Therefore, higher luminance can be obtained in the top emission structure in which light obtained from the light-emitting element 104 is extracted from the top surface. Note that in some cases, the wiring 110 and the light-emitting element 104 may not be connected.

  Further, when the switching transistor 101 is in a non-selected state (off state), the gate potential of the driving transistor 102 is held by the gate capacitance of the driving transistor 102. Note that FIG. 21 illustrates a configuration in which the gate potential is held by the gate capacitance of the driving transistor without providing a capacitor, but the present invention is not limited to this configuration, and a configuration in which a capacitor is provided may be employed.

  Further, in this embodiment, the ratio L / W between the channel length L and the channel width W of the driving transistor 102 is set larger than that of the AC transistor 103. Specifically, in the driving transistor 102, L is set larger than W, and more desirably 5/1 or more. Further, in the AC transistor 103, L is equal to or shorter than W. Accordingly, the current value flowing in the reverse direction when a reverse voltage is applied to the light emitting element 104 is made larger than the current value flowing in the forward direction when a forward voltage is applied to the light emitting element 104 in the pixel. Can do.

  Here, it can be said that the switching transistor preferably has a configuration with little leakage current (off-state current and gate leakage current). Note that the off-current is a current that flows between the source and the drain when the transistor is off, and the gate leakage current is a current that flows between the gate and the source or drain via the gate insulating film. Current.

  Therefore, the N-channel transistor used for the switching transistor 101 is preferably provided with a low concentration impurity region (also referred to as a lightly doped drain (LDD region)). This is because a transistor having a structure provided with an LDD region can reduce off-state current. In addition, the switching transistor 101 needs to have a large on-current when a current flows through the light-emitting element 104.

  In a more preferable mode, the switching transistor 101 is provided with an LDD region, and the LDD region is provided with a region overlapping with the gate electrode. Then, the switching transistor 101 can increase the on-current and further reduce the generation of hot electrons. Therefore, the reliability of the switching transistor 101 is improved.

  Further, the driving transistor 102 is also provided with an LDD region, and the LDD region overlaps with the gate electrode, whereby reliability is improved.

  The off-state current can also be reduced by reducing the thickness of the gate insulating film. Therefore, the thickness of the switching transistor 101 is preferably smaller than the thickness of the driving transistor 102.

  Further, when the switching transistor 101 has a double gate structure or other multi-gate structure, gate leakage current can be reduced. Further, by adopting a double gate structure or other multi-gate structure in the driving transistor 102, the gate leakage current can be reduced and the reliability can be improved.

  In particular, when an off-state current flows through the switching transistor 101, the gate capacitance of the driving transistor 102 cannot hold the voltage written during the writing period. Therefore, the switching transistor 101 is preferably provided with an LDD region, a thin gate insulating film, or a multi-gate structure to reduce off-state current.

  Next, the operation in the circuit configuration of FIG. 21 will be described with reference to FIG.

  First, in the writing period of FIG. 22A, when the scanning line G is selected, the switching transistor 101 whose gate electrode is connected to the scanning line G is turned on. Then, the potential Vsig of the video signal input to the signal line S is input to the gate electrode of the driving transistor 102 via the switching transistor 101, and the gate potential of the driving transistor 102 is driven by the gate capacitance of the driving transistor 102. Is retained.

  In addition, since the potential Vss1 of the power supply line V is set to be equal to or lower than the potential Vss of the counter electrode of the light emitting element 104 (that is, Vss ≧ Vss1 is satisfied), the light emitting element 104 does not emit light. As the potential Vss, for example, GND (ground potential), 0 V, or the like may be applied. Further, a reverse bias current flows through the light emitting element 104 due to the potential difference between Vss1 and Vss that is set. (However, it does not flow when Vss1 and Vss are at the same potential.)

  Further, the potential of the wiring 110 connected to the gate electrode of the AC transistor 103 becomes the same potential as the potential Vss of the counter electrode of the light-emitting element 104 by being connected to the counter electrode of the light-emitting element 104; Becomes Vss, which is equal to or higher than the potential Vss1 of the power supply line V.

  Therefore, when Vss1 is lower than Vss, the electrode of the AC transistor 103 connected to the power supply line V becomes a source electrode, and the potential of the source electrode of the AC transistor 103 is lower than the potential of the gate electrode. Therefore, the AC transistor 103 is turned on, and a reverse bias current flows through the light-emitting element 104. When Vss1 and Vss are at the same potential, the AC transistor is turned off and no current flows through the light-emitting element 104. Therefore, even if Vss1 is lower than Vss or the same potential as Vss, the light-emitting element 104 does not emit light in the writing period.

  Note that although the case where the driving transistor 102 is turned on by the potential Vsig of the video signal in the writing period has been described, the case where the driving transistor 102 is turned off by the potential Vsig of the video signal is also in order of the light emitting element 104. Since the direction bias current is not supplied, the light emitting element 104 does not emit light.

  Next, in the display period in FIG. 22B, the switching transistor 101 is turned off by controlling the potential of the scanning line G, and the potential Vsig of the video signal written in the writing period is changed to the gate of the driving transistor 102. Since it is held by the capacitor, the driving transistor 102 is turned on.

  In addition, since the potential Vdd1 of the power supply line V is set to a potential higher than the potential Vss of the counter electrode of the light emitting element 104 (that is, Vdd1> Vss is satisfied), a forward bias current flows to the light emitting element 104 and light emission occurs. The element 104 emits light.

  On the other hand, since the potential Vdd1 of the power supply line V is set higher than the potential Vss of the counter electrode of the light emitting element 104, the potential Vss of the wiring 110 connected to the gate electrode of the AC transistor 103 is The potential is lower than the potential Vdd1. Further, the electrode of the AC transistor 103 connected to the power supply line V becomes a drain electrode, and the drain electrode of the AC transistor 103 is higher in potential than the gate electrode, so that the AC transistor 103 is turned off. .

  Although the case where the driving transistor 102 is turned on by the potential Vsig of the video signal in the writing period has been described, in the case where the driving transistor 102 is turned off by the potential Vsig of the video signal, the order toward the light emitting element 104 is increased. Since the bias current in the direction is not supplied, the forward bias current is not supplied to the light emitting element 104 even in the display period.

  Next, in the reverse bias period (non-lighting period) in FIG. 22C, the switching transistor 101 is turned off by controlling the potential of the scanning line G.

  Further, the potential Vss1 ′ of the power supply line V is set to a potential lower than the potential Vss of the counter electrode of the light emitting element 104 (that is, Vss> Vss1 ′ is satisfied). Accordingly, the electrode of the AC transistor 103 connected to the power supply line V becomes a source electrode, and the potential of the gate electrode of the AC transistor is higher than that of the source electrode, so that the AC transistor 103 is turned on. . Accordingly, a reverse voltage is applied to the light emitting element 104, and a reverse bias current flows in the light emitting element 104 and the AC transistor 103.

  Note that when the driving transistor 102 is turned on by the potential Vsig of the video signal in the writing period and the display period, the gate capacitance holds the potential Vsig of the video signal even in the reverse bias period. The transistor 102 is turned on. As a result, a reverse bias current flows through the driving transistor 102. However, as described above, the current flowing in the driving transistor 102 is made larger than the current value flowing in the AC transistor 103 by making the L / W of the driving transistor 102 larger than the L / W of the AC transistor 103. The value becomes smaller. Needless to say, current is not supplied to the driving transistor 102 when the driving transistor 102 is turned off in the writing period and the display period.

  Further, the potential difference between Vss1 'and Vss in the reverse bias period may be larger than the potential difference between Vdd1 and Vss in the display period. As a result, the current value of the reverse bias current can be made larger than the current value of the forward bias current, and a larger current can further flow through the light emitting element 104 during the reverse bias period.

  In this embodiment, the operation is described by changing the potential of the power supply line V. However, the present invention is not limited to this. For example, the potential of the counter electrode of the light emitting element 104 (that is, the potential of the wiring 110 connected to the gate electrode of the AC transistor 103) may be changed, or the potential of the power supply line V and the counter electrode of the light emitting element 104 may be changed. Both potentials may be varied.

  Next, a method of driving by the digital time gray scale method using the pixel shown in FIG. 21 follows the timing charts of FIG. 9, FIG. 10, and FIG. In addition, since it becomes the same as the content demonstrated in FIG. 9, FIG.10 and FIG.23 in Embodiment 3, description is abbreviate | omitted here.

  As described above, in the structure of the present invention, when a reverse voltage is applied, a current sufficient to insulate a short-circuited portion can be passed, and the lifetime of the light-emitting element can be extended. In addition, since the circuit configuration can be constituted by a unipolar transistor, it can be manufactured at low cost.

  In addition, an amorphous silicon transistor can be used by manufacturing a transistor having a circuit structure as an N-type transistor. Therefore, since a transistor manufacturing technique using amorphous silicon that has already been established can be applied, a display device with favorable and stable operation characteristics can be obtained with a simple and inexpensive manufacturing process.

(Embodiment 7)
(Circuit configuration 6)
In this embodiment mode, a configuration different from the circuit configuration in FIG. 1 described in Embodiment Mode 1 will be described.

  24 controls the light emitting element 104, a transistor used as a switching element for controlling input of a video signal to the pixel (switching transistor 101), and a current value flowing through the light emitting element 104. Transistor (driving transistor 102) and a transistor that applies a reverse bias current to the light emitting element 104 when a reverse voltage is applied to the light emitting element 104 (first AC transistor 107, second AC transistor) 108). The switching transistor 101, the driving transistor 102, the first AC transistor 107, and the second AC transistor 108 have the same polarity, and as a feature of the present invention, N-type transistors are used as these transistors. And Further, although a capacitor is not provided in this embodiment, it may be provided as a capacitor for holding the potential of a video signal.

  As shown in FIG. 24, the gate electrode of the switching transistor 101 is connected to the scanning line G. One of the source electrode and the drain electrode of the switching transistor 101 is connected to the signal line S, and the other is connected to the gate electrode of the driving transistor 102. One of the source electrode and the drain electrode of the driving transistor 102 is connected to the power supply line V, and the other is connected to the pixel electrode of the light emitting element 104.

  In this embodiment mode, one of the source electrode and the drain electrode of the first AC transistor 107 is the gate electrode of the driving transistor 102, the other is the pixel electrode of the light-emitting element 104, and the driving transistor 102. It is connected to the source electrode or the drain electrode. The gate electrode of the first AC transistor 107 is connected to the second potential control line XL. Further, one of the source electrode and the drain electrode of the second AC transistor 108 is connected to the first potential control line WL and the other is connected to the pixel electrode of the light emitting element 104. The gate electrode of the second AC transistor 108 is connected to the source electrode or the drain electrode of the second AC transistor 108 connected to the pixel electrode of the light emitting element 104.

  Further, when the switching transistor 101 is in a non-selected state (off state), the gate potential of the driving transistor 102 is held by the gate capacitance of the driving transistor 102. Note that although FIG. 24 illustrates a structure in which the gate potential is held by the gate capacitance of the driving transistor without providing the capacitor element, the present invention is not limited to this structure, and a capacitor element may be provided.

  Further, the ratio L / W between the channel length L and the channel width W of the driving transistor 102 may be larger than L / W of the second AC transistor 108. Specifically, in the driving transistor 102, L is set larger than W, and more desirably 5/1 or more. Further, in the second AC transistor 108, L is equal to or shorter than W. Accordingly, the current value flowing in the reverse direction when a reverse voltage is applied to the light emitting element 104 is made larger than the current value flowing in the forward direction when a forward voltage is applied to the light emitting element 104 in the pixel. Can do.

  Here, it can be said that the switching transistor preferably has a configuration with little leakage current (off-state current and gate leakage current). Note that the off-current is a current that flows between the source and the drain when the transistor is off, and the gate leakage current is a current that flows between the gate and the source or drain via the gate insulating film. Current.

  Therefore, the N-channel transistor used for the switching transistor 101 is preferably provided with a low concentration impurity region (also referred to as a lightly doped drain (LDD region)). This is because a transistor having a structure provided with an LDD region can reduce off-state current. In addition, the switching transistor 101 needs to have a large on-current when a current flows through the light-emitting element 104.

  In a more preferable mode, the switching transistor 101 is provided with an LDD region, and the LDD region is provided with a region overlapping with the gate electrode. Then, the switching transistor 101 can increase the on-current and further reduce the generation of hot electrons. Therefore, the reliability of the switching transistor 101 is improved.

  Further, the driving transistor 102 is also provided with an LDD region, and the LDD region overlaps with the gate electrode, whereby reliability is improved.

  The off-state current can also be reduced by reducing the thickness of the gate insulating film. Therefore, the thickness of the switching transistor 101 is preferably smaller than the thickness of the driving transistor 102.

  Further, when the switching transistor 101 has a double gate structure or other multi-gate structure, gate leakage current can be reduced. Further, by adopting a double gate structure or other multi-gate structure in the driving transistor 102, the gate leakage current can be reduced and the reliability can be improved.

  In particular, when an off-state current flows through the switching transistor 101, the gate capacitance of the driving transistor 102 cannot hold the voltage written during the writing period. Therefore, the switching transistor 101 is preferably provided with an LDD region, a thin gate insulating film, or a multi-gate structure to reduce off-state current.

  Next, the operation in the circuit configuration of FIG. 24 will be described with reference to FIG.

  First, in the writing period in FIG. 25A, when the scanning line G is selected, the switching transistor 101 whose gate electrode is connected to the scanning line G is turned on. Then, the potential Vsig of the video signal input to the signal line S is input to the gate electrode of the driving transistor 102 via the switching transistor 101, and the gate potential is held by the gate capacitance of the driving transistor 102.

  In addition, since the potential Vss1 of the power supply line V is set to be equal to or lower than the potential Vss of the counter electrode of the light emitting element 104 (that is, Vss ≧ Vss1 is satisfied), the light emitting element 104 does not emit light. As the potential Vss, for example, GND (ground potential), 0 V, or the like may be applied. Further, a reverse bias current flows through the light emitting element 104 due to the potential difference between Vss1 and Vss that is set. (However, it does not flow when Vss1 and Vss are at the same potential.)

  On the other hand, in this writing period, the potential Vss3 of the second potential control line XL is set low so that the first AC transistor 107 is turned off. Further, since the potential Vdd2 of the first potential control line WL is set to a potential higher than the potential Vss of the counter electrode of the light emitting element 104 (that is, Vdd2> Vss is satisfied), the first potential control line WL The electrode of the second AC transistor 108 connected is a drain electrode, and the electrode of the second AC transistor 108 connected to the pixel electrode of the light emitting element 104 is a source electrode. Further, since the source electrode and the gate electrode of the second AC transistor 108 are connected, the second AC transistor 108 is turned off.

  Note that the case where the driving transistor 102 is turned on by the potential Vsig of the video signal in the writing period has been described; however, the current to the light-emitting element 104 is also applied when the driving transistor 102 is turned off by the potential Vsig of the video signal. Therefore, the light emitting element 104 does not emit light.

  Next, in the display period of FIG. 25B, the switching transistor 101 is turned off by controlling the potential of the scanning line G. In addition, since the potential Vsig of the video signal written in the writing period is held by the gate capacitance of the driving transistor 102, the driving transistor 102 is turned on. In addition, since the potential Vdd1 of the power supply line V is set to a potential higher than the potential Vss of the counter electrode of the light emitting element 104 (that is, Vdd1> Vss is satisfied), a forward bias current flows to the light emitting element 104 and light emission occurs. The element 104 emits light.

  On the other hand, as in the writing period, the potential Vss3 of the second potential control line XL is set low so that the first AC transistor 107 is turned off. In addition, the potential Vdd2 of the first potential control line WL is set to a potential higher than the potential of the counter electrode of the light emitting element 104 (that is, Vdd2> Vss is satisfied), and thus connected to the first potential control line WL. The electrode of the second AC transistor 108 is a drain electrode, and the electrode of the second AC transistor 108 connected to the pixel electrode of the light emitting element 104 is a source electrode. Further, since the source electrode and the gate electrode of the second AC transistor 108 are connected to each other, the second AC transistor 108 is turned off even in the display period.

  In the writing period, the case where the driving transistor 102 is turned on by the potential Vsig of the video signal has been described; however, when the driving transistor 102 is turned off by the potential Vsig of the video signal, the current to the light-emitting element 104 is Therefore, no current is supplied to the light-emitting element 104 even during the display period.

  Next, in the reverse bias period (non-lighting period) in FIG. 25C, the switching transistor 101 is turned off by controlling the potential of the scanning line G.

  Further, the potential Vss1 'of the power supply line V is set to a potential lower than the potential Vss of the counter electrode of the light emitting element 104 (that is, so as to satisfy Vss> Vss1'). In that state, when the driving transistor 102 is turned on, the electrode of the driving transistor 102 connected to the power supply line V becomes a source electrode, and the electrode of the driving transistor 102 connected to the pixel electrode of the light emitting element 104 becomes It becomes a drain electrode.

  Further, the potential Vdd3 of the second potential control line XL is set high so that the first AC transistor 107 is turned on. Accordingly, the gate electrode and the drain electrode of the driving transistor 102 have the same potential, and the driving transistor 102 is turned on.

  Further, by setting the potential Vss2 of the first potential control line WL to a potential lower than the potential Vss of the counter electrode of the light emitting element 104 (that is, so as to satisfy Vss> Vss2), the first potential control line WL is set. The electrode of the second AC transistor 108 connected to is a source electrode, and the electrode connected to the pixel electrode of the light-emitting element 104 is a drain electrode. Further, since the drain electrode and the gate electrode of the second AC transistor 108 are connected, the second AC transistor 108 is turned on.

  Therefore, a reverse voltage is applied to the light emitting element 104 by the two AC transistors, and a reverse bias current flows in the light emitting element 104, the driving transistor 102, and the second AC transistor 108.

  Note that, as described above, the current flowing through the second AC transistor 108 is supplied to the driving transistor 102 by making the L / W of the driving transistor 102 larger than the L / W of the second AC transistor 108. It can be made larger than the flowing current. That is, the current value of the reverse bias current is larger than the current value of the forward bias current, and a large current can flow through the light emitting element 104 during the reverse bias period.

  Further, the potential difference between Vss1 'and Vss in the reverse bias period may be larger than the potential difference between Vdd1 and Vss in the display period. Accordingly, the current value of the reverse bias current becomes larger than the current value of the forward bias current, and a large current can be passed through the light emitting element 104 during the reverse bias period.

  Note that although the potential of the counter electrode of the light-emitting element 104 is a fixed potential in this embodiment mode, the present invention is not limited to this. For example, the potential of the counter electrode of the light emitting element 104 may be changed, or both the potential of the power supply line V and the potential of the counter electrode of the light emitting element 104 may be changed.

  Next, the method of driving in the digital time gray scale method using the pixels shown in FIG. 24 follows the timing charts of FIGS. In addition, since it becomes the same as the content demonstrated in FIG. 9, FIG.10 and FIG.23 in Embodiment 3, description is abbreviate | omitted here.

  As described above, in the structure of the present invention, when a reverse voltage is applied, a current sufficient to insulate a short-circuited portion can be passed, and the lifetime of the light-emitting element can be extended. In addition, since the circuit configuration can be constituted by a unipolar transistor, it can be manufactured at low cost.

  In addition, an amorphous silicon transistor can be used by manufacturing a transistor having a circuit structure as an N-type transistor. Therefore, since a transistor manufacturing technique using amorphous silicon that has already been established can be applied, a display device with favorable and stable operation characteristics can be obtained with a simple and inexpensive manufacturing process.

(Embodiment 8)
(Circuit configuration 7)
In this embodiment mode, a configuration different from the circuit configuration in FIG. 1 described in Embodiment Mode 1 will be described.

  26 controls the light-emitting element 104, a transistor used as a switching element for controlling input of a video signal to the pixel (switching transistor 101), and a current value flowing through the light-emitting element 104. And a transistor (alternating current transistor 103) that applies a reverse bias current to the light emitting element 104 when a reverse voltage is applied to the light emitting element 104. The switching transistor 101, the driving transistor 102, and the AC transistor 103 have the same polarity. As a feature of the present invention, N-type transistors are used as these transistors. Further, although a capacitor is not provided in this embodiment, it may be provided as a capacitor for holding the potential of a video signal.

  As shown in FIG. 26, the gate electrode of the switching transistor 101 is connected to the scanning line G. One of the source electrode and the drain electrode of the switching transistor 101 is connected to the signal line S, and the other is connected to the gate electrode of the driving transistor 102. One of the source electrode and the drain electrode of the driving transistor 102 is connected to the power supply line V, and the other is connected to the pixel electrode of the light emitting element 104.

  In this embodiment mode, one of the source electrode and the drain electrode of the AC transistor 103 is connected to the power supply line V and the other is connected to the pixel electrode of the light-emitting element 104. The gate electrode of the AC transistor 103 is connected to the source electrode or the drain electrode of the AC transistor 103 connected to the pixel electrode of the light emitting element 104.

  Further, when the switching transistor 101 is in a non-selected state (off state), the gate potential of the driving transistor 102 is held by the gate capacitance of the driving transistor 102. Note that FIG. 26 illustrates a structure in which the gate potential is held by the gate capacitance of the driving transistor without providing a capacitor, but the present invention is not limited to this structure, and a capacitor may be provided.

  Further, in this embodiment, the ratio L / W between the channel length L and the channel width W of the driving transistor 102 is set larger than that of the AC transistor 103. Specifically, in the driving transistor 102, L is set larger than W, and more desirably 5/1 or more. Further, in the AC transistor 103, L is equal to or shorter than W. Accordingly, the current value flowing in the reverse direction when a reverse voltage is applied to the light emitting element 104 is made larger than the current value flowing in the forward direction when a forward voltage is applied to the light emitting element 104 in the pixel. Can do.

  Here, it can be said that the switching transistor preferably has a configuration with little leakage current (off-state current and gate leakage current). Note that the off-current is a current that flows between the source and the drain when the transistor is off, and the gate leakage current is a current that flows between the gate and the source or drain via the gate insulating film. Current.

  Therefore, the N-channel transistor used for the switching transistor 101 is preferably provided with a low concentration impurity region (also referred to as a lightly doped drain (LDD region)). This is because a transistor having a structure provided with an LDD region can reduce off-state current. In addition, the switching transistor 101 needs to have a large on-current when a current flows through the light-emitting element 104.

  In a more preferable mode, the switching transistor 101 is provided with an LDD region, and the LDD region is provided with a region overlapping with the gate electrode. Then, the switching transistor 101 can increase the on-current and further reduce the generation of hot electrons. Therefore, the reliability of the switching transistor 101 is improved.

  Further, the driving transistor 102 is also provided with an LDD region, and the LDD region overlaps with the gate electrode, whereby reliability is improved.

  The off-state current can also be reduced by reducing the thickness of the gate insulating film. Therefore, the thickness of the switching transistor 101 is preferably smaller than the thickness of the driving transistor 102.

  Further, when the switching transistor 101 has a double gate structure or other multi-gate structure, gate leakage current can be reduced. Further, by adopting a double gate structure or other multi-gate structure in the driving transistor 102, the gate leakage current can be reduced and the reliability can be improved.

  In particular, when an off-state current flows through the switching transistor 101, the gate capacitance of the driving transistor 102 cannot hold the voltage written during the writing period. Therefore, the switching transistor 101 is preferably provided with an LDD region, a thin gate insulating film, or a multi-gate structure to reduce off-state current.

  Next, the operation in the circuit configuration of FIG. 26 will be described with reference to FIG.

  First, in the writing period in FIG. 27A, when the scanning line G is selected, the switching transistor 101 whose gate electrode is connected to the scanning line G is turned on. Then, the potential Vsig of the video signal input to the signal line S is input to the gate electrode of the driving transistor 102 via the switching transistor 101, and the gate potential is held by the gate capacitance of the driving transistor 102.

  Further, since the potential Vss1 of the power supply line V is set to a potential that is the same as or lower than the potential Vss of the counter electrode of the light emitting element 104 (that is, Vss ≧ Vss1 is satisfied), the light emitting element 104 does not emit light. As the potential Vss, for example, GND (ground potential), 0 V, or the like may be applied. Further, a reverse bias current flows through the light emitting element 104 due to the potential difference between Vss1 and Vss that is set. (However, it does not flow when Vss1 and Vss are at the same potential.)

  On the other hand, in this writing period, the potential Vss1 of the power supply line V is set to be the same as or lower than the potential of the counter electrode of the light emitting element 104. Therefore, when Vss1 and Vss are the same potential, the AC transistor 103 is The light-emitting element 104 is turned off and no current flows. When Vss1 is lower than Vss, the electrode of the AC transistor 103 connected to the power supply line V is a source electrode, and the electrode connected to the pixel electrode of the light-emitting element 104 is a drain electrode. Further, since the source electrode and the gate electrode of the AC transistor 103 are connected, the AC transistor 103 is turned on, and a reverse bias current flows through the light-emitting element 104. Therefore, even if Vss1 is the same potential as Vss or lower than Vss, the light-emitting element 104 does not emit light in the reverse bias period.

  Note that although the case where the driving transistor 102 is turned on by the potential Vsig of the video signal in the writing period has been described, the case where the driving transistor 102 is turned off by the potential Vsig of the video signal is also in order of the light emitting element 104. Since the direction bias current is not supplied, the light emitting element 104 does not emit light.

  Next, in the display period of FIG. 27B, the switching transistor 101 is turned off by controlling the potential of the scanning line G. Then, since the potential Vsig of the video signal written in the writing period is held by the gate capacitance of the driving transistor 102, the driving transistor 102 is turned on.

  In addition, since the potential Vdd1 of the power supply line V is set to a potential higher than the potential Vss of the counter electrode of the light emitting element 104 (that is, Vdd1> Vss is satisfied), a forward bias current flows to the light emitting element 104 and light emission occurs. The element 104 emits light.

  On the other hand, since the potential Vdd1 of the power supply line V is set higher than the potential Vss of the counter electrode of the light emitting element 104, the electrode of the AC transistor 103 connected to the power supply line V becomes a drain electrode, and the pixel electrode of the light emitting element 104 The electrode connected to becomes a source electrode. Further, since the source electrode and the gate electrode of the AC transistor 103 are connected, the AC transistor 103 is turned off.

  Note that the case where the driving transistor 102 is turned on by the potential Vsig of the video signal in the writing period has been described; however, when the driving transistor 102 is turned off by the potential Vsig of the video signal, the order toward the light-emitting element 104 is increased. Since the bias current in the direction is not supplied, the forward bias current is not supplied to the light emitting element 104 even in the display period.

  Next, in the reverse bias period (non-lighting period) in FIG. 27C, the switching transistor 101 is turned off by controlling the potential of the scanning line G.

  Further, the potential Vss1 ′ of the power supply line V is set to a potential lower than the potential Vss of the counter electrode of the light emitting element 104 (that is, Vss> Vss1 ′ is satisfied). Accordingly, the electrode of the AC transistor 103 connected to the power supply line V becomes a source electrode, and the electrode connected to the pixel electrode of the light emitting element 104 becomes a drain electrode. Further, since the drain electrode and the gate electrode of the AC transistor 103 are connected, the AC transistor 103 is turned on. Thus, a reverse voltage is applied to the light emitting element 104, and a reverse bias current flows in the light emitting element 104 and the AC transistor 103.

  Note that when the driving transistor 102 is turned on by the potential Vsig of the video signal in the writing period and the display period, the gate capacitance holds the potential Vsig of the video signal even in the reverse bias period. The transistor is turned on. As a result, a reverse bias current flows through the driving transistor 102. However, as described above, the current flowing in the driving transistor 102 is made larger than the current value flowing in the AC transistor 103 by making the L / W of the driving transistor 102 larger than the L / W of the AC transistor 103. The value becomes smaller. Needless to say, current is not supplied to the driving transistor 102 when the driving transistor 102 is turned off in the writing period and the display period.

  Further, the potential difference between Vss1 'and Vss in the reverse bias period may be larger than the potential difference between Vdd1 and Vss in the display period. As a result, the current value of the reverse bias current can be made larger than the current value of the forward bias current, and a larger current can further flow through the light emitting element 104 during the reverse bias period.

  Note that although the potential of the counter electrode of the light-emitting element 104 is a fixed potential in this embodiment mode, the present invention is not limited to this. For example, the potential of the counter electrode of the light emitting element 104 may be changed, or both the potential of the power supply line V and the potential of the counter electrode of the light emitting element 104 may be changed.

  Next, the method of driving in the digital time gray scale method using the pixels shown in FIG. 26 follows the timing charts of FIGS. In addition, since it becomes the same as the content demonstrated in FIG. 9, FIG.10 and FIG.23 in Embodiment 3, description is abbreviate | omitted here.

  As described above, in the structure of the present invention, when a reverse voltage is applied, a current sufficient to insulate a short-circuited portion can be passed, and the lifetime of the light-emitting element can be extended. In addition, since the circuit configuration can be constituted by a unipolar transistor, it can be manufactured at low cost.

  In addition, an amorphous silicon transistor can be used by manufacturing a transistor having a circuit structure as an N-type transistor. Therefore, since a transistor manufacturing technique using amorphous silicon that has already been established can be applied, a display device with favorable and stable operation characteristics can be obtained with a simple and inexpensive manufacturing process.

  Examples of the present invention will be described below.

  A circuit for inputting a signal for driving the display in the digital time gray scale method to the signal line driver circuit and the scanning line driver circuit of the display will be described with reference to FIG.

  In this embodiment, a display device that displays an image by inputting a 4-bit digital video signal to the display device will be described as an example. However, the present invention is not limited to 4 bits.

  The digital video signal is read into the signal control circuit 601 and the digital video signal VD is output to the display 600.

  In the present embodiment, the digital video signal edited by the signal control circuit 601 and converted into a signal input to the display is called a digital video signal VD.

  Signals and driving voltages for driving the signal line driving circuit 607 and the scanning line driving circuit 608 of the display 600 are input by the display controller 602.

  The configurations of the signal control circuit 601 and the display controller 602 will be described.

  Note that the signal line driver circuit 607 of the display 600 includes a shift register 610, a LAT (A) 611, and a LAT (B) 612. In addition, although not shown, a level shifter, a buffer, or the like may be provided. The present invention is not limited to such a configuration. Reference numeral 609 denotes a pixel portion.

  The signal control circuit 601 includes a CPU 604, a memory A 605, a memory B 606, and a memory controller 603.

  The digital video signal input to the signal control circuit 601 is controlled by the memory controller 603 and input to the memory A 605 via a switch. Here, the memory A 605 has a capacity capable of storing digital video signals for all the pixels of the display 600. When a signal for one frame period is stored in the memory A605, the signal of each bit is sequentially read out by the memory controller 603 and input to the signal line driver circuit 607 as a digital video signal VD.

  When reading of the signal stored in the memory A 605 starts, a digital video signal corresponding to the next frame period is input to the memory B 606 via the memory controller 603 and stored. Similarly to the memory A605, the memory B606 has a capacity capable of storing digital video signals for all the pixels of the display device.

  As described above, the signal control circuit 601 includes the memory A 605 and the memory B 606 capable of storing digital video signals for one frame period, and uses the memory A 605 and the memory B 606 alternately to generate digital video signals. The signal VD is sampled.

  Here, the signal control circuit 601 that stores signals by alternately using the two memories A605 and B606 is shown, but in general, the display device has a plurality of memories that can store information for a plurality of frames. These memories can be used alternately.

  A block diagram of the display device having the above structure is shown in FIG.

  The display device includes a signal control circuit 601, a display controller 602, and a display 600.

  The display controller 602 supplies the display 600 with a start pulse SP, a clock pulse CLK, a driving voltage, and the like.

  The signal control circuit 601 includes a CPU 604, a memory A 605, a memory B 606, and a memory controller 603.

  The memory A 605 includes memories 605_1 to 605_4 that store information on the first bit to the fourth bit of the digital video signal, respectively. Similarly, the memory B 606 is also composed of memories 606_1 to 606_4 that store information of the first bit to the fourth bit of the digital video signal, respectively. Each of the memories corresponding to these bits has a number of storage elements that can store a signal for one bit by the number of pixels constituting one screen.

  In general, in a display device capable of expressing gradation using an n-bit digital video signal, the memory A 605 includes memories 605_1 to 605_n that store information on first to nth bits, respectively. The Similarly, the memory B 606 includes the memories 606_1 to 606_n that store information of the first bit to the n-th bit, respectively. A memory corresponding to each of these bits has a capacity capable of storing a signal for one bit for each pixel constituting one screen.

  The configuration of the display controller 602 will be described below.

  FIG. 39 is a diagram showing the configuration of the display controller of the present invention.

  The display controller 602 includes a reference clock generation circuit 801, a horizontal clock generation circuit 803, a vertical clock generation circuit 804, a light emitting element power supply control circuit 805, and a drive circuit power supply control circuit 806.

  The clock signal 31 input from the CPU 604 is input to the reference clock generation circuit 801 and generates a reference clock. This reference clock is input to the horizontal clock generation circuit 803 and the vertical clock generation circuit 804.

  The horizontal clock generation circuit 803 receives a horizontal cycle signal 32 that determines a horizontal cycle from the CPU 604, and outputs a clock pulse S_CLK and a start pulse S_SP for the signal line driver circuit. Similarly, a vertical cycle signal 33 for determining a vertical cycle is input from the CPU 604 to the vertical clock generation circuit 804, and a clock pulse G_CLK and a start pulse G_SP for the scanning line driver circuit are output.

  The light emitting element power control circuit 805 is controlled by the light emitting element power control signal 34. For example, when the timing chart of FIG. 9 is used, the potential of the power supply line is set such that a voltage of 0 V is applied to the power supply line in the writing period Ta and a forward voltage is applied to the light emitting element in the display period Ts. In the reverse bias period BF, control is performed such that a reverse voltage is applied.

  In the case of using the timing chart of FIG. 23, the light-emitting element power supply control circuit 805 applies the potential of the power supply line to the light-emitting element in the writing period Ta, and the light-emitting element in the display period Ts. Is controlled to apply a forward voltage.

  The drive circuit power supply control circuit 806 controls the power supply voltage input to each drive circuit.

  Note that a driver circuit power supply control circuit 806 having a known configuration may be used.

  The signal control circuit 601, the memory controller 603, the CPU 604, the memory A 605, the memory B 606, and the display controller 602 described above may be formed on the same substrate as the pixels to be formed simultaneously with the display 600, or may be formed by an LSI chip. It may be attached to the substrate of the display 600 with COG, may be attached to the substrate using TAB, or may be formed on a substrate different from the display 600 and connected by electric wiring. .

  By using the present invention and a circuit that inputs to the signal line driving circuit and the scanning line driving circuit of the display, a current sufficient to insulate a short-circuited portion can be supplied when a reverse voltage is applied. The life of the light emitting element can be extended. In addition, since the circuit configuration can be constituted by a unipolar transistor, it can be manufactured at low cost.

  This embodiment can be combined with the above embodiment mode.

  In this embodiment, a configuration example of a signal line driver circuit for a digital time gray scale method used in the display device of the present invention will be described.

  An example of the structure of the signal line driver circuit is shown in FIG.

  The signal line driver circuit includes a shift register 901, a scanning direction switching circuit, LAT (A) 902, and LAT (B) 903. In FIG. 40, only a part of the LAT (A) 902 and a part of the LAT (B) 903 corresponding to one of the outputs from the shift register 901 are illustrated, but all the outputs from the shift register 901 are illustrated. In contrast, LAT (A) 902 and LAT (B) 903 having the same configuration correspond to each other.

  The shift register 901 includes a clocked inverter, an inverter, and a NAND. The shift register 901 receives the signal line driver circuit start pulse S_SP, and the signal line driver circuit clock pulse S_CLK and the signal line driver circuit inverted clock pulse S_CLKB, which is a signal whose polarity is inverted, cause the clocked inverter to operate. By changing between the conductive state and the non-conductive state, sampling pulses are output to the LAT (A) 902 in order from the NAND.

  The scanning direction switching circuit is constituted by a switch and functions to switch the scanning direction of the shift register 901 left and right as viewed in the drawing. In FIG. 40, when the left / right switching signal L / R corresponds to a low signal, the shift register 901 outputs sampling pulses sequentially from left to right as viewed in the drawing. On the other hand, when the left / right switching signal L / R corresponds to a high signal, sampling pulses are output sequentially from right to left in the drawing.

  Here, the LAT (A) 902 in each stage indicates the LAT (A) 904 that captures a video signal input to one signal line.

  The LAT (A) 904 includes a clocked inverter and an inverter.

  Here, the digital video signal VD output from the signal control circuit described in the first embodiment is input after being divided into p (p is a natural number). That is, signals corresponding to outputs to the p signal lines are input in parallel. When the sampling pulse is simultaneously input to the p LAT (A) 902 clocked inverters through the buffer, the p-divided input signals are respectively sampled simultaneously in the p LAT (A) 904. .

  Here, a signal line driver circuit that outputs a signal voltage to x signal lines is described as an example, so x / p sampling pulses are sequentially output from the shift register per horizontal period. In response to each sampling pulse, p LAT (A) 904 simultaneously samples a digital video signal corresponding to an output to p signal lines.

  In this embodiment, the method of dividing the digital video signal input to the signal line driving circuit into p-phase parallel signals and simultaneously capturing p digital video signals with one sampling pulse is referred to as p-division driving. I will call it. FIG. 40 shows four-division driving.

  By the divided driving, a margin can be given to sampling of the shift register of the signal line driver circuit. Thus, the reliability of the display device can be improved.

  When all signals in one horizontal period are input to each LAT (A) 904, the latch pulse S_LAT and the inverted latch pulse S_LATB whose polarity is inverted are input, and the signal input to each LAT (A) 904 is Output to LAT (B) 903 of each stage simultaneously.

  Here, the LAT (B) 903 of each stage indicates the LAT (B) 905 to which the signal from the LAT (A) 902 of each stage is input.

  Each LAT (B) 905 includes a clocked inverter and an inverter. The signal output from each LAT (A) 904 is held in the LAT (B) 905 and simultaneously output to each signal line S1 to Sx.

Although not shown here, a level shifter, a buffer, or the like may be provided as appropriate.

  The start pulse S_SP, the clock pulse S_CLK, and the like input to the shift register 901, LAT (A) 902, and LAT (B) 903 are input from the display controller shown in the first embodiment of the present invention.

  In this embodiment, the operation of inputting the digital video signal to the LAT (A) of the signal line driver circuit is controlled by the signal control circuit, and at the same time, the clock pulse S_CLK and the start pulse S_SP are input to the shift register of the signal line driver circuit. The display controller controls the operation and the operation of inputting a driving voltage for operating the signal line driving circuit.

  Note that the display device of the present invention is not limited to the configuration of the signal line driver circuit of this embodiment, and a signal line driver circuit having a known configuration can be used.

  Further, depending on the configuration of the signal line driving circuit, the number of signal lines input from the display controller to the signal line driving circuit and the number of power supply lines for driving voltage are different.

  By using the present invention and the above structure, when a reverse voltage is applied, a current sufficient to insulate a short-circuited portion can be passed, and the lifetime of the light-emitting element can be extended. In addition, since the circuit configuration can be constituted by a unipolar transistor, it can be manufactured at low cost.

  This embodiment can be combined with the above embodiment modes and embodiments.

  In this embodiment, a structural example of a scan line driver circuit used in the display device of the present invention will be described with reference to FIG.

  The scanning line driving circuit includes a shift register, a scanning direction switching circuit, and the like. Although not shown here, a level shifter, a buffer, or the like may be provided as appropriate.

  The shift register receives a start pulse G_SP, a clock pulse G_CLK, a driving voltage, and the like, and outputs a scanning line selection signal.

  The shift register 3601 includes clocked inverters 3602 and 3603, an inverter 3604, and a NAND circuit 3607. The shift register 3601 receives the start pulse G_SP, and the clocked inverters 3602 and 3603 change between a conductive state and a non-conductive state by an inverted clock pulse G_CLKB which is a signal whose polarity is inverted with respect to the clock pulse G_CLK. Sampling pulses are output in order from the NAND circuit 3607.

  The scanning direction switching circuit includes a switch 3605 and a switch 3606, and functions to switch the scanning direction of the shift register 3601 left and right as viewed in the drawing. In FIG. 41, when the scanning direction switching signal U / D corresponds to a low signal, the shift register 3601 outputs sampling pulses in order from the left to the right in the drawing. On the other hand, when the scanning direction switching signal U / D corresponds to a high signal, sampling pulses are output sequentially from right to left in the drawing.

  The sampling pulse output from the shift register 3601 is input to the NOR circuit 3608 and calculated as the enable signal ENB. This calculation is performed in order to prevent a situation in which adjacent scanning lines are simultaneously selected due to the rounding of sampling pulses. The signal output from the NOR circuit 3608 is output to the scanning lines G1 to Gy via the buffers 3609 and 3610.

Although not shown here, a level shifter, a buffer, or the like may be provided as appropriate.

  A start pulse G_SP, a clock pulse G_CLK, a driving voltage, and the like input to the shift register 3601 are input from the display controller shown in Embodiment 1 of this specification.

  Note that the display device of the present invention is not limited to the configuration of the scanning line driving circuit of this embodiment, and a scanning line driving circuit having a known configuration can be used.

  Further, depending on the configuration of the scanning line driving circuit, the number of signal lines input from the display controller to the scanning line driving circuit and the number of power supply lines for driving voltage are different.

  By using the above structure for the display device of the present invention, when a reverse voltage is applied, a current sufficient to insulate a short-circuited portion can be passed, and the lifetime of the light-emitting element can be extended. is there. In addition, since the circuit configuration can be constituted by a unipolar transistor, it can be manufactured at low cost.

  This embodiment can be combined with the above embodiment modes and embodiments.

  In this example, a structure of a display panel having the pixel structure described in the above embodiment mode is described with reference to drawings.

  FIG. 28A is a top view showing the display panel, and FIG. 28B is a cross-sectional view of FIG. 28A taken along A-A ′. A signal line driver circuit 6701, a pixel portion 6702, a first scan line driver circuit 6703, and a second scan line driver circuit 6706 indicated by dotted lines are included. Further, a sealing substrate 6704 and a sealing material 6705 are provided, and an inner side surrounded by the sealing material 6705 is a space 6707.

  Note that the wiring 6708 is a wiring for transmitting a signal input to the first scan line driver circuit 6703, the second scan line driver circuit 6706, and the signal line driver circuit 6701, and is an FPC (flexible) that serves as an external input terminal. Print circuit) 6709 receives a video signal, a clock signal, a start signal, and the like. An IC chip (a semiconductor chip on which a memory circuit, a buffer circuit, or the like is formed) 6718 and an IC chip 6719 are mounted with COG (Chip On Glass) or the like on a connection portion between the FPC 6709 and the display panel. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to the FPC. The display device in this specification includes not only a display panel body but also a state in which an FPC or a PWB is attached thereto. In addition, it is assumed that an IC chip or the like is mounted.

  Next, a cross-sectional structure will be described with reference to FIG. A pixel portion 6702 and its peripheral driver circuits (a first scan line driver circuit 6703, a second scan line driver circuit 6706, and a signal line driver circuit 6701) are formed over a substrate 6710. Here, signal lines A driver circuit 6701 and a pixel portion 6702 are shown.

  Note that the signal line driver circuit 6701 includes TFTs 6720 and 6721, and the TFTs 6720 and 6721 are formed of unipolar transistors as N-channel transistors. Note that a pixel can be formed using a unipolar transistor by applying any of the pixel structures described in the above embodiments to the pixel structure. Therefore, a unipolar display panel can be manufactured if the peripheral driver circuit is formed using N-channel transistors. In addition, a peripheral driver circuit can be formed using an NMOS circuit including N-channel transistors. Of course, in the peripheral driver circuit, not only a unipolar transistor using an N-channel transistor but also a P-channel transistor may be used to form a PMOS circuit or a CMOS circuit. In this embodiment, a display panel in which peripheral drive circuits are integrally formed on a substrate is shown. However, this is not always necessary, and all or part of the peripheral drive circuits are formed on an IC chip and mounted by COG or the like. May be. In that case, the driver circuit does not need to be unipolar and can be freely designed such as a combination of P-channel transistors.

  In addition, the pixel portion 6702 includes a TFT 6711 and a TFT 6712. Note that a source electrode of the TFT 6712 is connected to a first electrode (pixel electrode) 6713. An insulator 6714 is formed so as to cover an end portion of the first electrode 6713. Here, a positive photosensitive acrylic resin film is used.

  In order to improve the coverage, a curved surface having a curvature is formed at the upper end portion or the lower end portion of the insulator 6714. For example, in the case where positive photosensitive acrylic is used as a material for the insulator 6714, it is preferable that only the upper end portion of the insulator 6714 has a curved surface with a curvature radius (0.2 μm to 3 μm). As the insulator 6714, either a negative type that becomes insoluble in an etchant by photosensitive light or a positive type that becomes soluble in an etchant by light can be used.

  Over the first electrode 6713, a layer 6716 containing an organic compound and a second electrode (counter electrode) 6717 are formed. Here, as a material used for the first electrode 6713 which functions as an anode, a material having a high work function is preferably used. For example, in addition to a single layer film such as an indium tin oxide (ITO) film, an indium zinc oxide (IZO) film, a titanium nitride film, a chromium film, a tungsten film, a Zn film, or a Pt film Alternatively, a stacked layer of a titanium nitride film and a film containing aluminum as a main component, a three-layer structure of a titanium nitride film, a film containing aluminum as a main component, and a titanium nitride film can be used. Note that with a stacked structure, resistance as a wiring is low, good ohmic contact can be obtained, and a function as an anode can be obtained.

  The layer 6716 containing an organic compound is formed by an evaporation method using an evaporation mask or an inkjet method. For the layer 6716 containing an organic compound, a Group 4 metal complex of the periodic table of elements is used as a part thereof, and other materials that can be used in combination include high molecular weight materials even if they are low molecular weight materials. It may be. In addition, as a material used for a layer containing an organic compound, an organic compound is usually used in a single layer or a stacked layer. However, in this embodiment, an inorganic compound is used for a part of a film made of an organic compound. Include. Further, a known triplet material can be used.

Further, as a material used for the second electrode 6717 formed over the layer 6716 containing an organic compound, a material having a low work function (Al, Ag, Li, Ca, or an alloy thereof MgAg, MgIn, AlLi, CaF _2). Or calcium nitride). Note that in the case where light generated in the layer 6716 containing an organic compound transmits the second electrode 6717, the second electrode 6717 includes a thin metal film and a transparent conductive film (indium tin oxide ( A stack of ITO, Indium Tin Oxide), indium oxide-zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (ZnO), or the like) is preferably used.

  Further, a protective stack 6726 may be formed in order to seal the light emitting element 6725. Note that the protective stack 6726 is formed of a stack of a first inorganic insulating film, a stress relaxation film, and a second inorganic insulating film.

  Further, the light-emitting element 6725 is provided in the space 6707 surrounded by the protective laminate 6726, the substrate 6710, the sealing substrate 6704, and the sealant 6705 by attaching the sealing substrate 6704 to the protective laminate 6726 and the substrate 6710 with the sealant 6705. It has a structured. Note that the space 6707 includes a structure filled with a sealing material 6705 in addition to a case where the space 6707 is filled with an inert gas (nitrogen, argon, or the like).

  Note that an epoxy-based resin is preferably used for the sealant 6705. Moreover, it is desirable that these materials are materials that do not transmit moisture and oxygen as much as possible. In addition to a glass substrate and a quartz substrate, a plastic substrate made of FRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride), Mylar, polyester, acrylic, or the like can be used as a material used for the sealing substrate 6704.

  As described above, a display panel having the pixel configuration of the present invention can be obtained. Note that the above-described configuration is an example, and the configuration of the display panel of the present invention is not limited to this.

  As shown in FIG. 28, the signal line driver circuit 6701, the pixel portion 6702, the first scan line driver circuit 6703, and the second scan line driver circuit 6706 are integrally formed, whereby the cost of the display device can be reduced. In this case, the manufacturing process can be simplified by making the transistors used in the signal line driver circuit 6701, the pixel portion 6702, the first scan line driver circuit 6703, and the second scan line driver circuit 6706 unipolar. Therefore, further cost reduction can be achieved.

  Note that as a structure of the display panel, a signal line driver circuit 6701, a pixel portion 6702, a first scanning line driver circuit 6703, and a second scanning line driver circuit 6706 are integrally formed as shown in FIG. The configuration is not limited, and the signal line driver circuit 6801 shown in FIG. 29A corresponding to the signal line driver circuit 6701 may be formed over the IC chip and mounted on the display panel with COG or the like. Note that the substrate 6800, the pixel portion 6802, the first scan line driver circuit 6803, the second scan line driver circuit 6804, the FPC 6805, the IC chip 6806, the IC chip 6807, the sealing substrate 6808, and the sealing material in FIG. Reference numeral 6809 denotes a substrate 6710, a pixel portion 6702, a first scan line driver circuit 6703, a second scan line driver circuit 6706, an FPC 6709, an IC chip 6718, an IC chip 6719, a sealing substrate 6704, and a sealing material in FIG. This corresponds to 6705.

  That is, only the signal line driver circuit that requires high-speed operation of the driver circuit is formed on the IC chip using a CMOS or the like to reduce power consumption. Further, by using a semiconductor chip such as a silicon wafer as the IC chip, higher speed operation and lower power consumption can be achieved.

  By forming the first scan line driver circuit 6803 and the second scan line driver circuit 6804 integrally with the pixel portion 6802, cost reduction can be achieved. Further, the first scan line driver circuit 6803, the second scan line driver circuit 6804, and the pixel portion 6802 are formed of unipolar transistors, so that cost can be further reduced. As the structure of the pixel included in the pixel portion 6802, the pixel described in the above embodiment can be used.

  Thus, the cost of a high-definition display device can be reduced. Further, by mounting an IC chip on which a functional circuit (memory or buffer) is formed at a connection portion between the FPC 6805 and the substrate 6800, the substrate area can be effectively used.

  Further, the signal line driver circuit 6811 in FIG. 29B corresponding to the signal line driver circuit 6701, the first scanning line driver circuit 6703, and the second scanning line driver circuit 6706 in FIG. The line driver circuit 6814 and the second scan line driver circuit 6813 may be formed over an IC chip and mounted on the display panel with COG or the like. In this case, a high-definition display device can have lower power consumption. Note that the substrate 6810, the pixel portion 6812, the FPC 6815, the IC chip 6816, the IC chip 6817, the sealing substrate 6818, and the sealant 6819 in FIG. 29B are the substrate 6710, the pixel portion 6702, the FPC 6709, and the IC in FIG. It corresponds to a chip 6718, an IC chip 6719, a sealing substrate 6704, and a sealing material 6705.

  In addition, cost can be reduced by using amorphous silicon for the semiconductor layer of the transistor in the pixel portion 6812. Further, a large display panel can be manufactured.

  Further, the second scan line driver circuit, the first scan line driver circuit, and the signal line driver circuit are not necessarily provided in the row direction and the column direction of the pixels. For example, the peripheral drive circuit 6901 formed on the IC chip as shown in FIG. 30A is replaced with the first scan line drive circuit 6814, the second scan line drive circuit 6813, and the signal shown in FIG. The function of the line driver circuit 6811 may be provided. Note that the substrate 6900, the pixel portion 6902, the FPC 6904, the IC chip 6905, the IC chip 6906, the sealing substrate 6907, and the sealant 6908 in FIG. 30A are the substrate 6710, the pixel portion 6702, the FPC 6709, and the IC in FIG. It corresponds to a chip 6718, an IC chip 6719, a sealing substrate 6704, and a sealing material 6705.

  FIG. 30B is a schematic diagram for explaining the wiring connection of the display device in FIG. A substrate 6910, a peripheral driver circuit 6911, a pixel portion 6912, an FPC 6913, and an FPC 6914 are provided. An external signal and a power supply potential are input from the FPC 6913 to the peripheral driver circuit 6911. The output from the peripheral driver circuit 6911 is input to wirings in the row and column directions connected to the pixels included in the pixel portion 6912.

  Further, examples of light-emitting elements applicable to the light-emitting element 6725 are illustrated in FIGS. That is, a structure of a light-emitting element applicable to the pixel described in the above embodiment mode is described with reference to FIGS.

  A light emitting element in FIG. 31A includes an anode 7002 on a substrate 7001, a hole injection layer 7003 made of a hole injection material, a hole transport layer 7004 made of a hole transport material, a light emitting layer 7005, and an electron. In this element structure, an electron transport layer 7006 made of a transport material, an electron injection layer 7007 made of an electron injection material, and a cathode 7008 are stacked. Here, the light emitting layer 7005 may be formed of only one kind of light emitting material, but may be formed of two or more kinds of materials. Further, the structure of the element of the present invention is not limited to this structure.

  In addition to the layered structure in which the functional layers shown in FIG. 31A are stacked, an element using a polymer compound, a high-efficiency element using a triplet light emitting material that emits light from a triplet excited state in the light emitting layer, and the like. There are a wide variety of variations. The present invention can also be applied to a white light emitting element obtained by controlling the carrier recombination region by the hole blocking layer and dividing the light emitting region into two regions.

  In the element manufacturing method of the present invention shown in FIG. 31A, first, a hole injecting material, a hole transporting material, and a light emitting material are applied to a substrate 7001 having an anode 7002 (indium tin oxide (ITO)). Evaporate sequentially. Next, an electron transport material and an electron injection material are vapor-deposited, and finally a cathode 7008 is formed by vapor deposition.

  Next, materials suitable for the hole injection material, the hole transport material, the electron transport material, the electron injection material, and the light emitting material are listed below.

As the hole injection material, porphyrin compounds, phthalocyanine (hereinafter referred to as “H ₂ Pc”), copper phthalocyanine (hereinafter referred to as “CuPc”), and the like are effective as organic compounds. In addition, any material that has a smaller ionization potential than the hole transport material used and has a hole transport function can also be used as the hole injection material. There is also a material obtained by chemically doping a conductive polymer compound, and examples thereof include polyethylenedioxythiophene (hereinafter referred to as “PEDOT”) doped with polystyrene sulfonic acid (hereinafter referred to as “PSS”), polyaniline, and the like. An insulating polymer compound is also effective in terms of planarization of the anode, and polyimide (hereinafter referred to as “PI”) is often used. In addition, inorganic compounds are also used. In addition to metal thin films such as gold and platinum, there are ultra thin films of aluminum oxide (hereinafter referred to as “alumina”).

  The most widely used hole transport material is an aromatic amine-based compound (that is, a compound having a benzene ring-nitrogen bond). As widely used materials, 4,4′-bis (diphenylamino) -biphenyl (hereinafter referred to as “TAD”) and its derivative 4,4′-bis [N- (3-methylphenyl) -N-phenyl-amino] -biphenyl (hereinafter referred to as “TPD”), 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (hereinafter referred to as “α-NPD”) ). 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (hereinafter referred to as “TDATA”), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) And starburst aromatic amine compounds such as —N-phenyl-amino] -triphenylamine (hereinafter referred to as “MTDATA”).

As an electron transport material, a metal complex is often used, and Alq ₃ , BAlq, tris (4-methyl-8-quinolinolato) aluminum (hereinafter referred to as “Almq”), bis (10-hydroxybenzo [ h] -quinolinato) beryllium (hereinafter referred to as “Bebq”) and the like, and metal complexes having a quinoline skeleton or a benzoquinoline skeleton. Further, bis [2- (2-hydroxyphenyl) -benzoxazolate] zinc (hereinafter referred to as “Zn (BOX) ₂ ”), bis [2- (2-hydroxyphenyl) -benzothiazolate] zinc (hereinafter referred to as “Zn (BOX) ₂ ”) There is also a metal complex having an oxazole-based or thiazole-based ligand such as “Zn (BTZ) ₂ ”). In addition to metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (hereinafter referred to as “PBD”), OXD-7, and the like Oxadiazole derivative of TAZ, 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -2,3,4-triazole (hereinafter referred to as “p-EtTAZ”) ) And other phenanthroline derivatives such as bathophenanthroline (hereinafter referred to as “BPhen”) and BCP have electron transport properties.

  The electron transport material described above can be used as the electron injection material. In addition, an ultra-thin film of an insulator such as a metal halide such as calcium fluoride, lithium fluoride, or cesium fluoride, or an alkali metal oxide such as lithium oxide is often used. In addition, alkali metal complexes such as lithium acetylacetonate (hereinafter referred to as “Li (acac)”) and 8-quinolinolato-lithium (hereinafter referred to as “Liq”) are also effective.

As the luminescent material, various fluorescent dyes are effective in addition to the metal complexes such as Alq ₃ , Almq, BeBq, BAlq, Zn (BOX) ₂ , Zn (BTZ) _{2 described} above. As fluorescent dyes, blue 4,4′-bis (2,2-diphenyl-vinyl) -biphenyl and red-orange 4- (dicyanomethylene) -2-methyl-6- (p-dimethylaminostyryl)- 4H-pyran. A triplet light emitting material is also possible, and is mainly a complex having platinum or iridium as a central metal. As the triplet light emitting material, tris (2-phenylpyridine) iridium, bis (2- (4′-tolyl) pyridinato-N, C ^{2 ′} ) acetylacetonatoiridium (hereinafter referred to as “acacIr (tpy) ₂ ”), 2,3,7,8,23,13,17,18-octaethyl-21H, 23H porphyrin-platinum and the like are known.

  A highly reliable light-emitting element can be manufactured by combining the materials having the functions described above.

  If possible with the pixel structure of the above embodiment mode, a light-emitting element in which layers are formed in the reverse order of FIG. 31A may be used as shown in FIG. That is, a cathode 7018 on the substrate 7011, an electron injection layer 7017 made of an electron injection material, an electron transport layer 7016 made of an electron transport material, a light emitting layer 7015, a hole transport layer 7014 made of a hole transport material, and a positive electrode. This is an element structure in which a hole injection layer 7013 made of a hole injection material and an anode 7012 are laminated.

  In addition, in order to extract light emitted from the light emitting element, at least one of the anode and the cathode may be transparent. Then, a TFT and a light emitting element are formed on the substrate, and a top emission that extracts light emission from a surface opposite to the substrate, a bottom emission that extracts light emission from the surface on the substrate side, and a surface opposite to the substrate side and the substrate. The pixel structure of the present invention can be applied to a light emitting element having any emission structure.

  A light-emitting element having a top emission structure will be described with reference to FIG.

  A driving TFT 7101 is formed over a substrate 7100, a first electrode 7102 is formed in contact with a source electrode of the driving TFT 7101, and a layer 7103 containing an organic compound and a second electrode 7104 are formed thereover.

  The first electrode 7102 is an anode of the light emitting element. The second electrode 7104 is a cathode of the light emitting element. That is, a region where the layer 7103 containing an organic compound is sandwiched between the first electrode 7102 and the second electrode 7104 is a light-emitting element.

  Here, as a material used for the first electrode 7102 which functions as an anode, a material having a high work function is preferably used. For example, in addition to a single layer film such as a titanium nitride film, a chromium film, a tungsten film, a Zn film, or a Pt film, a stack of a titanium nitride film and a film containing aluminum as a main component, a titanium nitride film and aluminum as a main component A three-layer structure of a film and a titanium nitride film can be used. Note that with a stacked structure, resistance as a wiring is low, good ohmic contact can be obtained, and a function as an anode can be obtained. By using a metal film that reflects light, an anode that does not transmit light can be formed.

The material used for the second electrode 7104 functioning as a cathode is made of a material having a low work function (Al, Ag, Li, Ca, or an alloy thereof such as MgAg, MgIn, AlLi, CaF ₂ , or calcium nitride). A stack of a metal thin film and a transparent conductive film (indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or the like) is preferably used. Thus, a cathode capable of transmitting light can be formed by using a thin metal thin film and a transparent conductive film having transparency.

  In this manner, light from the light emitting element can be extracted to the upper surface as indicated by an arrow in FIG. That is, when applied to the display panel of FIG. 28, light is emitted to the sealing substrate 6704 side. Therefore, in the case where a light-emitting element having a top emission structure is used for a display device, the sealing substrate 6704 is a light-transmitting substrate.

  In the case where an optical film is provided, an optical film may be provided over the sealing substrate 6704.

  A light-emitting element having a bottom emission structure will be described with reference to FIG. Since the light-emitting element has the same structure as that shown in FIG.

  Here, as a material used for the first electrode 7102 functioning as an anode, a material having a high work function is preferably used. For example, a transparent conductive film such as an indium tin oxide (ITO) film or an indium zinc oxide (IZO) film can be used. By using a transparent conductive film having transparency, an anode capable of transmitting light can be formed.

As a material used for the second electrode 7104 functioning as a cathode, a material having a low work function (Al, Ag, Li, Ca, or an alloy thereof such as MgAg, MgIn, AlLi, CaF ₂ , or Ca ₃ N ₂ ) is used. A metal film made of can be used. Thus, by using a metal film that reflects light, a cathode that does not transmit light can be formed.

  As described above, light from the light emitting element can be extracted to the lower surface as indicated by an arrow in FIG. That is, when applied to the display panel of FIG. 28, light is emitted to the substrate 6710 side. Therefore, in the case where a light-emitting element having a bottom emission structure is used for a display device, the substrate 6710 is a light-transmitting substrate.

  In the case of providing an optical film, the substrate 6710 may be provided with an optical film.

  A light-emitting element having a dual emission structure will be described with reference to FIG. Since the light-emitting element has the same structure as that shown in FIG.

  Here, as a material used for the first electrode 7102 functioning as an anode, a material having a high work function is preferably used. For example, a transparent conductive film such as an indium tin oxide (ITO) film or an indium zinc oxide (IZO) film can be used. By using a transparent conductive film having transparency, an anode capable of transmitting light can be formed.

The material used for the second electrode 7104 functioning as a cathode is made of a material having a low work function (Al, Ag, Li, Ca, or an alloy thereof such as MgAg, MgIn, AlLi, CaF ₂ , or calcium nitride). A stack of a metal thin film and a transparent conductive film (such as indium tin oxide (ITO), indium zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (ZnO)) is preferably used. Thus, a cathode capable of transmitting light can be formed by using a thin metal thin film and a transparent conductive film having transparency.

  In this manner, light from the light emitting element can be extracted on both sides as indicated by arrows in FIG. That is, when applied to the display panel in FIG. 28, light is emitted to the substrate 6710 side and the sealing substrate 6704 side. Therefore, when a light-emitting element having a dual emission structure is used for a display device, both the substrate 6710 and the sealing substrate 6704 are light-transmitting substrates.

  In the case where an optical film is provided, the optical film may be provided on both the substrate 6710 and the sealing substrate 6704.

  In addition, the present invention can be applied to a display device that realizes full color display using a white light emitting element and a color filter.

  As shown in FIG. 33, a base film 7202 is formed over a substrate 7200, a driving TFT 7201 is formed thereon, a first electrode 7203 is formed in contact with the source electrode of the driving TFT 7201, and an organic film is formed thereon. A layer 7204 containing a compound and a second electrode 7205 are formed.

  The first electrode 7203 is an anode of the light emitting element. The second electrode 7205 is a cathode of the light emitting element. That is, a region where the layer 7204 containing an organic compound is sandwiched between the first electrode 7203 and the second electrode 7205 is a light-emitting element. In the configuration of FIG. 33, white light is emitted. A red color filter 7206R, a green color filter 7206G, and a blue color filter 7206B are provided above the light-emitting element, so that full color display can be performed. In addition, a black matrix (also referred to as BM) 7207 for separating these color filters is provided.

  The above-described structures of the light-emitting elements can be used in combination and can be used as appropriate for a display device having the pixel structure of the present invention. Further, the structure of the display panel and the light emitting element in this specification are examples, and the pixel structure of the present invention can be applied to display devices having other structures.

  Next, a partial cross-sectional view of a pixel portion of the display panel is shown.

  First, the case where an amorphous silicon (a-Si: H) film is used for a semiconductor layer of a transistor will be described. FIG. 34 shows a case of a top gate transistor, and FIGS. 35 and 36 show a case of a bottom gate transistor.

  FIG. 34A shows a cross section of a transistor having a forward stagger structure using amorphous silicon as a semiconductor layer. As shown in FIG. 34A, a base film 7602 is formed on a substrate 7601. Further, a pixel electrode 7603 is formed over the base film 7602. In addition, a first electrode 7604 made of the same material is formed in the same layer as the pixel electrode 7603.

As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, a plastic substrate, or the like can be used. The base film 7602 can be formed using a single layer such as aluminum nitride (AlN), silicon oxide (SiO ₂ ), or silicon oxynitride (SiO _x N _y ), or a stacked layer thereof.

  Further, a wiring 7605 and a wiring 7606 are formed over the base film 7602, and an end portion of the pixel electrode 7603 is covered with the wiring 7605. An N-type semiconductor layer 7607 and an N-type semiconductor layer 7608 having an N-type conductivity are formed over the wirings 7605 and 7606. A semiconductor layer 7609 is formed between the wiring 7605 and the wiring 7606 and over the base film 7602. A part of the semiconductor layer 7609 extends to the N-type semiconductor layer 7607 and the N-type semiconductor layer 7608. Note that this semiconductor layer is formed of an amorphous semiconductor film such as amorphous silicon (a-Si: H) or microcrystalline semiconductor (μ-Si: H). In addition, a gate insulating film 7610 is formed over the semiconductor layer 7609. In addition, an insulating film 7611 made of the same material as the gate insulating film 7610 is formed over the first electrode 7604. Note that a silicon oxide film, a silicon nitride film, or the like is used as the gate insulating film 7610.

  A gate electrode 7612 is formed over the gate insulating film 7610. A second electrode 7613 made of the same material and in the same layer as the gate electrode is formed over the first electrode 7604 with an insulating film 7611 interposed therebetween. A capacitor element 7619 in which an insulating film 7611 is sandwiched between the first electrode 7604 and the second electrode 7613 is formed. Further, an interlayer insulator 7614 is formed so as to cover an end portion of the pixel electrode 7603, the driving transistor 7618, and the capacitor 7619.

  A region 7615 containing an organic compound and a counter electrode 7616 are formed over the interlayer insulator 7614 and the pixel electrode 7603 located in the opening, and the layer 7615 containing an organic compound is sandwiched between the pixel electrode 7603 and the counter electrode 7616 Then, a light emitting element 7617 is formed.

  Alternatively, the first electrode 7604 illustrated in FIG. 34A may be formed using the first electrode 7620 as illustrated in FIG. The first electrode 7620 is formed using the same material as the wirings 7605 and 7606.

  FIG. 35 shows a partial cross section of a display panel using a bottom-gate transistor using amorphous silicon as a semiconductor layer.

  A base film 7702 is formed over the substrate 7701. Further, a gate electrode 7703 is formed over the base film 7702. In addition, a first electrode 7704 made of the same material is formed in the same layer as the gate electrode 7703. As a material for the gate electrode 7703, polycrystalline silicon to which phosphorus is added can be used. In addition to polycrystalline silicon, silicide which is a compound of metal and silicon may be used.

  A gate insulating film 7705 is formed so as to cover the gate electrode 7703 and the first electrode 7704. As the gate insulating film 7705, a silicon oxide film, a silicon nitride film, or the like is used.

  In addition, a semiconductor layer 7706 is formed over the gate insulating film 7705. In addition, a semiconductor layer 7707 made of the same material is formed in the same layer as the semiconductor layer 7706.

As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, a plastic substrate, or the like can be used. The base film 7602 can be formed using a single layer such as aluminum nitride (AlN), silicon oxide (SiO ₂ ), or silicon oxynitride (SiO _x N _y ), or a stacked layer thereof.

  N-type semiconductor layers 7708 and 7709 having N-type conductivity are formed over the semiconductor layer 7706, and an N-type semiconductor layer 7710 is formed over the semiconductor layer 7707.

  Wirings 7711 and 7712 are formed over the N-type semiconductor layers 7708 and 7709, respectively, and a conductive layer 7713 made of the same material as the wirings 7711 and 7712 is formed over the N-type semiconductor layer 7710.

  A second electrode including the semiconductor layer 7707, the N-type semiconductor layer 7710, and the conductive layer 7713 is formed. Note that a capacitor 7720 having a structure in which the gate insulating film 7705 is sandwiched between the second electrode and the first electrode 7704 is formed.

  In addition, one end portion of the wiring 7711 extends, and a pixel electrode 7714 is formed in contact with the upper portion of the extended wiring 7711.

  In addition, an insulator 7715 is formed so as to cover an end portion of the pixel electrode 7714, the driving transistor 7719, and the capacitor 7720.

  A layer 7716 containing an organic compound and a counter electrode 7717 are formed over the pixel electrode 7714 and the insulator 7715, and a light-emitting element 7718 is formed in a region where the layer 7716 containing an organic compound is interposed between the pixel electrode 7714 and the counter electrode 7717. Has been.

  The semiconductor layer 7707 and the N-type semiconductor layer 7710 which are part of the second electrode of the capacitor 7720 are not necessarily provided. That is, the capacitor may have a structure in which the second electrode is the conductive layer 7713 and the gate insulating film is sandwiched between the first electrode 7704 and the conductive layer 7713.

  Note that in FIG. 35A, the pixel electrode 7714 is formed before the wiring 7711 is formed, so that the second electrode 7721 and the first electrode including the pixel electrode 7714 as illustrated in FIG. A capacitor 7720 having a structure in which the gate insulating film 7705 is sandwiched between 7704 can be formed.

  Note that although an inverted staggered channel-etched transistor is shown in FIG. 35, a channel protective transistor may be used as a matter of course. The case of a transistor with a channel protective structure will be described with reference to FIGS.

  The transistor having the channel protective structure shown in FIG. 36A is an insulator serving as an etching mask over the region where the channel of the semiconductor layer 7706 of the driving transistor 7719 having the channel etch structure shown in FIG. The difference is that 7801 is provided, and other common parts use common reference numerals.

  Similarly, the transistor having the channel protection structure shown in FIG. 36B is etched on the region where the channel of the semiconductor layer 7706 of the driving transistor 7719 having the channel etch structure shown in FIG. A difference is that an insulator 7802 serving as a mask is provided, and common points are used for other common points.

  Note that the structure of the transistor and the structure of the capacitor which can be applied to the pixel structure of the present invention are not limited to the above structures, and various structures of transistors and structures of the capacitor can be used.

  By using the pixel configuration of the present invention, it is possible to suppress an initial failure and a progressive failure of a light emitting element, and to prevent a decrease in luminance due to deterioration of an electroluminescent layer. Further, by using an amorphous semiconductor film for a semiconductor layer (a channel formation region, a source region, a drain region, or the like) of a transistor included in the pixel of the present invention, manufacturing cost can be reduced.

  Note that this embodiment can be implemented in combination with the embodiment in this specification and other examples.

  FIG. 42 shows a layout diagram of the pixel configuration of FIG.

  42 includes a signal line 10001, a power supply line 10002, a scanning line 10003, a switching transistor 10004, a driving transistor 10005, a pixel electrode 10006, an alternating current transistor 10007, and a potential control line 10008. Corresponds to each.

  Note that the display device of the present invention is not limited to the layout configuration of this embodiment.

  By using the pixel configuration of the present invention, when a forward light emitting element driving voltage is applied to the light emitting element, a constant current can flow through the light emitting element, and the light emitting element is driven in the reverse direction. When a voltage is applied, a current sufficient to insulate the short-circuited portion can be supplied to the short-circuited portion, and the life of the light emitting element can be extended. In addition, since the circuit configuration can be constituted by a unipolar transistor, it can be manufactured at low cost.

  Although this embodiment uses the circuit configuration of FIG. 1 of the first embodiment described above, the present invention is not limited to this and can be combined with other embodiments and other examples.

  The display device of the present invention can be applied to various electronic devices. Specifically, it can be applied to a display portion of an electronic device. Such electronic devices include video cameras, digital cameras, goggles-type displays, navigation systems, sound playback devices (car audio, audio components, etc.), computers, game devices, portable information terminals (mobile computers, mobile phones, portable games) Or an image reproducing apparatus (specifically, an apparatus having a display capable of reproducing a recording medium such as a digital versatile disc (DVD) and displaying the image). .

  FIG. 43A illustrates a display, which includes a housing 84101, a support base 84102, a display portion 84103, and the like. A display device having the pixel structure of the present invention can be used for the display portion 84103. The display includes all display devices for displaying information such as for personal computers, for receiving television broadcasts, and for displaying advertisements. A display using the display device having the pixel structure of the invention for the display portion 84103 can prevent display failure and extend the lifetime of the light-emitting element. In addition, cost reduction can be achieved.

  In recent years, there is an increasing need for larger displays. As the display becomes larger, the price increases, so the problem is how to reduce the manufacturing cost and keep high-quality products at a low price.

  For example, by using the pixel structure described in the above embodiment for a pixel portion of the display panel, a display panel including a unipolar transistor can be provided. Therefore, the number of steps can be reduced and the manufacturing cost can be reduced.

  Further, as shown in FIG. 28A, a pixel panel and a peripheral driver circuit are integrally formed, whereby a display panel including a circuit formed of a unipolar transistor can be formed.

  Further, by using an amorphous semiconductor (eg, amorphous silicon (a-Si: H)) for a semiconductor layer of a transistor in a circuit included in the pixel portion, the process can be simplified and further cost reduction can be achieved. In this case, as shown in FIGS. 29B and 30A, a driver circuit around the pixel portion may be formed on the IC chip and mounted on the display panel by COG or the like. Thus, the use of an amorphous semiconductor makes it easy to increase the size of the display.

FIG. 43B shows a camera, which includes a main body 84201, a display portion 84202, an image receiving portion 84203, operation keys 84204, an external connection port 84205, a shutter 84206, and the like.

  In recent years, production competition has intensified along with the improvement in performance of digital cameras and the like. And how to keep high-performance products at low prices is important. A digital camera using the display device having the pixel structure of the invention for the display portion 84202 can prevent a display defect and extend the lifetime of the light-emitting element. In addition, cost reduction can be achieved.

  For example, by using the pixel structure of the above embodiment for a pixel portion, a pixel portion formed of a unipolar transistor can be formed. In addition, as shown in FIG. 29A, a signal line driver circuit with a high operating speed is formed on an IC chip, and a scanning line driver circuit with a relatively low operating speed is formed of a unipolar transistor together with a pixel portion. By integrally forming the circuit, high performance can be realized and cost can be reduced. Further, by applying an amorphous semiconductor, for example, amorphous silicon, to a semiconductor portion of a transistor used in a pixel portion and a scan line driver circuit which is integrally formed with the pixel portion, cost can be further reduced.

  FIG. 43C illustrates a computer, which includes a main body 84301, a housing 84302, a display portion 84303, a keyboard 84304, an external connection port 84305, a pointing mouse 84306, and the like. A computer using the display device having the pixel structure of the invention for the display portion 84303 can prevent a display defect and extend the lifetime of the light-emitting element. In addition, cost reduction can be achieved.

  FIG. 43D illustrates a mobile computer, which includes a main body 84401, a display portion 84402, a switch 84403, operation keys 84404, an infrared port 84405, and the like. A mobile computer using the display device having the pixel structure of the invention for the display portion 84402 can prevent a display defect and extend the lifetime of the light-emitting element. In addition, cost reduction can be achieved.

  FIG. 43E shows a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 84501, a housing 84502, a display portion A 84503, a display portion B 84504, and a recording medium (DVD or the like). A reading portion 84505, an operation key 84506, a speaker portion 84507, and the like are included. The display portion A 84503 can mainly display image information, and the display portion B 84504 can mainly display character information. An image reproducing device using the display device having the pixel structure of the present invention for the display portion A 84503 or the display portion B 84504 can prevent display defects and extend the lifetime of the light-emitting element. In addition, cost reduction can be achieved.

  FIG. 43F illustrates a goggle type display which includes a main body 84601, a display portion 84602, earphones 84603, and a support portion 84604. A goggle type display using the display device having the pixel structure of the present invention for the display portion 84602 can prevent a display defect and extend the lifetime of the light-emitting element. In addition, cost reduction can be achieved.

  FIG. 43G illustrates a portable game machine including a housing 84701, a display portion 84702, speaker portions 84703, operation keys 84704, a storage medium insert portion 84705, and the like. A portable game machine using the display device having the pixel structure of the invention for the display portion 84702 can prevent a display defect and extend the lifetime of the light-emitting element. In addition, cost reduction can be achieved.

  FIG. 43H illustrates a digital camera with a television receiving function, which includes a main body 84801, a display portion 84802, operation keys 84803, speakers 84804, a shutter 84805, an image receiving portion 84806, an antenna 84807, and the like. A digital camera with a television receiver function using the display device having the pixel structure of the present invention for the display portion 84802 can prevent a display defect and extend the lifetime of the light-emitting element. In addition, the pixel aperture ratio is high, and high-detail display is possible. In addition, cost reduction can be achieved.

  For example, by using the pixel configuration in the above embodiment for a pixel portion, the aperture ratio of the pixel can be improved. Specifically, the aperture ratio is improved by using an N-channel transistor as a driving transistor for driving the light-emitting element. Therefore, a digital camera with a television receiving function having a high-definition display portion can be provided.

  As described above, a digital camera with a multi-function television receiving function is required to be usable for a long time by one charge while being frequently used for viewing a television.

  For example, as shown in FIGS. 29B and 30A, it is possible to reduce power consumption by forming a peripheral drive circuit on an IC chip and using a CMOS or the like.

  Thus, the present invention can be applied to all electronic devices.

  Note that this example can be implemented in combination with any of the other embodiments and examples in this specification.

In this embodiment, a structure example of a mobile phone having a display device using the pixel structure of the present invention in a display portion will be described with reference to FIG.

  The display panel 8301 is incorporated in a housing 8330 so as to be detachable. The shape and size of the housing 8330 can be changed as appropriate in accordance with the size of the display panel 8301. A housing 8330 to which the display panel 8301 is fixed is fitted into a printed board 8331 and assembled as a module.

  The display panel 8301 is connected to the printed board 8331 through the FPC 8313. A signal processing circuit 8335 including a speaker 8332, a microphone 8333, a transmission / reception circuit 8334, a CPU, a controller, and the like is formed over the printed board 8331. Such a module is combined with the input means 8336 and the battery 8337 and stored in the housing 8339. The pixel portion of the display panel 8301 is arranged so that it can be seen from an opening window formed in the housing 8339.

  In the display panel 8301, a pixel portion and some peripheral driver circuits (a driver circuit having a low operating frequency among a plurality of driver circuits) are integrally formed using a TFT over a substrate, and some peripheral driver circuits (a plurality of driver circuits) are formed. A driving circuit having a high operating frequency among the circuits) may be formed over the IC chip, and the IC chip may be mounted on the display panel 8301 by COG (Chip On Glass). Alternatively, the IC chip may be connected to the glass substrate using TAB (Tape Auto Bonding) or a printed board. Note that FIG. 28A shows an example of the configuration of a display panel in which some peripheral drive circuits are formed integrally with a pixel portion on a substrate and an IC chip on which other peripheral drive circuits are formed is mounted by COG or the like. is there. With such a structure, the power consumption of the display device can be reduced, and the usage time by one charge of the mobile phone can be extended. In addition, the cost of the mobile phone can be reduced.

  The pixel structure described in the above embodiment can be applied as appropriate to the pixel portion.

  For example, in order to realize cost reduction by applying the pixel configuration shown in the above embodiment mode, the peripheral driving circuit formed integrally with the pixel portion and the pixel portion is configured with a unipolar transistor, thereby reducing the manufacturing process. Can be achieved.

  In order to further reduce power consumption, as shown in FIGS. 29B and 30A, a pixel portion is formed on a substrate using TFTs, and all peripheral drive circuits are formed on an IC chip. Then, the IC chip may be mounted on the display panel by COG (Chip On Glass) or the like. In the pixel portion, the pixel structure of the above embodiment mode is used, and an amorphous semiconductor film is used for a semiconductor layer of the transistor, so that manufacturing cost can be reduced.

  Further, the configuration shown in this embodiment is an example of a mobile phone, and the pixel configuration of the present invention is not limited to the mobile phone having such a configuration, and can be applied to mobile phones having various configurations.

  Note that this embodiment can be implemented in combination with the embodiment mode and other embodiments in this specification.

  In this embodiment, an example of a structure of an electronic device having a display device using the pixel structure of the present invention in a display portion, particularly a television receiver including an EL module will be described.

  FIG. 45 shows an EL module in which a display panel 7901 and a circuit board 7911 are combined. A display panel 7901 includes a pixel portion 7902, a scan line driver circuit 7903, and a signal line driver circuit 7904. On the circuit board 7911, for example, a control circuit 7912, a signal dividing circuit 7913, and the like are formed. The display panel 7901 and the circuit board 7911 are connected by a connection wiring 7914. An FPC or the like can be used for the connection wiring.

  In the display panel 7901, a pixel portion and some peripheral driver circuits (a driver circuit having a low operating frequency among a plurality of driver circuits) are integrally formed using a TFT over a substrate, and some peripheral driver circuits (a plurality of driver circuits) are formed. A driver circuit having a high operating frequency among the circuits) is formed over the IC chip, and the IC chip is preferably mounted on the display panel 7901 with COG (Chip On Glass) or the like. Alternatively, the IC chip may be mounted on the display panel 7901 using TAB (Tape Auto Bonding) or a printed board. FIG. 28A shows an example of a configuration in which a part of the peripheral drive circuit is formed integrally with the pixel portion on the substrate and the IC chip on which the other peripheral drive circuit is formed is mounted by COG or the like.

  The pixel structure described in the above embodiment can be applied as appropriate to the pixel portion.

For example, by applying the pixel configuration or the like shown in the above embodiment mode, the pixel portion and the peripheral driver circuit formed on the substrate integrated with the pixel portion are configured with a unipolar transistor in order to realize cost reduction. The number of processes can be reduced.

  In order to further reduce power consumption, a pixel portion is formed using a TFT on a glass substrate, all peripheral driving circuits are formed on an IC chip, and the IC chip is a COG (Chip On Glass) display panel. May be implemented.

  In addition, since the pixel can be formed using only the N-channel transistor by applying the pixel structure described in the above embodiment mode, an amorphous semiconductor (eg, amorphous silicon) is used for the semiconductor layer of the transistor. It becomes possible to do. That is, a large display device in which it is difficult to manufacture a uniform crystalline semiconductor film can be manufactured. In addition, by using an amorphous semiconductor film for a semiconductor layer of a transistor included in a pixel, a manufacturing process can be reduced and a manufacturing cost can be reduced.

Note that when an amorphous semiconductor film is applied to a semiconductor layer of a transistor included in a pixel, a pixel portion is formed using a TFT over a substrate, and all peripheral driver circuits are formed over an IC chip. The IC chip may be mounted on the display panel by COG (Chip On Glass). FIG. 29B shows an example of a configuration in which an IC chip in which a pixel portion is formed on a substrate and a peripheral driver circuit is formed on the substrate is mounted by COG or the like.

  With this EL module, an EL television receiver can be completed. FIG. 46 is a block diagram showing the main configuration of an EL television receiver. A tuner 8001 receives a video signal and an audio signal. The video signal includes a video signal amplifying circuit 8002, a video signal processing circuit 8003 that converts a signal output from the video signal into a color signal corresponding to each color of red, green, and blue, and uses the video signal as input specifications of the drive circuit. Processing is performed by a control circuit 8012 for conversion.

  The control circuit 8012 outputs a signal to each of the scan line side (scan line drive circuit 8021) and the signal line side (signal line drive circuit 8004). In the case of digital driving, a signal dividing circuit 8013 may be provided on the signal line side so that an input digital signal is divided into m pieces and supplied. Note that the display panel 8020 receives signals from the scan line driver circuit 8021 and the signal line driver circuit 8004.

  Of the signals received by the tuner 8001, the audio signal is sent to the audio signal amplifier circuit 8005, and the output is supplied to the speaker 8007 via the audio signal processing circuit 8006. The control circuit 8008 receives control information on the receiving station (reception frequency) and volume from the input unit 8009 and sends a signal to the tuner 8001 and the audio signal processing circuit 8006.

  FIG. 47A shows a television receiver in which an EL module of a different form from that in FIG. 46 is incorporated. In FIG. 47A, a display screen 8102 is formed of an EL module. The housing 8101 is appropriately provided with a speaker 8103, an operation switch 8104, and the like.

  FIG. 47B shows a television receiver that can carry only a display wirelessly. A housing and a signal receiver are incorporated in the housing 8112, and the display portion 8113 and the speaker portion 8117 are driven by the battery. The battery can be repeatedly charged by a charger 8110. The charger 8110 can transmit and receive a video signal, and can transmit the video signal to a signal receiver of the display. The housing 8112 is controlled by operation keys 8116. The device illustrated in FIG. 47B can also be referred to as a video / audio two-way communication device because a signal can be transmitted from the housing 8112 to the charger 8110 by operating the operation key 8116. Further, by operating the operation key 8116, a signal is transmitted from the housing 8112 to the charger 8110, and a signal that can be transmitted by the charger 8110 is received by another electronic device, so that communication control of the other electronic device can be performed. It can be said to be a general-purpose remote control device. The present invention can be applied to the display portion 8113.

  FIG. 48A shows a module in which a display panel 8201 and a printed wiring board 8202 are combined. The display panel 8201 includes a pixel portion 8203 provided with a plurality of pixels, a first scan line driver circuit 8204, a second scan line driver circuit 8205, and a signal line driver circuit that supplies a video signal to the selected pixel. 8206 is provided.

  The printed wiring board 8202 is provided with a controller 8207, a central processing unit (CPU 8208), a memory 8209, a power supply circuit 8210, an audio processing circuit 8211, a transmission / reception circuit 8212, and the like. The printed wiring board 8202 and the display panel 8201 are connected by an FPC 8213. The printed wiring board 8202 may be provided with a capacitor, a buffer circuit, or the like so that noise is added to the power supply voltage or the signal or the rise of the signal is not slowed. In addition, the controller 8207, the audio processing circuit 8211, the memory 8209, the CPU 8208, the power supply circuit 8210, and the like can be mounted on the display panel 8201 using a COG (Chip On Glass) method. The scale of the printed wiring board 8202 can be reduced by the COG method.

  Various control signals are input / output through an interface (I / F) 8214 provided on the printed wiring board 8202. In addition, an antenna port 8215 for transmitting and receiving signals to and from the antenna is provided on the printed wiring board 8202.

  FIG. 48B is a block diagram of the module shown in FIG. This module includes a VRAM 8216, DRAM 8217, flash memory 8218, and the like as the memory 8209. The VRAM 8216 stores image data to be displayed on the panel, the DRAM 8217 stores image data or audio data, and the flash memory stores various programs.

  The power supply circuit 8210 supplies power for operating the display panel 8201, the controller 8207, the CPU 8208, the sound processing circuit 8211, the memory 8209, and the transmission / reception circuit 8212. Depending on the specifications of the panel, the power supply circuit 8210 may be provided with a current source.

  The CPU 8208 includes a control signal generation circuit 8220, a decoder 8221, a register 8222, an arithmetic circuit 8223, a RAM 8224, an interface 8219 for the CPU 8208, and the like. Various signals input to the CPU 8208 through the interface 8219 are temporarily stored in the register 8222 and then input to the arithmetic circuit 8223, the decoder 8221, and the like. The arithmetic circuit 8223 performs an operation based on the input signal and designates a place to send various commands. On the other hand, the signal input to the decoder 8221 is decoded and input to the control signal generation circuit 8220. The control signal generation circuit 8220 generates a signal including various commands based on the input signal, and a location specified in the arithmetic circuit 8223, specifically, a memory 8209, a transmission / reception circuit 8212, an audio processing circuit 8211, a controller 8207, and the like. Send to.

  The memory 8209, the transmission / reception circuit 8212, the audio processing circuit 8211, and the controller 8207 operate according to the received commands. The operation will be briefly described below.

  A signal input from the input unit 8225 is sent to the CPU 8208 mounted on the printed wiring board 8202 via the I / F 8214. The control signal generation circuit 8220 converts the image data stored in the VRAM 8216 into a predetermined format in accordance with a signal sent from the input device 8225 such as a pointing device or a keyboard, and sends it to the controller 8207.

  The controller 8207 performs data processing on a signal including image data sent from the CPU 8208 in accordance with the panel specifications, and supplies the processed signal to the display panel 8201. Further, the controller 8207 generates an Hsync signal, a Vsync signal, a clock signal CLK, an AC voltage (AC Cont), and a switching signal L / R based on the power supply voltage input from the power supply circuit 8210 and various signals input from the CPU 8208. Generated and supplied to the display panel 8201.

  In the transmission / reception circuit 8212, signals transmitted / received as radio waves in the antenna 8228 are processed. Specifically, high-frequency signals such as isolators, band-pass filters, VCOs (Voltage Controlled Oscillators), LPFs (Low Pass Filters), couplers, and baluns are used. Includes circuitry. A signal including audio information among signals transmitted and received in the transmission / reception circuit 8212 is sent to the audio processing circuit 8211 in accordance with a command from the CPU 8208.

  A signal including audio information sent in accordance with a command from the CPU 8208 is demodulated into an audio signal by the audio processing circuit 8211 and sent to the speaker 8227. The audio signal sent from the microphone 8226 is modulated by the audio processing circuit 8211 and sent to the transmission / reception circuit 8212 in accordance with a command from the CPU 8208.

  The controller 8207, the CPU 8208, the power supply circuit 8210, the sound processing circuit 8211, and the memory 8209 can be mounted as a package of this embodiment.

  Of course, the present invention is not limited to a television receiver, and is applied to various uses as a display medium of a particularly large area such as a monitor of a personal computer, an information display board in a railway station or airport, an advertisement display board in a street, etc. can do.

  As described above, the display device using the pixel structure of the present invention can flow a constant current to the light emitting element when a forward light emitting element driving voltage is applied to the light emitting element. When applying the light-emitting element driving voltage in the direction, a current sufficient to insulate the short-circuited portion can be passed through the short-circuited portion, and the life of the light-emitting element can be extended. In addition, since the circuit configuration can be constituted by a unipolar transistor, it can be manufactured at low cost.

  In addition, an amorphous silicon transistor can be used by manufacturing a transistor having a circuit structure as an N-type transistor. Therefore, since a transistor manufacturing technique using amorphous silicon that has already been established can be applied, a display device with favorable and stable operation characteristics can be obtained with a simple and inexpensive manufacturing process.

  Note that this embodiment can be implemented in combination with the embodiment mode and other embodiments in this specification.

FIG. 10 is a circuit diagram of a pixel used in a display device of the present invention. FIG. 10 is a circuit diagram of a pixel used in a display device of the present invention. FIG. 11 is a diagram showing a timing chart when a digital time gray scale method is performed in the display device of the present invention. FIG. 5 is a timing chart when gradation display is performed in an analog manner in the display device of the present invention. 4A and 4B illustrate a display of the present invention. The figure which shows the structure of the pixel part of the display of this invention. FIG. 10 is a circuit diagram of a pixel used in a display device of the present invention. FIG. 10 is a circuit diagram of a pixel used in a display device of the present invention. FIG. 11 is a diagram showing a timing chart when a digital time gray scale method is performed in the display device of the present invention. FIG. 5 is a timing chart when gradation display is performed in an analog manner in the display device of the present invention. FIG. 10 is a circuit diagram of a pixel used in a display device of the present invention. FIG. 10 is a circuit diagram of a pixel used in a display device of the present invention. FIG. 10 is a circuit diagram of a pixel used in a display device of the present invention. FIG. 11 is a diagram showing a timing chart when a digital time gray scale method is performed in the display device of the present invention. FIG. 5 is a timing chart when gradation display is performed in an analog manner in the display device of the present invention. FIG. 10 is a circuit diagram of a pixel used in a display device of the present invention. FIG. 10 is a circuit diagram of a pixel used in a display device of the present invention. FIG. 10 is a circuit diagram of a pixel used in a display device of the present invention. FIG. 11 is a diagram showing a timing chart when a digital time gray scale method is performed in the display device of the present invention. FIG. 5 is a timing chart when gradation display is performed in an analog manner in the display device of the present invention. FIG. 10 is a circuit diagram of a pixel used in a display device of the present invention. FIG. 10 is a circuit diagram of a pixel used in a display device of the present invention. FIG. 11 is a diagram showing a timing chart when a digital time gray scale method is performed in the display device of the present invention. FIG. 10 is a circuit diagram of a pixel used in a display device of the present invention. FIG. 10 is a circuit diagram of a pixel used in a display device of the present invention. FIG. 10 is a circuit diagram of a pixel used in a display device of the present invention. FIG. 10 is a circuit diagram of a pixel used in a display device of the present invention. 4A and 4B each illustrate a display panel used in a display device of the present invention. 4A and 4B each illustrate a display panel used in a display device of the present invention. 4A and 4B each illustrate a display panel used in a display device of the present invention. 4A and 4B each illustrate a display panel used in a display device of the present invention. 4A and 4B each illustrate a display panel used in a display device of the present invention. 4A and 4B each illustrate a display panel used in a display device of the present invention. 4A and 4B each illustrate a display panel used in a display device of the present invention. 4A and 4B each illustrate a display panel used in a display device of the present invention. 4A and 4B each illustrate a display panel used in a display device of the present invention. FIG. 6 illustrates a configuration of a controller used in a display device of the present invention. 1 is a block diagram illustrating a configuration of a display device of the present invention. The figure which shows the structure of the display controller used with the display apparatus of this invention. FIG. 14 illustrates a structure of a source signal line driver circuit used in a display device of the present invention. FIG. 11 illustrates a structure of a gate signal line driver circuit used in a display device of the present invention. The layout drawing of the pixel of this invention. 4A and 4B each illustrate an electronic device to which a display device of the present invention can be applied. 4A and 4B each illustrate an electronic device to which a display device of the present invention can be applied. 4A and 4B each illustrate an electronic device to which a display device of the present invention can be applied. 4A and 4B each illustrate an electronic device to which a display device of the present invention can be applied. 4A and 4B each illustrate an electronic device to which a display device of the present invention can be applied. 4A and 4B each illustrate an electronic device to which a display device of the present invention can be applied.

Claims (3)

A first wiring, a second wiring, a third wiring, a fourth wiring,
A light emitting device having a pixel electrode and a counter electrode;
A first transistor that controls input of a video signal;
A second transistor for controlling a current flowing from the pixel electrode of the light emitting element to the counter electrode;
A third transistor for controlling a current flowing from the counter electrode of the light emitting element to the pixel electrode;
A gate electrode of the first transistor is electrically connected to the first wiring;
One of a source electrode or a drain electrode of the first transistor is electrically connected to the second wiring for supplying the video signal, and the other is electrically connected to a gate electrode of the second transistor,
One of a source electrode and a drain electrode of the second transistor is electrically connected to the third wiring, and the other is electrically connected to the pixel electrode;
One of a source electrode and a drain electrode of the third transistor is electrically connected to the pixel electrode and a gate electrode of the third transistor, and the other is electrically connected to the fourth wiring.
The first transistor, the second transistor, and the third transistor are N-channel transistors,
The potential of the third wiring is higher than that of the counter electrode,
The display device is characterized in that the potential of the fourth wiring is higher than the potential of the counter electrode in the writing period, higher than the potential of the counter electrode in the display period, and lower than the counter electrode in the reverse bias period . A first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring;
A light emitting device having a pixel electrode and a counter electrode;
A first transistor that controls input of a video signal;
A second transistor for controlling a current flowing from the pixel electrode of the light emitting element to the counter electrode;
A third transistor and a fourth transistor for controlling a current flowing from the counter electrode of the light emitting element to the pixel electrode;
A gate electrode of the first transistor is electrically connected to the first wiring;
One of a source electrode or a drain electrode of the first transistor is electrically connected to the second wiring for supplying the video signal, and the other is electrically connected to a gate electrode of the second transistor,
One of a source electrode and a drain electrode of the second transistor is electrically connected to the third wiring, and the other is electrically connected to the pixel electrode;
One of a source electrode and a drain electrode of the third transistor is electrically connected to a gate electrode of the second transistor, and the other electrode is electrically connected to the pixel electrode;
A gate electrode of the third transistor is electrically connected to the fourth wiring;
One of a source electrode and a drain electrode of the fourth transistor is electrically connected to the pixel electrode and a gate electrode of the fourth transistor, and the other is electrically connected to the fifth wiring.
The first transistor, the second transistor, the third transistor, and the fourth transistor are N-channel transistors,
The potential of the third wiring is higher than the potential of the counter electrode,
The display device characterized in that the potential of the fifth wiring is higher than the potential of the counter electrode in the writing period, higher than the potential of the counter electrode in the display period, and lower than the potential of the counter electrode in the reverse bias period. . In claim 1 or claim 2 ,
By changing the potential of the counter electrode to a fixed potential and changing the potential of the third wiring according to the direction of the current flowing through the light emitting element,
A display device, wherein a magnitude of a current flowing from the counter electrode to the pixel electrode is larger than a magnitude of a current flowing from the pixel electrode to the counter electrode.

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