JP2015181166A - display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device which enables the increase in the electron field-effect mobility of a thin-film transistor, and enables the achievement of a sufficient ON/OFF ratio while suppressing an off current.SOLUTION: A display device comprises: a first conductive layer making a gate electrode of a first transistor including a first oxide semiconductor layer; a second conductive layer making a gate electrode of a second transistor including a second oxide semiconductor layer; a third or fourth conductive layer making a source or drain electrode of the first transistor; a fifth or sixth conductive layer making a source or drain electrode of the second transistor; and a light-emitting element. The second conductive layer is electrically connected with the fourth conductive layer, and the sixth conductive layer is electrically connected with the light-emitting element. The third and fourth conductive layers are in contact with the first oxide semiconductor layer at the upper or lower surface thereof. The fifth and sixth conductive layers are in contact with the second oxide semiconductor layer at the upper or lower surface thereof. The first conductive layer is located over the first oxide semiconductor layer, and the second conductive layer is located over the second oxide semiconductor layer.

Description

The present invention relates to an oxide semiconductor, a thin film transistor using the oxide semiconductor, or a display device using the thin film transistor.

Hydrogenated amorphous silicon (a-Si: H) is mainly used as a material for thin film transistors. Hydrogenated amorphous silicon can deposit a thin film at a low temperature of 300 ° C. or lower, but has a drawback that mobility (field-effect mobility in a thin film transistor) can be obtained only about 1 cm ² / V · sec.

On the other hand, a homologous compound InMO ₃ (ZnO) m (M = In, Fe, Ga, or Al, m = 1 to 50) as an oxide semiconductor material capable of forming a thin film at a low temperature as in a-Si: H. A transparent thin film field effect transistor using a thin film as an active layer is disclosed (see Patent Document 1).

For the channel layer, an amorphous oxide having an electron carrier concentration of less than 10 ¹⁸ / cm ³ is used. The amorphous oxide is an oxide containing In, Ga, and Zn, and has an atomic ratio of In: Ga: A thin film transistor with Zn = 1: 1: m (m <6) is disclosed.

JP 2004-103957 A International Publication No. 05/088726

However, a thin film transistor using a conventional oxide semiconductor has an on / off ratio of only about 10 ³ . That is, even if a predetermined on-current is obtained as a thin film transistor, the off-current increases and it cannot be said that a normally-off transistor is configured, and it does not reach a practical level. If on-off ratio of about 10 ³ is the level that can be easily achieved in a thin film transistor using a conventional amorphous silicon.

Thus, another object is to obtain a sufficient on / off ratio while increasing the field-effect mobility of a thin film transistor and suppressing off-state current.

As an exemplary embodiment, an oxide semiconductor includes In, Ga, and Zn as components, and has a composition in which the concentration of Zn is lower than the concentrations of In and Ga. The oxide semiconductor preferably has an amorphous structure.

As an exemplary embodiment, the oxide semiconductor includes InMO ₃ (ZnO) _m (M = Ga, Fe, Ni
One or more elements selected from Mn, Co and Al, m is a non-integer of 1 to less than 50, and the Zn concentration is from In and M (M = Ga, Fe, Ni, Mn, Co and Al). One or more selected elements). The oxide semiconductor preferably has an amorphous structure.

Here, the value of m is preferably a non-integer of 1 or more and less than 50, more preferably a non-integer of less than 10. The value of m can be a non-integer of 50 or more, but it becomes difficult to maintain an amorphous state as the value of m increases.

As an exemplary embodiment, the thin film transistor includes an oxide semiconductor layer selected from the above embodiments as a channel formation region. It is preferable that an oxide insulating layer be provided in contact with the oxide semiconductor layer. It is a more preferable aspect that the oxide insulating layer is provided on the upper layer side and the lower layer side of the oxide semiconductor layer. It is preferable that a nitride insulating layer be provided outside the oxide semiconductor layer.

As an exemplary embodiment, the display device includes a thin film transistor selected from the above embodiments in at least one pixel.

As an exemplary embodiment, the display device includes the thin film transistor selected from the above embodiments in at least one pixel and a driver circuit that controls a signal sent to the thin film transistor provided in the pixel.

Of In, Ga, and Zn contained as constituent components of an oxide semiconductor, the carrier concentration can be lowered by making the Zn concentration lower than the In and Ga concentrations, and the oxide semiconductor has an amorphous structure. be able to.

By using such an oxide semiconductor layer as a channel formation region, off-state current of the thin film transistor can be reduced and a high on / off ratio can be obtained.

FIG. 14 is a cross-sectional view illustrating a structure of a TFT including an oxide semiconductor layer. FIG. 14 is a cross-sectional view illustrating a structure of a TFT including an oxide semiconductor layer. FIG. 14 is a cross-sectional view illustrating a structure of a TFT including an oxide semiconductor layer. FIG. 14 is a cross-sectional view illustrating a structure of a TFT including an oxide semiconductor layer. FIG. 6 illustrates one embodiment of a display device including a TFT including an oxide semiconductor layer. FIG. 6 is a circuit diagram illustrating a configuration of a selector circuit including a TFT using an oxide semiconductor layer. FIG. 6 is a timing chart illustrating an example of the operation of the selector circuit. FIG. 9 is a block diagram illustrating a shift register including a TFT including an oxide semiconductor layer. FIG. 10 is a circuit diagram illustrating a flip-flop circuit including a TFT including an oxide semiconductor layer. FIG. 6 is an equivalent circuit diagram of a pixel including a TFT using an oxide semiconductor layer and a light-emitting element. FIG. 6 is a plan view illustrating a pixel structure of a light-emitting device including a TFT including an oxide semiconductor layer. FIG. 14 is a cross-sectional view illustrating a pixel structure of a light-emitting device including a TFT including an oxide semiconductor layer. FIG. 10 illustrates a structure of an input terminal portion of a light-emitting device including a TFT including an oxide semiconductor layer. Sectional drawing which shows the structure of the contrast medium display apparatus (electronic paper) comprised by TFT using an oxide semiconductor layer. FIG. 6 is a plan view illustrating a pixel structure of a liquid crystal display device including a TFT including an oxide semiconductor layer. 9 is a cross-sectional view illustrating a pixel structure of a liquid crystal display device including a TFT including an oxide semiconductor layer. The figure which shows the X-ray-diffraction pattern (After film-forming, after 350 degreeC heat processing, after 500 degreeC heat processing) of an oxide semiconductor layer. The graph which shows the characteristic of the gate voltage (Vg) vs. drain current (Id) of a thin-film transistor.

Embodiments of the disclosed invention will be described below with reference to the drawings. However, the disclosed invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the invention. Therefore, the disclosed invention is not construed as being limited to the description of the embodiments below. In the embodiments described below, the same reference numerals may be used in common in different drawings.

(About oxide semiconductor materials)
An exemplary oxide semiconductor material according to this embodiment includes In, Ga, and Zn as constituent components.
Has a lower composition than In and Ga. For example, InMO ₃ (ZnO
) An oxide semiconductor material represented by _m , wherein the Zn concentration is In and M (M = Ga, Fe,
One or more elements selected from Ni, Mn, Co, and Al). In addition to the metal element contained as M, some of the above oxide semiconductors contain Fe, Ni, other transition metal elements, or oxides of the transition metal as impurity elements.

In the oxide semiconductor material represented by the above InMO ₃ (ZnO) _m , m is a non-integer of 1 or more and less than 50. It is known that the composition in the crystalline state is InGaO ₃ (ZnO) _m and m is an integer from 1 to less than 50, but considering the controllability in production, the composition is more InMO ₃ than the composition in which m is an integer. (ZnO) _m is preferable because it is easy to control and has a composition in which m is a non-integer. In order to stably maintain the amorphous structure of the oxide semiconductor material, m is preferably a non-integer.

Here, the value of m is preferably a non-integer of 1 or more and less than 50, more preferably a non-integer of less than 10. The value of m can be a non-integer of 50 or more, but it becomes difficult to maintain an amorphous state as the value of m increases.

InMO ₃ (ZnO) _m (M = one or more elements selected from Ga, Fe, Ni, Mn, Co, and Al, m is a non-integer of 1 to less than 50), and the composition of the oxide semiconductor material When the total of In, M, Zn, and O is 100%, the composition of each element is In
It is preferable to contain less than 20 atomic%, M (for example, Ga) less than 20 atomic%, and Zn less than 10 atomic%. As an oxide semiconductor material containing In, Ga, and Zn, more preferable composition ratios are In and Ga of 15.0 atomic percent to 20.0 atomic percent, and Zn of 5.0 atomic percent to 10.0 atomic percent. Is included.

The structure of the oxide semiconductor is an amorphous structure and is not crystallized even by heat treatment at 500 ° C. in a nitrogen atmosphere. When the heat treatment temperature is increased to 700 ° C., nanocrystals may be generated in the amorphous structure. In any case, the oxide semiconductor is a non-single-crystal semiconductor.

In order to have an amorphous structure as an oxide semiconductor, the concentration of Zn is In and G
The structure is stabilized by making it lower than the concentration of a. More preferably, the ratio of Zn to In and Ga should be less than half. When the proportion of Zn or ZnO increases, crystallization tends to occur, and when the proportion of Zn or ZnO increases, crystallization occurs in the state of film formation by sputtering or the like, or by heat treatment of several hundred degrees. In addition, when the Zn concentration is lower than the In and Ga concentrations, the composition range in which an amorphous structure can be obtained in the oxide semiconductor can be expanded.

(Method for manufacturing oxide semiconductor layer)
An oxide semiconductor layer is formed by physical vapor deposition (Physical Vapor Deposition).
: PVD) method. As a PVD method for manufacturing the oxide semiconductor layer, a sputtering method, a resistance heating vapor deposition method, an electron beam vapor deposition method, an ion beam deposition method, or the like can be applied. In order to facilitate the process, it is preferable to apply a sputtering method.

As a preferable film forming method, oxidation is performed on the substrate while reacting with oxygen using a metal target such as In, M (M = Ga, Fe, Ni, Mn, Co and Al selected from one or a plurality of elements), Zn or the like. Reactive sputtering method for depositing a semiconductor layer, In, M (M = Ga, Fe, Ni
, One or a plurality of elements selected from Mn, Co, and Al), a sputtering method in which an oxide semiconductor layer is deposited on a substrate using a Zn oxide sintered body as a target, or the sintered body as a target A reactive sputtering method is used in which an oxide semiconductor layer is deposited on a substrate while being reacted with oxygen.

As an example of the target used in the sputtering method, In ₂ O ₃ , Ga ₂ O ₃
And a sintered body of ZnO is applicable. The composition ratio of such a target is In ₂
Equivalent proportions of O ₃ , Ga ₂ O ₃ and ZnO or ZnO with respect to In ₂ O ₃ and Ga ₂ O ₃
It is preferable to reduce the ratio. The composition of the oxide semiconductor layer deposited on the substrate varies depending on the sputtering rate of the target material with respect to the sputtering gas, but at least the composition ratio of the target contains In, Ga, and Zn as constituent components. Thus, an oxide semiconductor layer whose concentration is lower than that of In and Ga can be obtained.

Sputtering is performed by applying DC power to the target and generating plasma in the deposition chamber. A pulse direct current (DC) power source is preferable because dust can be reduced and the film thickness can be uniform.

Of In, Ga, and Zn contained as constituent components of an oxide semiconductor, the carrier concentration can be lowered by making the Zn concentration lower than the In and Ga concentrations, and the oxide semiconductor has an amorphous structure. be able to.

(About thin film transistors)
As a substrate for manufacturing a thin film transistor having an oxide semiconductor layer as a channel formation region, a glass substrate, a plastic substrate, a plastic film, or the like can be used. As the glass substrate, glass substrates such as barium borosilicate glass, aluminoborosilicate glass, and aluminosilicate glass can be used. For example, boric acid (
It is preferable to use a glass substrate containing more barium oxide (BaO) than B ₂ O ₃ ) and having a strain point of 730 ° C. or higher. The oxide semiconductor layer can be formed at 200 ° C. or less by a sputtering method, and plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polyimide. A plastic film in which the thickness of the substrate and the plastic material is 200 μm or less can be used.

FIGS. 1A and 1B illustrate an example of a thin film transistor manufactured over the surface of such a substrate 101. Here, FIG. 1A is an example of a plan view of a thin film transistor, and FIG.
Sectional drawing corresponding to a -B1 cutting line is shown.

1A and 1B is a bottom gate type in which a gate electrode 102 and a gate insulating layer 103 are formed from the substrate 101 side, and an oxide semiconductor layer 106 is formed over the gate insulating layer 103. It has the structure of. The source electrode 104 and the drain electrode 105 are provided between the gate insulating layer 103 and the oxide semiconductor layer 106. That is, the gate insulating layer 103, the source electrode 104, and the drain electrode 105 overlap with the gate electrode 102.
Are provided so as to be in contact with a part of the side surface and part of the upper surface. The structure in which the source electrode 104 and the drain electrode 105 are provided over the gate insulating layer 103 has an advantage that the base surface before the oxide semiconductor layer 106 is formed can be cleaned by plasma treatment.

The gate electrode 102 is preferably formed of a refractory metal such as Ti, Mo, Cr, Ta, or W. The gate electrode 102 is provided with an Al film or a layer of a refractory metal typified by Mo, Cr, Ti on the upper layer side of an Al film to which a metal such as Si, Ti, Nd, Sc, or Cu is added. You may have the structure which has.

The gate insulating layer 103 is preferably formed using silicon oxide or nitride such as silicon oxide, silicon nitride, or silicon oxynitride. This is because an OH group can be included in the gate insulating layer 103 and the OH group can act on the oxide semiconductor layer 106. In particular, when the gate insulating layer 103 is formed using silicon oxide, leakage current between the source electrode and the gate electrode of the thin film transistor and between the drain electrode and the gate electrode can be reduced to about 10 ⁻¹⁰ A or less. These insulating layers can be formed by a plasma CVD method or a sputtering method.

For example, as the gate insulating layer 103, a silicon oxide layer can be formed by a CVD method using an organosilane gas. Examples of the organic silane gas include ethyl silicate (TEOS: chemical formula Si (OC ₂ H ₅ ) ₄ ), tetramethylsilane (TMS: chemical formula Si (CH ₃ ) ₄ ), tetramethylcyclotetrasiloxane (TMCTS), and octamethylcyclotetrasiloxane. (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH
Silicon-containing compounds such as (OC ₂ H ₅ ) ₃ ) and trisdimethylaminosilane (SiH (N (CH ₃ ) ₂ ) ₃ ) can be used.

The source electrode 104 and the drain electrode 105 are preferably formed of a refractory metal such as Ti, Mo, Cr, Ta, or W. In particular, it is preferable to use a metal material having a high affinity for oxygen as represented by Ti. This is because an ohmic contact with the oxide semiconductor layer 106 is easily formed. Similar effects can be obtained with Mo in addition to Ti. Etching is preferably performed so that the end surfaces of the source electrode 104 and the drain electrode 105 are tapered. This is because the contact area with the oxide semiconductor layer 106 can be increased. Further, an oxide semiconductor layer having an oxygen deficiency defect (an oxide semiconductor layer having a lower resistance than the oxide semiconductor layer included in the channel formation region) is provided between the source electrode 104 and the drain electrode 105 and the oxide semiconductor layer. It may be provided.

As another embodiment of the source electrode 104 and the drain electrode 105, the electrode includes an Al film or
It has a configuration in which a layer of a refractory metal typified by Mo, Cr, Ti is provided on the upper layer side and / or lower layer side of an Al film to which a metal such as Si, Ti, Nd, Sc, or Cu is added. May be. This is advantageous in forming a wiring for transmitting a signal in the same layer simultaneously with the layer in which the source electrode 104 and the drain electrode 105 are formed. The refractory metal layer provided in contact with the Al film is preferably provided in order to prevent hillocks and whiskers from being generated in the Al film. Hillock is a phenomenon in which swell occurs when Al grows in crystal and the growth components collide with each other. Whisker is a phenomenon in which needle-like growth occurs due to abnormal growth of Al.

The oxide semiconductor layer 106 is formed by a PVD method typified by a sputtering method. As described above, the sputtering target is In, M (M = Ga, Fe, Ni, Mn
, One or a plurality of elements selected from Co and Al), and a sintered body of an oxide of Zn is preferably used. For example, the oxide semiconductor layer is formed by a sputtering method using a sintered body of In ₂ O ₃ , Ga ₂ O _3, and ZnO as a target.

As the sputtering gas, a rare gas typified by argon is used. In order to control oxygen deficiency defects in the oxide semiconductor layer, a predetermined amount of oxygen gas may be added to the rare gas. By increasing the ratio of oxygen gas to rare gas as a sputtering gas, oxygen deficiency defects in the oxide semiconductor can be reduced. By controlling oxygen deficiency defects in the oxide semiconductor, the threshold voltage of the thin film transistor can be controlled.

Before the oxide semiconductor layer 106 is formed, it is preferable to perform a treatment for generating a plasma by introducing argon gas into a deposition chamber of a sputtering apparatus to clean the deposition surface.
Nitrogen, helium, or the like may be used instead of the argon atmosphere. Alternatively, an argon atmosphere may be used in which oxygen, N ₂ O, or the like is added. Also, Cl ₂ , CF _{4 in} an argon atmosphere
You may perform in the atmosphere which added etc.

After the oxide semiconductor layer 106 is formed, 200 ° C. or higher and 600 ° C. in air or nitrogen atmosphere
A heat treatment is performed at a temperature not higher than ° C., preferably not lower than 300 ° C. and not higher than 400 ° C. This heat treatment can increase the field-effect mobility of the thin film transistor. A field-effect mobility of a thin film transistor including an oxide semiconductor described in this embodiment can be 5 cm ² / Vsec or more.

In the thin film transistor as described above, when a voltage of about 5 V is applied between the source electrode and the drain electrode, the current between the source electrode and the drain electrode when the voltage is not applied to the gate electrode is set to 1 × 10 ⁻¹¹ A or less. It is possible. Even when a voltage of −10 V is applied to the gate electrode, the current between the source electrode and the drain electrode is 1 × 10 ⁻¹¹ A or less.

2A and 2B illustrate an example of a thin film transistor manufactured over the surface of the substrate 101. FIG. Here, FIG. 2A is an example of a plan view of a thin film transistor, and FIG. 2B is a cross-sectional view corresponding to a cut line A2-B2.

2A and 2B is a bottom gate type in which a gate electrode 102 and a gate insulating layer 103 are formed from the substrate 101 side, and an oxide semiconductor layer 106 is formed over the gate insulating layer 103. It has the structure of. The source electrode 104 and the drain electrode 105 are in contact with each other on the side surface and the top surface of the oxide semiconductor layer 106.

In the thin film transistor having such a structure, the gate insulating layer 103 and the oxide semiconductor layer 106 and the conductive layer for forming the source electrode 104 and the drain electrode 105 can be formed in succession. That is, the interface between the gate insulating layer 103 and the oxide semiconductor layer 106 and the interface between the oxide semiconductor layer 106 and the conductive layer are stacked without being exposed to the air, so that each interface is prevented from being contaminated. Can do.

Further, by removing the surface layer portion of the oxide semiconductor layer 106 exposed between the source electrode 104 and the drain electrode 105 by etching, off-state current can be reduced. Further, by performing oxygen plasma treatment on the exposed portion of the oxide semiconductor layer 106 or the surface removed by etching, the resistance of the surface layer portion exposed to plasma can be increased. This is because the oxygen deficiency defect of the oxide semiconductor is oxidized and the carrier concentration (electron concentration) is reduced. This oxygen plasma treatment can also reduce the off-state current of the thin film transistor.

3A and 3B illustrate an example of a thin film transistor manufactured over the surface of the substrate 101. FIG. Here, FIG. 3A is an example of a plan view of the thin film transistor, and FIG. 2B is a cross-sectional view corresponding to a cut line A3-B3.

3A and 3B, a thin film transistor includes a source electrode 104, a drain electrode 105, an oxide semiconductor layer 106, a gate insulating layer 103, and a gate electrode 102 from the substrate 101 side.
The top gate type structure is formed. Even in the thin film transistor having such a structure, the oxide semiconductor layer 106 is formed of InMO ₃ (ZnO) _m (M = Ga, Fe, Ni,
One or a plurality of elements selected from Mn, Co, and Al, m and a non-integer of 1 to less than 50), and the composition of the oxide semiconductor material is 100% of the total of In, M, Zn, and O The off-state current of the thin film transistor can be reduced by including less than 20 atomic% of In, less than 20 atomic% of M (for example, Ga), and less than 10 atomic% of Zn as the composition of each element. And a high on / off ratio can be obtained.

FIG. 4A illustrates an example in which the oxide insulating layer 107 is provided on the opposite side (back channel side) of the oxide semiconductor layer 106 to the gate insulating layer 103. As described above, aluminum oxide, aluminum oxynitride, yttrium oxide, and hafnium oxide are used for the oxide insulating layer 107 in addition to silicon oxide. 4A, the oxide semiconductor layer 106 includes the gate insulating layer 10.
3 is sandwiched between the silicon oxide 3 and the oxide insulating layer 107, oxygen can be prevented from being released from the oxide semiconductor layer 106 to form an oxygen deficiency defect.

FIG. 4B illustrates a structure in which a nitride insulating layer 108 is provided outside the oxide insulating layer 107. As the nitride insulating layer 108, silicon nitride, aluminum nitride, or the like can be used.
By providing the nitride insulating layer 108, contamination from the external environment due to water vapor, organic matter, and ionic metal can be prevented. Note that it is also effective that the gate insulating layer 103 has a two-layer structure of a silicon nitride layer and a silicon oxide layer in the structure in FIG. Accordingly, the upper layer side and the lower layer side of the oxide semiconductor layer 106 are sandwiched between the oxide insulating layer and the nitride insulating layer, and the above effect can be further enhanced.

(About devices using thin film transistors)
A thin film transistor using an oxide semiconductor described in this embodiment has high field-effect mobility and a high on / off ratio, and thus can be applied to various uses. An example of the display device will be described as an example.

FIG. 5 shows a display device 109 in which a pixel portion 110, a scanning line driver circuit 111, and a selector circuit 112 are provided on a substrate 101 on the signal line side. The switching element provided in the pixel portion 110, the scan line driver circuit 111, and the selector circuit 112 on the signal line side are formed of thin film transistors in which a channel formation region is provided in an oxide semiconductor layer. Field effect mobility of 5 cm ²
When a thin film transistor in which a channel formation region is provided in an oxide semiconductor layer of / V · sec to 20 cm ² / V · sec is used, the scan line driver circuit 111 and the signal line side selector circuit 1 are used.
12 can be configured. The selector circuit 112 is a circuit that selects the signal line 116 and is a circuit that distributes the video signal sent from the driver IC 114 to the predetermined signal line 116 at a predetermined timing. Here, since the thin film transistor is an n-channel type, the scan line driver circuit 111 and the selector circuit 112 on the signal line side are circuits composed of n-channel type thin film transistors.

A pixel transistor 117 is provided in the pixel portion 110 configured by a plurality of scanning lines 115 and signal lines 116 intersecting each other. The pixel transistors 117 are arranged in a matrix. The pixel transistor 117 receives a scanning signal from the scanning line 115,
A video signal is input from the signal line 116. A video signal is input from the driver IC 114 to the input terminal 113. The driver IC 114 is a circuit formed on a single crystal substrate,
TAB (tape-automated bonding) method or COG (chip)
on glass) method.

FIG. 6 shows a structural example of the selector circuit 112 composed of n-channel thin film transistors. The selector circuit 112 is configured by arranging a plurality of switch circuits 119. One switch circuit 119 has a plurality of signal lines 116 (with respect to one video signal input line 120 (
S <b> 1 to S <b> 3) extend to the pixel unit 110. The switch circuit 119 is provided with switching elements 121 corresponding to the number of signal lines 116. The switching element 121 includes a thin film transistor in which a channel formation region is provided in an oxide semiconductor layer, whereby the switch circuit 119 can be operated at high speed according to the frequency of the video signal. In FIG. 6, the switching element 121 corresponds to the signal line 116 (S1).
a, switching element 121b corresponding to signal line 116 (S2), signal line 116 (S3)
1 shows an example of a switch circuit 119 provided with a switching element 121c. On / off of the switching element 121 is controlled by a signal of the synchronization signal input line 122 that is input through a path different from the video signal input line 120.

The operation of the selector circuit 112 shown in FIG. 6 will be described with reference to the timing chart shown in FIG. The timing chart illustrated in FIG. 7 shows a case where the i-th scanning line is selected and the video signal input line 120 of a certain column is connected to the selector circuit 112. The selection period of the i-th scanning line is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. This timing chart shows the timing when the switching element 121a, the switching element 121b, and the switching element 121c are turned on / off when the i-th scanning line is selected, and the signal input to the video signal input line 120. ing.

As shown in FIG. 7, in the first sub-selection period T1, the switching element 121a is turned on, and the switching element 121b and the switching element 121c are turned off. At this time, the video signal VD (1) input to the video signal input line 120 is output to the signal line 116 (S1) via the switching element 121a. In the second sub-selection period T2, the switching element 121b is turned on, the switching element 121a and the switching element 121c are turned off, and the video signal VD (2) is transmitted through the switching element 121b to the signal line 116 (S2).
Is output. In the third sub-selection period T3, the switching element 121c is turned on, the switching element 121a and the switching element 121b are turned off, and the video signal VD (3) is output to the signal line 116 (S3) via the switching element 121c. .

As described above, the selector circuit 112 in FIG. 6 divides one gate selection period into three to
During the gate selection period, a video signal can be input from one video signal input line 120 to the three signal lines S1 to S3. Therefore, by providing the selector circuit 112 on the substrate 101 together with the pixel transistor 117, the input terminal 113 for inputting the signal of the driver IC.
As compared with the case where the selector circuit 112 is not provided. Thereby, the frequency of occurrence of contact failure between the driver IC and the input terminal 113 can be reduced.

The scan line driver circuit 111 can also be formed using a thin film transistor in which a channel formation region is provided in an oxide semiconductor layer. In the scan line driver circuit 111, a shift register is included as one component. A selection signal is generated by inputting a clock signal (CLK) and a start pulse signal (SP) to the shift register. The generated selection signal is buffered and amplified in the buffer and supplied to the corresponding scanning line 115. One scanning line 115 is connected to the gate electrode of the pixel transistor 117 for one line. Here, one mode of the shift register 123 used for part of the scan line driver circuit 111 is described with reference to FIGS.

FIG. 8 shows the configuration of the shift register 123. The shift register 123 is configured by connecting a plurality of stages of flip-flop circuits 124. An example of the flip-flop circuit 124 is shown in FIG. The flip-flop circuit 124 illustrated in FIG. 9 includes a plurality of thin film transistors (hereinafter referred to as “TFT” in the description of FIG. 9). The flip-flop circuit 124 shown in FIG. 9 includes n-channel TFTs, and includes TFT (1) 125, TFT (2
) 126, TFT (3) 127, TFT (4) 128, TFT (5) 129, TFT (6)
) 130, TFT (7) 131 and TFT (8) 132 constitute a circuit.
The n-channel TFT is assumed to be in a conductive state when the gate-source voltage (Vgs) exceeds the threshold voltage (Vth).

In the flip-flop circuit 124 shown in FIG. 9, all TFTs are described as enhancement-type n-channel transistors. For example, the TFT (3) 127 can drive a drive circuit even if a depletion-type n-channel transistor is used. It can also be made.

The first electrode (one of the source electrode and the drain electrode) of the TFT (1) 125 is the wiring (4) 1
36, the second electrode (the other of the source electrode and the drain electrode) of the TFT (1) 125 is connected to the wiring (3) 135.

A first electrode of the TFT (2) 126 is connected to the wiring (6) 138, and a second electrode of the TFT (2) 126 is connected to the wiring (3) 135.

The first electrode of the TFT (3) 127 is connected to the wiring (5) 137, the second electrode of the TFT (3) 127 is connected to the gate electrode of the TFT (2) 126, and the gate of the TFT (3) 127 The electrode is connected to the wiring (5) 137.

The first electrode of the TFT (4) 128 is connected to the wiring (6) 138, the second electrode of the TFT (4) 128 is connected to the gate electrode of the TFT (2) 126, and the gate of the TFT (4) 128 The electrode is connected to the gate electrode of the TFT (1) 125.

The first electrode of the TFT (5) 129 is connected to the wiring (5) 137, the second electrode of the TFT (5) 129 is connected to the gate electrode of the TFT (1) 125, and the gate of the TFT (5) 129 The electrode is connected to the wiring (1) 133.

The first electrode of the TFT (6) 130 is connected to the wiring (6) 138, the second electrode of the TFT (6) 130 is connected to the gate electrode of the TFT (1) 125, and the gate of the TFT (6) 130 The electrode is connected to the gate electrode of the TFT (2) 126.

The first electrode of the TFT (7) 131 is connected to the wiring (6) 138, the second electrode of the TFT (7) 131 is connected to the gate electrode of the TFT (1) 125, and the gate of the TFT (7) 131 is connected. The electrode is connected to the wiring (2) 134. The first electrode of the TFT (8) 132 is the wiring (6) 1
38, the second electrode of the TFT (8) 132 is connected to the gate electrode of the TFT (2) 126, and the gate electrode of the TFT (8) 132 is connected to the wiring (1) 133.

A thin film transistor in which a channel formation region is provided in the oxide semiconductor layer has high field-effect mobility, so that the operating frequency can be increased. Further, since the thin film transistor has high frequency characteristics, the scan line driver circuit 111 can be operated at high speed, and the display device can be operated at a high frame frequency.

In FIG. 5, the configuration of the pixel portion 110 varies depending on the display medium 118. When the liquid crystal element in which the liquid crystal material is interposed between the electrodes is used as the display medium 118, the display medium 118 can be controlled by the pixel transistor 117 as shown in FIG. The same applies to the display medium 118 in which a contrast medium (electronic ink, electrophoretic material) is sandwiched between a pair of electrodes. The pixel portion 110 constituted by these display media 118 can be operated in combination with the above driving circuit.

In the case where a light-emitting element formed using an electroluminescent material is used as the display medium 118, the response speed is higher than that of a liquid crystal element and the like, which is more suitable for the time gray scale method than the liquid crystal element. For example, when display is performed by the time gray scale method, one frame period is divided into a plurality of subframe periods. Then, in accordance with the video signal, the light emitting element is turned on or off in each subframe period. By dividing into a plurality of subframe periods, the total length of a period during which a pixel actually emits light during one frame period can be controlled by a video signal, and gradation can be displayed.

An example of a pixel when the pixel portion 110 is formed of a light emitting element is shown in FIG. FIG.
A structure of a pixel to which digital time gray scale driving can be applied will be described. Here, an example is shown in which two n-channel thin film transistors each using an oxide semiconductor layer for a channel formation region are used for one pixel.

The pixel 139 includes a switching TFT 140, a driving TFT 141, a light emitting element 142, and a capacitor 145. The switching TFT 140 has a gate connected to the scanning line 115, a first electrode (one of the source electrode and the drain electrode) connected to the signal line 116, and a second electrode (the other of the source electrode and the drain electrode) connected to the driving TFT 141. Connected to the gate. The driving TFT 141 has a gate connected to the power supply line 146 through the capacitor element 145, a first electrode connected to the power supply line 146, and a second electrode connected to the first electrode (pixel electrode) 143 of the light emitting element 142. ing. The second electrode (counter electrode) 144 of the light emitting element 142 is connected to the common potential line 147.

A low power supply potential is set for the second electrode (counter electrode) 144 of the light emitting element 142. In addition,
The low power supply potential is a potential satisfying the low power supply potential <the high power supply potential with reference to the high power supply potential set in the power supply line 146. For example, GND, 0V, or the like may be set as the low power supply potential. . The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 142 and a current is passed through the light emitting element 142 to cause the light emitting element 142 to emit light. Each potential is set to be equal to or higher than the forward threshold voltage.

In the case of the voltage input voltage driving method, the driving TFT 14 is connected to the gate of the driving TFT 141.
A video signal is input so that 1 is sufficiently on or off. That is, the driving TFT 141 is operated in a linear region. Since the driving TFT 141 is operated in a linear region, a voltage higher than the voltage of the power supply line 146 is applied to the gate of the driving TFT 141. Note that a voltage equal to or higher than (power supply line voltage + threshold voltage of the driving TFT 141) is applied to the signal line 116.

The pixel configuration shown in FIG. 10 can perform analog gradation driving instead of digital time gradation driving. When analog gradation driving is performed, the light emitting element 1 is connected to the gate of the driving TFT 141.
A voltage equal to or higher than the forward voltage of 42 + the threshold voltage of the driving TFT 141 is applied. The forward voltage of the light-emitting element 142 refers to a voltage for obtaining desired luminance, and includes at least a forward threshold voltage. Note that a current can be supplied to the light-emitting element 142 by inputting a video signal that causes the driving TFT 141 to operate in a saturation region. In order to operate the driving TFT 141 in the saturation region, the potential of the power supply line 146 is set higher than the gate potential of the driving TFT 141. By making the video signal analog, current corresponding to the video signal can be supplied to the light emitting element 142 to perform analog gradation driving.

FIG. 10 shows an example in which the driving TFT 141 for controlling the driving of the light emitting element 142 and the light emitting element are electrically connected. However, a current control TFT is connected between the driving TFT 141 and the light emitting element 142. It may be a configuration.

The display device 109 illustrated in FIG. 5 illustrates an example in which the selector circuit 112 that selects the signal line 116 is provided; however, the field-effect mobility of the thin film transistor in which the oxide semiconductor layer is a channel formation region is 10 cm / V · sec or more. Can be obtained, the function of the driver IC 114 can be realized by the thin film transistor. That is, the scan line driver circuit and the signal line driver circuit can be formed over the substrate 101 with a thin film transistor in which the oxide semiconductor layer is a channel formation region.

(Light emitting device)
As an embodiment of the display device, the pixel structure of the light-emitting device is described with reference to FIGS.
) Will be described. Here, FIG. 11 is an example of a plan view of a pixel, and FIG.
FIG. 12B shows a cross-sectional view corresponding to the C2-D2 cut line. In the following description, FIG. 11 and FIGS. 12A and 12B are referred to. Note that an equivalent circuit of the pixel shown in FIG. 11 is the same as FIG.

A channel formation region of the switching TFT 140 is formed in the oxide semiconductor layer 153. The oxide semiconductor layer 153 is equivalent to that described in this embodiment. Switching TFT
140 includes a gate electrode 148 formed of the same layer as the scanning line 115, and includes a gate insulating layer 1.
An oxide semiconductor layer 153 is provided over the layer 52. The oxide semiconductor layer 153 is in contact with the source / drain electrode 155 and the source / drain electrode 156 which are formed over the gate insulating layer 152 in the same layer as the signal line 116. The source / drain electrode 156 is connected to the gate insulating layer 1
The gate electrode 1 of the driving TFT 141 is formed by a contact hole 159 provided in the gate electrode 52.
49.

Note that a source / drain electrode refers to an electrode provided in a portion functioning as a source or a drain in a thin film transistor mainly including a source, a drain, and a gate.

The signal line 116, the source / drain electrode 155, and the source / drain electrode 156 are preferably formed of an Al film or an Al film to which a metal such as Si, Ti, Nd, Sc, or Cu is added. This is to reduce the resistance of the wiring or electrode. It is preferable that a refractory metal layer represented by Mo, Cr, Ti is provided on the upper layer side and / or the lower layer side of the Al film. This is to prevent hillocks and whiskers from occurring in the Al film.

The gate electrode 149 also serves as the capacitor electrode 150 of the capacitor 145. The capacitor element 145 is formed of the same layer as the capacitor electrode 150, the gate insulating layer 152, and the power supply line 146.
51 is formed by laminating.

The gate electrode 149 of the driving TFT 141 is formed using the same layer as the scan line 115, and the oxide semiconductor layer 154 is provided over the gate insulating layer 152. The oxide semiconductor layer 154 is in contact with a source / drain electrode 157 and a source / drain electrode 158 which are formed over the gate insulating layer 152 as the same layer as the power supply line 146.

An oxide insulating layer 107 is provided for the oxide semiconductor layer 153 and the oxide semiconductor layer 154. The first electrode (pixel electrode) 143 is provided over the oxide insulating layer 107. First electrode (
The pixel electrode 143 and the source / drain electrode 158 are connected by a contact hole 160 provided in the oxide insulating layer 107. The partition wall layer 161 that opens the first electrode (pixel electrode) 143 is formed of an inorganic insulating material or an organic insulating material. The end of the opening of the partition wall layer 161 is formed in a curved surface with a gentle gradient.

The light emitting element 142 has an E between the first electrode (pixel electrode) 143 and the second electrode (counter electrode) 144.
The L layer 162 is provided. One of the first electrode (pixel electrode) 143 and the second electrode (counter electrode) 144 is an electrode for hole injection, and the other is an electrode for electron injection. The electrode for hole injection is preferably formed of a material having a work function of 4 eV or more, and includes indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, and titanium oxide. Indium tin oxide, indium tin oxide,
A material such as indium zinc oxide or indium tin oxide to which silicon oxide is added is used. The electrode for electron injection is preferably formed of a material having a work function of less than 4 eV, Ca, Al,
The EL layer 162 in which CaF, MgAg, AlLi, or the like is desirable is a layer for obtaining light emission by electroluminescence, and is configured by appropriately combining a layer that transports carriers (holes or electrons) and a light-emitting layer.

FIG. 13 shows a configuration of the input terminal 113 of the light emitting device. FIG. 13A shows a plan view of the input terminal 113. The input terminal 113 is provided at the end of the substrate 101. G shown in FIG.
A cross-sectional view corresponding to the −H cut line is shown in FIG.

FIG. 13B shows an example in which the input terminal layer 170 is formed of the same layer as the scanning line 115. A gate insulating layer 152 and an oxide insulating layer 107 are stacked on the upper layer side of the input terminal layer 170. By providing an opening 173 in these insulating layers, the input terminal layer 170 is formed so as to be exposed from the insulating layer. ing. A transparent conductive film 172 that covers the opening 173 and is in contact with the input terminal layer 170 is provided. The transparent conductive film 172 is provided to prevent contact resistance from increasing when the flexible printed wiring and the input terminal 113 are connected. When the surface of the input terminal layer 170 formed of metal is oxidized, the contact resistance increases. However, if the transparent conductive film 172 that is an oxide conductive material is provided, an increase in the contact resistance can be prevented.

FIG. 13C illustrates an example in which the input terminal layer 171 is formed using the same layer as the signal line 116. An oxide insulating layer 107 is provided on the upper side of the input terminal layer 171, and the input terminal layer 171 is formed to be exposed from the insulating layer by providing an opening 173 in the insulating layer. The transparent conductive film 172 is provided for the same reason as described above.

(Contrast medium display device)
FIG. 14A illustrates one mode of a display device (also referred to as “electronic paper”) using a contrast medium 163. The contrast medium 163 is held between the first electrode (pixel electrode) 143 and the second electrode (counter electrode) 144 together with the filler 164, and the contrast changes when a potential difference is applied between the two electrodes. The second electrode (counter electrode) 144 is the counter substrate 16.
5 is provided.

For example, as a twisting ball display method, spherical particles separately painted in white and black are used as the first electrode (
There is a system in which display is performed by controlling the direction of spherical particles which are arranged between a pixel electrode) 143 and a second electrode (counter electrode) 144 and cause a potential difference between the two electrodes.

In addition, an electrophoretic element can be used instead of the twisting ball. A diameter of 10 μm enclosing transparent filler 164, positively charged white particles and negatively charged black particles.
A microcapsule of about 200 μm is used. The microcapsule is sandwiched between the first electrode (pixel electrode) 143 and the second electrode (counter electrode) 144, and the white particles positively charged and the black particles negatively charged by the potential difference between the two electrodes are in different directions. Move to. A display element to which this principle is applied is an electrophoretic display element, and is generally called electronic paper.
Since the electrophoretic display element has higher reflectance than the liquid crystal display element, an auxiliary light is unnecessary, power consumption is small, and the display portion can be recognized even in a dim place. Further, even when power is not supplied to the display portion, an image once displayed can be held; therefore, a semiconductor device with a display function from a radio wave source (simply a display device or a semiconductor having a display device) Even when the device is also moved away, the displayed image can be stored.

(Liquid crystal display device)
As an embodiment of the display device, a structure of a pixel of the liquid crystal display device will be described with reference to FIGS. Here, FIG. 15 is an example of a plan view of the pixel, and FIG. 16 shows a cross section corresponding to the E1-F1 cutting line. In the following description, reference is made to FIGS.

The pixel of the liquid crystal display device illustrated in FIGS. 15 and 16 includes a switching TFT 140 connected to the scanning line 115 and the signal line 116. The source / drain electrode 155 of the switching TFT 140 is connected to the signal line 116, and the source / drain electrode 156 is connected to the first electrode (pixel electrode) 143 through a contact hole 167 provided in the oxide insulating layer 107. ing. The capacitor element 145 has a stacked structure of a capacitor line 166, a gate insulating layer 103, and a source / drain electrode 156 that are formed in the same layer as the gate electrode 102.
The switching TFT 140 controls on / off of a signal applied to the first electrode (pixel electrode) 143. The structure of the switching TFT 140 is the same as that described with reference to FIG.

The liquid crystal layer 169 is provided between the first electrode (pixel electrode) 143 and the second electrode (counter electrode) 144. The first electrode (pixel electrode) 143 is provided over the oxide insulating layer 107. An alignment film 168 is provided on the first electrode (pixel electrode) 143 and the second electrode (counter electrode) 144.

As described above, a thin film transistor in which a channel formation region is formed in the oxide semiconductor layer according to this embodiment can complete a display device with excellent operating characteristics.

(Composition of oxide semiconductor layer)
An oxide semiconductor layer was formed over a glass substrate by a sputtering method under the following conditions.
(Condition 1)
Target composition: In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 1
(In: Ga: Zn = 1: 1: 0.5)
Ar gas flow rate: 40sccm
Pressure: 0.4Pa
Power (DC): 500W
Substrate temperature: Room temperature (Condition 2)
Target composition: In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 1
(In: Ga: Zn = 1: 1: 0.5)
Ar gas flow rate: 10 sccm
Oxygen gas flow rate: 5 sccm
Pressure: 0.4Pa
Power (DC): 500W
Substrate temperature: room temperature

The oxide semiconductor layer manufactured under Condition 1 was subjected to inductively coupled plasma mass spectrometry (Inductive
y Coupled Plasma Mass Spectrometer: ICP-M
S analysis). A typical measurement example is shown in Table 1. The oxide semiconductor film obtained under Condition 1 is InGa _0.95 Zn _0.41 O _3.33 . An oxide semiconductor film obtained under Condition 2 is InGa _0.94 Zn _0.40 O _3.31 .

Thus, it can be confirmed that _m in InMO ₃ (ZnO) _m is not an integer by ICP-MS analysis. Further, it is confirmed from the composition ratio that the concentration of Zn is lower than the concentration of each element of In and Ga.

(Structure of oxide semiconductor layer)
Under the condition 2 described above, the structure of the oxide semiconductor layer formed on the glass substrate with a thickness of 400 nm was evaluated by X-ray diffraction.

FIG. 17 shows a sample (as-depo) as fabricated under condition 2, 3 in a nitrogen atmosphere after film formation.
2 shows an X-ray diffraction pattern of a sample heat-treated at 50 ° C. for 1 hour and a sample heat-treated at 500 ° C. for 1 hour in a nitrogen atmosphere after film formation. A halo pattern was observed in all samples, and it was confirmed that the samples had an amorphous structure.

As the composition of the _{target, In 2 O 3: Ga 2} O 3: ZnO = 1: 1: was also examined 2 samples, evaluation by X-ray diffraction results indicate a similar trend, in this embodiment It has been confirmed that the oxide semiconductor layer to be manufactured has an amorphous structure.

(Characteristics of thin film transistors)
FIG. 18 shows characteristics of gate voltage (Vg) versus drain current (Id) of the thin film transistor.
The structure of the thin film transistor is the bottom gate type structure shown in FIG.
m, and the channel width is 100 μm. The oxide semiconductor layer is manufactured under the above condition 2. The field-effect mobility is 15 cm ² / V · sec or more and 1 × 10 ⁻¹¹ A or less off current, and the ratio of on current to off current (on / off ratio) is 10 ⁸ or more. As described above, in this embodiment, a thin film transistor having an unprecedented high on / off ratio is obtained.

DESCRIPTION OF SYMBOLS 101 Substrate 102 Gate electrode 103 Gate insulating layer 104 Source electrode 105 Drain electrode 106 Oxide semiconductor layer 107 Oxide insulating layer 108 Nitride insulating layer 109 Display device 110 Pixel portion 111 Scan line driver circuit 112 Selector circuit 113 Input terminal 114 Driver IC
115 scanning line 116 signal line 117 pixel transistor 118 display medium 119 switch circuit 120 video signal input line 121 switching element 121a switching element 121b switching element 121c switching element 122 synchronization signal input line 123 shift register 124 flip-flop circuit 125 TFT (1)
126 TFT (2)
127 TFT (3)
128 TFT (4)
129 TFT (5)
130 TFT (6)
131 TFT (7)
132 TFT (8)
133 Wiring (1)
134 Wiring (2)
135 Wiring (3)
136 Wiring (4)
137 Wiring (5)
138 Wiring (6)
139 Pixel 140 Switching TFT
141 Driving TFT
142 Light-Emitting Element 143 First Electrode (Pixel Electrode)
144 Second electrode (counter electrode)
145 Capacitance element 146 Power supply line 147 Common potential line 148 Gate electrode 149 Gate electrode 150 Capacitance electrode 151 Capacitance electrode 152 Gate insulating layer 153 Oxide semiconductor layer 154 Oxide semiconductor layer 155 Source / drain electrode 156 Source / drain electrode 157 Source / drain Electrode 158 Source / drain electrode 159 Contact hole 160 Contact hole 161 Partition layer 162 EL layer 163 Contrast medium 164 Filler 165 Counter substrate 166 Capacitor line 167 Contact hole 168 Alignment film 169 Liquid crystal layer 170 Input terminal layer 171 Input terminal layer 172 Transparent conductive Membrane 173 Opening

Claims (2)

A first conductive layer having a region to be a gate electrode of the first transistor;
A second conductive layer having a region to be a gate electrode of the second transistor;
A first oxide semiconductor layer having a channel formation region of the first transistor;
A second oxide semiconductor layer having a channel formation region of the second transistor;
A third conductive layer having a region to be one of a source electrode and a drain electrode of the first transistor;
A fourth conductive layer having a region to be the other of the source electrode and the drain electrode of the first transistor;
A fifth conductive layer having a region to be one of a source electrode and a drain electrode of the second transistor;
A sixth conductive layer having a region to be the other of the source electrode and the drain electrode of the second transistor;
The second conductive layer is electrically connected to the fourth conductive layer;
The sixth conductive layer is electrically connected to the light emitting element;
The upper surface or the lower surface of the third conductive layer has a region in contact with the first oxide semiconductor layer,
The upper surface or the lower surface of the fourth conductive layer has a region in contact with the first oxide semiconductor layer,
The upper surface or the lower surface of the fifth conductive layer has a region in contact with the second oxide semiconductor layer,
An upper surface or a lower surface of the sixth conductive layer has a region in contact with the second oxide semiconductor layer;
The first conductive layer is above the first oxide semiconductor layer;
The display device, wherein the second conductive layer is located above the second oxide semiconductor layer. In claim 1,
The display device is characterized in that an insulating layer having a region to be a gate insulating layer of the first transistor has an end portion that overlaps with the third conductive layer or the fourth conductive layer.

Images