JP2007129601A - Synchronous circuit system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To effectively reduce the simultaneous switching noise by changing the driving power of an output buffer. <P>SOLUTION: Data on an internal data bus 12 are taken in flip flops 15a-15c via delay circuits 14a-14c from an internal clock 13, and outputted to outside respectively from output buffers 16a-16c at different timings to reduce the simultaneous switching noise. The driving power of the output buffer 16b of the flip flop 15b having the later output timing is made larger than that of the output buffer 16a of the flip flop 15a having the earlier output timing. Accordingly, a setup margin is ensured, thereby preventing the timing error. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a synchronous circuit system with low switching noise.

  In general, a synchronous circuit system is composed of a plurality of semiconductor integrated circuits composed of a plurality of circuit blocks that perform various functions. The semiconductor integrated circuit of the synchronous circuit system has an interface circuit including a buffer, and the semiconductor integrated circuits transmit and receive data between the interface circuits synchronized with the clock. Since each circuit block of the semiconductor integrated circuit operates in synchronization with the same clock, a plurality of signals change simultaneously in the interface circuit.

  While such a synchronous circuit system has an advantage that timing adjustment is easy, when many signals change simultaneously, so-called simultaneous switching noise is generated due to power supply noise or inductive noise between signal lines. Cause malfunction. This simultaneous switching noise also causes EMI (Electro Magnet Interference).

FIG. 5 is a diagram for explaining the mechanism of simultaneous switching noise. When the buffer 1026 switches from Lo to Hi, a current flows from the power source 1021 in the direction of arrow A ₁ , and a voltage proportional to the amount of current change is generated in the power source side inductor 1024, causing a voltage drop on the power source side of the buffer 1026. It becomes noise. Similarly, in the process in which the buffer 1026 is switched from Hi to Lo, a current in the direction of the arrow A ₂ flows to the GND (ground) 1022, and a voltage proportional to the amount of change in the current is generated in the GND side inductor 1025. The voltage rises on the side and becomes noise.

  FIG. 6 shows the relationship between the change in the output waveform and the power supply / GND noise. 6A shows the waveform of the output Vo that changes from Lo to Hi in the buffer, FIG. 6B shows the amount of current ip from the power supply, and FIG. 6C shows the change in the power supply potential Vp. 6D shows the waveform of the output Vo that changes from Hi to Lo of the buffer, FIG. 6E shows the amount of current ig to GND, and FIG. 6F shows the GND potential Vg. When the output waveform changes from Lo to Hi as shown in FIG. 6A, a current change as shown in FIG. 6B occurs, and the power supply potential changes as shown in FIG. When the output waveform changes from Hi to Lo as shown in (d) of FIG. 6, a current change as shown in (e) occurs, and the GND potential changes as shown in (f).

  In recent years, in order to reduce power consumption, a method of lowering the power supply voltage has been taken, and the operation margin of the semiconductor integrated circuit tends to decrease. Among them, the influence of simultaneous switching noise is increasing.

  Conventionally, as a method of avoiding simultaneous switching noise, a method of changing the output timing of each output buffer has been proposed (see Patent Document 1 and Patent Document 2).

  For example, as shown in FIG. 7, delay circuits 1014a, 1014b, and 1014c are inserted into an internal clock 1013 for synchronization of flip-flops 1015a, 1015b, and 1015c connected to each output stage. This changes the output timing of the flip-flops 1015a, 1015b, and 1015c via the output buffers 1016a, 1016b, and 1016c, and reduces simultaneous switching noise.

  8 and 9 show the amount of current and the voltage variation due to the timing change of the output buffer. FIG. 8A shows the change in the amount of current ip and the power supply potential Vp when the timing is not changed, and the simultaneous switching noise. Represents Ve. On the other hand, when the output timing is changed, the peak value of the current amount ip is suppressed as shown in FIG. 9A, so that the fluctuation of the power supply potential Vp can be suppressed and the simultaneous switching noise Ve is reduced. It becomes possible to do.

FIG. 10 is a configuration example of the synchronous circuit system. A clock signal C for synchronization is output from the clock generator 1001 and supplied to the semiconductor integrated circuits 1002 and 1003. The data D ₁ is output from the semiconductor integrated circuit 1002 in response to the clock signal C and input to the semiconductor integrated circuit 1003. At this time, the semiconductor integrated circuit 1002 is on the driver side, and the semiconductor integrated circuit 1003 is on the receiver side. Data D ₂ is output from the semiconductor integrated circuit 1003 in response to the clock signal C and input to the semiconductor integrated circuit 1002. At this time, the semiconductor integrated circuit 1003 is on the driver side, and the semiconductor integrated circuit 1002 is on the receiver side. Note that the synchronization clock may be directly output from the semiconductor integrated circuit.

  In the synchronous circuit system, it is necessary to satisfy a desired setup / hold timing for the clock signal on the receiver side in order to exchange signals accurately.

11 and 12 show timing charts on the receiver side of the synchronous circuit system. FIG. 11 shows a case where the bus cycle is slow, and FIG. 12 shows a case where the bus cycle is early. 11 (a) and 12 (a) show the waveform of the clock signal C for synchronization, and FIG. 10 (b) and FIG. 11 (b) show the waveform of the data signal D. Represents. On the receiver side, the data signal D needs to maintain the data level between the setup Ta and the hold Tb, which is the input reference time with respect to the clock edge E serving as a reference. Tm ₁ is a margin on the setup side, and Tm ₂ is a margin on the hold side. The output timing of the output buffer can be adjusted within the range of the setup side margin Tm ₁ and the hold side margin Tm ₂ . With the recent increase in bus speed, this margin adjustment range tends to decrease.
JP-A-9-93108 JP 2000-307395 A

  However, the method of merely changing the output timing of each output buffer for suppressing simultaneous switching noise has the following problems.

  A buffer with a slow output timing is affected by the switching noise of the fast buffer, and the waveform becomes dull. FIG. 13 is a diagram showing a difference in output waveform due to a difference in output timing. As shown in FIG. 13A, in the output waveform of the buffer whose output timing is relatively early, the influence of simultaneous switching is small, and the waveform switching time Ts hardly changes. However, as shown in FIG. 13B, in the output waveform of the buffer whose change timing is relatively late, the waveform becomes dull due to the effect of simultaneous switching, and the waveform switching time Ts becomes large, so that the timing constraint at the receiver cannot be satisfied. It becomes a problem.

FIG. 14 shows a timing chart in the case where the phase of the driver is simply changed without considering the waveform dullness due to the simultaneous switching noise. That is, the setup Ta of the data signals Da to Dc synchronized with the clock edge (rice edge) E of the clock signal C, the setup side margin Tm ₁ , the hold Tb and the hold side margin Tm ₂ are shown. For the adjusted buffer timing change amount Te, waveform dullness De due to simultaneous switching noise occurs. For this reason, the data signal Dc having a relatively late switch timing causes a timing error at the setup side margin Tm ₁ . In order to consider such waveform dullness De, it is necessary to reduce the buffer timing change amount Te.

  In order to reduce the simultaneous switching noise, it is necessary to increase the buffer timing change amount. However, due to the above-mentioned waveform dullness, the timing change amount cannot be set sufficiently large especially for a high-speed bus. It becomes.

  Further, when focusing on simply improving the waveform dullness and increasing the overall buffer capacity, the influence of simultaneous switching noise of a driver with a fast phase increases. For this reason, the amount of timing change on the output side must be set much smaller, and simply increasing the buffer capacity uniformly cannot be an effective method.

  The present invention has been made in view of the above-mentioned unsolved problems of the prior art, and is to provide a synchronous circuit system capable of effectively reducing simultaneous switching noise and suppressing power consumption. .

  To achieve the above object, a synchronous circuit system of the present invention supplies a plurality of circuit blocks that synchronously output a plurality of signals from an internal circuit, and supplies clock signals having different phases to the plurality of circuit blocks. And a clock circuit for distributing the output timing of each circuit block, and an output buffer disposed on the output side of each circuit block, wherein the drive capacity of the output buffer is different for each circuit block. And

  By changing the drive capability of the output buffer for each circuit block, it is possible to set a large amount of change in output timing by the clock circuit, and to effectively reduce simultaneous switching noise. In addition, power consumption can be suppressed by optimizing the output buffer drive capability.

  FIG. 1 shows the best mode for carrying out the present invention.

  The semiconductor integrated circuit 11 has an internal data bus 12 and an internal clock 13 for transmitting and receiving a plurality of signals of the internal circuit. The data on the internal data bus 12 is fetched from the internal clock 13 to the flip-flops 15a, 15b, and 15c that are output side circuit blocks at different timings by the delay circuits 14a, 14b, and 14c that are clock circuits. The fetched data is output to the outside by output buffers 16a, 16b and 16c having different driving capabilities.

  Here, the driving capability of the output buffer 16b connected to the flip-flop 15b with the later output timing is larger than that of the output buffer 16a connected to the flip-flop 15a with the earlier output timing. In addition, the driving capacity of the output buffer 16c connected to the flip-flop 15c having a later output timing is larger than that of the output buffer 16b connected to the flip-flop 15b.

  In this way, when changing the timing of each output stage that constitutes the data bus, the simultaneous switching noise is effectively reduced without causing a timing error by changing the buffer drive capacity according to the timing change amount. can do.

  In addition, by reducing the drive capability of a buffer with early output timing, it is possible to reduce the influence of simultaneous switching noise from the early buffer and to further increase the amount of change in buffer timing.

  Note that the number of output buffers is not limited to three, and may be any number as long as it is two or more.

  The delay circuit for the internal clock may determine the delay value corresponding to the buffer drive capability or may be set individually. Further, the buffer drive capability may have a plurality of set values.

FIG. 2 shows a timing chart representing the operation of the apparatus of FIG. Data signals Da to Dc synchronized with the clock edge E of the clock signal C supplied from the internal clock 13 are set up Ta, setup side margin Tm ₁ , hold Tb, hold side margin Tm ₂ , and adjusted output timing. Change amount Te. In order to prevent a timing error due to waveform dullness De due to simultaneous switching noise, the setup side margin Tm ₁ is ensured by sequentially increasing the drive capability of the output buffers 16 b and 16 c that output the data signals Db and Dc whose output timing is late. As a result, since the output timing change amount Te can be increased without causing a timing error, simultaneous switching noise can be effectively reduced.

  In other words, in synchronous circuit systems, the drive capacity of the output buffer of the circuit block with a slow output timing is relatively strong, and the drive capacity of the output buffer of the circuit block with a fast output timing is relatively weak, so that simultaneous switching noise can be reliably ensured Reduce. In addition, by optimizing the driving capability of each output buffer in this way, the power consumption of the driver can be reduced.

  The driver power supply may be divided for each driver driving capability. In this synchronous circuit system, the circuit block on the output side may be composed of an LSI. The output timing and buffer driving capability may be set individually for each bit, or may be set in a group of several bits.

  FIG. 3 shows a synchronous circuit system according to one embodiment. The timings of the internal clocks 113 of the flip-flops 115a to 115e that are output side circuit blocks that receive the internal data bus 112 are individually changed by delay buffers 114a to 114e that are clock circuits. Further, the drive capacities of the output buffers 116a to 116e are set higher in order according to the buffer delay of the delay buffers 114a to 114e.

  For example, the output buffer 116a having a relatively early output timing has a driving capacity of 4 mA, the next output buffer 116b has a driving capacity of 6 mA, and the next output buffer 116c has a driving capacity of 8 mA. Further, the next output buffer 116d uses a drive capacity of 10 mA, and the next output buffer 116e uses a drive capacity of 12 mA. As described above, by setting the drive capacities of the output buffers 116a to 116e in order, the amount of change in the timing of the internal clock 113 can be increased.

  4A shows the power fluctuation due to the simultaneous switching when the buffer driving capacity is not changed, and FIG. 4B shows the power fluctuation due to the simultaneous switching when the buffer driving capacity is changed.

  By changing the drive capability of the output buffer in accordance with the buffer delay, the output timing change amount Te can be increased as shown in FIG. As a result, the simultaneous switching noise (maximum value) Ve can be reduced. It can also contribute to Triva's power saving.

It is a figure explaining the structure of the synchronous circuit system by one Embodiment. It is a figure which shows the timing chart of the apparatus of FIG. It is a schematic diagram which shows the synchronous circuit system by one Example. It is a figure explaining the power supply fluctuation | variation by simultaneous switching. It is a figure explaining power supply noise and ground noise. It is a figure explaining the change and noise of an output waveform. It is a figure explaining the synchronous circuit system by one prior art example. It is a graph which shows the power supply fluctuation | variation when not changing an output timing. It is a graph which shows the power supply fluctuation | variation at the time of changing output timing. It is a figure which shows the whole structure of a synchronous circuit system. It is a figure which shows a margin when a bus cycle is late. It is a figure which shows a margin when a bus cycle is early. It is a figure which shows the waveform change by the difference in output timing. It is a figure which shows the timing chart at the time of changing only the phase of a clock signal simply.

Explanation of symbols

11, 111 Semiconductor integrated circuit 12, 112 Internal data bus 13, 113 Internal clock 14a-14c Delay circuit 15a-15c, 115a-115e Flip-flop 16a-16c, 116a-116e Output buffer 114a-114e Delay buffer

Claims (3)

  A plurality of circuit blocks that synchronously output a plurality of signals from the internal circuit, and a clock circuit that distributes the output timing of each circuit block by supplying clock signals having different phases to the plurality of circuit blocks, and An output buffer disposed on the output side of each circuit block, wherein the output buffer has a different driving capability for each circuit block.   2. The synchronous circuit system according to claim 1, wherein the drive capability of each output buffer corresponds to the output timing of the circuit block by each clock signal.   3. The synchronous circuit system according to claim 2, wherein the drive capacity of the output buffer of the circuit block with a slow output timing is made larger than the drive capacity of the output buffer of a circuit block with a fast output timing.

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