JP2008084882A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit in which power consumption of a clock buffer can be reduced without causing malfunction due to clock skew. <P>SOLUTION: Functional blocks 1, 2 and 3 included in a semiconductor integrated circuit are connected, respectively, with power supplies VDD1, VDD2 and VDD3 and their voltages are controlled individually. The functional blocks 1, 2 and 3 have clock buffers CK1, CK2 and CK3, respectively. Power supplies of the clock buffers CK1-CK3 for distributing clock to each functional block are connected with a power supply VDDck for clock buffer independently from the power supply of each functional block and control the voltages independently from the power supplies VDD1-VDD3 of the functional blocks. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit capable of controlling a power supply voltage for each functional block.

  In recent years, with the progress of miniaturization of the manufacturing process of semiconductor integrated circuits, the number of integrated transistors has dramatically increased, and the operation speed has been improved, so that a system operating at a high frequency can be mounted. ing.

  As a result, the power consumption during operation of the semiconductor integrated circuit is increasing, and this increase in power consumption is a serious problem particularly in battery-powered integrated circuits for portable information devices.

  Therefore, as a design technology that reduces the power consumption during operation of semiconductor integrated circuits, the power supply voltage supplied to each functional block constituting the semiconductor integrated circuit can be controlled, and only functional blocks that require high-speed operation can be powered. A technique of increasing the voltage and decreasing the power supply voltage is used for the functional block operating at low speed.

  However, when such a technique is used, if clock clocks for supplying clocks are distributed in each functional block, the clock buffer of the functional block that operates at a high voltage and the clock buffer of the functional block that operates at a low voltage A clock skew occurs between the function blocks and a malfunction occurs in signal transmission between functional blocks. Therefore, as a method for avoiding this problem, it has been proposed to concentrate all clock buffers on functional blocks operating at a high voltage (see, for example, Patent Document 1).

However, the above-described method causes a problem that the clock buffer always operates at a high voltage, and the power consumed by the clock buffer cannot be reduced. In particular, when the clock frequency is high, the ratio of the power consumed by the clock buffer increases, which causes a problem that the power consumption of the semiconductor integrated circuit is reduced.
JP 2002-312058 (page 17-18, FIG. 17)

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit capable of reducing the power consumption of a clock buffer without causing a malfunction due to clock skew.

  According to one aspect of the present invention, the clock distribution circuit includes a plurality of functional blocks in which supplied power supply voltages are individually controlled, and a clock distribution circuit that distributes a common clock to the plurality of functional blocks. Is provided separately from the power supply voltages of the plurality of functional blocks. A semiconductor integrated circuit is provided.

  According to the present invention, the power supply voltage of the clock buffer that supplies the clock to the functional block is controlled independently as the voltage common to the clock buffer separately from the power supply voltage of each functional block. However, the delay time of the clock buffer output can be kept constant, and the occurrence of skew between the clock buffer outputs can be prevented.

  Further, since the power supply voltage of the clock buffer can be made lower than the voltage supplied to the functional block, the power consumption of the clock buffer can be reduced.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing the concept of the configuration of a semiconductor integrated circuit according to Embodiment 1 of the present invention. The semiconductor integrated circuit of this embodiment is composed of a plurality of functional blocks, and the power supply voltage of each functional block is individually controlled. Thus, for each functional block, the power supply voltage can be controlled such that the power supply voltage is increased when high speed operation is required and the power supply voltage is decreased when low speed operation is acceptable.

  In FIG. 1, a functional block 1, a functional block 2, and a functional block 3 are shown as such functional blocks. The power supplies of the respective functional blocks are represented as VDD1, VDD2, and VDD3. The voltages of the power supplies VDD1, VDD2 and VDD3 are individually controlled.

  The functional circuit included in each functional block is connected to each power source. That is, the functional circuit included in the functional block 1, for example, the flip-flop FF1 is connected to the power supply VDD1, and the functional circuit included in the functional block 2, for example, the flip-flop FF2 is connected to the power supply VDD2, and the functional circuit included in the functional block 3. For example, the flip-flop FF3 is connected to the power supply VDD3.

  Each functional block has a clock buffer that supplies a clock to a built-in functional circuit. That is, the functional block 1 has a clock buffer CK1, the functional block 2 has a clock buffer CK2, and the functional block 3 has a clock buffer CK3.

  The clock buffer CK1, the clock buffer CK2, and the clock buffer CK3 have a clock CK that is a clock signal as a common input. Therefore, the functional block 1, the functional block 2, and the functional block 3 operate in synchronization with the clock CK.

  As described above, in the semiconductor integrated circuit of this embodiment, the clock buffer CK1, the clock buffer CK2, and the clock buffer CK3 are distributed and arranged in each functional block.

  Conventionally, in such an arrangement, the power source of each clock buffer has been the power source of each functional block. However, in this embodiment, the power supply of each clock buffer is not the power supply of each functional block, but is the clock buffer power supply VDDck, which is the power supply common to each clock buffer.

  The voltage of the clock buffer power supply VDDck is controlled separately from the voltages of the power supplies VDD1, VDD2 and VDD3 of each functional block.

  Therefore, even when the voltages of the power supplies VDD1, VDD2 and VDD3 of the functional block are changed for adjusting the operation speed, the voltage of the clock buffer power supply VDDck can always be kept constant.

  In this embodiment, the voltage of the clock buffer power supply VDDck is set equal to the maximum voltage among the power supply voltages supplied to the functional blocks. As a result, even if any functional block operates at the maximum power supply voltage, the clock having the maximum operating speed can be supplied to the block.

  FIG. 2 shows an example of the relationship between the voltages of the power supplies VDD1 to VDD3 of the functional blocks 1 to 3 and the voltage of the clock buffer power supply VDDck. Here, it is assumed that any one of the voltages vd1, vd2, and vd3 (vd1> vd2> vd3) is supplied to the functional blocks 1 to 3.

  FIG. 2A shows an example when the voltage of the power supply VDD1 is vd1, the voltage of the power supply VDD2 is vd2, and the voltage of the power supply VDD3 is vd3. In this case, the voltage of the clock buffer power supply VDDck is vd1, which is the maximum voltage among the power supply voltages vd1 to vd3 supplied to the functional block.

  FIG. 2B is an example when the voltage of the power supply VDD1 is vd2, the voltage of the power supply VDD2 is vd1, and the voltage of the power supply VDD3 is vd3. Also in this case, the voltage of the clock buffer power supply VDDck is assumed to be vd1, which is the maximum voltage among the power supply voltages vd1 to vd3 supplied to the functional block.

  FIG. 2C shows an example when the voltage of the power supply VDD1 is vd3, the voltage of the power supply VDD2 is vd2, and the voltage of the power supply VDD3 is vd1. Also in this case, the voltage of the clock buffer power supply VDDck is assumed to be vd1, which is the maximum voltage among the power supply voltages vd1 to vd3 supplied to the functional block.

  As described above, in this embodiment, even when the voltages of the power supplies VDD1 to VDD3 of the functional blocks 1 to 3 vary between vd1 to vd3, the voltage of the clock buffer power supply VDDck is the maximum voltage vd1. .

  As described above, in this embodiment, even when the clock buffers CK1 to CK3 are distributed in the functional blocks 1 to 3, the power supply is the common clock buffer power supply VDDck. Therefore, no matter how the power supply voltages of the functional blocks 1 to 3 change, the output delays of the clock buffers CK1 to CK3 are not affected by the change and are constant.

  FIG. 3A shows the phase relationship between the outputs of the clock buffers CK1 to CK3 of this embodiment. Here, it is assumed that each clock buffer is designed as a clock distribution circuit so that the output delays are equal.

  That is, if the output delay of the clock buffer 1 is d1, the output delay of the clock buffer 2 is d2, and the output delay of the clock buffer 3 is d3, d1 = d2 = d3. The relationship of this output delay does not change even if the power supplies VDD1 to VDD3 of the functional blocks 1 to 3 change.

  On the other hand, for example, when the power supply voltage of each clock buffer is the voltage of each functional block, the output delay of each clock buffer is affected by the change in the power supply voltage of each functional block. FIG. 3B shows the situation for reference.

  FIG. 3B shows an example when the power supplies VDD1 to VDD3 of the functional blocks 1 to 3 are set as shown in FIG. That is, in this example, the voltage of the power supply VDD1 is vd1, the voltage of the power supply VDD2 is vd2, and the voltage of the power supply VDD3 is vd3 (vd1> vd2> vd3). Since the output delay of the clock buffer increases as the power supply voltage decreases, in this case, d1 <d2 <d3. That is, a clock skew occurs at each output of the clock buffers CK1 to CK3.

  On the other hand, in this embodiment, as described above, even if the power supplies VDD1 to VDD3 of the functional blocks 1 to 3 change, clock skew does not occur in the outputs of the clock buffers CK1 to CK3.

  According to the present embodiment, since the power supply voltage of the clock buffer distributed and arranged in the functional block is controlled separately from the power supply voltage of each functional block, each power block voltage can be changed. The power supply voltage of the clock buffer can be made constant, and the output delay of each clock buffer can be made constant. Thereby, the occurrence of skew between clock buffer outputs can be prevented.

  FIG. 4 is a block diagram showing the concept of the configuration of the semiconductor integrated circuit according to the second embodiment of the present invention. The semiconductor integrated circuit of this embodiment is also composed of a plurality of functional blocks as in the first embodiment, and the power supply voltage of each functional block is individually controlled.

  The difference between the present embodiment and the first embodiment is that the functional block constituting the semiconductor integrated circuit according to the present embodiment does not have a clock buffer therein, and the clock buffer of the clock distribution circuit arranged outside the clock block receives clocks. It is a point to receive supply.

  In FIG. 4, a functional block 11, a functional block 12, and a functional block 13 are shown as such functional blocks. In addition, a clock distribution circuit 10 that supplies a clock to these functional blocks is shown.

  The clock distribution circuit 10 includes a clock buffer CK11, a clock buffer CK12, and a clock buffer CK13. The clock CK is input to each of the clock buffer CK11, the clock buffer CK12, and the clock buffer CK13. The clock buffer CK11 supplies a clock to the functional block 11, the clock buffer CK12 supplies a clock to the functional block 12, and the clock buffer CK13 supplies a clock to the functional block 13.

  In such a semiconductor integrated circuit of this embodiment, the functional block 11 is connected to the power supply VDD1, the functional block 12 is connected to the power supply VDD2, and the functional block 13 is connected to the power supply VDD3. The clock distribution circuit 10 is connected to the clock buffer power supply VDDck.

  Also in the present embodiment, the clock buffer power supply VDDck is controlled separately from the power supply VDD1 to VDD3 of the functional block. Therefore, even when the power supply VDD1 to VDD3 of the functional block is changed for adjusting the operation speed, the voltage of the clock buffer power supply VDDck can always be kept constant. As a result, no matter how the power supply voltages of the functional blocks 1 to 3 change, the output delays of the clock buffers CK1 to CK3 are not affected by the change and are constant. That is, in the present embodiment, as in the first embodiment, it is possible to prevent the occurrence of skew between the outputs of the clock buffers CK1 to CK3.

  Further, in this embodiment, the layout of the semiconductor integrated circuit is also advantageous by arranging the clock buffer outside the functional block.

  That is, when the functional block includes a clock buffer connected to the clock buffer power supply VDDck, it is necessary to wire the functional block power supply and the clock buffer power supply to the functional block. Since it is not necessary to wire the clock buffer power VDDck to each functional block, the power wiring to the functional block can be easily performed when the semiconductor integrated circuit is laid out on the chip.

  Further, since the clock buffer is arranged outside the functional block, the degree of freedom of arrangement of the clock buffer can be improved. Thereby, it is possible to more easily distribute an equal clock to each functional block.

  According to this embodiment, since the power supply voltage of the clock buffer is controlled separately from the power supply voltage of each functional block, skew between clock buffer outputs can be prevented and the clock buffer is arranged outside each functional block. Therefore, power supply wiring can be easily performed for each functional block in the chip layout, and the degree of freedom of arrangement of the clock buffer can be improved.

  In the first and second embodiments, it has been shown that the skew between the outputs of the clock buffer can be prevented by controlling the power supply voltage of the clock buffer separately from the functional block.

  In addition, the power consumption of the clock buffer can be reduced by controlling the power supply voltage of the clock buffer separately from the functional block. In this embodiment, an example is shown.

When the operating speed of the clock of the semiconductor integrated circuit has a margin, it operates sufficiently even if the power supply voltage of the clock buffer is lowered. Therefore, in this embodiment, the voltage of the power supply for the clock buffer is set to vd4 lower than the maximum value vd1 of the power supply voltage supplied to the functional block, as shown in FIG. When the semiconductor integrated circuit is a CMOS type, the power consumption of the semiconductor integrated circuit is proportional to the square of the power supply voltage. Therefore, when the power supply voltage of the clock buffer is lowered from vd1 to vd4, the power consumption in the clock buffer can be reduced to (vd4 / vd1) ² . Since the clock constantly changes, the ratio of the power consumption of the clock buffer to the power consumption of the CMOS type semiconductor integrated circuit is often high. Therefore, the effect of reducing the power consumption of the entire semiconductor integrated circuit by reducing the power consumption of the clock buffer is high.

  In this case, as shown in FIG. 5B, the output delays d11 to d13 of the clock buffers CK1 to CK3 are larger than the output delays d1 to d3 shown in FIG. There is no skew.

  According to this embodiment, since the power supply voltage of the clock buffer is controlled separately from the power supply voltage of each functional block, the skew between the clock buffer outputs can be prevented and the power supply voltage of the clock buffer can be reduced. The power consumption of the clock buffer can be reduced.

1 is a block diagram showing a concept of a configuration of a semiconductor integrated circuit according to Embodiment 1 of the present invention. FIG. 3 is a diagram showing an example of the relationship between each functional block and the power supply voltage of the clock buffer in the semiconductor integrated circuit shown in FIG. 1. FIG. 3 is a waveform diagram showing a phase relationship between clock buffer outputs in the semiconductor integrated circuit according to the first embodiment. FIG. 5 is a block diagram showing a concept of a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention. FIG. 10 is a diagram illustrating a setting example of a power supply voltage of a clock buffer and an output waveform in a semiconductor integrated circuit according to a third embodiment of the present invention.

Explanation of symbols

1, 2, 3, 11, 12, 13 Functional block 10 Clock distribution circuit VDD1, VDD2, VDD3 Power supply VDDck Clock buffer power supply CK Clock CK1, CK2, CK3, CK11, CK12, CK13 Clock buffers FF1, FF2, FF3, FF11 , FF12, FF13 flip-flop

Claims (5)

A plurality of functional blocks whose power supply voltages to be supplied are individually controlled;
A clock distribution circuit for distributing a common clock to the plurality of functional blocks;
A semiconductor integrated circuit, wherein a power supply voltage of the clock distribution circuit is controlled separately from power supply voltages of the plurality of functional blocks.   2. The semiconductor integrated circuit according to claim 1, wherein a power supply voltage of the clock distribution circuit is controlled to a voltage equal to a maximum voltage among power supply voltages supplied to the plurality of functional blocks.   2. The semiconductor integrated circuit according to claim 1, wherein a power supply voltage of the clock distribution circuit is controlled to a voltage lower than a maximum voltage among power supply voltages supplied to the plurality of functional blocks.   4. The semiconductor integrated circuit according to claim 1, wherein clock buffers constituting the clock distribution circuit are distributed and arranged in the plurality of functional blocks. 5.   4. The semiconductor integrated circuit according to claim 1, wherein a clock buffer constituting the clock distribution circuit is arranged outside the plurality of functional blocks. 5.

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