JP2828041B2 - Clock distribution method and clock distribution circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock distribution technique, and more particularly to a clock signal distribution method and a clock distribution circuit for distributing and wiring a clock signal to a plurality of logic blocks in a layout of a semiconductor integrated circuit or the like.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit, when a synchronous clock signal is supplied to a plurality of logical blocks at the same timing, as shown in FIG. The single type buffers 103 to 109 are arranged in a tree shape on the clock line, and the wiring between the clock generation circuit 101 and each buffer is set to have the same wiring length.
A method (clock tree synthesis) for reducing the propagation delay difference (clock skew) of the clock signal from 10 to 103 is adopted. This method is also called a “tree-shaped wiring driving method”.

In order to reduce clock skew in a clock tree, for example, Japanese Patent Application Laid-Open No.
No. 76 discloses that the delay times of all clock trees are equalized by equalizing the delays extending to each level of the entire tree, and the delay of each level is adjusted by adjusting the capacity of the terminator of each net at each level. Or by adjusting the driving capability of each buffer (driver) at each level, and if the capacity of the net is too low to be corrected by the buffer, then selectively add a capacitance terminator to the net and add A method has been proposed for equalizing clock transmission delays between clocks.

For example, Japanese Patent Laid-Open No. 4-269860 discloses that a tree is branched at an equal wiring delay time in consideration of a wiring capacity and a wiring resistance of a wiring between a clock generating circuit and each buffer. Have been proposed to make the clock transmission delays equal.

[0005]

However, even in the method proposed in the above publication, minute variations in the wiring of the clock line occur, and the wiring, the wiring capacitance, and the wiring resistance between the buffers on the clock line are completely the same. And the clock skew never goes to zero.

[0006] Further, with the advance of fine processing technology, finer wiring has progressed, and the influence of wiring delay due to wiring resistance has increased, so that fine wiring variations cannot be ignored.

[0007] The clock skew causes a malfunction in the sequential circuit in particular, so that the clock frequency naturally has an upper limit, which hinders the improvement of the operating frequency of the semiconductor integrated circuit.

As described above, the above-described conventional clock distribution system based on clock tree synthesis has a problem in that there is a limit in reducing clock skew because minute clock line variations occur. .

Further, when the driving capability of the buffer on the clock line is increased, the gate width of the transistor constituting the buffer is increased or the number of transistors is increased, so that the size of the buffer itself is increased and the height of the semiconductor integrated circuit is increased. Not only does this hinder density, but it also increases power consumption.

Therefore, the present invention has been made in view of the above circumstances, and an object of the present invention is to reduce a delay time of a clock signal supplied to a plurality of logic blocks preferably arranged on a semiconductor substrate or the like. It is an object of the present invention to provide a clock distribution method and a circuit for improving the operation frequency of a circuit by making the same for any of the logic blocks.

[0011]

In order to achieve the above object, a clock distribution method according to the present invention is directed to a method of synchronizing a synchronous clock signal from a clock generation circuit to a plurality of logic blocks via a buffer arranged in a tree-like manner. In the clock distribution method of supplying at a timing, a delay time of a tree path from the clock generation circuit to the logic block is calculated, and a buffer on the tree is selectively replaced with a plurality of buffers having different input logic thresholds. Then, the propagation delay time of each tree is adjusted to be the same.

Further, the clock distribution circuit according to the present invention is a clock distribution circuit which supplies a synchronous clock signal from a clock generation circuit to a plurality of logical blocks at the same timing via buffers arranged in a tree shape. Buffers having different input logic thresholds are mixed on a line, and the propagation delay time of each tree is the same.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments and examples of the present invention will be described below in order. According to a preferred embodiment of the present invention, in a preferred embodiment, a synchronous clock signal from a clock generation circuit is obtained from circuit connection information of a clock tree in which standard buffers are arranged in a tree shape for a plurality of logical blocks and delay information of the buffer. Calculate the propagation delay time of each tree leading to each logical block, detect the tree of the minimum propagation delay time from the calculated propagation delay information, and for the standard buffer not involved in the tree of the minimum propagation delay time, The input logic threshold value is different from the standard buffer,
From among a plurality of buffers prepared in advance, the buffer is selectively replaced with a buffer that reduces the propagation delay time of the tree after replacing the standard buffer, so that the propagation delay time of each tree becomes the same. Automatically adjust to Here, the "standard buffer" refers to a standard buffer whose input logical threshold value (input terminal voltage at which the logical value of the buffer output is inverted) used for the clock tree is about 1/2 of the power supply voltage.

In the present invention, a plurality of buffers having different input logic thresholds from the standard buffer are prepared, and the driving capability (current driving capability) of these buffers is made equal to that of the standard buffer. Then, the standard buffers on the clock tree are selectively replaced with buffers having different input logic thresholds, and the delay value of each branch of the clock tree is finely adjusted.

FIG. 1 is a flowchart for explaining the overall processing in the embodiment of the present invention.

First, in a first step, a clock tree is created by the clock tree synthesis means 11 using a standard buffer, and a net list 13 including the wiring capacity and the wiring resistance of the semiconductor integrated circuit is created. The clock tree synthesis means 11 uses a conventional one.

Next, in a second step, the skew calculating means 14 calculates the clock skew. At this time, the delay difference (clock skew) of each branch of the clock tree is calculated by a circuit simulator or the like using the netlist 13 and the delay library 12. The delay library 12 stores the delay of the standard buffer in the clock tree, information on an increase in delay due to the output load capacity, information on input voltage rounding due to the output load capacity, and the like. The delay library 12 also includes information of the buffer list 15 having different input logic thresholds.

Next, in a third step, for the clock tree created in the first step, the shortest tree path delay time calculating means 16 calculates a tree having the shortest propagation delay time among the branches of the clock tree. Get directions,
The propagation delay time is extracted.

Next, in a fourth step, the buffer replacement means 17 replaces the standard buffers of all other tree paths with the delay library 12 so as to match the propagation delay time of the tree path with the shortest propagation delay time. Referring to the buffer list 15, a buffer having a different input logical threshold value from the standard buffer is selected from the buffer list 15, and a buffer to be replaced is determined.

At this time, if the root (root) side of the clock tree is set to a higher tree level (that is, the tree level is lower at the leaf side of the tree), the evaluation of the buffer replacement decision is first made at the lower tree level. , That is, from the side far from the clock generation circuit. Further, the standard buffer associated with the tree path having the shortest propagation delay time, that is, the standard buffer located closer to the clock generation circuit from the tree having the shortest propagation delay time is not replaced.

The input voltage rounding of the clock signal input to the standard buffer to be evaluated is calculated with reference to the delay library 12, and the calculated rounding of the input signal waveform after the buffer replacement is smaller than that of the standard buffer. The buffer to be replaced is selected so that the propagation delay time between input and output is reduced.

When the clock input of the logic block to which the clock is supplied is set to high active, the rising speed of the output voltage is made faster than that of the standard buffer by replacing with a buffer having a low input logic threshold value. .

Conversely, when the clock input of the logic block to which the clock is supplied is low active, the buffer is replaced with a buffer having a high input logic threshold value.
Make the output voltage fall speed faster than the standard buffer.

This processing is sequentially performed toward the higher tree level, and when the delay time of the tree path in which the buffer is replaced approaches the propagation time of the tree path having the shortest propagation delay time, the buffer replacement processing is performed. To end.

Here, if the propagation delay time in the tree is reduced by replacing the buffer at the higher tree level with the buffer at the lower tree level, the buffer at the lower tree level is replaced. It does not replace the higher buffer, but replaces the higher buffer at the tree level.

FIG. 2 is a diagram for explaining an embodiment of the present invention. By clock tree synthesis, D-type flip-flops 30, 31,
32, 33, standard buffers 23, 24, 2
Synchronous clock signals are distributed via 5, 26, 27, 28 and 29. Each D-type flip-flop takes in the data signal at the clock high active, that is, at the rising edge of the clock signal.

In FIG. 2, P1 is a clock generation circuit 2
2 represents a tree path reaching the D-type flip-flop 30 via the standard buffers 23, 24, 26, and P2 represents a standard path 23, 24, 2 from the clock generation circuit 22.
7 represents a tree path reaching the D-type flip-flop 31 via the clock signal generator 7, and P3 represents the D-type flip-flop 3 from the clock generation circuit 22 via the standard buffers 23, 25 and 28.
2 and a tree path P4 from the clock generation circuit 23 to the D-type flip-flop 33 via the standard buffers 23, 25 and 29.

First, the propagation delay time TP1 of the tree path P1 and the propagation delay time TP of the tree path P2 are referred to by a circuit simulator or the like with reference to the delay library of each buffer.
2. The propagation delay time TP3 of the tree path P3 and the propagation delay time TP4 of the tree path P4 are measured.

Next, the propagation delay times TP1, TP2, TP
3 and TP4, respectively, to identify the shortest tree path. Here, it is assumed that TP1 is the minimum and the shortest tree path is P1.

Therefore, the standard buffers to be replaced are not related to the tree path P1 (not the buffers 24, 26 on the shortest tree path P1), and the standard buffers 25, 27, 2
8, 29.

The other tree routes P2, P3, P4
And the propagation delay time difference between the shortest tree route P1 and TP2-TP1 = ΔT21, TP3-TP1 = ΔT31, and TP4-TP1 = ΔTP41, respectively.

The standard buffer is replaced for the tree path P2. Since the D-type flip-flop 31 is clock high active, by replacing the standard buffer 27 with a buffer having a lower input logic threshold value, the output voltage can be raised earlier than before the replacement, and the delay time difference ΔT21 is reduced. Make it smaller. At this time, buffers are sequentially selected from a replaceable buffer list. That is, the output voltage rounding of the buffer 24 due to the output load amount is calculated by a circuit simulator or the like, and the time from the input rising to the output rising of the buffer replacing the standard buffer 27 affected by the output voltage rounding is calculated.
Select the buffer that minimizes 1.

Similarly, the standard buffer 28 is replaced for the tree path P3, and the standard buffer 29 is also replaced for the tree path P4. These tree paths P
3. In P4, standard buffer 2 with high tree level
If ΔT31 and ΔT41 are smaller by replacing only 5 than by replacing the standard buffers 28 and 29,
Only the standard buffer 25 is replaced. Of course, replacing all of the standard buffers 25, 28, and 29 results in ΔT31, T
When 41 becomes smaller, all of them are replaced.

Note that there are the following precautions in the buffer replacement process. For example, if a plurality of standard buffers on the clock line are replaced in series with buffers having a low input logic threshold, the output rises faster than the standard buffer at the rising edge of the clock signal, but the output rises at the falling edge of the clock signal. Conversely, since the signal rises later than the standard buffer, the propagation delay does not change after all in the rising and falling of the clock signal, and the effect of skew reduction by buffer replacement having different input logic thresholds is reduced.

For this reason, if a buffer having a different logic threshold value is replaced closest to the logic block receiving the clock signal, that is, farthest from the clock generation circuit, the operation of the logic block receiving the clock is directly affected. , High effect.

Further, where the input rounding of the input voltage is large, the change in the input logic threshold value of the buffer greatly affects the output. Therefore, it is highly effective to replace the buffer with a buffer having a different input logic threshold value.

FIG. 3 is a diagram for explaining an embodiment in which the present invention is applied to a large-scale circuit. The circuit shown in FIG. 3 has a clock tree of two mutually independent synchronous clock signals from the clock generation circuits 38 and 39. In this case, the buffer is replaced for each clock tree to reduce clock skew.

As an operational effect of each of the above embodiments, the buffer on the clock line in the clock tree is replaced with a buffer having a different input logic threshold value, and the output of the replaced buffer is replaced by the output rounding effect of the preceding stage. By making the transition faster than the standard buffer before replacement, the delay time of the clock signal is made equal to any logic block, thereby preventing the malfunction of the logic block,
It is possible to improve the operating frequency of the circuit.

When the input clock signal is high active, the output delay time difference Δt between after buffer replacement and before buffer replacement can be approximated by the following equation (1).

[0040]

(Equation 1)

For example, the input voltage rounding of the buffer for replacing the clock signal occurs at one nanosecond per volt (ns), and the input logic threshold of the standard buffer is 1.65.
[V], the input logic threshold of the buffer to be replaced is 1.4
In the case of [V], the rising of the output of the buffer after the replacement is 150 picoseconds (ps) earlier than before the buffer replacement.

Therefore, when the clock skew occurs several hundreds of picoseconds, this embodiment can reduce the clock skew to several tens of picoseconds or less.

In the above embodiment, the size of the buffer to be replaced does not need to be changed, so that, for example, the degree of integration of the semiconductor integrated circuit does not need to be changed. Further, since the driving capability of the buffer does not need to be changed, the power consumption of the semiconductor integrated circuit does not increase by replacing the buffer. In the above embodiment, since the buffer is changed to a buffer having a different input logic threshold, the noise margin is low, and the buffer having the changed input logic threshold may malfunction due to a voltage change due to noise. Naturally, it is necessary to give sufficient consideration to noise suppression.

[0044]

As described above, according to the present invention,
By replacing the buffer on the clock line in the clock tree with a buffer having a different input logic threshold, and by the effect of the previous output rounding, the output of the replaced buffer is shifted earlier than the standard buffer before replacement. , It is possible to reduce the propagation delay difference (clock skew) between the trees. Therefore, according to the present invention, there is an effect that the delay time of the clock signal is made equal to any logic block, malfunction of the logic block is prevented, and the operating frequency of the circuit can be improved.

One example of the effect of the present invention is quantitatively described. When the input clock signal is high active, for example, the input voltage rounding of the buffer for replacing the clock signal is one.
When 1 nanosecond (ns) occurs per volt, the input logic threshold of the standard buffer is 1.65 [V], and the input logic threshold of the buffer to be replaced is 1.4 [V], compared to before the buffer replacement. The rising edge of the buffer output after replacement is 150
When the clock skew is increased by several hundred picoseconds due to the picosecond (ps) being faster, the present invention can reduce the clock skew to several tens of picoseconds or less.

Further, according to the present invention, since the size of the buffer to be replaced does not need to be largely changed, the degree of integration of the semiconductor integrated circuit does not need to be changed.

Further, according to the present invention, since the drive capability of the buffer does not need to be changed, the power consumption of the semiconductor integrated circuit does not increase.

[Brief description of the drawings]

FIG. 1 is a flowchart for explaining processing in an embodiment of the present invention.

FIG. 2 is a diagram for explaining an embodiment of the present invention.

FIG. 3 is a diagram for explaining an embodiment in which the present invention is applied to a large-scale circuit.

FIG. 4 is a diagram for explaining a clock tree.

[Explanation of symbols]

 23-29 Buffer 30-33 D-type flip-flop 34-37 Logic block group 38, 39 Clock generation circuit P1-P4 Tree path 102-109 Buffer 110-113 Logic block

Claims (4)

(57) [Claims] 1. A clock distribution method for supplying a synchronous clock signal from a clock generation circuit to a plurality of logic blocks at the same timing through buffers arranged in a tree pattern, wherein the clock generation circuit is connected to the logic blocks. The delay time of the tree path to the tree is calculated, and the buffer on the tree is selectively replaced with a plurality of buffers having different input logic threshold values, and the propagation delay time of each tree is adjusted to be the same. Clock distribution method. 2. A synchronous clock signal from a clock generating circuit is transferred to each of the logical blocks from circuit connection information of a clock tree in which standard buffers are arranged in a tree-like manner for a plurality of logical blocks and delay information of the buffers. Calculate the propagation delay time of the leading tree, detect the tree of the minimum propagation delay time from the calculated propagation delay information, and, for a standard buffer that is not involved in the tree of the minimum propagation delay time, From among a plurality of buffers prepared in advance with different threshold values, the buffer is selectively replaced with a buffer that reduces the propagation delay time of the tree after replacing the standard buffer, and the propagation delay of each tree is reduced. A clock distribution method, wherein the clock is automatically adjusted so that the times are the same. 3. The clock distribution method according to claim 2, wherein the driving capability of the buffer replaced with the standard buffer is made equal to that of the standard buffer. 4. A clock distribution circuit for supplying a synchronous clock signal from a clock generation circuit to a plurality of logic blocks at the same timing via buffers arranged in a tree pattern, wherein an input logic threshold value is provided on a clock line. A clock distribution circuit, wherein buffers different from each other are mixed and the propagation delay time of each tree is the same.