JP2005122457A - Clock transmission circuit and method for designing it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock transmission circuit capable of reducing the power consumption by a clock line and facilitating to design the layout of a semiconductor integrated circuit, and a method for designing it. <P>SOLUTION: The clock transmission circuit transmits clocks outputted from a clock source to a transmission destination circuit and includes at least one clock dividing circuit positioned in the vicinity of the clock source for outputting a second clock obtained when the frequency of a first clock outputted from the clock source is divided into a frequency that is 1/2 to the power of m (m is a natural number); and at least one clock restoration circuit positioned in the vicinity of the receiving circuit for restoring, according to the second clock outputted from the clock dividing circuit, a clock whose frequency is equal to the frequency of the second clock multiplied by two to the power of n (n is a natural number) and which the receiving circuit needs, to supply the restored clock to the receiving circuit. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a clock transmission circuit for transmitting a clock output from a clock supply source to a transmission destination circuit and a design method thereof.

  The clock output from the clock supply source is transmitted to the transmission destination circuit using this clock via the clock line (clock net). For example, in the case of a semiconductor integrated circuit, this clock line is connected from a clock supply source such as a PLL circuit (phase-locked loop circuit) to a plurality of transmission destination circuits including a circuit such as a flip-flop. It becomes long. For this reason, the clock frequency (the number of times of switching) in the clock line extremely affects the increase in power consumption.

  Conventionally, as one method for reducing the power consumption of a semiconductor integrated circuit, for example, as disclosed in Patent Document 1, a method of temporarily lowering the frequency of a clock that is a reference operation signal is known.

  Patent Document 1 relates to a frequency control circuit, which can supply a system clock having a plurality of clock frequencies that achieve different throughputs, and that corresponds to a control signal with respect to a target circuit that performs processing in synchronization with the system clock. When a clock supply circuit that supplies a system clock having a clock frequency and a throughput T is required, the two clock frequencies are determined from the value of the throughput T and the value of the throughput that can be realized from the clock frequency that can be generated by the clock supply circuit. And a control means for outputting a control signal to the clock supply circuit for determining the period and selecting two clock frequencies for each determined period and outputting the selected clock frequency as a system clock.

  As described above, Patent Document 1 discloses a technique for controlling the clock frequency in accordance with the throughput required for the system. When high throughput is not required in the system, the clock frequency is decreased, and conversely When high throughput is required, control is performed to increase the clock frequency. That is, the cited document 1 is a technique for increasing the power consumption reduction effect by performing this control dynamically and speedily.

  As described above, one of the conventional logic circuit approaches for reducing power consumption has been to reduce the clock frequency when a high-speed clock is not required. However, when a high-speed clock is really necessary, it is necessary to increase the clock frequency, and the power consumption at that time is still high. Also, when designing a semiconductor integrated circuit, it is necessary to design with the maximum frequency of the clock as a target. Therefore, special care for the clock line has always been necessary when designing the layout mainly.

JP 2003-140767 A

  An object of the present invention is to provide a clock transmission circuit and a design method thereof that can solve the problems based on the above-described prior art, reduce power consumption in a clock line, and facilitate layout design of a semiconductor integrated circuit. It is to provide.

To achieve the above object, the present invention provides a clock transmission circuit for transmitting a clock output from a clock supply source to a transmission destination circuit,
Based on a first clock that is arranged in the vicinity of the transmission destination circuit and is output from the clock supply source, the transmission destination circuit requires an n-th power of 2 (n is a natural number) required by the transmission destination circuit. A clock transmission circuit comprising: at least one clock recovery circuit that recovers a clock having a frequency and supplies the clock to the transmission destination circuit.

The present invention is a clock transmission circuit for transmitting a clock output from a clock supply source to a transmission destination circuit,
At least one clock that is arranged in the vicinity of the clock supply source and outputs a second clock obtained by dividing the first clock output from the clock supply source to a frequency that is a power of ½ m (m is a natural number). A frequency dividing circuit and a second power of 2 times the second clock required by the transmission destination circuit based on a second clock that is arranged in the vicinity of the transmission destination circuit and is output from the clock frequency division circuit A clock transmission circuit comprising: at least one clock recovery circuit that recovers a clock having a frequency (n is a natural number) and supplies the clock to the transmission destination circuit.

  Here, it is preferable that the clock recovery circuit includes means for outputting a clock having a frequency equal to the clock input to the clock recovery circuit and supplying the clock to the transmission destination circuit during a scan test.

  Further, the clock recovery circuit is arranged outside the semiconductor integrated circuit, and based on the clock output from the semiconductor integrated circuit, two clocks output from the semiconductor integrated circuit required by the transmission destination circuit are required. It is preferable to restore the clock multiplied by n.

The present invention also provides a design method for the clock transmission circuit described above,
Make the clock recovery circuit into a cell library in advance,
When designing a logic circuit of a semiconductor integrated circuit, the clock recovery circuit is arranged between a clock route buffer and a circuit that operates using a clock output from the clock recovery circuit in the transmission destination circuit.
In designing a layout of the semiconductor integrated circuit, a clock transmission circuit design method is provided in which a clock tree is synthesized from the clock root buffer in consideration of a delay time due to the clock restoration circuit.

  According to the present invention, since the clock frequency in the clock line can be lowered below the clock frequency required by the transmission destination circuit, the power consumption in the clock line can be greatly reduced, and the semiconductor integrated circuit When designing the layout, it is possible to eliminate the need for special care for the clock line, and the design can be easily performed.

  Hereinafter, a clock transmission circuit and a design method thereof according to the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

FIG. 1 is a schematic configuration diagram of an embodiment of a clock transmission circuit of the present invention.
The clock transmission circuit 10 shown in FIG. 1 transmits a clock output from the clock supply source 16 to a transmission destination circuit 18 that uses this clock via a clock line 30. And a clock recovery circuit 14.

  The clock divider circuit 12 is arranged in the vicinity of the clock supply source 16 and divides the clock output from the clock supply source 16 to a frequency that is ½ m times (where m is a natural number) and outputs it. The frequency-divided clock output from the clock frequency dividing circuit 12 is supplied to the clock restoration circuit 14 via the clock line 30.

  The configuration of the clock divider circuit 12 is not limited in any way, but in the case of this embodiment, a flip-flop 20 that divides the clock output from the clock supply source 16 to a frequency that is ½ times and outputs it is provided. A clock output from the clock supply source 16 is input to the clock input terminal of the flip-flop 20, and a signal output from the inverted output Q is input to the data input terminal. From the output terminal Q of the flip-flop 20, a clock obtained by dividing the clock output from the clock supply source 16 to a frequency ½ times is output.

  On the other hand, the clock restoration circuit 14 is arranged in the vicinity of the transmission destination circuit 18 and based on the frequency-divided clock output from the clock division circuit 12, the clock division circuit 12 required by the transmission destination circuit 18. A clock having a frequency that is a power of 2 to the nth power (n is a natural number) of the divided clock output from is restored. The recovered clock output from the clock recovery circuit 14 is supplied to the transmission destination circuit 18 via the clock route buffer 22.

  The configuration of the clock recovery circuit 14 is not limited at all, but in the case of the present embodiment, the clock CLK_out having a frequency twice that of the clock CLK divided by half the frequency output from the clock frequency divider circuit 12 is obtained. It is to be restored, and includes two buffers 24 and 26 connected in series and an EXOR circuit 28 as a delay circuit. The EXOR circuit 28 receives the divided clock CLK output from the clock dividing circuit 12 and the clock CLK_delay obtained by delaying the clock CLK by two buffers 24 and 26 of the delay circuit for a predetermined time. The The EXOR circuit 28 outputs the restored clock CLK_out.

  The clock supply source 16 is a circuit that generates a clock such as a PLL circuit, for example, but any conventionally known clock supply source can be used in the present invention. The transmission destination circuit 18 is a circuit including a circuit that operates using a clock, such as a latch or a flip-flop. The clock route buffer 22 is used as a symbol for clock tree synthesis when designing a logic circuit of a semiconductor integrated circuit, and the number and arrangement of circuits using a clock included in the transmission destination circuit 18 when designing a layout. Is synthesized as a clock tree.

  In the clock transmission circuit 10 shown in FIG. 1, as shown in the timing chart of FIG. 2, the clock output from the clock supply source 16 is divided into ½ times the frequency by the flip-flop 20 of the clock frequency dividing circuit 12. And output as a clock CLK after frequency division. The divided clock CLK is transmitted to the clock restoration circuit 14 through the clock line 30, and the divided clock CLK and the clock CLK are transmitted through the two buffers 24 and 26 of the delay circuit for a predetermined time. EXOR with the delayed clock CLK_delay is taken, and the recovered clock CLK_out having a frequency twice that of the clock CLK is output from the EXOR circuit 28, ie, the clock recovery circuit 14.

As shown in the timing chart of FIG. 2, the operation timing of the clock CLK_delay varies between the worst case (Best) and the best case (Best), and the duty ratio of the clock CLK_out changes. The high-level and low-level pulse widths of the clock CLK_out need to satisfy the specifications of a circuit such as a flip-flop (FF) included in the transmission destination circuit 18, but in the case of this embodiment, in the worst case The pulse width of the low level of the clock CLK_out is not less than t _ckl (Min), which is the minimum value of the low level required by the flip-flop, and in the best case, the pulse width of the high level of the clock CLK_out requires the flip-flop. As long as it is equal to or higher than t _ckh (Min) which is the minimum value of the high level, no problem occurs.

  In the clock transmission circuit 10, the clock output from the clock supply source 16 is divided and transmitted via the clock line 30, and then the clock having the frequency required by the transmission destination circuit 18 immediately before the transmission destination circuit 18 is obtained. Restored. That is, since the clock frequency in the clock line 30 can be made lower than the clock frequency required by the transmission destination circuit 18, power consumption in the clock line 30 can be greatly reduced, and the semiconductor integrated circuit When performing layout design, care for the clock line 30 can be handled in the same manner as other signal lines, and the design can be easily performed.

  Note that the effect of reducing the power consumption depends on how the delay circuit used in the clock recovery circuit 14 is made and, for example, when a PLL circuit is used as the clock supply source 16, the power consumption of the PLL circuit or the like.

  However, the effect of reducing the power consumption in the PLL circuit and the clock line 30 when the frequency of the transmitted clock is ½ m times power is much higher than the power consumption in the clock recovery circuit 14. In particular, since the power consumption of the PLL circuit greatly depends on the oscillation frequency of the voltage controlled oscillator, the effect of reducing the power consumption of the PLL circuit can greatly contribute to the reduction of the power consumption of the entire semiconductor integrated circuit. In addition, since a PLL circuit having a low maximum oscillation frequency of the voltage controlled oscillator can be used, it is possible to select a type of PLL circuit that consumes less power.

  As shown in FIG. 3, for example, when a PLL circuit or the like is used as the clock supply source 16, the frequency of the clock output from the PLL circuit is preliminarily determined from the clock divider circuit 12 of the clock transmission circuit 10 shown in FIG. By setting the frequency equal to the frequency-divided clock CLK to be output, the clock frequency dividing circuit 12 can be made unnecessary, and the power consumption of the clock frequency dividing circuit 12 and the PLL circuit can be reduced. In particular, since the power consumption of the PLL circuit is large, a further significant power consumption reduction effect can be obtained.

  It is also possible to make the clock transmission circuit of the present invention compatible with a scan test. In this case, the circuit configuration shown in FIG. 4 can be used as the clock recovery circuit 14 although it is not limited at all. The clock restoration circuit 14 shown in the figure is further provided with an AND circuit 32 in the clock restoration circuit 14 shown in FIG. The AND circuit 32 receives the frequency-divided clock CLK output from the clock frequency dividing circuit 12 and the scan mode signal SCANMODE. The output signal of the AND circuit 32 is input to the buffer 24.

  In the clock restoration circuit 14 shown in FIG. 4, the scan mode signal SCANMODE is a signal that becomes low level, for example, during a scan test. Therefore, during the scan test, the output signal of the AND circuit 32 is fixed at a low level, and the clock CLK is output as it is from the EXOR circuit 28 as the restored clock CLK_out. Further, by using the bypass mode of the PLL circuit serving as the clock supply source 16, the clock input from the outside to the PLL circuit is directly output from the PLL circuit, and the transmission destination circuit 18 is directly controlled by the clock input from the outside. Can be made possible.

  In the above embodiment, an example in which the clock output from the clock supply source 16 is divided into ½ times the frequency has been described. However, in the present invention, the frequency is divided into ½ times the frequency. Without being limited to the above, the frequency can be divided to a frequency of ½ m times as described above.

  FIG. 5 is a schematic configuration diagram of another embodiment of the clock transmission circuit of the present invention, and FIG. 6 is a timing chart showing the operation timing thereof. FIG. 5 shows that the clock output from the PLL circuit 16 in the clock transmission circuit shown in FIG. 3 is a clock having the same frequency as that obtained by dividing the clock required by the transmission destination circuit 18 by a quarter of the frequency. Then, the clock recovery circuit 14 recovers the clock having the four times frequency required by the transmission destination circuit 18 on the basis of the clock CLK frequency-divided to ¼ times the frequency. 2 shows an example of a clock transmission circuit in the case of supplying to the circuit.

  As shown in FIG. 5, the clock recovery circuit 14 that recovers a clock having a frequency four times that of the clock CLK is a clock CLK_d1 that is delayed from the clock CLK output from the PLL circuit 16 by different predetermined times. , CLK_d2, CLK_d3, and three sets of delay circuits 34a, 34b, 34c, two EXOR circuits 36a, 36b, and an OR circuit 38, each composed of two buffers connected in series.

  The EXOR circuit 36a is supplied with the clock CLK output from the PLL circuit 16 and divided by a quarter of the frequency, and the clock CLK_d1 obtained by delaying the clock CLK by the delay circuit 34a. The clock CLK_d2 obtained by delaying the clock CLK_d1 by the delay circuit 34b and the clock CLK_d3 obtained by delaying the clock CLK_d2 by the delay circuit 34c are input to 36b. The output signals of the EXOR circuits 36a and 36b are input to the OR circuit 38. The OR circuit 38 outputs a restored clock CLK_out having a frequency four times that of the clock CLK.

  As described above, the PLL circuit 16 outputs the clock CLK having a frequency equal to the clock obtained by dividing the clock required by the transmission destination circuit 18 to a frequency that is ¼ times the clock CLK. Is supplied to the clock recovery circuit 14.

  In the clock restoration circuit 14, the delay circuits 34a, 34b, and 34c generate clocks CLK_d1, CLK_d2, and CLK_d3 that are delayed from the clock CLK by different predetermined times. As shown in the timing chart of FIG. 6, the clock CLK_d1 is delayed by the delay time of the delay circuit 34a with respect to the clock CLK, the clock CLK_d2 is delayed by the delay time of the delay circuit 34b with respect to the clock CLK_d1, and the clock CLK_d3 Is delayed by the delay time of the delay circuit 34c with respect to the clock CLK_d2.

  The EXOR of the clock CLK and the clock CLK_d1 is taken, and the EXOR circuit 36a outputs a signal EX1 having a high level pulse width substantially equal to the delay time of the delay circuit 34a as shown in the timing chart of FIG. . Similarly, EXOR of the clock CLK_d2 and the clock CLK_d3 is taken, and a signal EX2 having a pulse width substantially equal to the delay time of the delay circuit 34c is output from the EXOR circuit 36b. The time interval between the high level of the signal EX1 and the high level of the signal EX2 is a time interval substantially equal to the delay time of the delay circuit 34b.

  Subsequently, the outputs of the EXOR circuits 36a and 36b are ORed, and a clock CLK_out having a frequency four times that of the clock CLK is output from the OR circuit 38 as shown in the timing chart of FIG. The data is supplied to the transmission destination circuit 18 via the route buffer 22.

  In the clock transmission circuit shown in FIG. 5, the frequency of the clock CLK output from the PLL circuit 16 is ½ times that shown in FIG. 4 times. In the above embodiment, the clock is divided by 1/4 frequency and transmitted, and restored to a clock having a frequency of 4 times at the transmission destination. Similarly, the clock is divided by 1/2 to the mth power. It is possible to transmit the signal around the clock and restore it to a clock having a frequency of 2n times the transmission destination. Note that m and n may be the same value or different values.

  In addition, as shown in FIG. 7, the PLL circuit 16 may be used to match the phase of a reference clock (external CLK) input from the outside and a clock used internally (internal CLK). In this case as well, the present invention can be similarly applied. In the clock transmission circuit shown in FIG. 7, as shown in the timing chart of FIG. 8, the clock CLK output from the flip-flop 20 of the clock frequency dividing circuit 12 is obtained by dividing the external CLK by a half frequency. However, the internal CLK is recovered by the clock recovery circuit 14, has a frequency twice that of the clock CLK, and is phase-synchronized with the external CLK.

  Next, FIG. 9 is a schematic configuration diagram of another embodiment of the clock transmission circuit of the present invention. This figure shows an example in which the clock transmission circuit of the present invention is applied to a large-scale semiconductor integrated circuit when a plurality of clocks having different frequencies are required. In the figure, a PLL circuit is used as the clock supply source 16, and the clocks output from the two clock divider circuits 12a and 12b and the PLL circuit 16 and the two clock divider circuits 12a and 12b are respectively supplied. Two clock recovery circuits 14a, 14b, 14c, three clock route buffers 22a, 22b, 22c and three transmission destination circuits 18a, 18b, 18c respectively corresponding thereto are shown.

  The PLL circuit 16 outputs a clock having a frequency equal to the clock obtained by dividing the clock having the frequency required by the transmission destination circuit 18a by a half frequency. The clock divider circuit 12a outputs a clock obtained by dividing the clock output from the PLL circuit 16 by a half frequency, and the clock divider circuit 12b further outputs the clock output from the clock divider circuit 12a. A clock obtained by dividing the frequency by ½ times, that is, a clock obtained by dividing the clock output from the PLL circuit 16 to ¼ times the frequency is output.

  On the other hand, the clock restoration circuits 14a, 14b, and 14c restore clocks having a frequency twice that of the clocks output from the PLL circuit 16 and the clock divider circuits 12a and 12b, respectively, and clock root buffers 22a, 22b, and 22c, respectively. To the destination circuits 18a, 18b and 18c. That is, assuming that the frequency of the clock required by the transmission destination circuit 18a is 1 (clock having a frequency twice that of the clock output from the PLL circuit 16), the transmission destination circuits 18b and 18c are respectively connected to the transmission destination circuit 18a. A clock having a frequency ½ times and ¼ times that of the clock supplied to is supplied.

  As described above, by providing a plurality of clock frequency dividing circuits 12, clocks having different frequencies are generated, and by providing a plurality of clock restoration circuits 14 corresponding thereto, the transmission destination circuit 18 requires. A plurality of clocks having different frequencies can be handled.

  Next, a method for designing a clock transmission circuit of the present invention will be described.

  FIG. 10 shows an example of a clock transmission circuit designed using the clock recovery circuit 14 shown in FIG. 4 as a cell library and using the clock recovery circuit 14 converted into the cell library. In the design method of the clock transmission circuit of the present invention, as described above, the clock restoration circuit 14 is made into a cell library, and when designing the logic circuit of the semiconductor integrated circuit, the clock route buffer 22 and the transmission destination circuit 18 When the clock recovery circuits 14a, 14b, 14c,... Are arranged between the flip-flops 40a, 40b, 40c,... And the layout design is performed, the delay time due to the clock recovery circuits 14a, 14b, 14c,. Thus, the clock tree 42 is synthesized from the clock root buffer 22.

  By making the clock restoration circuit 14 into a cell library, it becomes possible to accurately predict the fluctuation in the output timing of the restored clock CLK_out output from the clock restoration circuit 14 after layout. Therefore, when synthesizing the clock tree 42 from the clock root buffer 22, the synthesizing tool takes into account the delay time of the clock recovery circuit 14, and there is a skew between the clocks supplied to the respective flip-flops 40a, 40b, 40c. It is possible to synthesize the clock tree 42 so that there is not.

  Note that the flip-flops 40a, 40b, and 40c included in the transmission destination circuit 18 represent a circuit that operates using the clock transmitted by the clock transmission circuit of the present invention, and are not limited thereto. For example, a latch or a logic gate circuit may be used.

  Moreover, although the said embodiment gave and demonstrated the example in the case of applying this invention to the inside of a semiconductor integrated circuit, this invention is not limited to this, As shown in an example in FIG. The same applies to the outside.

  In the example shown in FIG. 11, the clock output from the output pin 48 via the I / O buffer (input / output buffer) 46 of the semiconductor integrated circuit 44 is transmitted to the clock restoration circuit 14 existing outside the semiconductor integrated circuit 44. Further, the restored clock output from the clock restoration circuit 14 is supplied to the transmission destination circuit 18. In this case, the operating frequency of the clock in the I / O buffer 46 of the semiconductor integrated circuit 44 can be lowered to a frequency that is ½ m times the power. Since the I / O buffer 46 has a very large cell size compared to the internal circuit, the power consumption can be greatly reduced by lowering the clock frequency to a frequency that is ½ m times the frequency of the clock.

  Also, on the substrate on which the semiconductor integrated circuit 44, the clock recovery circuit 14, and the transmission destination circuit 18 are mounted, the clock frequency in the clock line 30 can be lowered, and the power consumption can be reduced in the same manner. In addition, it is possible to dispense with special care when laying out the substrate wiring.

The present invention is basically as described above.
As described above, the clock transmission circuit and the design method thereof according to the present invention have been described in detail. However, the present invention is not limited to the above embodiment, and various improvements and modifications may be made without departing from the gist of the present invention. Of course.

1 is a schematic configuration diagram of an embodiment of a clock transmission circuit of the present invention. 3 is a timing chart of an embodiment illustrating an operation of the clock transmission circuit illustrated in FIG. 1. FIG. 6 is a schematic configuration diagram of another embodiment of a clock transmission circuit of the present invention. It is a block schematic diagram of another embodiment of the clock recovery circuit used in the clock transmission circuit of the present invention. FIG. 6 is a schematic configuration diagram of another embodiment of a clock transmission circuit of the present invention. 6 is a timing chart of an embodiment illustrating an operation of the clock transmission circuit illustrated in FIG. 5. FIG. 6 is a schematic configuration diagram of another embodiment of a clock transmission circuit of the present invention. 8 is a timing chart of an embodiment illustrating the operation of the clock transmission circuit illustrated in FIG. 7. FIG. 6 is a schematic configuration diagram of another embodiment of a clock transmission circuit of the present invention. FIG. 6 is a schematic configuration diagram of another embodiment of a clock transmission circuit of the present invention. FIG. 6 is a schematic configuration diagram of another embodiment of a clock transmission circuit of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Clock transmission circuit 12 Clock division circuit 14 Clock restoration circuit 16 Clock supply source 18 Transmission destination circuit 20, 40a, 40b, 40c Flip-flop 22 Clock route buffer 24, 26 Buffer 28, 36a, 36b EXOR circuit 30 Clock line 32 AND Circuit 34a, 34b, 34c Delay circuit 38 OR circuit 42 Clock tree 44 Semiconductor integrated circuit 46 I / O buffer 48 Output pin

Claims (5)

A clock transmission circuit for transmitting a clock output from a clock supply source to a transmission destination circuit;
Based on a first clock that is arranged in the vicinity of the transmission destination circuit and is output from the clock supply source, the transmission destination circuit requires an n-th power of 2 (n is a natural number) required by the transmission destination circuit. A clock transmission circuit comprising: at least one clock recovery circuit that recovers a clock having a frequency and supplies the clock to the transmission destination circuit. A clock transmission circuit for transmitting a clock output from a clock supply source to a transmission destination circuit;
At least one clock that is arranged in the vicinity of the clock supply source and outputs a second clock obtained by dividing the first clock output from the clock supply source to a frequency that is a power of ½ m (m is a natural number). A frequency dividing circuit and a second power of 2 times the second clock required by the transmission destination circuit based on a second clock that is arranged in the vicinity of the transmission destination circuit and is output from the clock frequency division circuit A clock transmission circuit comprising: at least one clock recovery circuit that recovers a clock having a frequency (n is a natural number) and supplies the clock to the transmission destination circuit.   3. The clock transmission circuit according to claim 1, wherein the clock recovery circuit includes means for outputting a clock having a frequency equal to a clock input to the clock recovery circuit and supplying the clock to the transmission destination circuit during a scan test. .   The clock recovery circuit is arranged outside the semiconductor integrated circuit, and based on the clock output from the semiconductor integrated circuit, the clock output from the semiconductor integrated circuit required by the transmission destination circuit is raised to the second power of n. The clock transmission circuit according to claim 1, which restores a double clock. A method for designing a clock transmission circuit according to any one of claims 1 to 3,
Make the clock recovery circuit into a cell library in advance,
When designing a logic circuit of a semiconductor integrated circuit, the clock recovery circuit is arranged between a clock route buffer and a circuit that operates using a clock output from the clock recovery circuit in the transmission destination circuit.
A clock transmission circuit design method comprising: synthesizing a clock tree from the clock root buffer in consideration of a delay time due to the clock restoration circuit when designing the layout of the semiconductor integrated circuit.

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