KR100838365B1 - Circuit and method for aligning data - Google Patents

Abstract

A circuit and a method for aligning data are provided to improve the degradation of jitter skew characteristics generated by using several clocks for data arrangement, by using a clock with high frequency in a first latch part. A first latch part(320) latches serially inputted data by using a plurality of first clocks having different phase and equal frequency. A second latch part(330) latches the data outputted from the first latch part by using a plurality of second clocks with more various phases and lower frequency than the first clock. A divider part(350) generates the second clock by dividing the first clock. A timing control part(340) aligns parallel data outputted from the second latch part by controlling timing of the parallel data.

Description

Circuit and method for aligning data

1 is a diagram illustrating a process in which clocks having four different phases latch data in series;

2 is a block diagram of a conventional data alignment circuit.

3 is a block diagram of an embodiment of a data alignment circuit according to the present invention;

4a, b, and c are views related to the frequency divider 350 of FIG. 3, and FIG. 4a is a frequency converting part, FIG. 4b is a phase converting part, and FIG. .

5 is a timing diagram showing the overall operation of the data alignment circuit of FIG.

* Explanation of symbols for the main parts of the drawings

320: first latch portion 330: second latch portion

340: timing adjusting unit 350: dispensing unit

The present invention relates to a data alignment circuit, and more particularly, to a technique for aligning serially input data in parallel.

In order to process data at high speed between various semiconductor chips or within a chip, data is generally transmitted and received using a serial interface. The receiver in the chip then receives this serial data and internally aligns the data in parallel. For example, the 4 bit prefetch and 8 bit prefetch specified in the specification of the semiconductor memory device (DRAM) correspond to the definition of how much data to make in parallel. do.

In general, in order to align serially input data in more than four bits in parallel, four phase clocks using four different phases made in a phase locked loop (PLL) are used. The reason for using clocks with four different phases is that four clocks are required to latch and parallelize each data in series. FIG. 1 illustrates a process of latching data coming in series by clocks clk <0>, clk <1>, clk <2>, and clk <3> having four different phases.

2 is a configuration diagram of a conventional data alignment circuit.

The conventional data alignment circuit receives data serially through the buffer 210 and then latches it with clocks clk000, clk090, clk180, and clk270 having four different phases to catch data. The data caught by the latches 221, 222, 223, and 224 outputs the data in parallel by adjusting the timing in the timing controller 230.

For example, as shown in the figure, when data 0,1,2,3 are input in series, the data is stored at each latch 221, 222, 223, and 224. Latch using clocks (clk000, clk090, clk180, clk270) having different phases, adjust the timing of the latched data, and then simultaneously synchronize the data 0,1,2,3 (Data 0,1,2,3). Output in parallel.

At this time, the clocks (clk00, clk090, clk180, clk270) having four different phases are generally supplied from the phase locked loop (PLL).

As described above, the conventional data alignment circuit uses a clock having four different phases to parallelize serially input data 1: 4. In this case, paralleling to 1: 4 means that four data inputted in series are arranged in parallel and outputted in parallel (data inputted from one terminal to four terminals). In this case, a frequency of a clock having a different phase The lower the frequency of the data is used, the lower the frequency of the jitter becomes worse, so there is a problem in that the loss of jitter characteristics when using the conventional method.

In addition, in the process of transferring a clock having four different phases made in the PLL from the PLL to the data alignment circuit as in the prior art, skew between clocks becomes worse due to coupling noise between the lines. There is also a problem.

In particular, in a GDDR memory device using a data alignment circuit, 32 or more pieces of data may be arranged in parallel. In this case, the number of clocks used and the number of lines for transferring clocks increase, so that the above-described jitter, skew, etc. The problem is even worse.

The present invention has been proposed to solve the above problems of the prior art, and is to improve the deterioration of characteristics such as jitter skew, which is caused by the use of various clocks for data alignment in the data alignment circuit.

One embodiment of a data alignment circuit according to the present invention for achieving the above object, the first latch unit for latching and outputting data input in series using a plurality of first clocks having different phases and the same frequency ; And a second latch unit for latching data output from the first latch unit into a plurality of second clocks having a lower frequency than that of the first clock and having more various phases, and outputting the parallel data.

In addition, in the case of serial-to-parallel conversion of data to 1: 4 (output of data input through one serial terminal to four parallel terminals), an embodiment of the data alignment circuit according to the present invention is characterized by A first latch unit configured to latch and output data inputted in series using an inverted clock inverted from an external clock; And a second latch unit for latching and outputting the data output from the first latch unit using four second clocks having a frequency that is 1/2 times the frequency of the clock and having different phases.

In addition, an embodiment of the data alignment method according to the present invention includes a first step of latching data serially input using a plurality of first clocks having different phases and the same frequency; And a second step of latching the data latched in the first step into a plurality of second clocks having a lower frequency than the first clock and having more various phases and outputting the same in parallel.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can more easily practice the present invention.

3 is a configuration diagram of an embodiment of a data alignment circuit according to the present invention.

As shown in the drawing, a data alignment circuit according to the present invention includes a first latch for latching and outputting data input in series using a plurality of first clocks (clk, clkb) having different phases and the same frequency. Part 320; And a plurality of second clocks (clk <0>, <1>, <2>) having a frequency lower than that of the first clock (clk, clkb) and having more various phases, from the data output from the first latch unit 320. And a second latch portion 330 latched and output in parallel. The timing adjusting unit 340 adjusts the timing of the data parallelized by the second latch unit 330 to output aligned data.

The first latch unit 320 is the first latching data serially input through the buffer 310, etc., latches the data using a plurality of first clocks having different phases and having the same frequency. In the conventional data alignment circuit, when parallelizing data at 1: 4, a clock having four different phases is used. However, the first latch unit of the present invention uses only two clocks, not four clocks, even when data is latched 1: 4. That is, when data is to be parallelized to 1: N, the first latch unit 320 uses fewer clocks than N without using N clocks as in the related art. In this case (1: 4), the first clocks clk and clkb used in the first latch unit 320 need only have two phases, so that a clock of a low frequency is not required as in the prior art. Therefore, it is possible to solve the problem that the jitter characteristic of the clock deteriorates by using a low frequency clock.

As shown in the drawing, the first latch unit 320 has the same number as the first clock (clk, clkb), which operates by receiving the first clock (clk, clkb) and data (in the embodiment shown in the drawing). In this case, two latches 321 and 322 may be included.

The second latch unit 330 may output data output from the first latch unit 320 to a frequency lower than the first clocks clk and clkb (that is, to have a long period), and to have a plurality of phases having more various phases. It latches to the second clocks clk <0>, <1>, <2>, and <3> and outputs them in parallel. That is, the second latch unit 330 latches using N clocks when attempting to parallelize data at 1: N as in the related art. Since the second latch unit 330 needs to use the second clocks clk <0>, <1>, <2>, and <3> having more various phases than the first latch unit 320, The frequency of the second clocks (clk <0>, <1>, <2>, <3>) used by the latch unit 330 is lowered, but the result latched by the first latch unit 320 immediately before Since the jitter characteristic of the clock is slightly deteriorated, it is not a problem in the second latch unit 330.

As illustrated in the drawing, the second latch unit 330 may receive data output from the second clocks clk <0>, <1>, <2>, <3> and the first latch unit 320. It may be configured to include the same number of latches (331, 332, 333, 334) of the second clock (clk <0>, <1>, <2>, <3>) to operate.

The data alignment circuit according to the present invention divides the first clock (clk, clkb) input from the PLL to generate a second clock (clk <0>, <1>, <2>, <3>) It may be characterized in that it further comprises (350). In this case, instead of receiving four (or N) clocks from the PLL, only two (or less than N) clocks need to be transmitted. Therefore, it is possible to reduce the number of lines for receiving the clock. This solves the problem of poor clock skew due to coupling noise between lines, and has the advantage of reducing the overall circuit area due to the reduced number of lines.

The timing adjusting unit 340 adjusts the timing of the data already parallelized by the second latch unit 330, and adjusts the delay of the data to simultaneously output the parallelized data. For example, when serial data is parallelized to 1: 4, four data are output at the same time. The timing adjusting unit 340 is the same as the conventional timing adjusting unit 230 of FIG. 2, and is not newly added in the present invention, and thus a detailed description thereof will be omitted.

4a, b, and c are views related to the frequency divider 350 of FIG. 3, and FIG. 4a is a frequency converting part, FIG. 4b is a phase converting part, and FIG. to be.

FIG. 4A is a circuit for generating clk2 and clk2b clocks that are half of the frequencies of the first clocks clk and clkb using the first clocks clk and clkb. This may be composed of a combination of D flip-flops 401 and 402 and inverters 403 and 404, as is well known, and the timing of the input and output clocks clk, clkb, clk2 and clk2b is shown in FIG. 4C. Is shown.

4B is a circuit for generating second clocks clk <0>, <1>, <2>, and <3> having various phases by using clk2 and clk2b of FIG. 4A. The second clocks (clk <0>, <1>, <2>, and <3>) having various phases are AND gates 405 and 406 that logically combine the first clocks (clk and clkb) with clk2 and clk2b, respectively. , 407, and 408, and the timings of the clocks clk, clkb, clk2, clk2b, and clk 0, 1, 2, and 3 input and output to the AND gates 405, 406, 407, and 408, respectively. Is shown in FIG. 4C.

FIG. 5 is a timing diagram illustrating an overall operation of the data alignment circuit of FIG. 3.

As shown in the drawing, when data 0,1,2,3,4,5,6,7 are serially inputted in sequence, 0,2,4,6 is designated by clk, which is the first clock, in the first latch unit. (Latch output) Then use the second clock clk <0>, clk <1>, clk <2>, and clk <3> in the second latch section. Latch the data 0, 1, 2, 3, and adjust it with the timing controller to align the data in parallel and output it. Since the parallelization process of 1: 4 is shown, 0, 1, 2, and 3 are output in parallel first, and then 4, 5, 6, and 7 are output in parallel.

Referring to FIGS. 3 and 5 again, the data sorting method according to the present invention will be described. In the present invention, in the method of sorting data input in series in parallel, a plurality of first clocks having the same frequency as different phases ( a first step of latching data serially input using clk and clkb); And a plurality of second clocks (clk <0>, <1>, <2>, and <3) having a frequency lower than that of the first clocks (clk and clkb) and having more various phases of the data latched in the first step. Align the data, including the second step of latching with>) and outputting in parallel.

Preferably, the method may further include dispensing the first clocks clk and clkb to generate the second clocks clk <0>, <1>, <2>, and <3>.

Further, the method may further include a third step of adjusting and aligning timing of data output in parallel in the second step.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be appreciated by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

The above-described present invention solves the problem that the jitter characteristic of the clock is deteriorated by using a low frequency clock, as the first latch latches data primarily by using a high frequency clock. There is an advantage.

In addition, when a clock is input from an external circuit such as a PLL (Phase Locked Loop) or the like, a smaller number of clocks may be input than in the related art, thereby reducing the number of lines for delivering clocks. Coupling noise between them can solve the problem of clock skew, and the reduced number of lines makes it possible to reduce the area of the entire circuit.

Claims (17)

A first latch unit for latching and outputting data inputted in series using a plurality of first clocks having different frequencies and the same frequency; And A second latch unit for latching data output from the first latch unit into a plurality of second clocks having a lower frequency than that of the first clock and having a different phase; Data alignment circuit comprising a. The method of claim 1, The second clock is, And the number is larger than the first clock. The method of claim 1, The first clock is, And a clock inputted from the outside of the data alignment circuit and a clock inverted of the clock. The method of claim 3, wherein The second clock is, And dividing the first clock. The method of claim 1, The first latch unit, And the same number of latches as the first clock, the first clock and the data being operated. The method of claim 5, The second latch unit, And the same number of latches as the second clock, the second clock and the data output from the first latch unit. The method of claim 4, wherein The data alignment circuit, And a divider for dividing the first clock to generate the second clock. The method of claim 1, The data alignment circuit, And a timing adjusting unit for adjusting and aligning timing of parallel data output from the second latch unit. A first latch unit for latching and outputting data input in series by using an inverted clock inverting an externally input clock and an externally input clock; And A second latch unit for latching and outputting the data output from the first latch unit using four second clocks having a frequency that is 1/2 times the frequency of the clock and having different phases. Data alignment circuit comprising a. The method of claim 9, The data alignment circuit, And a divider for dividing the clock and the inverted clock to generate the second clock. The method of claim 9, The first latch unit includes two latches for latching the data to the clock and the inverted clock, respectively. And the second latch unit comprises four latches for latching data output from the first latch unit into the four second clocks, respectively. The method of claim 9, The data alignment circuit, And a timing adjusting unit for adjusting and aligning timing of parallel data output from the second latch unit. The method of claim 10, The dispensing unit, A plurality of D flip-flops for producing a clock having a frequency of 1/2 using the clock and the inverted clock; And A plurality of AND gates for adjusting a phase of an output clock of the D flip-flop Data sorting circuit comprising a. A first step of latching data serially input using a plurality of first clocks having different frequencies and the same frequency; And A second step of latching the data latched in the first step into a plurality of second clocks having a lower frequency than that of the first clock and having more various phases and outputting them in parallel; Data sorting method comprising a. The method of claim 14, The first clock is, A data alignment circuit comprising a clock input from the outside and a clock inverted from the clock. The method of claim 15, The data sorting method, Dividing the first clock to generate the second clock. The method of claim 14, The data sorting method, And a third step of adjusting and aligning timing of data output in parallel in the second step.

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