JP2007129069A - Semiconductor device and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce interwiring capacitance and improve reliability in a wiring structure in which a silicon nitride liner film is provided on an upper face of a buried wiring. <P>SOLUTION: Trenches 11 are formed in a first interlayer dielectric 10 on a semiconductor substrate, and then, a first wiring 12 is formed in each of the trenches 11. After that, the upper parts of the first wiring 12 are removed so that each upper face of the first wiring 12 is lower than the upper face of the first interlayer dielectric 10. The silicon nitride liner film 13 is formed on the first interlayer dielectric 10 and the first wiring 12. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a technique effective for a semiconductor device having an embedded wiring mainly composed of copper.

  The embedded wiring of the semiconductor device is formed by a so-called damascene method in which a wiring material is embedded in a wiring trench or a connection via formed in an interlayer insulating film. Copper is commonly used as the material for the embedded wiring, but copper is likely to diffuse into the interlayer insulating film such as silicon oxide, and the diffused copper drifts at a high speed when voltage is applied to the interlayer insulating film. As a result, there arises a problem that the time-dependent dielectric breakdown (TDDB) is likely to occur.

  Therefore, when forming an embedded wiring mainly composed of copper, a thin barrier metal is provided on the surface (side surface and bottom surface) to suppress diffusion of copper in the embedded wiring into the interlayer insulating film. This has been done conventionally. Further, a liner film made of a silicon nitride film (SiN) is formed on the interlayer insulating film in which the embedded wiring is formed, thereby covering the upper surface of the interlayer insulating film and the embedded wiring, thereby It is also practiced to prevent copper from diffusing into the upper interlayer insulating film (for example, Patent Document 1).

JP 2003-188254 A

  However, if the upper surface of the interlayer insulating film on which the buried wiring is formed is covered with a liner film, copper diffusion to the upper interlayer insulating film can be prevented, but the copper diffusion is laterally performed along the liner film. spread. In particular, when the wiring interval is shortened for high integration, TDDB is likely to occur due to the influence of copper diffused in the lateral direction.

  In recent years, the inter-wiring capacitance tends to be reduced by using a low dielectric constant insulating film (low-k film) having a dielectric constant lower than that of silicon oxide as an interlayer insulating film. However, since the silicon nitride used for the liner film has a relatively high dielectric constant, the provision of the liner film causes a problem that the inter-wiring capacitance increases. When the inter-wiring capacitance increases, a signal delay is caused thereby, which hinders high-speed operation of the semiconductor device.

  In order to prevent TDDB and reduce the capacitance between wirings, it is conceivable to select a material other than silicon nitride as the liner film, but the silicon nitride film is used as an etching stopper when forming a via hole for connecting wirings. However, it is difficult to make other choices in practice.

  The present invention has been made to solve the above-described problems. In a wiring structure in which a silicon nitride liner film is provided on the upper surface of an embedded wiring, the inter-wiring capacitance can be reduced and the reliability can be improved. An object of the present invention is to provide a semiconductor device and a manufacturing method thereof.

  A semiconductor device according to a first aspect of the present invention includes a trench formed in an interlayer insulating film on a semiconductor substrate, a wiring formed in the trench and having an upper surface lower than the upper surface of the interlayer insulating film, and the interlayer An insulating film and a silicon nitride liner film formed on the wiring are provided.

  A semiconductor device according to a second aspect of the present invention includes a trench formed in an interlayer insulating film on a semiconductor substrate, a wiring formed in the trench, a wiring formed on the wiring, and the wiring together with the wiring. And a silicon nitride liner film formed thereon.

  A method for manufacturing a semiconductor device according to a third aspect of the present invention includes: (a) a step of forming a trench in an interlayer insulating film on a semiconductor substrate; (b) a step of forming a wiring in the trench; ) Removing the upper portion of the wiring so that the upper surface of the wiring is lower than the upper surface of the interlayer insulating film; and (d) forming a silicon nitride liner film on the interlayer insulating film and the wiring. A process.

  According to the first and third aspects of the present invention, since the upper surface of the wiring is formed lower than the upper surface of the interlayer insulating film, the liner film formed thereon is not flat but has a step. . Therefore, the substantial distance (distance along the liner film) between adjacent wirings can be increased. Therefore, generation of TDDB due to copper diffusing from the wiring in the lateral direction along the liner film can be suppressed, and the reliability of the semiconductor device can be improved. In addition, since the capacitance between wirings can be reduced, it is possible to contribute to high-speed operation of the semiconductor device.

  According to the second aspect of the present embodiment, since the liner film is disposed only on the upper surface of the wiring and does not remain on the upper surface of the interlayer insulating film, an interface between the liner film and the interlayer insulating film is formed between the wirings. Thus, copper can be prevented from diffusing laterally from the wiring, and the occurrence of TDDB can be suppressed. Further, it is possible to prevent the capacitance between adjacent wirings from increasing due to the influence of the liner film, and it is possible to contribute to speeding up the operation of the semiconductor device.

<Embodiment 1>
FIG. 1 shows a method for manufacturing a semiconductor device according to the first embodiment of the present invention. The structure of the semiconductor device and the manufacturing method thereof according to the present embodiment will be described below with reference to FIG.

  First, a first interlayer insulating film 10 made of, for example, silicon oxide formed on a semiconductor substrate (not shown) is selectively etched to form a trench 11 (FIG. 1A). After depositing a barrier metal (not shown) as necessary, copper as a wiring material is deposited, and excess copper on the first interlayer insulating film 10 is removed by CMP (Chemical Mechanical Polishing) to thereby form the trench 11. A first wiring 12 is formed inside (FIG. 1B).

  Then, for example, the upper surface portion of the first wiring 12 is selectively removed by wet etching using sulfuric acid / hydrogen peroxide (mixed solution of sulfuric acid and hydrogen peroxide solution), and the thickness of the first wiring 12 in the trench 11 is increased. The depth is made smaller than the depth of the trench 11. That is, the upper surface of the first wiring 12 is made lower than the upper surface of the first interlayer insulating film 10 (FIG. 1C). Thereafter, a liner film 13 is formed on the first interlayer insulating film 10 and the first wiring 12 by depositing a silicon nitride film over the entire surface by sputtering (FIG. 1D). In FIG. 1D, the first interlayer insulating film 10 has a rounded shape, which is due to sputter etching associated with the sputtering method.

  After the liner film 13 is formed, a second insulating film 20 of silicon oxide is formed thereon, and the second insulating film 20 is selectively etched to form a via hole 21 and a wiring trench 22 (FIG. 1 ( e)). At this time, the liner film 13 functions as an etching stopper. After the liner film 13 in the via hole 21 is removed, a barrier metal (not shown) and copper as a wiring material are deposited to fill the via hole 21 and the trench 22. Then, excess copper on the second insulating film 20 is removed by CMP, thereby forming the via 23 and the second wiring 24 (FIG. 1F).

  According to the present embodiment, since the upper surface of the first wiring 12 is formed lower than the upper surface of the first interlayer insulating film 10, the liner film 13 formed thereon is not flat but has a step. Therefore, the substantial distance (distance along the liner film 13) between the adjacent first wirings 12 can be increased. Therefore, generation of TDDB due to copper diffusion in the lateral direction along the liner film 13 can be suppressed, which can contribute to the improvement of the reliability of the semiconductor device. In addition, since the capacitance between wirings can be reduced, it is possible to contribute to high-speed operation of the semiconductor device. Further, it is also effective when the position of the via 23 is shifted as shown in FIG.

<Embodiment 2>
FIG. 3 shows a method for manufacturing a semiconductor device according to the second embodiment of the present invention. In the figure, the same elements as those shown in FIG. The structure of the semiconductor device according to the present embodiment and the method for manufacturing the semiconductor device will be described below with reference to FIG.

  First, as in the first embodiment, the first wiring 12 is formed in the trench 11 formed in the first interlayer insulating film 10, and then the upper surface portion of the first wiring 12 is selectively removed to obtain the first The upper surface of the wiring 12 is made lower than the upper surface of the first interlayer insulating film 10 (FIG. 3A). Then, a liner film 13 is formed on the first interlayer insulating film 10 and the first wiring 12 (FIG. 3B).

  In the present embodiment, after the liner film 13 is formed, the liner film 13 on the first interlayer insulating film 10 is removed by CMP so that the liner film 13 remains only on the upper surface of the first wiring 12 (FIG. 3 (b)). As a result, as shown in FIG. 3B, the liner film 13 is embedded in the trench 11 together with the first wiring 12.

  Thereafter, in the same manner as the process described in the first embodiment with reference to FIGS. 1E and 1F, the second insulating film 20 of silicon oxide is formed on the entire surface, and the via 23 and the second wiring 24 are formed therein. Is embedded (FIG. 3D).

  According to the present embodiment, the liner film 13 is disposed only on the upper surface of the first wiring 12 and does not remain on the upper surface of the first interlayer insulating film 10. An interface with the interlayer insulating film 10 is not formed, copper diffusion in the lateral direction can be suppressed, and generation of TDDB can be suppressed. Further, the capacitance between the adjacent first wirings 12 can be reduced, which can contribute to the speeding up of the operation of the semiconductor device.

<Embodiment 3>
FIG. 4 shows a method for manufacturing a semiconductor device according to the third embodiment of the present invention. In the figure, the same elements as those shown in FIG. Hereinafter, the structure of the semiconductor device according to the present embodiment and the method for manufacturing the same will be described with reference to FIG.

  First, as in the first embodiment, the first wiring 12 is formed in the trench 11 formed in the first interlayer insulating film 10, and then the upper surface portion of the first wiring 12 is selectively removed to obtain the first The upper surface of the wiring 12 is made lower than the upper surface of the first interlayer insulating film 10 (FIG. 4A).

  Here, in the present embodiment, the upper surface of the first interlayer insulating film 10 is etched. Since the first interlayer insulating film 10 is etched from the edge portion at a high rate, the top surface has a rounded shape (FIG. 4B). Alternatively, instead of this etching step, overpolishing may be performed by increasing the copper polishing rate in the CMP for forming the first wiring 12. Also in this case, the same shape as in FIG. 4B is obtained in which the upper surface of the first wiring 12 is lower than the upper surface of the first interlayer insulating film 10 and the upper surface of the first interlayer insulating film 10 is rounded. .

  Thereafter, a liner film 13 is formed on the first interlayer insulating film 10 and the first wiring 12 (FIG. 4C). Then, the liner film 13 on the first interlayer insulating film 10 is removed by CMP. Since the upper surface of the first interlayer insulating film 10 is rounded, the first wiring 12 is polished from a high portion (that is, the central portion) of the first interlayer insulating film 10 and the liner film 13 is divided at that portion ( FIG. 4 (d)).

  Thereafter, in the same manner as the process described in the first embodiment with reference to FIGS. 1E and 1F, the second insulating film 20 of silicon oxide is formed on the entire surface, and the via 23 and the second wiring 24 are formed therein. Is embedded (FIG. 4E).

  As in the second embodiment, when the upper surface of the first interlayer insulating film 10 is flat, the liner film 13 is not divided on the first interlayer insulating film 10 if the thickness of the liner film 13 varies. A thin remaining portion is formed, and the effect of the present invention cannot be sufficiently obtained. In the present embodiment, the liner film 13 can be surely divided on the first interlayer insulating film 10 as compared with the second embodiment, and the reliability of the semiconductor device can be further improved.

  In the present embodiment, the larger the distance between the separated liner films 13, that is, the exposed width W1 of the upper surface of the first interlayer insulating film 10 in the step of FIG. At the same time, the capacitance between the first wirings 12 can be reduced. The width W1 is desirably equal to or greater than ½ of the interval W2 between the first wirings 12.

<Embodiment 4>
FIG. 5 shows a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention. In the figure, the same elements as those shown in FIG. Hereinafter, the structure of the semiconductor device according to the present embodiment and the method for manufacturing the same will be described with reference to FIG.

  First, as in the first embodiment, the first wiring 12 is formed in the trench 11 formed in the first interlayer insulating film 10, and then the upper surface portion of the first wiring 12 is selectively removed to obtain the first The upper surface of the wiring 12 is made lower than the upper surface of the first interlayer insulating film 10 (FIG. 5A).

  Here, in the present embodiment, a silicon oxide film 15 is formed on the first interlayer insulating film 10 and the first wiring 12, and then a resist is formed at a predetermined position on the first interlayer insulating film 10 between the first wirings 12. A pattern 16 is formed (FIG. 5B). Then, by selectively removing the silicon oxide film 15 by etching using the resist pattern 16 as a mask, a pattern 15 a (hereinafter referred to as “oxide film”) of the silicon oxide film 15 is formed on the first interlayer insulating film 10 between the first wirings 12. Pattern 15a ") (FIG. 5C).

  Thereafter, a liner film 13 is formed on the first interlayer insulating film 10 and the first wiring 12 (FIG. 5D). Then, the liner film 13 is removed by CMP so that the upper surface of the oxide film pattern 15a is exposed. As a result, the liner film 13 is divided at the formation region of the oxide film pattern 15a (FIG. 5E). In other words, the region where the silicon oxide film 15 is disposed becomes a region where the liner film 13 is divided.

  Thereafter, in the same manner as the process described in the first embodiment with reference to FIGS. 1E and 1F, the second insulating film 20 of silicon oxide is formed on the entire surface, and the via 23 and the second wiring 24 are formed therein. Is embedded (FIG. 5F).

  According to the present embodiment, if the oxide film pattern 15a is formed in advance at a position where the liner film 13 is desired to be divided, the liner film 13 can be reliably divided at that portion, and further reliability of the semiconductor device can be obtained. It is possible to improve the performance. Further, as compared with the second and third embodiments, the margin of the CMP amount of the liner film 13 is increased by the thickness of the oxide film pattern 15a.

  Also in this embodiment, the wider the distance between the divided first wirings 12, that is, the width W3 of the oxide film pattern 15a (see FIG. 5E), the more the copper can be diffused in the lateral direction. The width W3 is desirably equal to or greater than ½ of the interval W4 between the first wirings 12.

  In the present embodiment, the material of the pattern 15a is a silicon oxide film, but is not limited thereto. For example, if the pattern 15a is formed using an insulating material having a dielectric constant lower than that of the liner film 13 (silicon nitride) such as a low-k film, the capacitance between the first wirings 12 can be reduced. The pattern 15a may be formed using a polysilicon film. Since polysilicon is a conductor, the effect of reducing the wiring inertia cannot be obtained, but it is possible to prevent lateral diffusion of copper. There is also an advantage that formation is relatively easy.

8 is a diagram showing a method for manufacturing the semiconductor device according to the first embodiment. FIG. FIG. 6 is a diagram for explaining an effect of the first embodiment. FIG. 10 is a diagram illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a diagram illustrating the method of manufacturing the semiconductor device according to the third embodiment. FIG. 10 is a diagram illustrating a method for manufacturing the semiconductor device according to the fourth embodiment.

Explanation of symbols

10 first interlayer insulating film, 11 trench, 12 first wiring, 13 liner film, 15 silicon oxide film, 15a oxide film pattern, 16 resist pattern, 20 second insulating film, 21 via hole, 22 trench, 23 via, 24 first 2 wiring.

Claims (13)

A trench formed in an interlayer insulating film on a semiconductor substrate;
A wiring formed in the trench and having an upper surface lower than the upper surface of the interlayer insulating film;
A semiconductor device comprising: the interlayer insulating film; and a silicon nitride liner film formed on the wiring. The semiconductor device according to claim 1,
A plurality of the wirings;
The semiconductor device, wherein the liner film is divided on the interlayer insulating film between the wirings. The semiconductor device according to claim 2,
A semiconductor device, wherein an upper surface of the interlayer insulating film between the wirings is rounded. The semiconductor device according to claim 2,
A semiconductor device, further comprising a predetermined film selectively formed in a region where the interlayer insulating film is divided. The semiconductor device according to claim 4,
The semiconductor device according to claim 1, wherein the predetermined film is an insulating film having a dielectric constant lower than that of the liner film. The semiconductor device according to claim 4,
The semiconductor device according to claim 1, wherein the predetermined film is a polysilicon film. A trench formed in an interlayer insulating film on a semiconductor substrate;
Wiring formed in the trench;
A semiconductor device comprising: a silicon nitride liner film formed on the wiring and formed in the trench together with the wiring. (A) forming a trench in an interlayer insulating film on a semiconductor substrate;
(B) forming a wiring in the trench;
(C) removing the upper portion of the wiring so that the upper surface of the wiring is lower than the upper surface of the interlayer insulating film;
(D) forming a silicon nitride liner film on the interlayer insulating film and the wiring, and a method for manufacturing a semiconductor device. A method for manufacturing a semiconductor device according to claim 8, comprising:
(E) A method of manufacturing a semiconductor device, further comprising the step of removing the liner film on the interlayer insulating film. A method for manufacturing a semiconductor device according to claim 9, comprising:
(F) A method of manufacturing a semiconductor device, further comprising a step of rounding the upper surface of the interlayer insulating film by etching or polishing, which is performed before the step (d). . A method for manufacturing a semiconductor device according to claim 8, comprising:
(G) a step that is performed before the step (d) and selectively forms a predetermined film at a predetermined position on the interlayer insulating film;
(H) A method of manufacturing a semiconductor device, further comprising a step of removing the liner film on the predetermined film, which is performed after the step (d). A method for manufacturing a semiconductor device according to claim 11, comprising:
The method of manufacturing a semiconductor device, wherein the predetermined film is an insulating film having a dielectric constant lower than that of the liner film. A method for manufacturing a semiconductor device according to claim 11, comprising:
The method for manufacturing a semiconductor device, wherein the predetermined film is the polysilicon film.

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