JP2007123661A - Thin-film transistor and method of manufacturing same - Google Patents

Thin-film transistor and method of manufacturing same Download PDF

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JP2007123661A
JP2007123661A JP2005315785A JP2005315785A JP2007123661A JP 2007123661 A JP2007123661 A JP 2007123661A JP 2005315785 A JP2005315785 A JP 2005315785A JP 2005315785 A JP2005315785 A JP 2005315785A JP 2007123661 A JP2007123661 A JP 2007123661A
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film transistor
thin film
ingasno
thin
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JP5098151B2 (en
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Masato Kon
真人 今
Hiroshi Kukimoto
宏 柊元
Mamoru Ishizaki
守 石崎
Manabu Ito
学 伊藤
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Toppan Inc
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin-film transistor having an active layer capable of being deposited at a room temperature by suppressing variations in performance of individual products. <P>SOLUTION: By using InGaSnO<SB>x</SB>(4≤x≤5) as a material of the thin-film transistor, an amorphous InGaSnO<SB>x</SB>(4≤x≤5) semiconductor can be formed on a flexible board at a room temperature with a wide process window, and the thin-film transistor having high bending strength can be manufactured while suppressing the variations between products at the minimum. Further, a sputtering method, especially, an InGaSnO<SB>5</SB>target is used as the manufacturing method to make an oxygen flow rate 2-4%, and thus, mobility of about 1 cm<SP>2</SP>/Vs can be stably obtained. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、電子回路を構成する素子として用いることができる、InGaSnO(4≦x≦5)を主たる構成成分とする非単結晶材料を活性層として用いる薄膜トランジスタに関する。 The present invention relates to a thin film transistor using, as an active layer, a non-single-crystal material mainly composed of InGaSnO x (4 ≦ x ≦ 5), which can be used as an element constituting an electronic circuit.

電界効果型トランジスタは、半導体メモリ集積回路の単位電子素子、高周波信号増幅素子、液晶駆動用素子等各種のスイッチング素子として用いられ、特に薄膜化したものは薄膜トランジスタ(Thin Film Transistor:TFT)としてよく知られている。   Field effect transistors are used as various switching elements such as unit electronic elements of semiconductor memory integrated circuits, high frequency signal amplifying elements, liquid crystal driving elements, and the thinned transistors are well known as thin film transistors (TFTs). It has been.

これらトランジスタの活性層には、シリコンまたはシリコン化合物が広く用いられている。高速動作が必要な高周波増幅素子、集積回路用素子等には、シリコン単結晶が用いられ、また、低速動作で充分な表示素子用には、大面積化の要求からアモルファスシリコンが使われている。   Silicon or silicon compounds are widely used for the active layers of these transistors. Single-crystal silicon is used for high-frequency amplifying elements and integrated circuit elements that require high-speed operation, and amorphous silicon is used for display elements that are sufficient for low-speed operation due to the demand for large area. .

紙の代替として期待されるフレキシブルディスプレイには、フレキシブル基板を用いることが要求される。このような基板は一般に耐熱温度が低いため、プロセス温度のさらなる低下が要求される。アモルファスシリコン薄膜の作製にはCVDが広く用いられており、特にプラズマCVDではプラズマが原料ガスであるシランを分解するため、熱CVDと比較して低い温度で成膜できるが、それでも200〜300℃の反応温度が必要である。   A flexible display expected as a substitute for paper is required to use a flexible substrate. Since such a substrate generally has a low heat-resistant temperature, further reduction in the process temperature is required. CVD is widely used for producing an amorphous silicon thin film. In particular, plasma CVD decomposes silane, which is a raw material gas, so that it can be formed at a lower temperature than thermal CVD, but still 200 to 300 ° C. The reaction temperature is required.

近年、室温成膜が可能で電界効果移動度がアモルファスシリコンと同等以上の酸化物半導体InGaZnOが発表され、薄膜トランジスタの活性層としての可能性が示された。(例えば、非特許文献1を参照。) In recent years, an oxide semiconductor InGaZnO 4 which can be formed at room temperature and has a field effect mobility equal to or higher than that of amorphous silicon has been announced, and has shown the possibility as an active layer of a thin film transistor. (For example, refer nonpatent literature 1.)

InGaZnOは透明導電膜として知られていた材料であるが、成膜時に酸素分圧を制御することでキャリア源となっている酸素空孔を低減し、off電流を低減させることに成功している。また容易にアモルファス状態が得られるため、フレキシブルディスプレイへの応用に適している。 InGaZnO 4 is a material known as a transparent conductive film, but it has succeeded in reducing oxygen vacancies as a carrier source and controlling off current by controlling the oxygen partial pressure during film formation. Yes. Moreover, since an amorphous state can be easily obtained, it is suitable for application to a flexible display.

K.Nomura,H.Ohta,A.Takagi,T.Kamiyama,M.Hirano,H.Hosono,「Nature」,2004年11月25日,432,p.488−492K. Nomura, H. Ohta, A. Takagi, T. Kamiyama, M. Hirono, H. Hosono, “Nature”, November 25, 2004, 432, p. 488-492

ディスプレイへの応用には、大面積に均一成膜が可能なスパッタ法が適しているが、薄膜トランジスタの活性層にこのInGaZnOを用いると、表示素子として必要な電界効果移動度1cm/V・s付近の電界効果移動度が得られる酸素流量の範囲は非常に狭く(図1参照)、製品にばらつきが生じてしまうという問題があった。 For application to a display, a sputtering method capable of uniformly forming a film over a large area is suitable. However, when this InGaZnO 4 is used for an active layer of a thin film transistor, a field effect mobility required for a display element is 1 cm 2 / V ·. The range of the oxygen flow rate at which field effect mobility near s can be obtained is very narrow (see FIG. 1), and there is a problem that variations occur in products.

本発明は、係る従来技術の状況に鑑みてなされたもので、成膜時のプロセスウィンドウが充分に広い材料を用いることで、個々の製品の性能のばらつきを低く抑えることが可能となる、室温成膜可能な薄膜トランジスタを提供することを目的とする。   The present invention has been made in view of the state of the related art, and by using a material having a sufficiently wide process window at the time of film formation, it is possible to suppress variation in performance of individual products at a low temperature. An object of the present invention is to provide a thin film transistor that can be formed.

上記の課題を達成するために、まず第1の発明は、InGaSnO(4≦x≦5)薄膜を活性層に用いたことを特徴とする薄膜トランジスタである。本材料を用いると、成膜時の酸素流量比の範囲に充分な幅を持たせることができる(図1参照)。 In order to achieve the above object, a first invention is a thin film transistor characterized by using an InGaSnO x (4 ≦ x ≦ 5) thin film as an active layer. When this material is used, a sufficient range can be provided in the range of the oxygen flow rate ratio during film formation (see FIG. 1).

また、第2の発明は、前記InGaSnO(4≦x≦5)が非単結晶薄膜であることを特徴とする請求項1記載の薄膜トランジスタである。非単結晶材料にすることで曲げに対する耐性が高まり、フレキシブルディスプレイへの応用が可能となる。 The second invention is the thin film transistor according to claim 1, wherein the InGaSnO x (4 ≦ x ≦ 5) is a non-single-crystal thin film. By using a non-single crystal material, resistance to bending is increased, and application to a flexible display becomes possible.

また、第3の発明は、前記薄膜トランジスタの基板がフレキシブル基板であることを特徴とする請求項1または2に記載の薄膜トランジスタである。適当なゲート絶縁膜や電極材料を選定しこれらも含めフレキシブル基板上に形成することで、トランジスタを含めた基板全体を曲げることが可能になる。   The third invention is the thin film transistor according to claim 1 or 2, wherein the substrate of the thin film transistor is a flexible substrate. By selecting appropriate gate insulating films and electrode materials and forming them on a flexible substrate, the entire substrate including the transistor can be bent.

また、第4の発明は、InGaSnO(4≦x≦5)薄膜をスパッタ法を用いて形成することを特徴とする請求項1乃至3の何れかに記載の薄膜トランジスタの製造方法である。スパッタ法を用いることで大面積に均一成膜することが可能になる。 The fourth invention is a method of manufacturing a thin film transistor according to any one of claims 1 to 3, wherein an InGaSnO x (4 ≦ x ≦ 5) thin film is formed by a sputtering method. By using the sputtering method, a uniform film can be formed over a large area.

また、第5の発明は、InGaSnO(4≦x≦5)薄膜の形成において、InGaSnOターゲットを用いることを特徴とする請求項4に記載の薄膜トランジスタの製造方法である。InGaSnOターゲットを用いることでInGaSnO(4≦x≦5)薄膜の形成が容易になる。 The fifth invention is the method of manufacturing a thin film transistor according to claim 4, wherein an InGaSnO x (4 ≦ x ≦ 5) thin film is formed using an InGaSnO 5 target. By using an InGaSnO 5 target, formation of an InGaSnO x (4 ≦ x ≦ 5) thin film is facilitated.

また、第6の発明は、前記スパッタ法における酸素流量比を2〜4%とするものである。酸素流量比、すなわち酸素流量/(Ar流量+酸素流量)を2〜4%とすることでおよそ1cm/V・s程度の移動度が安定して得られる。 In the sixth invention, the oxygen flow rate ratio in the sputtering method is 2 to 4%. By setting the oxygen flow rate ratio, that is, the oxygen flow rate / (Ar flow rate + oxygen flow rate) to 2 to 4%, a mobility of about 1 cm 2 / V · s can be stably obtained.

以上の構成から、本発明には、以下の効果がある。
薄膜トランジスタの活性層の材料としてInGaSnO(4≦x≦5)を用いることで、フレキシブル基板上に室温で非単結晶材料InGaSnO(4≦x≦5)半導体を、広いプロセスウィンドウで成膜することが可能になり、曲がる薄膜トランジスタを製品間のばらつきを最小限に抑えて作製することが可能になる。
From the above configuration, the present invention has the following effects.
By using InGaSnO x (4 ≦ x ≦ 5) as the material of the active layer of the thin film transistor, a non-single-crystal material InGaSnO x (4 ≦ x ≦ 5) semiconductor is formed over a flexible substrate at room temperature with a wide process window. Thus, a bent thin film transistor can be manufactured with minimum variation between products.

本発明の実施の形態について、図1及び図2を用いて以下詳細に説明する。   Embodiments of the present invention will be described in detail below with reference to FIGS.

本発明の薄膜トランジスタの一例を、図1に示す。本実施の形態ではボトムゲート型であるが、トップゲート型でもよい。図2の例では、活性層4にInGaSnO(4≦x≦5)を用いている。 An example of the thin film transistor of the present invention is shown in FIG. Although the bottom gate type is used in this embodiment mode, a top gate type may be used. In the example of FIG. 2, InGaSnO x (4 ≦ x ≦ 5) is used for the active layer 4.

次に製造方法について図2を用いて説明する。まず、基板1を用意する(図3(a))。基板1の材料としては、軽量、フレキシブルなプラスチック基板を用いることができるが、ガラス基板やシリコン基板なども使用できる。フレキシブルなプラスチック基板としては、例えば、ポリエチレンテレフタレート(PET)、ポリエチレンナフタレート(PEN)、ポリエーテルスルフォン(PES)、ポリイミド(PI)、ポリエーテルイミド(PEI)、ポリスチレン(PS)、ポリ塩化ビニル(PVC)、ポリエチレン(PE)、ポリプロピレン(PP)、ナイロン等が使用可能である。ただし、密着性向上のためにUVやプラズマ等による表面処理を行うとよい。   Next, a manufacturing method is demonstrated using FIG. First, the substrate 1 is prepared (FIG. 3A). As a material for the substrate 1, a lightweight and flexible plastic substrate can be used, but a glass substrate, a silicon substrate, or the like can also be used. Examples of flexible plastic substrates include polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), polyimide (PI), polyetherimide (PEI), polystyrene (PS), polyvinyl chloride ( PVC), polyethylene (PE), polypropylene (PP), nylon and the like can be used. However, surface treatment with UV, plasma, or the like may be performed to improve adhesion.

次に基板1上にゲート電極2を形成する(図3(b))。ゲート電極の材料や作製法、パターニング方法は問わない。金属、合金や透明導電膜のマスク蒸着(スパッタを含む)やスクリーン印刷等が一例として挙げられる。スクリーン印刷の場合、Pt、Au、Ag、Cu、Ni等の金属のペーストや、ポリエチレンジオキシチオフェン(PEDOT)、ポリアニリン(PANI)等の有機導電体ペーストを使用できる。   Next, the gate electrode 2 is formed on the substrate 1 (FIG. 3B). The material, manufacturing method, and patterning method of the gate electrode are not limited. Examples include mask vapor deposition (including sputtering), screen printing, and the like of metals, alloys, and transparent conductive films. In the case of screen printing, a metal paste such as Pt, Au, Ag, Cu, or Ni, or an organic conductor paste such as polyethylenedioxythiophene (PEDOT) or polyaniline (PANI) can be used.

次にゲート絶縁膜3を作製する(図3(c))。ゲート絶縁膜3の材料や作製法、パターニング法は問わない。例えば、SiO、SiN、Al等が使用できるが、HfOやYなどの高誘電率(high−k)材料を用いるのが好ましい。 Next, the gate insulating film 3 is produced (FIG. 3C). The material, manufacturing method, and patterning method of the gate insulating film 3 are not limited. For example, SiO 2 , SiN, Al 2 O 3 or the like can be used, but it is preferable to use a high dielectric constant (high-k) material such as HfO 2 or Y 2 O 3 .

次に活性層4を形成する(図3(d))。材料にはInGaSnO(4≦x≦5)を用いる。形成方法は大面積均一成膜ができるスパッタ法が好ましく、InGaSnOターゲットを用いると容易に形成できる。パルスレーザーデポジション(PLD)など他の方法でも可能である。 Next, the active layer 4 is formed (FIG. 3D). InGaSnO x (4 ≦ x ≦ 5) is used as the material. The formation method is preferably a sputtering method capable of uniform film formation over a large area, and can be easily formed using an InGaSnO 5 target. Other methods such as pulsed laser deposition (PLD) are also possible.

次にソース・ドレイン電極5を形成し、薄膜トランジスタが完成する(図3(e))。ソース・ドレイン電極の材料や作製法、パターニング方法は問わない。金属、合金や透明導電膜のマスク蒸着(スパッタを含む)やスクリーン印刷等が一例として挙げられる。スクリーン印刷の場合、Pt、Au、Ag、Cu、Ni等の金属のペーストや、PEDOT、PANI等の有機導電体ペーストを使用できる。   Next, the source / drain electrodes 5 are formed to complete the thin film transistor (FIG. 3E). There are no limitations on the material, fabrication method, and patterning method of the source / drain electrodes. Examples include mask vapor deposition (including sputtering), screen printing, and the like of metals, alloys, and transparent conductive films. In the case of screen printing, a metal paste such as Pt, Au, Ag, Cu, or Ni, or an organic conductor paste such as PEDOT or PANI can be used.

InGaSnO(4≦x≦5)を活性層として用いると、酸素流量比が2%〜4%の広範囲でおよそ1cm/V・s程度の移動度が安定して得られる。 When InGaSnO x (4 ≦ x ≦ 5) is used as the active layer, a mobility of about 1 cm 2 / V · s can be stably obtained in a wide range where the oxygen flow rate ratio is 2% to 4%.

基板1としてPENを用い(図3(a))、これに錫ドープインジウム酸化物(ITO)をDCマグネトロンスパッタ法により50nmの膜厚で成膜し、パターニングしてゲート電極2を形成した(図3(b))。パターニングには一般的なリソグラフィーを用い、ウェットエッチングによってITO層を加工した。次にプラズマCVDを用いて50℃以下の基板温度でSiOを300nm形成し、ゲート絶縁膜3とした(図3(c))。InGaSnOターゲットを用いてRFマグネトロンスパッタ法により酸素流量比(酸素流量/(Ar流量+酸素流量))2%でInGaSnO(4≦x≦5)薄膜を50nm成膜し、一般的なリソグラフィーを用いてパターニングし、活性層4を形成した(図3(d))。最後にITOをDCマグネトロンスパッタ法により50nmの膜厚で成膜し、パターニングしてソース・ドレイン電極5を形成し(図3(e))、非単結晶薄膜トランジスタが完成した(図2)。チャネル長は50μm、チャネル幅は800μmである。 PEN was used as the substrate 1 (FIG. 3 (a)), and tin-doped indium oxide (ITO) was formed to a thickness of 50 nm by DC magnetron sputtering, and patterned to form the gate electrode 2 (FIG. 3). 3 (b)). For patterning, general lithography was used, and the ITO layer was processed by wet etching. Next, 300 nm of SiO 2 was formed by plasma CVD at a substrate temperature of 50 ° C. or less to form a gate insulating film 3 (FIG. 3C). Using an InGaSnO 5 target, an InGaSnO x (4 ≦ x ≦ 5) thin film having a thickness of 50 nm is formed by an RF magnetron sputtering method at an oxygen flow rate ratio (oxygen flow rate / (Ar flow rate + oxygen flow rate)) of 2%. The active layer 4 was formed by patterning (FIG. 3D). Finally, ITO was deposited to a thickness of 50 nm by DC magnetron sputtering and patterned to form source / drain electrodes 5 (FIG. 3E), thereby completing a non-single-crystal thin film transistor (FIG. 2). The channel length is 50 μm and the channel width is 800 μm.

この素子の電界効果移動度を測定した結果、1cm/V・sが得られた。 As a result of measuring the field effect mobility of this element, 1 cm 2 / V · s was obtained.

同様に酸素流量比4%及び6%で素子を作製し、それぞれ1.4及び0.01cm/V・sが得られた。 Similarly, devices were produced at an oxygen flow rate ratio of 4% and 6%, and 1.4 and 0.01 cm 2 / V · s were obtained, respectively.

このような薄膜トランジスタの活用例としては、フレキシブルディスプレイなどが挙げられる。   An example of the use of such a thin film transistor is a flexible display.

本発明の薄膜トランジスタの構成例を示す側面断面図である。It is side surface sectional drawing which shows the structural example of the thin-film transistor of this invention. 本発明の薄膜トランジスタの製造工程の一例を示す側面断面図である。It is side surface sectional drawing which shows an example of the manufacturing process of the thin-film transistor of this invention. InGaZnOと本発明のInGaSnO(4≦x≦5)の成膜時の酸素流量比と作製したデバイスの電界効果移動度の関係を示す図である。InGaZnO is a diagram showing a field-effect mobility of the relationship between the device fabricated with the oxygen flow ratio during the deposition of InGaSnO x (4 ≦ x ≦ 5 ) 4 and the present invention.

符号の説明Explanation of symbols

1・・・基板
2・・・ゲート電極
3・・・ゲート絶縁膜
4・・・活性層
5・・・ソース・ドレイン電極
DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Gate electrode 3 ... Gate insulating film 4 ... Active layer 5 ... Source / drain electrode

Claims (6)

InGaSnO(4≦x≦5)薄膜を活性層に用いたことを特徴とする薄膜トランジスタ。 A thin film transistor using an InGaSnO x (4 ≦ x ≦ 5) thin film as an active layer. 前記InGaSnO(4≦x≦5)が非単結晶薄膜であることを特徴とする請求項1記載の薄膜トランジスタ。 The thin film transistor according to claim 1, wherein the InGaSnO x (4 ≦ x ≦ 5) is a non-single-crystal thin film. 前記薄膜トランジスタの基板がフレキシブル基板であることを特徴とする請求項1または2に記載の薄膜トランジスタ。   The thin film transistor according to claim 1 or 2, wherein the substrate of the thin film transistor is a flexible substrate. 請求項1〜3の何れかに記載の薄膜トランジスタの製造方法であって、InGaSnO(4≦x≦5)薄膜をスパッタ法で形成することを特徴とする薄膜トランジスタの製造方法。 4. The method of manufacturing a thin film transistor according to claim 1, wherein an InGaSnO x (4 ≦ x ≦ 5) thin film is formed by a sputtering method. 前記スパッタ法に用いるターゲットとして、InGaSnOターゲットを用いることを特徴とする請求項4に記載の薄膜トランジスタの製造方法。 The method for manufacturing a thin film transistor according to claim 4, wherein an InGaSnO 5 target is used as a target used in the sputtering method. 前記スパッタ法における酸素流量比が2〜4%であることを特徴とする請求項4または5に記載の薄膜トランジスタの製造方法。   6. The method of manufacturing a thin film transistor according to claim 4, wherein an oxygen flow rate ratio in the sputtering method is 2 to 4%.
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US8999208B2 (en) 2010-02-24 2015-04-07 Idemitsu Kosan Co., Ltd. In-Ga-Sn oxide sinter, target, oxide semiconductor film, and semiconductor element
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JP2016026268A (en) * 2015-10-14 2016-02-12 出光興産株式会社 In-Ga-Sn-BASED OXIDE SINTERED BODY, TARGET, OXIDE SEMICONDUCTOR FILM AND SEMICONDUCTOR ELEMENT
JP2017165646A (en) * 2017-03-10 2017-09-21 出光興産株式会社 In-Ga-Sn OXIDE SINTERED BODY, TARGET, OXIDE SEMICONDUCTOR FILM, AND SEMICONDUCTOR ELEMENT

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