JP2007114154A - Probe for scanning probe microscope and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a probe for SPM which can be mass-produced, and a method of manufacturing the same. <P>SOLUTION: The method includes steps of: preparing a semiconductor substrate 1; forming a wiring 15 for forming the probe on surface of the semiconductor substrate 1 via a first interlayer dielectric 12 and a second interlayer dielectric 14; forming passivation film 16 covering the wiring 15; forming a through hole 16a; and forming the probe 5 having a shape of projecting from the passivation film 16 inside the through hole 16a by heating the semiconductor substrate 4 and growing part of the wiring 15 in a columnar shape inside the through hole 16a, sequentially performed in this order. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a probe for a scanning probe microscope and a manufacturing method thereof.

  A scanning probe microscope (abbreviation: SPM) scans a physical quantity between target objects with a probe (probe) and analyzes the shape and properties of the surface of the target object at the atomic level as three-dimensional information. It is a microscope. In addition, SPM types include a scanning tunneling microscope (abbreviation: STM) that detects and uses tunneling current, and an atomic force microscope (abbreviation: AFM) that detects and uses atomic force. Etc.

By the way, the probe used for this SPM is manufactured by, for example, an electrolytic polishing method. This electrolytic polishing method is a method in which the tip of a base material of a probe is immersed in an electrolytic solution, and the probe is etched by an electrochemical reaction to control the shape and sharpen the leading edge (for example, non-patent) Reference 1).
"Electrolytic polishing of STM probe", [online], JPO website homepage (other reference information), Internet <URL: http://www.jpo.go.jp/shiryou/s_sonota/hyoujun_gijutsu/spm/3_a_1_a .htm>

  However, the above-described electropolishing method is not suitable for mass production of the probe because the probe is manufactured one by one.

  An object of this invention is to provide the probe for SPM which can be mass-produced, and its manufacturing method in view of the said point.

  In order to achieve the above object, according to the method for manufacturing an SPM probe of the present invention, a through hole (16a) having a depth reaching the first film from the surface of the second film is formed in the second film (16). And heating the substrate (1) to grow a part of the first film (15) into a columnar shape protruding from the surface of the second film (16) inside the through hole (16a). And a step of forming the probe (5).

  When the substrate is heated after the formation of the through hole, a part of the first film is formed in the through hole due to the thermal stress applied to the first film due to the difference in linear expansion coefficient between the first film and the second film. Discovered the phenomenon of growing in a columnar shape. The manufacturing method of the present invention is a method for manufacturing a probe utilizing this phenomenon.

  In addition, since the manufacturing method of the present invention is a method using a wiring process when manufacturing an IC, a plurality of first films are formed on a single substrate in the same manner as in the manufacture of an IC. By forming the probe from the film, a plurality of probes can be formed simultaneously on one substrate. Therefore, according to the present invention, mass production of the probe is possible.

  In the manufacturing method of the present invention, for example, in the step of forming the first film (15), a plurality of first films (15) are formed in an array on the surface of the same substrate (1), and the probe ( 5) forming a plurality of probes (5) in an array on the same substrate (1) by forming the probes (5) from each of the plurality of first films (15). Can do.

  Thus, in the case where a plurality of probes are formed in an array, a plurality of probes can be formed with the same positional accuracy as the manufacture of the IC. For this reason, according to the manufacturing method of this invention, manufacture of a multiprobe is easy.

  Further, for example, after the step of preparing the substrate (1), a step of forming a driving body (22) for driving the probe (5) on the surface of the substrate (1), and the driving body (22) and the electricity And forming a probe and a driving body on the same substrate.

  At this time, the step of forming the first film (15) and the step of forming the electrode wiring (23) can be performed simultaneously.

  Further, for example, in the step of preparing the substrate, the semiconductor substrate (1) in which the semiconductor elements constituting the circuit are formed in a region different from the region where the probe (5) is to be formed can be prepared. A probe can be formed on a semiconductor substrate on which elements are formed. According to the manufacturing method of the present invention, the probe and the circuit can be integrated in this way.

  At this time, in the step of forming the first film (15), the wiring (35) electrically connected to the semiconductor element is formed on the surface of the semiconductor substrate (1), and at the same time, the same material as the wiring (35). The 1st film | membrane (15) comprised by this can be formed.

  Note that the wiring and the first film can be formed separately, but by forming the wiring and the first film in this way, the manufacturing process can be simplified as compared with the case where they are formed separately. .

  Further, when the circuit unit and the probe are separated, a wiring process for electrically connecting the circuit unit and the probe is required. For example, the metal wiring of the circuit unit and the first film In the case of a continuous shape, the connecting step can be omitted.

  For example, in the step of forming the first film, the first film (15) having a width of 1 μm or less and a length of 40 μm or more is formed, and in the step of forming the through hole (16a), one first film is formed. One through hole (16a) is preferably formed in the film (15).

  Further, for example, in the step of forming the first film, it is preferable to form the first film (15) made of a metal material containing Al as a main component.

  Further, for example, a layer (19) having an opening smaller in width than the through hole (16a) is formed between the step of forming the through hole (16a) and the step of forming the probe (5). A step of forming on the bottom surface of (16a) is performed. In the step of forming the probe (5), the probe (5) can be formed from the opening.

  Thus, by forming the probe from the hole, the width of the probe can be made smaller than the width of the through hole. That is, the width of the probe can be controlled to a desired size by arbitrarily changing the size of the hole regardless of the width of the through hole.

  Further, for example, after the step of forming the probe (5), a step of processing the tip (5a) of the probe (5) can be performed. For example, the tip of the probe can be processed by isotropic etching. Thereby, a probe can be processed into a desired shape.

  For example, after the step of forming the probe (5), a step of covering the probe (5) with a film (42) made of a material different from that of the probe (5) can be performed. In this case, a probe made of any material can be produced by arbitrarily selecting the material of the film covering the probe.

  The SPM probe of the present invention is disposed on the surface of the substrate (1), covers the first film (15) made of a conductive material, and the first film (15). A second film (16) having a smaller linear expansion coefficient than the film (15) and made of an insulating material, and a through-hole having a depth reaching the first film (15) from the surface of the second film (16) (16a) is formed of a material constituting the first film (15), has a length protruding from the first film (15) onto the surface of the second film (16), and the first film ( 15) and a probe (5) having a continuous shape.

  Further, in this SPM probe, for example, a plurality of first films (15) are arranged in an array on the surface of the same substrate (1), and the probes are formed from each of the plurality of first films (15). It can be set as the structure in which (5) was formed.

  In addition, for example, a driving body (22) for driving the probe (5) is formed in a region different from the region where the probe is formed on the surface of the substrate (1). You can also.

  Further, for example, a semiconductor element constituting a circuit and the probe (5) can be formed on the same semiconductor substrate.

  In addition, the code | symbol in the parenthesis of each means described in a claim and this column is an example which shows a corresponding relationship with the specific means as described in embodiment mentioned later.

(First embodiment)
FIG. 1 shows a cross-sectional view of a semiconductor chip having an SPM probe in the first embodiment of the present invention, and FIG. 2 shows a planar layout of wiring, electrodes, etc. in the cantilever part 2 in FIG. 1 corresponds to a cross-sectional view taken along line AA in FIG. 1 and 2, the same reference numerals are given to the same components.

  The SPM probe of this embodiment is formed on the same semiconductor chip together with the cantilever part and the circuit part.

  Specifically, as shown in FIG. 1, a cantilever portion 2 and a circuit portion 3 are formed on a semiconductor substrate 1. As shown in FIGS. 1 and 2, the cantilever portion 2 has one end 2a fixed to the semiconductor substrate 1 and the other end 2b by a cavity portion 4 formed below and around the cantilever portion 2 in the semiconductor substrate 1. Is not fixed to the semiconductor substrate 1, that is, a structure having a free end on one side.

  Further, the cantilever part 2 is formed adjacent to the probe forming part 6 where the probe 5 is formed in the vicinity of the free end 2b, and a drive mechanism for driving the probe 5 is formed. The probe driving unit 7 is provided.

  As shown in FIG. 1, the probe forming section 6 includes a field insulating film 11 formed on the surface of the semiconductor substrate 1, a first interlayer insulating film 12 formed on the field insulating film 11, A lower layer wiring 13 formed on the interlayer insulating film 12, a second interlayer insulating film 14 formed on the lower layer wiring 13 and on the first interlayer insulating film 12 on which the lower layer wiring 13 is not formed, Formed inside a probe forming wiring 15 formed on the two-layer insulating film 14, a passivation film 16 formed on the probe forming wiring 15, and a through hole 16 a provided in the passivation film 16. It is comprised from the probe 5 made.

  Here, a silicon substrate is used as the semiconductor substrate 1, a silicon oxide film is used as the field insulating film 11 and the first interlayer insulating film 12, a polysilicon film is used as the lower wiring 13, and a BPSG film is used as the second interlayer insulating film 14. Can be used.

  The probe forming wiring 15 is a wiring used for forming the probe 5. As the probe forming wiring 15, a metal material containing Al as a main component, that is, an Al wiring made of Al alone or an Al alloy such as Al—Cu can be used. The probe forming wiring 15 has an elongated linear shape, for example, a width of 1 μm, a length of 40 μm, and a thickness of 0.5 μm.

  Further, as shown in FIG. 2, an upper layer wiring 17 is formed on the second interlayer insulating film 14 so as to be separated from the probe forming wiring 15. As the upper layer wiring 17, for example, an Al wiring is used.

  The probe forming wiring 15 and the upper layer wiring 17 are electrically connected to the lower layer wiring 13 through vias 18 formed in the second interlayer insulating film 14, respectively. The via 18 is made of a conductor made of a material different from that of the probe forming wiring 15, for example, tungsten. However, the material of the lower layer wiring 13 is made different from the material of the probe forming wiring 15, or the design is made sufficiently short even if the material of the lower layer wiring 13 is the same as the material of the probe forming wiring 15. The material of the via 18 can be made the same as the material of the probe forming wiring 15 by the above device.

  The probe forming wiring 15 is electrically connected to the upper layer wiring 17 through the lower layer wiring 13, and the upper layer wiring 17 is electrically connected to a signal amplification circuit (not shown) formed on the semiconductor substrate 1. Connected.

  The passivation film 16 covers the surface excluding the lower surface of the probe forming wiring 15, that is, the upper surface and the side surface. The passivation film 16 is made of a material having a smaller linear expansion coefficient than the probe forming wiring 15. At this time, the linear expansion coefficient of the passivation film 16 is preferably 1/10 or less of the linear expansion coefficient of the probe forming wiring 15. For example, a silicon oxide film or a silicon nitride film can be used as the passivation film 16.

  The through hole 16 a provided in the passivation film 16 has a depth that reaches the probe formation wiring 15 from the surface of the passivation film 16. The number of through holes 16a is, for example, one for one probe forming wiring 15.

  The probe 5 is columnar and has a length that protrudes from the probe forming wiring 15 onto the surface of the passivation film 16. The probe 5 is continuous from the surface of the probe forming wiring 15 and is integrated with the probe forming wiring 15. The probe 5 is made of the same element as all or part of the elements constituting the probe forming wiring 15. For example, it is composed of an Al single crystal. The width of the probe 5 is smaller than the width of the through hole 16a.

  The probe driving unit 7 is a mechanism for moving the probe 5 in the vertical direction and the plane direction. Similar to the probe forming unit 6, the probe driving unit 7 includes a field insulating film 11, a first interlayer insulating film 12, a second interlayer insulating film 14, and a passivation film 16 formed on the semiconductor substrate 1. And. Furthermore, the pointer drive unit 7 includes a lower electrode 21 and a piezoelectric body 22 stacked between the first interlayer insulating film 12 and the second interlayer insulating film 14, and the second interlayer insulating film 14 and the second interlayer insulating film 14. The film 14 is composed of an upper electrode 23 formed in an opening 14 a located above the piezoelectric body 22.

  Here, the lower electrode 21 is connected to the lower surface of the piezoelectric body 22. As the lower electrode 21, a film made of the same material as that of the lower layer electrode 13 of the probe forming unit 6, for example, a polysilicon film can be used.

  As the piezoelectric body 22, a known material such as AlN, ZnO, or PZT can be used.

  The upper electrode 23 is electrically connected to the upper surface of the piezoelectric body 22. As the upper electrode 23, a film made of the same material as the probe forming wiring 15, for example, an Al wiring can be used. As shown in FIG. 2, the upper electrode 23 is electrically connected to a drive circuit (not shown) formed on the same semiconductor substrate 1.

  The circuit unit 3 is a region that constitutes a signal amplification circuit for amplifying a signal output from the probe 5, a drive control circuit for driving the probe 5, a feedback circuit, and the like. When the signal from the probe 5 is input to the signal amplification circuit, this signal is amplified and calculated by the feedback circuit. Thereafter, the calculation result is input to the drive control circuit, and a drive signal is output from the drive control circuit to the piezoelectric body 22. As a result, the cantilever portion 2, that is, the probe 5 is driven by the piezoelectric body 22.

  In the circuit section 3, semiconductor elements such as transistors constituting the above-described circuit are formed. That is, the circuit unit 3 includes a semiconductor region 31 formed on the semiconductor substrate 1, an element isolation film 32 formed on the semiconductor substrate 1, and a gate electrode 33 formed on the semiconductor substrate 1, as shown in FIG. The semiconductor region 31 is electrically connected to the interlayer insulating film 14 formed on the semiconductor substrate 1 and the gate electrode 33 and the contact 34 formed on the interlayer insulating film 14 and formed on the interlayer insulating film 14. The wirings 35 are connected to each other, and the passivation film 16 is formed on the interlayer insulating film 14 and the wirings 35.

  Note that a polysilicon film can be used as the gate electrode 33. Further, an Al wiring can be used as the wiring 35.

  Next, a method for manufacturing the SPM probe having the above structure will be described.

  3A to 3C show a manufacturing process of the SPM probe in the present embodiment. 3A to 3C correspond to the probe forming unit 6 in FIG. Hereinafter, a description will be given with reference to FIGS. 1 and 3.

  As shown in FIG. 3A, a step of preparing the semiconductor substrate 1, a step of forming a first interlayer insulating film 12 in a region where the probe forming portion 6 is to be formed in the semiconductor substrate 1, and a first A step of forming a lower layer wiring 13 on the interlayer insulating film 12, a step of forming a second interlayer insulating film 14 on the lower layer wiring 13 and the first interlayer insulating film 12, and a via hole 18a in the second interlayer insulating film 14. , A step of forming the probe forming wiring 15 on the second interlayer insulating film 14, and a step of forming the passivation film 16 on the probe forming wiring 15 are sequentially performed.

  Here, in the step of preparing the semiconductor substrate 1, as shown in FIG. 1, the field insulating film 11 is formed in the region where the cantilever part 2 is to be formed in the semiconductor substrate 1, and the region where the circuit part 3 is to be formed. In addition, the semiconductor substrate 1 on which the semiconductor region 31 and the element isolation film 32 are formed is prepared.

  Further, the step of forming the first interlayer insulating film 12 is performed simultaneously with the formation of the gate oxide film in the region where the circuit portion 3 is to be formed, as shown in FIG.

  The step of forming the lower layer wiring 13 is performed simultaneously with the formation of the gate electrode 33 in the region where the circuit part 3 is to be formed and the formation of the lower electrode 21 in the region where the probe driving part 7 is to be formed. In this step, for example, after a polysilicon film is formed, the polysilicon film is patterned by photolithography and etching.

  Further, between the step of forming the lower layer wiring 13 and the step of forming the second interlayer insulating film 14, the piezoelectric body 22 is formed on the lower layer wiring 21 in the region where the probe driving unit 7 is to be formed. Perform the process.

  The step of forming the second interlayer insulating film 14 is performed simultaneously with the formation of the second interlayer insulating film 14 in the region where the probe driving unit 7 and the circuit unit 3 are to be formed.

  In addition to the step of forming the via hole 18 a after the step of forming the second interlayer insulating film 14, the step of forming the opening 14 a in the region where the probe driving unit 7 is to be formed, and the formation of the circuit unit 3. In the region, a step of forming a contact hole 34a in the second interlayer insulating film 14 is performed.

  When the via hole 18a is formed, the via hole 18a is disposed near the end of the probe forming wiring 15 opposite to the end where the probe 5 is formed. Note that the via hole 18a may be arranged at another position. When the via hole 18a is formed and the material of the via 18 is the same as the material of the probe forming wiring 15, the number of via holes 18a is as small as possible with respect to one probe forming wiring 15, for example, one. It is preferable to do.

  Then, after forming the via hole 18a, the via 18 is formed inside the via hole 18a. At this time, when the lower layer wiring 13 is made of a material different from the probe forming wiring 15, for example, polysilicon, the via 18 is made of the same Al metal or Al alloy as the probe forming wiring 15. On the other hand, when the lower layer wiring 13 is made of the same material as the probe forming wiring 15, the via 18 is made of a material different from that of the probe forming wiring 15. This is because when thermal stress is applied to the probe forming wiring 15, the thermal stress is prevented from being dispersed from the probe forming wiring 15 to the lower layer wiring 13.

  Further, in the step of forming the probe forming wiring 15, for example, after an Al metal film or an Al alloy film is formed, the Al metal film or the Al alloy film is patterned by photolithography and etching.

  At this time, the probe forming wiring 15 is formed in an elongated linear shape. The reason why the shape is elongated is to make it easier for stress due to a difference in linear expansion coefficient, which will be described later, to be applied to the probe forming wiring 15. Further, the length and width of the probe forming wiring 15 are set so that the later-described difference in linear expansion coefficient is appropriate. For example, the width is 1 μm, the length is 40 μm, and the thickness is 0.5 μm. According to the investigation results of the present inventors, when the Al alloy film is covered with a silicon oxide film, the columnar portion grows from the Al alloy film when the width is 1.0 μm or less and the length is 40 μm or more. I know. Therefore, it is preferable that the probe forming wiring 15 has a width of 1 μm or less and a length of 40 μm or more.

  This step is performed simultaneously with the formation of the upper electrode 23 in the region where the probe drive unit 7 is to be formed and the formation of the wiring 35 in the region where the circuit unit 3 is to be formed. At this time, the via 18 of the probe forming part 6 and the contact 14 of the circuit part 3 are formed.

  In the step of forming the passivation film 16, the passivation film 16 is formed so that the passivation film 16 covers the side surface and the upper surface of the probe forming wiring 15. This step is performed simultaneously with the formation of the passivation film 16 in the region where the probe driving unit 7 and the circuit unit 3 are to be formed, as shown in FIG.

  Then, after the step shown in FIG. 3A, as shown in FIG. 3B, a step of forming a through hole 16a in the passivation film 16 is performed in the region where the probe forming portion 6 is to be formed. At this time, it is preferable that the number of through holes 16a is as small as possible with respect to one probe forming wiring 15, for example, one. Further, the opening width of the through hole 16a is set to 400 nm, for example. Although not shown, this step is performed simultaneously with the formation of the pad opening in the pad region of the semiconductor substrate 1.

  Subsequently, as shown in FIG. 3C, a step of forming the probe 5 inside the through hole 16a is performed. In this step, the entire semiconductor substrate 1 is heated. At this time, the heating is performed in vacuum, and the heating temperature is set to 450 ° C. or higher, for example. In this embodiment, this process also serves as annealing of the passivation film 16.

  As a result, thermal stress resulting from the difference in linear expansion coefficient between the passivation film 16 and the probe forming wiring 15 is applied to the probe forming wiring 15, and a part of the probe forming wiring 15 is formed inside the through hole 16a. Grows in a columnar shape. This column-shaped portion becomes the probe 5.

  At this time, the probe 5 grows from the probe forming wiring 15 along the through hole 16 a and has a length protruding from the passivation film 16. Moreover, it is preferable to set the length of the probe 5 to such a length that the probe 5 and the surface of the passivation film 16 in the cantilever part 2 do not interfere when the cantilever part 2 bends.

  The width of the probe 5 is on the order of submicrons, for example, 100 nm or less. In addition, about the width | variety of the probe 5, it can set arbitrarily by changing the width | variety of the through hole 16a small.

  Thereafter, although not shown, the cavity 4 is formed in the semiconductor substrate 1. For example, after forming a photoresist on the front surface and the back surface of the semiconductor substrate 1 and patterning the photoresist on the back surface side, anisotropic etching is performed from the back surface side using a chemical solution such as KOH. Thereby, the cantilever part 2 is formed.

  As described above, the SPM probe 5 having the structure shown in FIG. 1 can be manufactured.

  Next, main effects of this embodiment will be described.

  (1) In this embodiment, the step of preparing the semiconductor substrate 1 and the probe forming wiring 15 are formed on the surface of the semiconductor substrate 1 via the first interlayer insulating film 12 and the second interlayer insulating film 14. A step of forming a passivation film 16 covering the probe forming wiring 15; a step of forming a through hole 16a in the passivation film 16; and heating the semiconductor substrate 4 so that the probe is formed inside the through hole 16a. By growing a part of the forming wiring 15 in a columnar shape, a step of forming the probe 5 having a shape protruding from the passivation film 16 inside the through hole 16a is sequentially performed.

  Since the manufacturing method of the probe 5 is a method using a wiring process when manufacturing an IC, a plurality of probe forming wirings 15 are formed on a single semiconductor wafer, as in the manufacture of an IC. The probe 5 can be formed simultaneously from the respective probe forming wirings 15. For this reason, according to the manufacturing method of this embodiment, mass production of the probe 5 is easy.

  Further, in this embodiment, since the probe 5 is formed by growing a part of the probe forming wiring 15 in a columnar shape, the probe 5 having a structure integrated with the wiring 15 is manufactured. Can do. Thus, in the method of manufacturing only the probe, a process of electrically connecting the probe and the wiring after manufacturing only the probe is required, whereas according to the present embodiment, the probe and the wiring Can be omitted. In other words, according to the present embodiment, after forming the probe 5, the probe forming wiring 15 can be used as it is as a wiring electrically connected to the probe 5.

  (2) In the present embodiment, the cantilever unit 2 having the probe 5 and the probe driving unit 7 for driving the probe on the same semiconductor substrate, and the circuit unit 3 for driving the probe driving unit 7, etc. Is manufacturing.

  Thus, since the manufacturing method of the probe 5 of this embodiment is a method using the wiring process at the time of manufacturing IC, in the case where the cantilever is manufactured by the semiconductor microfabrication technology as in this embodiment, The cantilever part 2, the circuit part 3, and the probe 5 can be formed on the same semiconductor substrate. That is, according to this embodiment, the probe 5 and the circuit unit 3 can be easily integrated.

  Further, according to the present embodiment, the drive control of the probe 5 and the control for processing the signal from the probe 5 can be unified.

  Further, since the probe 5 and the circuit unit 3 are formed on the same semiconductor substrate, the circuit unit 3 amplifies the signal transmitted from the probe 5 to the circuit unit 3 even if the signal is weak. And the signal reliability is high.

  (3) In the present embodiment, the probe forming wiring 15, the upper electrode 23 electrically connected to the piezoelectric body 22, and the wiring 35 electrically connected to the semiconductor region 31 are formed simultaneously. .

  Thereby, the manufacturing process is simplified as compared with the case where the probe forming wiring 15 of the probe forming section 6, the upper electrode 23 of the probe driving section 7, and the wiring 35 of the circuit section 3 are formed separately. Can be

  In the present embodiment, a pad opening is formed in the passivation film 16 in the pad region of the semiconductor substrate 1, and at the same time, a through hole 16 a is formed in the passivation film 16 in a region where the probe forming portion 6 is to be formed. ing.

  Thereby, a manufacturing process can be simplified compared with the case where the opening part for pads and the through-hole 16a are formed separately.

  In other words, in this embodiment, the probe forming wire 15 and the through hole 16a of the probe forming unit 6 are formed at the same time as each component of the circuit unit 3 and the probe driving unit 7, thereby forming the circuit unit 3 The probe 5 can be manufactured without adding a new process to the manufacturing process of the probe driving unit 7.

  (4) In the present embodiment, when the probe 5 and the circuit unit 3 are formed on the same semiconductor substrate, wiring for electrically connecting the probe 5 and the circuit unit 3 is formed at the same time.

  For this reason, according to this embodiment, it is not necessary to perform the process of connecting the probe 5 and the circuit part 3 separately.

  (5) In this embodiment, after performing the step of forming the through hole 16a in the passivation film 16, the entire semiconductor substrate 1 is heated to grow a part of the probe forming wiring 15 in a columnar shape. The probe 5 is formed inside the through hole 16a. Therefore, according to the present embodiment, the probe 5 having a structure integrated with the probe forming wiring 15 can be formed.

  Here, since the electropolishing method described in the background section above is a method of manufacturing only the probe, after the probe is manufactured, the probe is fixed to the cantilever, and the probe and the wiring are electrically connected. The process of connecting to is required.

  On the other hand, in the present embodiment, the probe 5 is formed directly on the cantilever portion 2 and, when the probe 5 is formed, the probe 5 is integrated with the probe forming wiring 15. The step of fixing the probe to the cantilever and electrically connecting the probe and the wiring can be omitted.

(Second Embodiment)
4A and 4B show a manufacturing process of the SPM probe in the second embodiment. 4 (a) and 4 (b), the same reference numerals as those in FIGS. 3 (b) and 3 (c) are given to the same components as those in FIGS. 3 (b) and 3 (c), respectively.

  The manufacturing process of this embodiment is obtained by adding the process shown in FIG. 4A between the process shown in FIG. 3B and the process shown in FIG. 3C in the first embodiment. .

  That is, after forming the through hole 16a in the passivation film 16 in the step shown in FIG. 3B, the aperture layer 19 is formed on the bottom surface of the through hole 16a in the step shown in FIG. The aperture layer 19 is a layer that covers the surface of the probe forming wiring 15 inside the through hole 16a and has an opening having a width smaller than the width of the through hole 16a.

  For example, a laminated film of a TiN (titanium nitride) film and a Ti (titanium) film can be formed on the inner wall of the through hole 16a. In this case, the TiN film is composed of a plurality of columnar crystals, and a gap is generated between adjacent columnar crystals. This gap is the opening.

  Thereafter, as shown in FIG. 4B, the probe 5 is formed by heating the semiconductor substrate 1 as in the step shown in FIG. At this time, the probe 5 grows from the opening of the aperture layer 19. For this reason, the width | variety of the probe 5 can be made small compared with the case where the aperture layer 19 is not formed like 1st Embodiment. At this time, it is preferable that the aperture layer 19 has one opening in one through hole.

  Here, for reference, FIGS. 5A and 5B show electron micrographs of the probe 5 manufactured by the manufacturing method of the present embodiment. FIG. 5A is a photograph when a plurality of through holes are formed, and the probe 5 is formed in one of the through holes, and FIG. 5B is a view in FIG. It is an enlarged view of the area | region enclosed with the broken line. At this time, Al-0.5% Cu alloy wiring is used as the probe forming wiring 15.

  As shown in FIG. 5, according to the present embodiment, the probe 5 having a width smaller than the opening width of the through hole 16a can be formed.

(Third embodiment)
FIG. 6 shows a manufacturing process of the SPM probe in the third embodiment.

  As in this embodiment, after the step of forming the probe 5 shown in FIG. 3C, the step of processing the tip of the probe 5 can be performed. For example, by applying isotropic etching to the probe 5, the tip 5a of the probe 5 can be sharpened as shown in FIG.

  Instead of isotropic etching, electrolytic emission in which a high electric field is applied in vacuum can be applied to the probe 5.

  Moreover, the tip 5a of the probe 5 can be processed into other shapes such as a flat shape, a round shape, and a trapezoid shape by performing other processing such as anisotropic etching according to the application.

(Fourth embodiment)
7A and 7B show a manufacturing process of the SPM probe in the fourth embodiment.

  After performing the step of forming the probe 5 shown in FIG. 3C as in the present embodiment, the surface of the probe 5 is made of a material different from the portion grown from the probe forming wiring 15 in a columnar shape. A step of covering with the constructed film can also be performed.

  For example, as shown in FIG. 7A, after the probe 5 is formed, a W (tungsten) film 41 is formed on the surface of the passivation film 16 and the probe 5. Thereafter, as shown in FIG. 7B, by etching back the W film 41, the tip side portion of the probe 5 can be covered with the W film 42 having a melting point higher than that of Al.

  Thereby, when using the probe 5 in the state where the high voltage was applied, the deformation | transformation of the probe 5 by heat_generation | fever can be suppressed.

  The tip side portion of the probe 5 can be covered not only with the W film 42 but also with a film made of another material. For example, the tip side portion of the probe 5 can be covered with an insulating film such as SiN (silicon nitride). Thereby, the probe 5 can be used as an AFM probe.

  Thus, the probe 5 made of an arbitrary material can be manufactured by covering the surface of the probe 5 with a film made of a material different from the portion of the probe forming wiring 15 grown in a columnar shape.

  In the present embodiment, the case where the etch back is adopted as the film forming means for covering the probe 5 has been described as an example, but other means may be adopted. For example, a means for selectively forming a film on the surface of the probe 5 can be employed.

(Fifth embodiment)
FIG. 8 shows a planar layout of a semiconductor substrate on which the probe 5 in the fifth embodiment is formed. As in this embodiment, multiple probes can be formed by arranging a plurality of probes regularly on the same semiconductor substrate, that is, in the form of an array. At this time, a cantilever array using a known MEMS technology can be used.

  For example, as shown in FIG. 8, 32 cantilever portions 2 having the structure shown in FIG. 2 are formed on the same semiconductor substrate 1. In this case, in the step of forming the probe forming wiring 15, a plurality of probe forming wirings 15 are formed in an array on the surface of the same semiconductor substrate. In the step of forming the probe 5, the probe 5 is formed from each of the plurality of probe forming wires 15.

  In the present embodiment, a scan control circuit 3a, a feedback circuit 3b, an amplifier circuit 3c, a cache memory 3d, an input / output circuit 3e, and a circuit unit 3 are adjacent to the cantilever unit 2 on the semiconductor substrate 1. A signal arithmetic circuit 3f is formed. Then, a plurality of pads 8 are formed on the outer periphery of the plurality of cantilever portions 2 and the circuit portion 3 in the semiconductor substrate. In FIG. 8, the wiring that electrically connects the cantilever portion 2 and each circuit portion 3 and the wiring that electrically connects each circuit portion 3 and each pad 8 are omitted.

  In this case, a signal from each probe 5 is taken out from the pad 8 arranged corresponding to each probe 5. At this time, the signal of each probe 5 is output as it is, amplified by the amplifier circuit 3c, the signal of each probe 5 is temporarily stored in the cache memory 3d, serially output, or calculated by the signal calculation circuit 3f Or output the result.

  Next, main effects of this embodiment will be described.

  When a plurality of probes are integrated and used as a multi-probe, it is required to mount a plurality of probes in a highly integrated manner.

  However, in the method of manufacturing one probe at a time, like the electrolytic polishing method described in the background section above, a cantilever and a plurality of probes are prepared separately, and a plurality of probes are provided on the cantilever. Therefore, the relative positional accuracy of the plurality of probes was low. Further, after manufacturing the probe, it is necessary to prepare a drive unit and a circuit unit which are separate from the probe, and to mount the probe and the probe separately.

  For this reason, in the above-described electropolishing method, a plurality of probes cannot be mounted with high integration, and application to the multi-probe field such as high-density storage is difficult.

  In contrast, in the present embodiment, the probes 5 are formed in an array on the same semiconductor substrate 1 by the manufacturing method described in the first embodiment. For this reason, according to the present embodiment, since the plurality of probes 5 can be formed with the same positional accuracy as that of the IC, the multi-probe can be easily manufactured.

  In addition to the use as a microscope, a general SPM has a use for processing micro orders and nano orders. Therefore, if the multi-probe of this embodiment is used, for example, application to large-capacity high-density recording becomes possible. In this case, writing and erasing are performed by processing the recording medium using each probe 5, and reading is performed by microscopic observation using each probe 5.

(Sixth embodiment)
FIG. 9 shows a planar layout of the probe forming wiring 15 in the sixth embodiment. In FIG. 9, the same reference numerals as those in FIG.

  In each of the above-described embodiments, the case where the probe forming wiring 15 has a linear shape has been described as an example. On the other hand, as shown in FIG. 9, the probe forming wiring 15 can be configured to have a linear portion 15a and a reservoir portion 15b. The linear portion 15a corresponds to the probe forming wiring 15 in FIG. Therefore, in other words, in this embodiment, the probe forming wiring 15 has a shape in which a reservoir portion 15b is added to the probe forming wiring 15 in FIG.

  The linear shape portion 15a has a through hole 16a for forming the probe 5 on one end side and a via hole 18a for electrically connecting to the lower layer wiring 13 on the other end side. . For this reason, the linearly shaped portion 15 a is a portion that functions as an electrical wiring that transmits a signal from the probe 5 to the lower layer wiring 13. On the other hand, the reservoir portion 15b is a portion that has one end continuous with the linear shape portion 15a but does not function as electrical wiring because the other end is not connected to anything.

  Here, the reservoir portion 15b is a portion for lengthening the probe forming wiring 15 as compared with the case of only the linear shape portion 15a, and a portion serving as a raw material supply source for forming the probe 5. It is. Since the manufacturing method of the probe 5 according to the above-described embodiment is a method of forming the probe 5 by supplying the raw material from the probe forming wiring 15, the reservoir portion 15 b is provided in this way. It is possible to secure a source of raw materials for probe formation.

  Further, by providing the reservoir portion 15b, the probe forming wiring 15 can be made longer than when the reservoir portion 15b is not provided, and the probe forming wiring due to the difference in linear expansion coefficient with the passivation film 16 is provided. The stress to 15 can be increased. As a result, the probe 5 can be easily formed.

  In the present embodiment, the reservoir 15b is bent a plurality of times. Thereby, the area of the formation region of the reservoir portion 15b is reduced. The shape of the reservoir portion 15b is not limited to this, and may be other shapes such as a linear shape.

  Specifically, when the probe forming wiring 15 is made of Al metal or an Al alloy and the passivation film 16 is made of a silicon oxide film, the width is preferably 1 μm or less and the length is 100 μm or more.

(Other embodiments)
(1) FIG. 10 shows a cross-sectional view of the cantilever portion 2 in another embodiment. In the first embodiment, the case where the cavity 4 is formed in the semiconductor substrate 1 by performing anisotropic etching from the back side of the semiconductor substrate 1 has been described. However, as shown in FIG. The cavity 4 can also be formed in the semiconductor substrate 1 by anisotropic etching from the side.

  (2) In each of the above embodiments, the case where the number of through holes 16a is one for one probe forming wiring 15 has been described as an example. The number 16a may be other numbers.

  (3) In each of the above-described embodiments, the case where the piezoelectric body 22 is formed as the probe driving body has been described as an example. However, other mechanisms such as a capacitive mechanism may be used.

  (4) In each of the above-described embodiments, the cantilever part 2 and the circuit part 3 share the insulating film 14 and the passivation film 16 formed on the surface of the semiconductor substrate 1, and the probe forming part 6 has a probe. When the needle forming wiring 15 is formed simultaneously with the upper electrode 23 of the probe driving section 7 and the wiring 35 of the circuit section 3, the probe forming section 6, the probe driving section 7 and the circuit section 3 are formed simultaneously. Was described as an example.

  On the other hand, if the probe forming unit 6 can be formed simultaneously with the probe driving unit 7 and the circuit unit 3, the probe forming wiring 15 and the probe forming wiring 15 of the probe forming unit 6 are covered. The film can be formed simultaneously with the probe driving unit 7 and other components in the circuit unit 3.

  For example, the second film in the probe forming unit 6 and the interlayer insulating film 14 in the circuit unit 3 can be shared. That is, the interlayer insulating film 14 in the circuit unit 3 can be used as the second film.

  In this case, in the probe forming part 6, the interlayer insulating film 14 is the uppermost layer so that the probe 5 is located on the outermost surface of the semiconductor substrate. Further, in the probe forming unit 6, the through hole for forming the probe 5 can be performed simultaneously with the formation of the via hole in the circuit unit 3.

  (5) In each of the above embodiments, the probe forming unit 6, the probe driving unit 7, and the circuit unit 3 are formed on the same semiconductor substrate 1 from the viewpoint of reducing the number of manufacturing steps. The case where the needle forming unit 6, the probe driving unit 7, and the circuit unit 3 are formed simultaneously has been described as an example.

  On the other hand, the probe forming unit 6 is formed simultaneously with either the probe driving unit 7 or the circuit unit 3, or the probe forming unit 6 is formed in a separate process from the probe driving unit 7 and the circuit unit 3. It can also be formed.

  (6) In the first embodiment, the case where the probe forming wiring 15 is used as the wiring electrically connected to the probe 5 has been described as an example. However, the probe forming wiring 15 is simply used as the probe. It can also be used only for forming. In this case, a wiring for transmitting a signal from the probe 5 is electrically connected to the probe 5.

  (7) In each of the embodiments described above, the probe forming unit 6 forms the first interlayer insulating film 12 and the second interlayer insulating film 14 between the semiconductor substrate 1 and the probe forming wiring 15. Although described as an example, not only the first interlayer insulating film 12 and the second interlayer insulating film 14 but various films can be formed.

  (8) In each of the above-described embodiments, the case where the cantilever portion 2 and the circuit portion 3 are formed on the same semiconductor substrate has been described as an example. However, they can be formed on separate semiconductor substrates. That is, the cantilever portion 2 and the circuit portion 3 can be separate components. In this case, for example, an input / output pad for electrically connecting the probe and the piezoelectric body to the circuit is formed on the semiconductor substrate on which the cantilever portion is formed.

  (9) In each of the above embodiments, the case where the probe forming unit 6 is formed simultaneously with the probe driving unit 7 and the probe 5 is integrated with the cantilever unit 2 has been described as an example. It is also possible to form only. In this case, for example, an input / output pad for electrically connecting the probe to a circuit is formed on the semiconductor substrate on which the probe forming unit 6 is formed.

  (10) In each of the embodiments described above, the case where the semiconductor substrate 1 is used as the substrate has been described as an example. However, the substrate is not limited to a semiconductor substrate such as silicon, and a substrate made of another material such as metal can be used.

  For example, when an insulating substrate is used instead of the semiconductor substrate 1, the probe forming wiring 15 can be formed directly on the surface of the substrate.

  (11) In each of the above-described embodiments, a case where a film made of Al metal or an Al alloy is used as the first film and a silicon oxide film is formed as the second film has been described as an example.

  On the other hand, when the substrate is heated after the through hole is formed, a part of the first film is formed in the through hole due to the thermal stress applied to the first film due to the difference in the linear expansion coefficient between the first film and the second film. Can be formed as a first film, a conductive film composed of a conductive material such as metal, and a second film composed of an insulating material. An insulating film can be formed.

It is sectional drawing of the semiconductor chip which has the probe for SPM in 1st Embodiment of this invention. 2 is a planar layout of wiring, electrodes and the like in the cantilever part 2 in FIG. 1. It is a figure which shows the manufacturing process of the probe for SPM in 1st Embodiment. It is a figure which shows the manufacturing process of the probe for SPM in 2nd Embodiment. It is an electron micrograph of the probe 5 manufactured with the manufacturing method of 2nd Embodiment. It is a figure which shows the manufacturing process of the probe for SPM in 3rd Embodiment. It is a figure which shows the manufacturing process of the probe for SPM in 4th Embodiment. It is a top view of the semiconductor substrate in which the probe 5 in 5th Embodiment is formed. It is a top view of the probe formation wiring 15 in 6th Embodiment. It is sectional drawing of the cantilever part 2 in other embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 5 ... Probe 5 ... Probe formation wiring, 16 ... Passivation film | membrane, 16a ... Through-hole.

Claims (15)

Preparing a substrate (1);
Forming a first film (15) made of a conductive material on the surface of the substrate (1);
Covering the first film (15) and forming a second film (16) made of an insulating material having a smaller linear expansion coefficient than that of the first film (15);
Forming a through hole (16a) having a depth reaching the first film from the surface of the second film in the second film (16);
The substrate (1) is heated to grow a part of the first film (15) into a columnar shape protruding from the surface of the second film (16) inside the through hole (16a). And a step of forming the probe (5). A method of manufacturing a probe for a scanning probe microscope, comprising: In the step of forming the first film (15), a plurality of the first films (15) are formed in an array on the surface of the same substrate (1),
In the step of forming the probe (5), the probe (5) is formed on the same substrate (1) by forming the probe (5) from each of the plurality of first films (15). 2. The method of manufacturing a probe for a scanning probe microscope according to claim 1, wherein a plurality of the probes are formed in an array. After the step of preparing the substrate (1), a step of forming a driver (22) for driving the probe (5) on the surface of the substrate (1); 3. A method of manufacturing a probe for a scanning probe microscope according to claim 1 or 2, further comprising the step of forming an electrode wiring (23) connected in an electrically connected manner. The method of manufacturing a probe for a scanning probe microscope according to claim 3, wherein the step of forming the first film (15) and the step of forming the electrode wiring (23) are performed simultaneously. In the step of preparing the substrate, a semiconductor element constituting a signal amplification circuit for amplifying a signal output from the probe (5) is formed in a region different from a region where the probe (5) is to be formed. A method of manufacturing a probe for a scanning probe microscope according to claim 1, wherein a semiconductor substrate (1) is prepared. In the step of forming the first film (15), a wiring (35) electrically connected to the semiconductor element is formed on the surface of the semiconductor substrate (1), and at the same time, the same as the wiring (35). The method for manufacturing a probe for a scanning probe microscope according to claim 5, wherein the first film (15) made of a material is formed. In the step of forming the first film, the first film (15) having a width of 1 μm or less and a length of 40 μm or more is formed,
The process of forming the through hole (16a) includes forming one through hole (16a) for one first film (15). A method for producing a probe for a scanning probe microscope according to claim 1. The said 1st film | membrane is formed, The said 1st film | membrane (15) comprised with the metal material which has Al as a main component is formed, The one of Claim 1 thru | or 7 characterized by the above-mentioned. A method for manufacturing a probe for a scanning probe microscope. Between the step of forming the through hole (16a) and the step of forming the probe (5), a layer (19) having an opening smaller in width than the through hole (16a) is formed on the through hole. (16a) having a step of forming on at least the bottom surface,
The probe for a scanning probe microscope according to any one of claims 1 to 8, wherein, in the step of forming the probe (5), the probe (5) is formed from the opening. Manufacturing method. The scanning type according to any one of claims 1 to 9, further comprising a step of processing the tip (5a) of the probe (5) after the step of forming the probe (5). A method for manufacturing a probe for a probe microscope. The step of forming the probe (5) includes a step of covering the probe (5) with a film (42) made of a material different from that of the probe (5). The manufacturing method of the probe for scanning probe microscopes as described in any one of thru | or 10. A first film (15) disposed on the surface of the substrate (1) and made of a conductive material;
A second film (16) covering the first film (15), having a smaller linear expansion coefficient than the first film (15), and made of an insulating material;
The first film (15) is formed of a material constituting the first film (15) in a through hole (16a) having a depth reaching the first film (15) from the surface of the second film (16). A scanning having a length protruding from the film (15) onto the surface of the second film (16) and comprising a probe (5) having a continuous shape with the first film (15). Type probe microscope probe. A plurality of the first films (15) are arranged in an array on the surface of the same substrate (1), and the probe (5) is formed from each of the plurality of first films (15). The probe for a scanning probe microscope according to claim 12, wherein the probe is used. A driving body (22) for driving the probe (5) is formed on a surface of the substrate (1) different from a region where the probe is formed. The probe for a scanning probe microscope according to claim 12 or 13. The substrate is a semiconductor substrate (1);
A semiconductor constituting a signal amplification circuit for amplifying a signal output from the probe (5) in a region different from the region where the probe (5) is formed in the semiconductor substrate (1). The probe for a scanning probe microscope according to claim 12, wherein an element is formed.

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