JP2007021713A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem wherein a semiconductor device equipped with a microstructure having a space and an electric circuit for controlling the microstructure, etc. over one substrate is difficult to be manufactured. <P>SOLUTION: In this semiconductor device, the microstructure and the electric circuit for controlling the microstructure can be provided over the one substrate by manufacturing the microstructure in a such way that a structural layer having polycrystalline silicon obtained by thermal crystallization or laser crystallization by using a metal element is formed and processed at low temperature. As the electric circuit, a wireless communication circuit for carrying out wireless communication with an antenna is given. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device that includes a microstructure and a semiconductor integrated circuit over the same substrate and performs wireless communication with the outside. The present invention also relates to a method for manufacturing a semiconductor device.

  In recent years, research on micro mechanical systems called MEMS has been actively conducted. MEMS (Micro Electro Mechanical System) is an abbreviation for a microelectromechanical system, and is sometimes simply called a micromachine. A micromachine generally refers to a microdevice in which “a microstructure having a three-dimensional structure and a movable structure” and “an electric circuit having a semiconductor element” are integrated using a semiconductor microfabrication technique. Unlike the semiconductor element, the microstructure has a three-dimensional structure and has a movable portion. And it can have a function of a switch, a variable capacitor, or an actuator.

Since micromachines can control their microstructures by means of electrical circuits, they are not a central processing control type like conventional computer-based devices, and information obtained by sensors is processed by electrical circuits and actuators, etc. It is thought that it is possible to build an autonomous decentralized system that performs a series of actions to take action through the. Many studies have been made on such micromachines (see Patent Document 1).
Japanese Patent Application Laid-Open No. 2004-1201

  On the other hand, with the development of wireless communication technology, development of devices capable of transmitting and receiving information through wireless communication while being small in size is underway. This includes a wireless chip that stores information in an electric circuit, a reader / writer that reads and writes information stored in the wireless chip, and a system that processes the read information and controls the reader / writer. The wireless chip may be called by various names such as an RFID tag, an IC tag, and a wireless tag. The wireless chip is basically battery-free, and can obtain driving power from electromagnetic waves from the reader / writer and perform wireless communication with the reader / writer. In recent years, there have been many studies on the wireless chip and the individual identification information management technology using the wireless chip.

  It has been difficult to manufacture the microstructure and the semiconductor element constituting the micromachine using an equivalent process. This is because the manufacturing of a microstructure has a different process from that of manufacturing a semiconductor element, such as sacrificial layer etching.

Further, a semiconductor element often has a protective film or wiring formed thereon, and in such a case, how to seal the microstructure is a big problem.

As described above, since the different processes are included, there is a possibility that the microstructure or the semiconductor element may be destroyed and may not function. For this reason, micromachines that are currently in practical use are those in which a microstructure and a semiconductor element are manufactured in separate steps.

  Therefore, an object of the present invention is to provide a micromachine (hereinafter referred to as a semiconductor device) having a microstructure and a semiconductor element over the same insulating substrate.

  Furthermore, the present invention provides a microstructure, a semiconductor integrated circuit that controls the microstructure, and a wireless communication circuit that performs wireless communication on the same substrate, obtains driving power from outside by wireless communication, and further wirelessly It is an object to provide a semiconductor device capable of transmitting and receiving information through communication.

  Another object of the present invention is to provide a method for manufacturing the semiconductor device.

In view of the above problems, the present invention is characterized by a semiconductor device in which a microstructure and an electric circuit are integrally formed over an insulating surface, and the electric circuit can receive power and signals by wireless communication using an antenna. The microstructure includes a structural layer including polycrystalline silicon that is thermally crystallized or laser crystallized using a metal element. Such polycrystalline silicon can also be applied to a semiconductor element constituting an electric circuit. Note that the insulating surface refers to the surface of a glass substrate, a plastic substrate, or a substrate in which an insulating protective film is formed over a conductive substrate or a semiconductor substrate. In addition, the structural layer has a three-dimensional structure constituting the microstructure, and is characterized in that a space is provided between layers provided above or below the structural layer. In addition, such a space allows the microstructure to have a movable portion.

In the present invention, the following means are specifically taken.

The semiconductor device of the present invention includes an antenna, a microstructure, and an electric circuit over an insulating surface, and the antenna and the microstructure are connected to the electric circuit, respectively, and the microstructure is thermally crystallized using a metal element. Alternatively, the structure body includes a structure layer including polycrystalline silicon that is laser-crystallized, and the microstructure includes a space provided between the insulating surface and the structure layer.

In addition, the semiconductor device of the present invention includes an antenna, a microstructure, and an electric circuit over an insulating surface, and the antenna and the microstructure are connected to the electric circuit, respectively, and the microstructure is a conductive lower layer. One of the lower layer and the structural layer includes polycrystalline silicon that is thermally crystallized or laser-crystallized using a metal element, and the microstructure includes the lower layer, the structural layer, and the structural layer. It has the space provided between these, It is characterized by the above-mentioned.

The structural layer of the present invention comprises Ni (nickel), Fe (iron), Ru (ruthenium), Rh (rhodium), Pd (palladium), Os (osmium), Ir (iridium), Pt (platinum), Cu ( It is characterized by being thermally crystallized or laser crystallized using one or more metal elements of copper) and Au (gold). When crystallization is performed using such a metal element, the crystallization process can be performed at a low temperature, and a substrate having a low strain point such as a glass substrate can be used.

In addition, the structure layer may have a single-layer structure of polycrystalline silicon that is thermally crystallized or laser-crystallized using a metal element, or a stacked structure including the polycrystalline silicon. For example, the structural layer may have a laminated structure including the polycrystalline silicon and one or more selected from amorphous silicon and silicide. In the stacked structure, a plurality of polycrystalline silicon, a plurality of amorphous silicon, and a plurality of silicides may be provided. Silicide includes silicide using a metal element used for crystallization of silicon and silicide using a metal element different from the metal element.

The structural layer may be provided with a region containing polycrystalline silicon selectively. For example, a region including the polycrystalline silicon and one or more regions selected from amorphous silicon and silicide can be included.

In the semiconductor device of the present invention, the electric circuit includes a wireless communication circuit and a processing circuit, the antenna is connected to the wireless communication circuit, and the microstructure is connected to the processing circuit.

The electric circuit may include a semiconductor element and a microstructure, and the antenna may be connected to the electric circuit.

Further, the electrical circuit includes a power supply circuit, a clock generation circuit, a demodulation circuit, a modulation circuit, an information determination circuit, a memory, a memory control circuit, an arithmetic circuit, and a microstructure control circuit.

The semiconductor device of the present invention can include a substrate (referred to as a counter substrate) facing the insulating surface. Further, the counter substrate can have a protective layer. The protective layer is provided in a portion facing a region where the microstructure is not provided.

The antenna included in the semiconductor device of the present invention can be provided over the counter substrate. The antenna can be connected to an electric circuit.

In addition, in the microstructure, a space is formed by removing all or part of a sacrificial layer including a metal element, a metal element compound, silicon, silicon oxide, silicon nitride, or silicon oxynitride by etching. Is done. Such a space can be described as being in contact with the structural layer. That is, the sacrificial layer refers to a layer that is removed by etching. Then, after the stacked structure forming the microstructure is formed, the movable portion of the microstructure can be operated by the formed space where the sacrificial layer is removed by etching. In the case where a conductive material such as a metal element or a metal element compound is used for the sacrificial layer, a part of the sacrificial layer can be used as the conductive layer.

For example, the microstructure of the present invention is characterized in that a space (referred to as a first space) is provided between the structural layer and the insulating surface.

In the microstructure, a first space is provided between the structural layer and the insulating surface, and a space (denoted as a second space) is provided between the structural layer and a layer provided on the structural layer. It is provided.

The microstructure has a conductive lower layer on an insulating surface, and a space (denoted as a third space) is provided between the lower layer and the structural layer. .

The microstructure has a conductive lower layer on the insulating surface, and a third space is provided between the lower layer and the structural layer, and between the layers provided on the structural layer. A second space is provided.

The lower layer included in the microstructure of the present invention can be formed using a conductive material such as a metal element, a metal element compound, silicide, or silicon having impurities, and can function as a lower electrode. A voltage or the like can be applied to the lower electrode in order to control the movable structural layer.

Further, the structural layer is preferably processed into a shape with rounded corners as viewed from above, that is, patterned. Further, the structural layer is preferably formed so that the cross section has a taper angle.

In a method for manufacturing a semiconductor device of the present invention, a first sacrificial layer is formed in a first region over an insulating surface, and a layer including silicon is formed on the first sacrificial layer and the second region in the first region. The layer having silicon is thermally crystallized or laser-crystallized using a metal element, and the layer having crystallized silicon is patterned to form a structural layer in the first region and a layer in the second region. Forming a semiconductor layer, forming a first insulating layer on the structural layer and the semiconductor layer, forming a first conductive layer on the first insulating layer, and patterning the first conductive layer; A gate electrode is formed in the second region, the first sacrificial layer is removed by etching, and a first space is formed between the insulating surface and the structural layer. The first region is a region where a microstructure is formed, and the second region is a region where a semiconductor element is formed.

In the method for manufacturing a semiconductor device of the present invention, a first sacrificial layer is formed in a first region over an insulating surface, a layer including silicon is formed over the first sacrificial layer, and a layer including silicon is formed. Are patterned by thermal crystallization or laser crystallization using a metal element and patterning the crystallized silicon layer, thereby forming a structural layer in the first region and a semiconductor layer in the second region. The first insulating layer is formed over the semiconductor layer, the first conductive layer is formed over the first insulating layer, and the first conductive layer is patterned, so that the second region is formed in the first region. A gate electrode is formed in the sacrificial layer and the second region, a second insulating layer is formed on the second sacrificial layer and the gate electrode, and a first contact hole is formed in the second insulating layer And forming a second conductive layer on the second insulating layer and patterning the second conductive layer. Thus, a wiring that connects the first region and the second region is formed, and the second contact hole that exposes the first sacrificial layer and a part of the second sacrificial layer to the second insulating layer is formed. Forming an etchant through the second contact hole, removing the first sacrificial layer and the second sacrificial layer by etching, a first space between the insulating surface and the structural layer, and A second space is formed between the structural layer and the second insulating layer.

In the above method for manufacturing a semiconductor device, a first conductive layer serving as a lower layer can be formed over an insulating surface, and a first sacrificial layer can be formed over the first conductive layer.

In addition, in the method for manufacturing a semiconductor device of the present invention, a layer including silicon is formed over an insulating surface, the layer including silicon is thermally crystallized or laser-crystallized using a metal element, and the layer including crystallized silicon is included. To form a lower layer in the first region, a semiconductor layer in the second region, a third sacrificial layer on the lower layer, and a first layer on the lower layer and the semiconductor layer. An insulating layer is formed, a first conductive layer is formed over the third sacrificial layer, and the first conductive layer is patterned, whereby a structural layer is formed in the first region and a gate electrode is formed in the second region. And the third sacrificial layer is removed by etching to form a third space between the lower layer and the structural layer.

In addition, in the method for manufacturing a semiconductor device of the present invention, a layer including silicon is formed over an insulating surface, the layer including silicon is thermally crystallized or laser-crystallized using a metal element, and the layer including crystallized silicon is included. To form a lower layer in the first region, a semiconductor layer in the second region, a first insulating layer on the lower layer and the semiconductor layer, and on the first insulating layer, A third sacrificial layer is formed in the first region, and a third conductive layer and a fourth conductive layer are stacked over the first insulating layer and the third sacrificial layer, and the fifth conductive layer is formed. By patterning the layer and the sixth conductive layer, a structural layer and a fourth sacrificial layer are formed in the first region, and a gate electrode is formed in the second region. On the fourth sacrificial layer and the gate electrode, Forming a second insulating layer, forming a first contact hole in the second insulating layer; A second conductive layer is formed on the second insulating layer, and the second conductive layer is patterned to form a wiring connecting the first region and the second region, thereby forming a third sacrificial layer and a fourth sacrificial layer; A second contact hole is formed in the second insulating layer so that a part of the sacrificial layer is exposed, the third sacrificial layer and the fourth sacrificial layer are removed by etching, and a third layer in contact with the structural layer is formed. A space and a second space are formed, respectively.

In the above method for manufacturing a semiconductor device, a protective layer may be formed on a portion of the counter substrate facing a region where the microstructure is not provided, and the insulating surface and the counter substrate may be fixed and bonded to face each other. Good.

In the above method for manufacturing a semiconductor device, a fifth conductive layer functioning as an antenna is formed over a counter substrate, and a protective layer is formed in a portion facing a region where the structural layer on the fifth conductive layer is not provided. Forming a third contact hole in the protective layer, forming a sixth conductive layer so as to fill the third contact hole, patterning, and electrically connecting the wiring layer and the sixth conductive layer to each other. The insulating surface and the counter substrate face each other so as to be connected.

In the method for manufacturing a semiconductor device, the layer including silicon can be formed by stacking one or more selected from polycrystalline silicon, amorphous silicon, and silicide. The layer containing silicon can be crystallized by adding a metal element over amorphous silicon and irradiating the region to which the metal element is added with a laser. The metal element can be added to the entire surface or selectively.

As the metal element, any one or more of Ni, Fe, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au can be used.

In the above method for manufacturing a semiconductor device, the first sacrificial layer and the second sacrificial layer can be formed using the same material and removed by etching in the same process. Similarly, the third sacrificial layer and the fourth sacrificial layer can be formed using the same material and simultaneously removed by etching.

In the above method for manufacturing a semiconductor device, any one of the structural layer and the first to fourth sacrificial layers may be formed so that the upper surface has a polygonal shape with rounded corners and the cross section has a taper. desirable.

  The present invention uses a polycrystalline silicon crystallized using a metal element such as nickel for a structure layer of a microstructure and an active layer of a semiconductor element, thereby forming the microstructure and the semiconductor element on the same substrate. Thus, a semiconductor device can be provided. The microstructure thus formed can withstand external forces and stresses, and thus can be formed over the same substrate as the semiconductor element.

  In addition, according to the present invention, a microstructure and a semiconductor element are manufactured over the same substrate, so that a semiconductor device that does not require assembly or a package and does not require manufacturing costs can be provided.

  In addition, the semiconductor device of the present invention has a wireless communication circuit and can perform power supply and control by wireless communication. Accordingly, wiring for supplying power or controlling the semiconductor device is not necessary, so that a highly flexible semiconductor device that operates physically independently can be provided. Furthermore, by including a central processing arithmetic circuit and the like for controlling the microstructure, it is possible to provide a semiconductor device that performs a series of operations of “detection, determination, and action” only by wireless communication control.

  Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description. It will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the following embodiments and examples. Note that in describing the structure of the present invention with reference to the drawings, the same portions are denoted by the same reference numerals in different drawings.

(Embodiment 1)
In this embodiment mode, a semiconductor device of the present invention is described with reference to drawings.

  The semiconductor device of the present invention can manage individual identification information using wireless communication. That is, the semiconductor device of the present invention includes a wireless chip that enables individual identification information management using wireless communication. A semiconductor device provided with a wireless chip can perform driving communication with a reader / writer by obtaining driving power from electromagnetic waves emitted from the reader / writer. Therefore, the semiconductor device of the present invention can take a battery-free system. However, a battery or the like may be mounted on the semiconductor device in order to supplement the driving power.

  FIG. 1A shows a structure of a semiconductor device of the present invention. A semiconductor device 101 of the present invention includes an antenna 12, a microstructure 13, and an electric circuit 14. The electric circuit 14 includes a wireless communication circuit 15 and a processing circuit 16. The antenna 12 is connected to the wireless communication circuit 15 and can exchange signals and the like with each other. Further, the microstructure 13 is connected to the processing circuit 16 and can exchange signals and the like with each other.

  When the antenna 12 and the wireless communication circuit 15 approach the reader / writer 17, the antenna 12 receives the electromagnetic waves radiated from the reader / writer 17 and can be supplied with driving power for driving the semiconductor device 101. The antenna 12 can transmit and receive information to and from the reader / writer 17 using electromagnetic waves. The processing circuit 16 can perform operations such as controlling the microstructure 13 based on information received from the reader / writer 17 or processing information received from the object 110 by the microstructure 13. The processing circuit 16 may have a so-called feedback mechanism that controls the microstructure 13 by processing information obtained from the microstructure 13 and processing, and information transmitted from the reader / writer 17 together.

  The microstructure 13 connected to the processing circuit 16 is, for example, a structure that functions as a sensor or an actuator. Since the microstructure 13 has a minute structure, the scaling law is applied, and a minute change of the object 110 can be captured and converted into a signal.

  The reader / writer 17 has a function of supplying driving power to the semiconductor device 101 via electromagnetic waves and transmitting / receiving information to / from the semiconductor device 101 using electromagnetic waves. The operation of the reader / writer 17 is controlled by a system, for example, a computer 18 here. The reader / writer 17 and the computer 18 can also use wired communication connected via a communication line such as USB (Universal Serial Bus) or wireless communication using infrared rays or the like.

  In addition, the semiconductor device 101 of the present invention can use a microstructure for an electric circuit. For example, as illustrated in FIG. 1B, the semiconductor device 101 includes an antenna 12 and an electric circuit 14, and the electric circuit 14 can be formed using a semiconductor element 31 and a microstructure 32. As in FIG. 1A, the electric circuit 14 includes a wireless communication circuit, a processing circuit, and the like, and the antenna is connected to a circuit having a wireless communication function in the electric circuit 14. Here, the microstructure 32 constituting the electric circuit 14 can function as a switch or a capacitor, for example. By configuring the circuit using the microstructure 32 having a high response speed that functions as a switch or a capacitor, wireless communication using a higher frequency can be performed.

  As shown in the figure, the semiconductor device 101 of the present invention has an antenna 12 and a wireless communication circuit 15 so that it does not have wiring for inputting driving power and control signals from the outside, and physically It is characterized by not being connected to others. That is, the semiconductor device 101 of the present invention enables wireless communication.

  FIG. 2 shows a detailed configuration of the electric circuit 14 included in the semiconductor device 101. First, the electric circuit 14 has a function of receiving electromagnetic waves radiated from the outside such as the reader / writer 17 and generating electric power for driving the semiconductor device 101 and further communicating with the outside wirelessly. Therefore, the electric circuit 14 has various circuits necessary for wireless communication such as the power supply circuit 11, the clock generation circuit 19, the demodulation circuit 113, the modulation circuit 114, the decoding circuit 116, the encoding circuit 117, and the information determination circuit 118. . Further, the circuit configuration may be different depending on the frequency of electromagnetic waves used for wireless communication or the communication method.

  The electric circuit 14 has a function of controlling the microstructure 13 and a function of processing information from the reader / writer 17. Therefore, the electric circuit 14 includes a memory, a memory control circuit, an arithmetic circuit, and the like. 2 shows a configuration in which the electric circuit 14 includes a memory 121, a memory control circuit 122, an arithmetic circuit 123, a microstructure control circuit 124, an A / D conversion circuit 125, and a signal amplification circuit 126.

  The power supply circuit 11 has a diode and a capacitor, and can rectify an AC voltage generated in the antenna 12 to maintain a constant voltage, and supply the constant voltage to each circuit. The clock generation circuit 19 includes a filter and a frequency dividing circuit, can generate a clock having a necessary frequency based on the AC voltage generated in the antenna 12, and can supply the clock to each circuit. Here, the frequency of the clock generated by the clock generation circuit 19 is basically equal to or lower than the frequency of the electromagnetic wave used by the reader / writer 17 and the semiconductor device 101 for communication. The clock generation circuit 19 includes a ring oscillator, and can generate a clock having an arbitrary frequency by inputting a voltage from the power supply circuit 11.

  The demodulation circuit 113 includes a filter and an amplifier circuit, and can demodulate a signal included in the AC voltage generated in the antenna 12. The demodulation circuit 113 has a circuit having a different configuration depending on a modulation method used for wireless communication. The decoding circuit 116 decodes the signal demodulated by the demodulation circuit 113. This decoded signal is a signal transmitted from the reader / writer 17. The information determination circuit 118 includes a comparison circuit and the like, and can determine whether or not the decoded signal is a correct signal transmitted from the reader / writer 17. When it is determined that the information is correct, the information determination circuit 118 transmits a signal indicating correctness to each circuit such as the memory control circuit 122, the arithmetic circuit 123, and the microstructure control circuit 124, and the circuit that receives the signal. Can perform a predetermined operation.

  The encoding circuit 117 encodes data to be transmitted from the semiconductor device 101 to the reader / writer 17. The modulation circuit 114 modulates the encoded data and transmits it to the reader / writer 17 via the antenna 12.

Data to be transmitted to the reader / writer is data unique to the semiconductor device stored in the memory or data obtained by a function of the semiconductor device. Data unique to a semiconductor device is data such as individual identification information, and data obtained by a function of a semiconductor device is, for example, data obtained by a microstructure or some calculation based on them. Data, etc. Such data is stored in a memory included in the semiconductor device, for example, a nonvolatile memory.

  The memory 121 can include a volatile memory and a nonvolatile memory, and stores data unique to the semiconductor device 101 (individual identification information), information obtained from the microstructure 13, and the like. Although only one memory 121 is illustrated in FIG. 2, a plurality of memories may be provided depending on the type of information to be stored and the function of the semiconductor device 101. The memory control circuit 122 has a function of controlling the memory 121 when reading information stored in the memory 121 and writing information into the memory 121. Specifically, operations such as generation of a write signal, a read signal, a memory selection signal, and the like, and designation of an address can be performed.

  The microstructure control circuit 124 can generate a signal for controlling the microstructure 13. For example, when the microstructure 13 is controlled by a command from the reader / writer 17, a signal for controlling the microstructure 13 is generated based on the signal decoded by the decoding circuit 116. In addition, when data such as a program for controlling the operation of the microstructure 13 is stored in the memory 121, a signal for controlling the microstructure 13 is generated based on the data read from the memory 121. In addition, it may have a feedback function for generating a signal for controlling the microstructure 13 based on the data in the memory 121, the data from the reader / writer 17, and the data obtained from the microstructure 13. Is possible.

  For example, the arithmetic circuit 123 can process data obtained from the microstructure 13. It is also possible to perform information processing or the like when the microstructure control circuit 124 has a feedback function. The A / D conversion circuit 125 is a circuit that performs conversion between analog data and digital data. The A / D conversion circuit 125 transmits a control signal to the microstructure 13 or converts data from the microstructure 13 and transmits it to each circuit. be able to. The signal amplification circuit 126 can amplify a weak signal obtained from the microstructure 13 and transmit the amplified signal to the A / D conversion circuit 125.

  In FIG. 1, the electric circuit has the wireless communication circuit 15 and the processing circuit 16, but the detailed circuit described with reference to FIG. 2 clearly shows the wireless communication circuit 15 and the processing circuit 16. It may not be possible to distinguish. This is because, for example, the memory 121 can be provided in either or both of the wireless communication circuit 15 and the processing circuit 16. As a more specific example, the electric circuit 14 includes a non-rewritable nonvolatile memory for storing information unique to the semiconductor device, data for controlling the microstructure, and data obtained from the microstructure. It is possible to provide a non-rewritable nonvolatile memory as the wireless communication circuit 15 and a rewritable nonvolatile memory as the processing circuit 16.

  Therefore, the electric circuit 14 includes a wireless communication circuit 15 that is a circuit for performing wireless communication, and a processing circuit 16 that processes an instruction from the reader / writer 17 that controls the microstructure 13. Specific circuits for realizing these functions include the power supply circuit 11 and the memory 121 described with reference to FIG. Whether these circuits constitute the wireless communication circuit 15 or the processing circuit 16 may vary depending on the function of the semiconductor device 101 or the like.

Note that the semiconductor device 101 of the present invention is not limited to the specific configuration example described above. That is, the semiconductor device 101 receives a driving power supply from the semiconductor device 101 by wireless communication from the outside, and performs a wireless communication circuit 105 that performs wireless communication, a processing circuit 16 that has a semiconductor element and controls the microstructure 13, and a processing circuit It has the micro structure 13 controlled by 16, and is not limited to other structures. In addition, the semiconductor device 101 of the present invention includes an antenna and an electric circuit 14, and the electric circuit 14 can also be constituted by a semiconductor element 131 and a microstructure 32.

  Conventionally, when handling minute objects such as millimeters or less, first the structure of the minute object is expanded, and humans and computers obtain the information to determine the information processing and operation, and then reduce the operation And it needed a process of communicating to a minute object.

  However, the semiconductor device according to the present invention described above can handle a minute one only by a human or computer transmitting a high-level conceptual command. That is, when a human or a computer determines a purpose and transmits a command, the semiconductor device can take an action such as obtaining information on an object and performing information processing using a sensor or the like.

  In the present embodiment, the case where the object is a minute “thing” has been described. For example, the object itself has a size in meters, but a weak signal (for example, light) emitted from the object. And minute changes in pressure). The semiconductor device of the present invention includes a microstructure and an electric circuit, and can have a size of micrometer to millimeter. Therefore, when a semiconductor device is incorporated as a part of a mechanical device or handled by a general user, it may have a size in units of meters so that it can be easily handled and used at the time of assembly.

(Embodiment 2)
The microstructure included in the semiconductor device of the present invention differs in shape and configuration depending on the function of the semiconductor device. In this embodiment, the case where a microstructure functions as a sensor, an actuator, or a switch is described.

For example, the sensor can detect the concentration, pressure, flow rate, etc. of the object. As a typical example of a microstructure having a function as a sensor, a structural layer 402 is provided over a substrate as illustrated in FIG. 3A, and a space is provided between the substrate and the structural layer. The microstructure 401 provided can be given. When a force is applied from the outside to the microstructure having such a structure, the structural layer is deformed, and the capacitance held between the lower layer 403 and the structural layer changes. By detecting this change in capacitance, the applied force can be measured. The amount of change in capacitance can be obtained by measuring the potential of the lower layer. Further, a lower layer 403 having conductivity may be provided below the structural layer 402, and the lower layer 403 can be used as an electrode. When used as an electrode, a voltage can be applied to the lower layer 403 to control the movement of the structural layer 402.

  Next, the actuator will be described. An actuator replaces an electrical signal with motion (mechanical energy). A typical example is a gear driven by electrostatic force (electrostatic force) (see FIG. 3B). FIG. 3B shows a cross-sectional view of the gear. The actuator shown in FIG. 3B is provided with a rotating body 405 that rotates about a shaft 404 provided on a substrate 407. The rotating body 405 can be moved by a space provided below and on the side thereof. Polycrystalline silicon can be used for the rotating body and the shaft.

In order to make the rotating body easy to move, a low friction layer 406 may be provided on a surface close to the rotating body 405. The low friction layer 406 can be formed of diamond-like carbon (DLC).

In addition, a structure in which a comb-shaped structure layer is engaged and the distance between the layers is changed by an electrostatic force can be used (see FIG. 4A). FIG. 4A illustrates a structure in which the fixed electrode 408 and the movable electrode 409 are engaged with each other, and electrostatic attraction works between the electrodes by applying a voltage between the fixed electrode 408 and the movable electrode 409. The movable electrode 409 can move to the fixed electrode 408 side.

In addition, as a switch, a switch having a structure in which adhesion and separation of a conductive layer can be controlled using a control electrode, and conduction / non-conduction can be physically determined (see FIG. 4B). The switch illustrated in FIG. 4B includes a switch element 410 and a microstructure 415 provided over a substrate. The switch element 410 includes a control electrode 411, a space 418 obtained by removing the sacrificial layer 412, a structural layer 417, and a cantilever 414. The cantilever beam 414 can move because of the space 418. The microstructure 415 includes a lower electrode 416 and a space 413 obtained by removing the sacrificial layer. The microstructure 415 can function as a capacitor that holds electric charge between the lower electrode 416 and the structural layer 417, and can also function as a sensor or a switch when the structural layer 417 is movable. Such a microstructure 415 can be used as a memory element. Note that the structural layer 417 can be shared between the microstructure 415 and the switch element 410.

  By using a combination of such microstructures, semiconductor devices having various functions can be manufactured. For example, a specific substance can be detected by a sensor of a microstructure and the substance can be captured by an actuator, or the semiconductor device can be moved by an actuator until the sensor detects a specific object.

  The semiconductor device of the present invention having the above configuration can also be used for machine maintenance, for example. A semiconductor device includes a sensor and a self-propelled actuator with a microstructure, moves while detecting whether there is a defective portion inside the machine, processes information obtained from the sensor by a processing circuit, and has a defective portion. When information determined to be obtained is obtained, communication with the outside can be performed using a wireless communication circuit. Furthermore, the defective portion can be repaired by joint work of a plurality of semiconductor devices.

Note that this embodiment can be freely combined with the above embodiment.

(Embodiment 3)
In this embodiment, the case where a microstructure is used for a wireless communication circuit is described.

In order to perform wireless communication, the wireless communication circuit includes passive elements such as inductors and capacitors, and active elements such as switches, in addition to semiconductor elements typified by transistors. Although these elements can be manufactured using a technique for manufacturing a semiconductor element, there is a problem. For example, a transistor used as a switching element has such drawbacks that the difference in input voltage between when the switch is on and when it is off cannot be increased, or that the reaction speed cannot be increased.

However, it is considered that the above-described defects can be improved by manufacturing these elements using a microstructure. For example, a switch made of a microstructure can completely insulate a signal transmission path when turned off. In addition, the control electrode of the switch and the signal transmission path can be completely insulated. Furthermore, there is an advantage that the reaction speed is increased by the scaling law. Therefore, the semiconductor device 101 of the present invention can have the microstructure 32 in the electric circuit 14.

Note that this embodiment can be freely combined with the above embodiment.

(Embodiment 4)
In this embodiment mode, a method for manufacturing a semiconductor device of the present invention will be described. The semiconductor device of the present invention includes a microstructure and a semiconductor element over an insulating surface. Here, a method for manufacturing the microstructure and the semiconductor element over the same substrate is described with reference to drawings. In the drawings, a top view is shown on the upper side, and a sectional view in the top view OP or QR is shown on the lower side. Furthermore, a wireless communication circuit can be formed using a semiconductor element formed over an insulating surface.

  The microstructure and the semiconductor element included in the semiconductor device of the present invention can be manufactured over a substrate having an insulating surface. Here, the substrate having an insulating surface is a glass substrate, a quartz substrate, a plastic substrate, or the like. Furthermore, it is also possible to use a conductive substrate such as a metal element or a substrate in which a layer is formed using an insulating material on a semiconductor substrate such as silicon. By forming the microstructure and the semiconductor element over a plastic substrate, a highly flexible, lightweight, and thin semiconductor device can be manufactured. In addition, a light and thin semiconductor device can be formed by manufacturing a semiconductor device over a glass substrate and then thinning the substrate by polishing the substrate from the back surface.

  First, the base layer 202 is formed over the substrate 201 having an insulating surface (see FIG. 5A). The base layer 202 can be formed with a single layer or a stacked structure using an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the case where a two-layer structure is used as the base layer 202 is described.

As the first layer of the base layer 202, a silicon oxynitride layer having a thickness of 10 nm to 200 nm (preferably 50 nm to 100 nm) is formed. The silicon oxynitride layer can be formed using SiH ₄ , NH ₃ , N ₂ O, and H ₂ as a reactive gas by a plasma CVD method. Next, a silicon oxynitride layer with a thickness of 50 nm to 200 nm (preferably 100 nm to 150 nm) is formed as the second layer of the base layer 202. The silicon oxynitride layer can be formed using SiH ₄ and N ₂ O as a reaction gas by a plasma CVD method.

  Next, a sacrificial layer (corresponding to a first sacrificial layer) 203 for forming a microstructure is formed over the base layer 202 and patterned into an arbitrary shape (see FIG. 5A). Such a sacrificial layer is provided in order to form a space included in the microstructure. That is, the space included in the microstructure is formed by removing the sacrificial layer by etching or the like. Since the space is formed below or above the structural layer, it can also be described as a space in contact with the structural layer. The first sacrificial layer 203 can be formed using a sputtering method, a CVD method, or the like using a metal element or a compound such as silicon, such as tungsten or silicon nitride. Patterning can be performed by forming a resist mask using photolithography and performing anisotropic dry etching.

  The thickness of the first sacrificial layer 203 should be determined in consideration of various factors such as the material of the first sacrificial layer 203, the structure and operation method of the microstructure, the sacrificial layer etching method, and the etchant. Can do. For example, if the first sacrificial layer 203 is too thin, the etchant does not diffuse and the first sacrificial layer 203 is not etched, or the structural layer buckles (the microstructure is attached to the substrate) after etching. A phenomenon occurs. On the other hand, if the sacrificial layer is too thick, when the microstructure is operated with an electrostatic force, the space formed after removing the sacrificial layer is too large, and the microstructure cannot be driven with the electrostatic force. Considering these factors, for example, in the case of forming a microstructure that is driven by an electrostatic force between the conductive layer and the structural layer formed under the first sacrificial layer 203, the first sacrificial layer 203 is It has a thickness of 0.5 μm or more and 3 μm or less, preferably 1 μm or more and 2 μm or less.

  Further, when a material that easily peels off from the base layer 202 due to a large internal stress, poor adhesion, or the like is used as the first sacrificial layer 203, a thick layer cannot be formed at a time. In the case where the first sacrificial layer 203 is formed using such a material, the first sacrificial layer 203 can be formed thick by repeating film formation and patterning.

  Next, a semiconductor layer 204 that forms a semiconductor element and a silicon layer that forms a structure layer 205 that forms a microstructure are formed, and processed into an arbitrary shape, that is, patterned (see FIG. 5B). The silicon layer (the semiconductor layer 204 and the structural layer 205 are collectively referred to as a silicon layer) is formed using a silicon-containing material and includes a crystalline silicon layer, an amorphous silicon layer, or a microcrystalline state. It can be formed with a silicon layer or the like. In this embodiment, a silicon layer having an amorphous state is formed, a metal element is added to the silicon layer, and a silicon layer having a crystal state crystallized by heat treatment or laser irradiation is formed.

  Crystallization of the silicon layer includes heat treatment that is heated by light emitted from a heating furnace or a lamp, laser irradiation, and the like, and can be crystallized using any one or both of them. In the case where a heating furnace is used as the heat treatment, the silicon layer having an amorphous state is heated at 400 to 550 ° C. for 2 to 20 hours. At this time, the temperature may be set in multiple stages in the range of 400 to 550 ° C. so that the temperature gradually increases. In the first low-temperature heating process at about 400 ° C., hydrogen or the like contained in the silicon layer having an amorphous state is generated, so that it is possible to reduce the roughness of the layer surface during crystallization.

Laser irradiation can be performed using a continuous wave laser beam (CW laser beam) or a pulsed laser beam (pulse laser beam). As the laser beam, Ar laser, Kr laser, excimer laser, YAG laser, Y ₂ O ₃ laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser, copper vapor A laser or a gold vapor laser oscillated from one or a plurality of types can be used. By irradiating the fundamental wave of such a laser beam and the second to fourth harmonics of the fundamental wave, a silicon layer having a crystal with a large grain size can be obtained. For example, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) can be used. Energy density of the laser is about 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 10 to 2000 cm / sec.

  The continuous wave fundamental laser beam and the continuous wave harmonic laser beam may be irradiated, or the continuous wave fundamental laser beam and the pulsed harmonic laser beam may be irradiated. You may make it do. By irradiating a plurality of laser beams, a wide energy range can be compensated. Also, it is a pulse oscillation type laser beam that oscillates at an oscillation frequency that allows irradiation of the next pulse of laser light after the amorphous silicon layer is melted by the laser light and solidifies. It is also possible to use a laser beam. By oscillating the laser beam at such a frequency, a silicon layer having crystal grains continuously grown in the scanning direction can be obtained. The oscillation frequency of such a laser beam is 10 MHz or more, which is significantly higher than a frequency band of several tens to several hundreds Hz that is normally used.

  In the thermal crystallization or laser crystallization process, a metal element that promotes crystallization of the silicon layer, such as nickel, is added. For example, a crystallization process can be performed by applying a solution containing nickel on a silicon layer having an amorphous state. By performing thermal crystallization using a metal element in this manner, the heating temperature for performing crystallization can be reduced, and a silicon layer having continuous crystal grain boundaries can be obtained. Here, as a metal element for promoting crystallization, Fe, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au, or the like can be used in addition to nickel.

  Further, since the metal element that promotes crystallization becomes a contamination source of the semiconductor device, it is desirable to perform a gettering step for removing the metal element after the silicon layer is crystallized. In the gettering step, after the silicon layer is crystallized, a layer serving as a gettering sink is formed on the silicon layer, and the metal element is moved to the gettering sink by heating. As the gettering sink, a polycrystalline semiconductor layer or a semiconductor layer to which an impurity is added can be used. For example, a polycrystalline semiconductor layer to which an inert element such as argon is added on a silicon layer can be formed and used as a gettering sink. By adding an inert element, the polycrystalline semiconductor layer can be distorted and the metal element can be captured more efficiently. A metal element can also be captured by forming a semiconductor layer to which an element such as phosphorus is added.

  Silicon layers manufactured through the gettering step can be used as the semiconductor layer 204 and the structural layer 205. In the case where the structure layer 205 needs to have conductivity, an impurity element such as phosphorus, arsenic, or boron can be added to the structure layer 205 in the same step as the impurity region of the semiconductor layer 204. In the case of manufacturing a microstructure which is controlled by an electrostatic force, the structural layer 205 is preferably conductive.

  The thickness of the structural layer 205 can be determined in consideration of various factors such as the thickness of the first sacrificial layer 203, the material of the structural layer 205, the structure of the microstructure, or the sacrificial layer etching method. . For example, when a substance having a large internal stress distribution difference is used as the material of the structural layer 205, the structural layer 205 is warped. However, a microstructure can be formed by using the warp of the structural layer 205. In addition, when the structural layer 205 is formed thick, the internal stress is distributed, which may cause warpage or buckling. On the other hand, if the structural layer 205 is thin, there is a risk that the microstructure will buckle due to the surface tension of the solution or the like used during the sacrifice layer etching. Therefore, in the case where the structural layer 205 is formed using the silicon layer having a crystal state of this embodiment mode, the film thickness is preferably greater than or equal to 0.5 μm and less than or equal to 10 μm, for example.

  In the case where the silicon layer included in the structural layer 205 is formed thick, the silicon layer can be formed at a time, but a thick layer can be formed by stacking the silicon layers. At this time, the silicon layer is formed by stacking a layer having polycrystalline silicon crystallized using the above process (hereinafter referred to as a layer having polycrystalline silicon) and a layer having amorphous silicon. You can also Furthermore, a silicon layer containing a metal element that promotes crystallization can be used. The silicon layer containing a metal element that promotes crystallization forms a so-called silicide. Thus, a silicide using a metal element that promotes crystallization may be used, or a silicide using a metal element different from the metal element may be used.

  Polycrystalline silicon has high toughness, and it is difficult for cracks to occur in the material, and further, the generated cracks are difficult to propagate. Furthermore, as shown in the above process, a layer having polycrystalline silicon crystallized using a metal element that promotes crystallization is crystallized without using a metal element because crystal grain boundaries are continuous. Higher toughness than a layer having polycrystalline silicon. Amorphous silicon has low toughness, but has high strength and is difficult to cause plastic deformation. Further, amorphous silicon has an advantage that it can be easily formed by a CVD method or a sputtering method. Silicide has high strength and conductivity. By forming a structural layer by selectively using silicon layers having different characteristics, a microstructure corresponding to the structure and function can be manufactured.

  Next, a first insulating layer 206 is formed over the semiconductor layer 204 and the structural layer 205 (see FIG. 5B). The first insulating layer 206 can be formed by a plasma CVD method, a sputtering method, or the like using an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, like the base layer 202. In this embodiment, a silicon oxynitride layer (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) is formed with a thickness of 50 nm by a plasma CVD method. Needless to say, the first insulating layer 206 is not limited to the silicon oxynitride film, and other insulating layers may be used as a single layer or a stacked structure.

  Alternatively, a metal element oxide having a high dielectric constant, such as hafnium (Hf) oxide, can be used as a material for the first insulating layer 206. By forming the first insulating layer 206 using such a high dielectric constant material, the semiconductor element can be driven at a low voltage, and a semiconductor device with low power consumption can be provided.

The first insulating layer 206 can also be formed by high-density plasma treatment. The high-density plasma treatment means that the plasma density is 1 × 10 ¹¹ cm ⁻³ or more, preferably 1 × 10 ¹¹ cm ⁻³ to 9 × 10 ¹⁵ cm ⁻³ , such as a microwave (for example, a frequency of 2.45 GHz). This is plasma processing using high frequency. When plasma is generated under such conditions, the low electron temperature is changed from 0.2 eV to 2 eV. As described above, high-density plasma characterized by a low electron temperature has low kinetic energy of active species, so that a film with less plasma damage and fewer defects can be formed.

  A substrate on which the semiconductor layer 204 and the structural layer 205 are formed is placed in a film formation chamber that enables such plasma treatment, and a distance between an electrode for plasma generation, a so-called antenna and an object to be formed is 20 mm to 80 mm, Preferably, the film forming process is performed from 20 mm to 60 mm. Such high-density plasma treatment can realize a low-temperature process (substrate temperature of 400 ° C. or lower). Therefore, glass or plastic with low heat resistance can be used as the substrate 201.

  The film formation atmosphere of such an insulating layer can be a nitrogen atmosphere or an oxygen atmosphere. The nitrogen atmosphere is typically a mixed atmosphere of nitrogen and a rare gas, or a mixed atmosphere of nitrogen, hydrogen, and a rare gas. As the rare gas, at least one of helium, neon, argon, krypton, and xenon can be used. The oxygen atmosphere is typically a mixed atmosphere of oxygen and a rare gas, a mixed atmosphere of oxygen, hydrogen, and a rare gas, or a mixed atmosphere of dinitrogen monoxide and a rare gas. As the rare gas, at least one of helium, neon, argon, krypton, and xenon can be used.

  By using such a process, damage to other films can be reduced and a dense insulating layer can be formed. In addition, an insulating layer formed by high-density plasma treatment can improve an interface state with a layer in contact with the insulating layer. That is, the interface state between the first insulating layer 206, the semiconductor layer 204, and the structural layer 205 can be improved by using high-density plasma treatment. As a result, the electrical characteristics of the semiconductor element can be improved. Further, a microstructure including the structural layer 205 with high strength can be manufactured.

  Although the case where high-density plasma treatment is used for forming the first insulating layer 206 has been described here, for example, the semiconductor layer 204 and the structural layer 205 may be subjected to high-density plasma treatment. The surface of the semiconductor layer 204 and the structural layer 205 can be modified by high-density plasma treatment. As a result, the electrical characteristics of the semiconductor element and the microstructure can be improved. Further, the high-density plasma treatment can be used not only when the first insulating layer 206 is formed but also when the base layer 202 and other insulating layers are formed.

  Next, a gate electrode 207 which forms a semiconductor element and a first conductive layer which is a second sacrificial layer 208 for forming a microstructure are formed over the first insulating layer 206 and formed into an arbitrary shape. Patterning is performed (see FIG. 5C). The first conductive layer (the gate electrode 207 and the second sacrificial layer 208 are collectively referred to as a first conductive layer) is formed using a conductive metal element or metal element compound such as tungsten, as a sputtering method, It can be formed using a CVD method or the like.

  The first conductive layer becomes the gate electrode 207 of the semiconductor element. Therefore, in consideration of conductivity, workability, and the like, the first conductive layer can be stacked using a plurality of conductive materials. FIG. 5C illustrates an example in which a single-layer first conductive layer is formed.

  In addition, the first conductive layer serves as a second sacrificial layer 208 for forming a microstructure. In the case where the second sacrificial layer 208 is etched at the same time as the first sacrificial layer 203, it is desirable to form the second sacrificial layer 208 using the same material as the first sacrificial layer 203. However, the present invention is not limited to these materials, and the first sacrificial layer 203 and the second sacrificial layer 208 may be manufactured using the same material or different materials.

For patterning the gate electrode 207 and the second sacrificial layer 208, a resist mask is formed by photolithography, and anisotropic dry etching is performed. As an example of dry etching, an ICP (Inductively Coupled Plasma) etching method can be used. As an etching gas, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl ₄ or CCl ₄ , a fluorine-based gas typified by CF ₄ , SF ₆ or NF _3, or O ₂ is appropriately used. it can. In addition, when the first conductive layer is formed using a plurality of conductive materials, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate 201 side, the amount of power applied to the substrate 201 side) The first conductive layer can be etched by appropriately adjusting the electrode temperature or the like.

Next, an impurity element is added to the semiconductor layer 204 included in the semiconductor element to form an N-type impurity region 112 and a P-type impurity region 111. Such an impurity region can be selectively formed by forming a resist mask by a photolithography method and adding an impurity element. The impurity element can be added by an ion doping method or an ion implantation method. Typically, phosphorus (P) or arsenic (As) is used as the impurity element imparting N-type, and boron (B) can be used as the impurity element imparting P-type. An impurity element imparting N-type is preferably added to the N-type impurity region 112 and the P-type impurity region 111 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ .

  Next, an insulating layer made of a nitrogen compound such as silicon nitride or an oxide such as silicon oxide is formed by a plasma CVD method or the like, and the insulating layer is subjected to anisotropic etching in the vertical direction so that the side surface of the gate electrode 207 is formed. An insulating layer (hereinafter referred to as a sidewall) 209 that is in contact is formed (see FIG. 7A). Next, an impurity element is added to the semiconductor layer 204 having the N-type impurity region 112 to form a high-concentration N-type impurity region 210 having an impurity concentration higher than that of the N-type impurity region 112 provided below the sidewall 209. . By providing a difference in impurity concentration using the side wall 209 in this manner, a short channel effect that occurs as the gate length of the semiconductor element is shortened can be prevented.

  In the case where the gate electrode 207 is formed by stacking different conductive materials to have a tapered shape, the sidewall 209 is not necessarily formed. This is because the N-type impurity region 112 and the high-concentration N-type impurity region 210 can be formed by adding the impurity element once.

  After the impurity region is formed, heat treatment, infrared light irradiation, or laser light irradiation is performed to activate the impurity element. Simultaneously with activation, plasma damage to the first insulating layer 206 and plasma damage to the interface between the first insulating layer 206 and the semiconductor layer 204 can be recovered. In particular, when the impurity element is activated from the front surface or the back surface using an excimer laser in an atmosphere of room temperature to 300 ° C., effective activation can be performed. Alternatively, the YAG laser may be activated by irradiation with the second harmonic, and the YAG laser is a preferable activation means because it requires less maintenance.

  In addition, after a passivation film made of an insulating layer such as a silicon oxynitride film or silicon oxide is formed so as to cover the conductive layer or the semiconductor layer 204 to be the gate electrode 207, heat treatment, infrared light irradiation, or laser light irradiation is performed. It is also possible to perform hydrogenation by irradiation. For example, a silicon oxynitride film is formed to a thickness of 100 nm using a plasma CVD method, and then heated at 300 to 550 ° C. for 1 to 12 hours using a clean oven to hydrogenate the semiconductor layer. Can do. For example, a clean oven is used and heated in a nitrogen atmosphere at 410 ° C. for 1 hour. In this step, dangling bonds in the semiconductor layer 204 generated by the addition of the impurity element can be terminated by hydrogen contained in the passivation film. At the same time, the activation process of the impurity region can be performed.

Through the above steps, an N-type semiconductor element 213 and a P-type semiconductor element 214 are formed (see FIG. 7A). At this time, the structure layer 205 included in the microstructure may have an impurity region formed in a region not covered with the second sacrificial layer 208.

  Subsequently, an insulating layer 215 is formed so as to cover the whole (see FIG. 7B). The insulating layer 215 can be formed using an insulating inorganic material, an organic material, or the like. As the inorganic material, silicon oxide or silicon nitride can be used. As the organic material, polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, siloxane, or polysilazane can be used. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Polysilazane is formed using a polymer material having a bond of silicon (Si) and nitrogen (N) as a starting material.

  Next, the insulating layer 215 and the first insulating layer 206 are sequentially etched to form a first contact hole 216 (see a top view in FIG. 7B). As the etching process, a dry etching process or a wet etching process can be applied. In this embodiment mode, the first contact hole 216 is formed by dry etching.

  Next, a second conductive layer is formed over the insulating layer 215 and in the first contact hole 216, and patterned into an arbitrary shape, so that the source electrode, the drain electrode, and the wiring 217 constituting the electric circuit are formed. (See the cross-sectional view in FIG. 7B). As the wiring 217, a film made of an element of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), or silicon (Si) or an alloy film using these elements can be used.

  Next, the insulating layer 215 and the first insulating layer 206 are sequentially etched to form a second contact hole 218, thereby exposing the first sacrificial layer 203 and the second sacrificial layer 208 (FIG. 8). (See (A)). Note that FIG. 8A illustrates only a microstructure.

  As the etching process, a dry etching process or a wet etching process can be applied. In this embodiment mode, the second contact hole 218 is formed by dry etching. The second contact hole 218 is opened to etch away the first sacrificial layer 203 and the second sacrificial layer 208. Accordingly, the diameter is determined so that the etchant flows. For example, the diameter of the second contact hole 218 is preferably 2 μm or more.

  The second contact hole 218 can also be formed as a contact hole having a large diameter so that the first sacrificial layer 203 and the second sacrificial layer 208 can be easily etched. In other words, it is not necessary to form a small hole as shown in FIG. 8A, and the first sacrificial layer is exposed so that a portion where the insulating layer 215 is necessary (for example, an insulating layer on a semiconductor element) is left exposed. Two contact holes 218 may be formed.

  Next, the first sacrificial layer 203 and the second sacrificial layer 208 are removed by etching (see FIGS. 8B and 8C). For the etching, the sacrificial layer can be etched through the second contact hole 218 by using a wet etchant suitable for the material of the sacrificial layer or by dry etching. In the etching step, it is necessary to select an appropriate combination of the material of the structural layer 205, the material of the first sacrificial layer 203, the material of the second sacrificial layer 208, and the etchant that removes the sacrificial layer. For example, when a specific etching agent is determined, the first sacrificial layer 203 and the second sacrificial layer 208 may be formed using a material having a higher etching rate than the material of the structural layer 205.

For example, when the sacrificial layer is tungsten (W), etching can be performed by immersing in a solution in which 28% ammonia and 31% hydrogen peroxide solution are mixed at a ratio of 1: 2 for about 20 minutes. When the sacrificial layer is silicon dioxide, buffered hydrofluoric acid in which ammonium fluoride is mixed at a ratio of 7 to the 49% aqueous solution 1 of hydrofluoric acid can be used. When the sacrificial layer is silicon, hydroxide of alkali metal elements such as phosphoric acid, KOH, NaOH, CsOH, NH ₄ OH, hydrazine, EPD (a mixture of ethylenediamine, pyrocatechol, water), TMAH, IPA, NMD3 solution Etc. can be used. When drying after wet etching, to prevent buckling of the microstructure due to capillary action, rinse with a low-viscosity organic solvent (for example, cyclohexane), or dry under low temperature and low pressure conditions, or both This is done by a combination of Furthermore, it is also effective to perform freeze-drying.

In addition, in order to prevent buckling of the microstructure due to capillary action, plasma treatment for imparting water repellency to the surface of the microstructure can be performed. The sacrificial layer can be dry-etched using F ₂ or XeF ₂ under high pressure conditions such as atmospheric pressure. Here, if the first sacrificial layer 203 and the second sacrificial layer 208 are formed of different materials and cannot be etched with the same etchant, the sacrificial layer needs to be etched twice. In this case, it is necessary to sufficiently consider a selection ratio with a layer (for example, the structural layer 205 or the insulating layer 215) that is not removed but is in contact with the etching agent.

  By using such a process, the first sacrificial layer 203 is removed to form the first space 219, and the second sacrificial layer 208 is removed by etching to form the second space 220. The body 221 can be manufactured (see FIGS. 8B and 8C). Here, the microstructure 221 includes a first space 219 provided between the insulating substrate 201 and the structural layer 205. A second space 220 is provided between the structural layer 205 and the insulating layer 215 formed thereon. The structure layer 205 of the microstructure 221 can be moved by having such a structure.

  When crystallization is performed by laser crystallization or a combination of nickel and laser as in the above-described process, the crystallization can be performed at a lower temperature than crystallization by heat alone, so that the range of materials that can be used in the process is widened. For example, in the case where the semiconductor layer is crystallized only by heating, it is necessary to perform heating for about 1 hour at a temperature of about 1000 ° C., and a glass substrate that is weak against heat or a metal element having a melting point of 1000 ° C. or less cannot be used. . However, by using the above process, a glass substrate or the like having a distortion point of 593 ° C. can be used.

  In addition, compared with a semiconductor layer only formed by thermal crystallization, the semiconductor layer manufactured by the above process has continuous crystal grain boundaries, so that the covalent bond is not interrupted. Therefore, the stress concentration caused by the unpaired bond between the grain boundaries does not occur, and as a result, the fracture stress becomes higher than that of general polysilicon.

  Amorphous silicon has low toughness, but hardly undergoes plastic deformation. That is, it can be said that it is a hard but brittle substance like glass. In the present invention, since laser crystallization is performed, amorphous silicon and polycrystalline silicon can be separately formed depending on the portion of the substrate 201. By doing so, a microstructure in which polycrystalline silicon having continuous grain boundaries excellent in toughness and amorphous silicon which hardly causes plastic deformation can be manufactured.

  Amorphous silicon generally has internal residual stress after film formation. For this reason, it is difficult to form a thick film. In the polycrystalline silicon produced by the above process, the internal stress is relaxed and the film can be formed at a further low temperature process. Therefore, a semiconductor layer having an arbitrary thickness can be obtained by repeating the film formation and crystallization. It is also possible to pattern other materials on the semiconductor layer and further form a semiconductor layer thereon.

  Further, it is known that a silicon alloy such as nickel silicide is generally high in strength. By selectively leaving nickel in the semiconductor layer and applying an appropriate heat treatment, a microstructure that is harder and has higher conductivity can be manufactured. Therefore, the thickness of the structural layer 205 can be reduced, and a microstructure with high operating speed and excellent reactivity can be provided.

  In addition, according to the present invention, a microstructure and a semiconductor element are manufactured over the same substrate, so that a semiconductor device that does not require assembly or a package and does not require manufacturing costs can be provided.

  Note that this embodiment mode can be freely combined with the above embodiment modes.

(Embodiment 5)
In the case where the microstructure is moved by an electrostatic force, a lower layer 222 having conductivity may be formed below the base layer 202. Therefore, in this embodiment mode, a structure in which a lower layer made of a conductive material is provided below a base layer will be described.

  First, a conductive lower layer 222 is formed between the substrate 201 and the base layer 202 (see FIG. 9A). The lower layer 222 can be used as a common electrode, a control electrode, or the like. The lower layer 222 is formed by a CVD method or the like using a metal element such as tungsten or a conductive material as a material. Moreover, you may pattern into arbitrary shapes as needed. Further, when the base layer 202 has a stacked structure, the lower layer 222 can be formed between the base layers 202.

  In the above process, the semiconductor layer 204 and the semiconductor layer to be the structural layer 205 are formed over the first sacrificial layer 203, but an insulating layer is formed over the first sacrificial layer 203, Thereafter, a semiconductor layer can be formed. By using such a process, when the first sacrifice layer 203 is removed, the structural layer 205 can be protected by the insulating layer, and damage to the structural layer 205 can be reduced.

The lower layer thus provided can be used as a common electrode or a control electrode when the microstructure is moved by an electrostatic force.

The first sacrificial layer 203 and the second sacrificial layer 208 can be formed into a tapered shape 225 when viewed from a cross section (see FIG. 9A). Further, the structural layer 205 can also be formed into a tapered shape 225 when viewed from a cross section (see the cross-sectional view in FIG. 9A). As described above, since the sacrificial layer has a tapered cross section, it is possible to reduce generation of dust and adhesion of dust in an etching process, a cleaning process, and the like.

Further, the first sacrificial layer 203 and the second sacrificial layer 208 can be formed to have a shape 223 with rounded corners when viewed from above (see FIG. 9B). Further, the structural layer 205 can also be formed to have a shape 223 with rounded corners when viewed from above (see the top view in FIG. 9B). As described above, since the corners of the pattern of the sacrificial layer are rounded, generation of dust and adhesion of dust in the etching process, the cleaning process, and the like can be reduced.

  The first sacrificial layer 203, the second sacrificial layer 208, and the structural layer 205 are thicker than layers formed for manufacturing a semiconductor element. For example, the sacrificial layer and the structural layer have a thickness of about 1 μm, compared to the semiconductor layer 204 often having a thickness of about 60 nm. If these thick layers have a pattern having a right angle or an acute angle, or if the cross section of the layer is cut at a right angle to the substrate, the corner portion is peeled off, which causes dust that contaminates the semiconductor device. In addition, in the case of having a C-shaped or U-shaped (box-shaped) pattern, dust is trapped in the corner portion, and it is not possible to reduce dust even in the cleaning process. Therefore, it is desirable that the sacrificial layer and the structural layer have shapes 223 and 224 with rounded corners when viewed from above, and have shapes 225 and 226 having a tapered cross section.

  Note that the tapered shape and the rounded shape are not limited to the sacrificial layer and the structural layer constituting the microstructure. When a thick layer is formed, the corners are similarly viewed from the top. Preferably, the cross section has a rounded shape and the cross section has a tapered shape. For example, it is desirable that the gate electrode 207 and the wiring 217 having a relatively large thickness have shapes 227 and 228 with rounded corners when viewed from above, and have a tapered shape in cross section. As a result, generation of dust can be suppressed and yield can be improved.

  Note that this embodiment mode can be freely combined with the above embodiment modes.

(Embodiment 6)
In the microstructure included in the semiconductor device of the present invention, the structural layer may be a single layer or a stacked layer. In this embodiment mode, a structural layer having a stacked structure will be described.

FIG. 6A illustrates a case where silicon layers having different states are stacked in the silicon layer included in the structural layer 205. The first silicon layer 252, the second silicon layer 253, and the third silicon layer 254 are stacked on the first sacrificial layer 203 formed by the above-described process, thereby forming the structural layer 205. Can be configured. The first silicon layer 252, the second silicon layer 253, and the third silicon layer 254 include a layer including polycrystalline silicon, a layer including amorphous silicon, and a layer including silicide. , Can be arbitrarily laminated.

  For example, as the structural layer 205, a layer having amorphous silicon is formed in the first silicon layer 252, a layer having silicide is formed in the second silicon layer 253, and a third silicon layer is formed. A layer having polycrystalline silicon is formed at 254. In order to form such a structural layer 205, a layer containing amorphous silicon is formed as the first silicon layer 252 over the first sacrificial layer 203. Subsequently, in order to form the second silicon layer 253, a layer having amorphous silicon is formed, and a metal element for promoting crystallization is applied and crystallized by laser irradiation or the like. Then, in order to form the third silicon layer 254, a layer having amorphous silicon is formed, and a metal element that promotes crystallization is applied and crystallized by laser irradiation or the like. It can be formed by removing it by a gettering process.

  In this manner, the structural layer 205 having conductivity, high strength, and low damage is formed by stacking the layer having amorphous silicon, the layer having silicide, and the layer having polycrystalline silicon. Can do.

  Similarly, a layer having polycrystalline silicon is formed in the first silicon layer 252 and the third silicon layer 254, and a layer having amorphous silicon is formed in the second silicon layer 253. It is also possible to form. As described above, the structure layer 205 having both flexibility and hardness can be formed by sandwiching amorphous silicon that hardly causes plastic deformation between polycrystalline silicon having high toughness. In addition, by forming a layer including silicide in the second silicon layer 253, the structural layer 205 having both flexibility and hardness and conductivity can be formed. Here, the combination of stacks is not limited to the above example, and a layer having amorphous silicon, a layer having silicide, and a layer having polycrystalline silicon can be arbitrarily selected and stacked.

  6A illustrates an example in which the structural layer 205 includes three silicon layers, the present invention is not limited to three layers. For example, as shown in FIG. 6B, the silicon layer included in the structural layer 205 can be two layers. That is, the structural layer 205 can have a single-layer structure or a stacked structure including two or more layers.

  The structural layer 205 shown in FIG. 6B is formed by stacking a first silicon layer 255 and a second silicon layer 256 over the first sacrificial layer 203. As in FIG. 6A, the first silicon layer 255 and the second silicon layer 256 are a layer including polycrystalline silicon, a layer including amorphous silicon, and a layer including silicide. It can be arbitrarily laminated.

As described above, in the case where the thickness is required to obtain the strength of the structural layer 205, the layer having the necessary characteristics can be formed to be thicker by being laminated as described above. For example, even if the internal stress distribution difference is large and the layer cannot be formed thick at once, the stress can be relieved by repeatedly performing film formation and patterning.

  In addition, it is considered that the characteristics required for each layer are greatly different between the semiconductor layer 204 included in the semiconductor element and the structural layer 205 included in the microstructure. Further, the required characteristics of the structural layer 205 vary depending on the structure and use of the microstructure. Therefore, as illustrated in FIG. 6C, the semiconductor layer 204 and the structural layer 205 can be formed using silicon layers in different states.

  For example, the semiconductor layer 204 can be formed using a layer including polycrystalline silicon, and the structural layer 205 can be formed using a layer including amorphous silicon. In order to create a silicon layer in this way, amorphous silicon is formed on a substrate, a metal element that promotes crystallization is applied only to a region where a layer having polycrystalline silicon is to be formed, and a laser is applied only to the applied region. A layer having polycrystalline silicon can be selectively formed by crystallization by irradiation or the like.

  In this manner, by forming the semiconductor layer 204 with a layer containing polycrystalline silicon, a semiconductor element with high mobility and excellent element characteristics can be manufactured. Since the layer having polycrystalline silicon is crystallized using a metal element that promotes crystallization, the crystal grain boundary is continuous, and moves more than the layer having polycrystalline silicon crystallized without using a metal element. It is possible to manufacture a semiconductor device having a higher degree and superior characteristics. In addition, when the structural layer 205 is formed using a layer containing amorphous silicon, a microstructure with high strength can be manufactured in order to maintain the structure.

  In the stacked structure described with reference to FIGS. 6A and 6B, different silicon layers can be used for the semiconductor layer 204 and the structural layer 205. At this time, the stacked structure of the semiconductor layer 204 and the structural layer 205 may be the same or different.

  For example, the semiconductor layer 204 and the structural layer 205 can be formed by stacking a layer including amorphous silicon and a layer including polycrystalline silicon. The semiconductor layer 204 is formed by stacking a layer having amorphous silicon and a layer having polycrystalline silicon, and the structural layer 205 is formed by stacking a layer having amorphous silicon and a layer having silicide. can do. In order to manufacture the stacked structure of the semiconductor layer and the structural layer in such a manner, an amorphous silicon layer is first formed. Then, polycrystalline silicon and amorphous silicon for forming silicide are formed, a metal element that promotes crystallization is applied and crystallized by laser irradiation or the like, and only the metal element is formed into the semiconductor layer 204. Can be formed by removing the layer by a gettering process.

  In this manner, by forming the semiconductor layer 204 and the structural layer 205 by stacking silicon layers, the thick structural layer 205 can be formed using an easy process. Further, by forming the semiconductor layer 204 from a layer containing polycrystalline silicon, there is an advantage that the thick structural layer 205 can be formed without deteriorating semiconductor element characteristics.

  Furthermore, only one of the semiconductor layer 204 and the structural layer 205 can have a stacked structure. For example, the semiconductor layer 204 is formed of a layer having polycrystalline silicon with high mobility in order to improve semiconductor element characteristics, and the structural layer 205 is a layer having amorphous silicon in order to obtain strength suitable for the structure. A layer having silicide and a layer having polycrystalline silicon can be arbitrarily stacked and formed. Conversely, the semiconductor layer 204 can have a stacked structure, and the structural layer 205 can have a single-layer structure.

  Here, the stacked structure forming the semiconductor layer 204 and the structural layer 205 is not limited to the above example, and can be performed in any combination. In this manner, by forming the structure layer 205 and the semiconductor layer 204 in a stacked structure having different structures, a layer having characteristics suitable for forming a semiconductor element and a microstructure can be obtained.

  In addition, as shown in FIG. 6D, the silicon layer included in the structural layer 205 can be partially formed. FIG. 6D illustrates a structural layer 205 in which a first portion 257 of the structural layer and a second portion 258 of the structural layer are separately formed. The first portion 257 of the structural layer and the second portion 258 of the structural layer are formed by arbitrarily forming a layer having polycrystalline silicon, a layer having amorphous silicon, and a layer having silicide. Can do.

  For example, the first portion 257 of the structural layer can form an amorphous silicon layer, and the second portion 258 of the structural layer can form a layer having polycrystalline silicon. In order to create a silicon layer partially in this way, amorphous silicon is formed on the substrate, and a metal element that promotes crystallization is applied only to a portion where a layer having polycrystalline silicon is to be formed and applied. Only a portion can be crystallized by laser irradiation or the like. In the case where a portion to be formed becomes fine, a resist mask can be formed over amorphous silicon by using a photolithography method or the like, and partial crystallization can be performed. In addition, by changing the laser conditions for irradiating amorphous silicon (for example, reducing the irradiation intensity), only a part (for example, a column portion of a beam structure) is not crystallized, and amorphous silicon is left. It is also possible to crystallize this part.

  By forming the silicon layer partially in this manner, it is possible to form the structural layer 205 having a stiff property of the support portion and a flexible property of the movable portion.

  In addition, the structural layer 205 and the semiconductor layer 204 can be combined with a stacked structure and a partially formed structure by combining the methods described above. For example, as illustrated in FIG. 6B, the structure layer 205 is formed to have a two-layer structure, and the second silicon layer is formed using the first portion 257 and the first layer 257 as illustrated in FIG. The second portion 258 can be made separately.

  Further, as shown in FIG. 6D, the structural layer 205 is divided into a first portion 257 and a second portion 258, and either the first portion 257 or the second portion 258 is stacked. It is also possible to form it.

  As described above, the semiconductor layer 204 and the structural layer 205 can be formed by combining or separately forming silicon layers having a plurality of states. Since the semiconductor device of the present invention can be stacked and formed in various combinations, it is not limited to the combinations given in the above examples, and can be implemented in any combination.

  As in the above example, the semiconductor layer 204 included in the semiconductor element and the structural layer 205 included in the microstructure can be formed by stacking or partially forming silicon layers having different characteristics. In this manner, by forming the semiconductor layer 204 and the structural layer 205 separately, a layer having optimal characteristics for a semiconductor element and a microstructure can be formed.

  These lamination and creation can be performed by combining a plurality of film formation, crystallization, gettering, and the like. Alternatively, a metal element that promotes crystallization can be selectively applied, crystallization can be performed selectively by laser irradiation, or the metal element can be selectively removed by a gettering step. When the metal element is selectively applied, the metal element can be applied by using a droplet discharge method typified by inkjet or by selectively forming a mask.

  In addition, stacking and making can be performed by changing the laser conditions for crystallization. For example, by crystallizing amorphous silicon by irradiating a laser with reduced intensity, a layer having polycrystalline silicon in the upper layer and a layer having amorphous silicon in the lower layer can be formed. In addition, when a layer having a thick part and a thin part is crystallized by laser irradiation like a beam structure, the thin part of the layer is crystallized as a whole, and the thick part of the layer is crystallized only at the upper part of the layer. Can be made separately so that amorphous silicon remains.

  For example, when a combination of polycrystalline silicon having excellent toughness and amorphous silicon that hardly undergoes plastic deformation, a layer having strength and flexibility can be formed. In the layer having polycrystalline silicon crystallized by the above process, the grain boundary is continuous and the covalent bond is not interrupted. Therefore, the stress concentration caused by the crystal grain boundary becomes a defect and the fracture stress is high. Therefore, even if breakdown occurs due to crystal defects in the layer having amorphous silicon, the breakdown can be stopped because the breakdown does not easily propagate to the layer having polycrystalline silicon.

  Further, a silicon alloy such as nickel silicide has high strength and conductivity. Amorphous silicon is crystallized using a metal element that promotes crystallization, and after forming a layer having polycrystalline silicon, the whole or a part of the metal element is selectively left, and if necessary It can be used after heat treatment. In this way, by using a combination of a rigid and conductive silicide and polycrystalline silicon having excellent toughness, it is possible to form a conductive layer having strength and flexibility.

  In addition, when laser crystallization is performed using a metal element, the crystal growth direction of silicon proceeds in a direction perpendicular to the substrate. When laser crystallization is performed without using a metal element, the crystal growth direction is parallel to the substrate. Proceed to A combination of these can also be used. For example, when these layers are laminated, the crystal directions are different, so that even if breakdown occurs in one layer, cracks do not propagate to layers in different crystal directions, and no breakdown occurs. Therefore, in addition to the flexibility unique to polycrystalline silicon, a high-strength layer can be formed.

  As described above, the structural layer 205 having strength and electrical characteristics according to the specifications can be obtained by stacking different silicon layers, changing the ratio of the thickness of the silicon layers to be stacked, and combining the stacking and making. Can be formed. Further, by forming the semiconductor layer 204 and the structural layer 205 by using lamination or separate formation, a layer having optimal characteristics for a semiconductor element and a microstructure can be formed. Further, the above stacking and making can be easily performed. Accordingly, the semiconductor layer 204 and the structural layer 205 having desired properties can be easily formed.

  Note that this embodiment mode can be freely combined with the above embodiment modes.

(Embodiment 7)
Next, a method for manufacturing an antenna constituting the semiconductor device of the present invention will be described.

  First, as shown in FIG. 10A, the antenna 229 can be formed at the same time as forming the wiring 217 by forming the second conductive layer and performing patterning. This can be performed in a step before the first sacrificial layer and the second sacrificial layer are removed by etching. By forming the wiring 217 and the antenna 229 at the same time, the number of strokes can be reduced.

  As shown in FIG. 10B, the third protective layer 230 can be formed over the wiring 217 and the second insulating layer 228, and the antenna 231 can be formed thereover. In order to establish conduction between the antenna 231 and the wiring 217, a contact hole is formed in the third protective layer 230. This step is performed in a step before the sacrifice layer is removed by etching. Then, when the sacrificial layer is etched, the second contact hole 218 is opened in the second insulating layer 228 and the third protective layer 230. Then, an etching agent is introduced through the second contact hole 218, and the sacrificial layer can be removed by etching. This is because, as shown in FIG. 10A, when the wiring 217 and the antenna 229 cannot be formed at the same time, for example, the wiring 217 and the antenna 229 have different film thicknesses or the antenna 229 has a large area. Can be used.

  As shown in FIG. 10C, the semiconductor substrate can be provided with a counter substrate 232, and the antenna 233 can be formed over the counter substrate. At this time, in order to prevent the microstructure from being pressed and destroyed, a protective layer 234 can be provided in a portion not facing the microstructure. Thus, when the substrate 201 having an insulating surface and the counter substrate 232 are bonded to each other, the microstructure can be prevented from being destroyed. By using this method, the antenna 233 can be formed using a larger area than that illustrated in FIG. In addition, since the antenna 233 is formed over the counter substrate 232, damage to the microstructure and the semiconductor element can be reduced as compared with the case where the antenna is formed over the microstructure and the semiconductor element after being formed.

As shown in FIG. 10D, a ceramic antenna 235 (planar antenna) can be used as the antenna. The ceramic antenna 235 is configured such that a first conductive layer 237 that functions as a reflector and a second conductive layer 239 that functions as a grounding body sandwich a dielectric layer 238. Power can be supplied from the first conductive layer 237 to the layer including the microstructure and the semiconductor element by providing the power supply layer 240. Furthermore, it is possible to provide a power supply by providing a power supply point. FIG. 10D illustrates a ceramic antenna 235 having a structure in which the power feeding layer 240 is provided.

  The ceramic antenna 235 is formed of a dielectric layer 238 using ceramic, organic resin, a mixture thereof, or a magnetic material having a high dielectric constant, and conductive layers 237, 239, and 240 are formed on the surface of the dielectric layer. The surface of the dielectric layer 238 can be formed by a printing method, a plating method, or the like using the substance that is included. Alternatively, a conductive layer may be formed on the entire surface of the dielectric layer 238 by vapor deposition or sputtering, and the conductive layer may be processed into a desired shape by etching. it can.

  The second conductive layer 239 and the power feeding layer 240 manufactured as described above are electrically connected to a layer including a microstructure and a semiconductor element. Specifically, the second conductive layer 239 is connected to a portion that provides a ground potential of the layer including the semiconductor element, and the power feeding layer 240 is connected to the wireless communication circuit described with reference to FIG.

  The frequency band of the electromagnetic wave used for the wireless communication between the reader / writer and the semiconductor device is a long wave band up to 135 kHz, a short wave band of 6 to 60 MHz (typically 13.56 MHz), an ultra high frequency band of 400 to 950 MHz, 2 There is a microwave band of 25 GHz. The antenna can be appropriately designed according to the frequency of the electromagnetic wave used for communication. Further, the antenna can be provided separately from an antenna for communicating with the reader / writer and an antenna for supplying driving power.

  Note that this embodiment mode can be freely combined with the above embodiment modes.

(Embodiment 8)
In this embodiment mode, a method for manufacturing a microstructure and a semiconductor element over the same substrate in order to manufacture the semiconductor device of the present invention will be described with reference to drawings. In the drawing, a top view is shown on the upper side, and a sectional view in the top view OP or QR is shown on the lower side.

The microstructure and the semiconductor element included in the semiconductor device of the present invention can be manufactured over an insulating substrate.

First, the base film 302 is formed over the substrate 301 having an insulating surface (see FIG. 11A). As the base film 302, an insulating layer such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film can be formed with a single layer or a stacked structure. Although the case where a two-layer structure similar to that in Embodiment 4 is used as the base film 302 is described here, the base film 302 may have a structure in which an insulating layer is stacked in a single layer or three or more layers.

Next, a semiconductor layer 303 which forms a microstructure and a semiconductor layer 304 which forms a semiconductor element are formed and patterned into an arbitrary shape (see FIG. 11A). As the semiconductor layers 303 and 304, a material similar to that in Embodiment 4 and a material having a similar crystal structure can be used. In this embodiment, a crystalline semiconductor layer is formed by heat treatment using a metal element, as in Embodiment 4.

Further, since the semiconductor layer containing a metal element used for crystallization is excellent in conductivity, the metal element remains in the semiconductor layer 303 included in the microstructure, and only the semiconductor layer 304 included in the semiconductor element is selectively metal elements. It is also possible to remove. In addition, when the metal element contained in the semiconductor layer 303 included in the microstructure is removed, the portion of the semiconductor layer 303 included in the microstructure can be used without adding an impurity element. In the case where the semiconductor layer 303 needs to have conductivity when the microstructure is driven, an impurity that becomes P-type or N-type can be added. This impurity addition can be performed simultaneously with the impurity addition step when forming the impurity region of the semiconductor element. The semiconductor layer 303 given conductivity by this process is suitable for the structure of a microstructure controlled by electrostatic force.

Next, the insulating layer 305 is formed over the semiconductor layers 303 and 304 (see FIG. 11A). The insulating layer 305 can be formed using a material and a method similar to those in Embodiment 4. The insulating layer 305 formed in the region of the semiconductor element functions as a gate insulating layer.

The insulating layer 305 can be formed by high-density plasma treatment, and the conditions thereof are the same as those in Embodiment Mode 4.

Further, although the case where high-density plasma treatment is used for forming the insulating layer 305 has been described, the semiconductor layers 303 and 304 may be subjected to high-density plasma treatment. The semiconductor layer surface can be modified by high-density plasma treatment. As a result, the interface state can be improved, and the electrical characteristics of the semiconductor element and the microstructure can be improved. Furthermore, not only the insulating layer 305 but also the base film 302 and other insulating layers can be formed using high-density plasma treatment.

Next, a first sacrificial layer 306 is formed over the semiconductor layer 303 included in the microstructure and patterned into an arbitrary shape (see FIG. 11B). The first sacrificial layer 306 can be formed using a sputtering method, a CVD method, or the like using a metal element such as tungsten or silicon nitride or a compound such as silicon. For patterning, a resist mask is formed using a photolithography method, and anisotropic dry etching is performed.

The thickness of the first sacrificial layer 306 is determined in consideration of various factors such as the material of the first sacrificial layer 306, the structure and operation method of the microstructure, and the sacrificial layer etching method. For example, if the first sacrificial layer 306 is too thin, the etching agent does not diffuse and is not etched, or the structure layer buckles after etching. Further, when the microstructure is operated with an electrostatic force, if the first sacrificial layer is too thick, it cannot be driven. For example, when the microstructure is driven by electrostatic force between the conductive layer and the structural layer below the sacrificial layer, the first sacrificial layer 306 has a thickness of 0.5 μm to 3 μm, and preferably It is preferable to have 1 μm or more and 2.5 μm or less.

Next, a conductive layer which is the microstructure layer 307 and the second sacrificial layer 308 and serves as the gate electrode 309 of the semiconductor element is formed over the first sacrificial layer 306 and the insulating layer 305 to have an arbitrary shape. (See FIG. 11C). The conductive layer can be sequentially formed using a conductive metal element, a compound, or the like such as tungsten by a sputtering method, a CVD method, or the like. In this embodiment mode, a structure in which conductive layers are stacked is used. The stacked conductive layers may be formed of the same material or different materials.

As the conductive layer, the first conductive layer 310 which forms the structure layer 307 of the microstructure and the gate electrode 309 of the semiconductor element is formed. The conductive layer may be formed using an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material or a compound material containing the element as a main component, with a thickness of about 50 nm to 2 μm. A second conductive layer 311 constituting the second sacrificial layer 308 and the gate electrode 309 of the semiconductor element is formed thereon. The conductive layer may be formed with an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material or a compound material containing the element as a main component to a thickness of about 100 nm to 2 μm. Alternatively, a semiconductor layer typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or an AgPdCu alloy may be used as the first conductive layer and the second conductive layer.

The conductive layer is not limited to a two-layer structure, and may have a three-layer structure. For example, tungsten, tungsten nitride, or the like is used for the first layer, an alloy of aluminum and silicon (Al—Si), an alloy of aluminum and titanium (Al—Ti) is used for the second layer, a titanium nitride film is used for the third layer, A three-layer structure in which titanium films or the like are sequentially stacked may be used. In this case, the first layer and the second layer can be the structure layer of the microstructure, and the third layer can be the second sacrificial layer. Alternatively, the first layer can be a structural layer, and the second and third layers can be sacrificial layers. Of course, the conductive layer may have a single layer structure.

After that, patterning is performed according to the following procedure to form the structural layer 307, the second sacrificial layer 308, and the gate electrode 309. First, a resist mask is formed in a shape to be etched. Next, the second sacrificial layer 308 and the second conductive layer 311 are etched using an ICP (Inductively Coupled Plasma) etching method. At this time, the cross section may be patterned vertically by anisotropic etching, or may be etched in a tapered shape. Next, the etching conditions such as the amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, and the substrate-side electrode temperature are determined, and the structural layer 307 and the first conductive layer 310 are desired. Etch to taper shape. As an etching gas, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl ₄ or CCl ₄ , a fluorine-based gas typified by CF ₄ , SF ₆ or NF _3, or O ₂ is used. Can do.

When the sacrificial layer is etched to form a microstructure, it is preferable that the second sacrificial layer 308 and the first sacrificial layer 306 be etched at the same time because fewer steps are required. Therefore, the second sacrificial layer 308 is preferably formed using the same material as the first sacrificial layer 306. However, the present invention is not limited to these materials, and the first sacrificial layer 306 and the second sacrificial layer 308 may be manufactured using the same material or different materials.

Next, an impurity element is added to the semiconductor layer 304 included in the semiconductor element to form an N-type impurity region and a P-type impurity region. Such an impurity region can be selectively formed by forming a resist mask by a photolithography method and performing a doping treatment in which an impurity element is added. The impurity element can be added by an ion doping method or an ion implantation method. Typically, phosphorus (P) or arsenic (As) is used as the impurity element imparting N-type, and boron (B) can be used as the impurity element imparting P-type. An impurity element imparting N-type is preferably added to the N-type impurity region and the P-type impurity region in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ . If necessary, the gate electrode 309 is alternately etched and doped, whereby the impurity concentration of the semiconductor layer can be controlled to form a high-concentration impurity region or a low-concentration impurity region.

In the case where the gate electrode 309 is formed using a single conductive layer or the conductive layer having a stacked structure is not etched into a tapered shape, an insulating layer is formed over the gate electrode 309 and the insulating layer is made anisotropic. By etching, an insulating layer (side wall) in contact with the side surface of the gate electrode 309 can be formed. The sidewall can be manufactured in the same manner as in Embodiment Mode 4.

After the impurity region is formed, heat treatment, infrared light irradiation, or laser light irradiation may be performed to activate the impurity element. The activation can be performed by the same means as in the fourth embodiment.

In addition, after forming a passivation film made of an insulating layer such as a silicon oxynitride film or silicon oxide so as to cover the conductive layer or the semiconductor layer, heat treatment, infrared light irradiation, or laser light irradiation is performed to perform hydrogenation. May be performed. Hydrogenation can be performed in the same manner as in Embodiment Mode 4.

Through the above steps, an N-type semiconductor element 312 and a P-type semiconductor element 313 are formed (see FIG. 12A). At this time, impurity regions are formed in regions not covered with the first sacrificial layer 306, the structural layer 307, and the second sacrificial layer 308 in the semiconductor layer 303 included in the microstructure.

Subsequently, an insulating layer 314 is formed so as to cover the whole (see FIG. 12A). The insulating layer 314 can be formed using an insulating inorganic material, an organic material, or the like. The insulating layer 314 can be manufactured in a manner similar to that of the insulating layer 215 described in Embodiment 4.

Next, the insulating layer 314 and the insulating layer 305 are sequentially etched to form a first contact hole 315 for connecting a wiring to the semiconductor layers 303 and 304 and the structural layer 307 (see FIG. 12A). As the etching process, a dry etching method or a wet etching method can be applied. In this embodiment mode, the first contact hole 315 is formed by dry etching.

Next, the first contact hole 315 is filled, a wiring 316 is formed over the insulating layer 314, and patterned into an arbitrary shape, thereby forming a source electrode, a drain electrode, a wiring configuring an electric circuit, and the like. (See FIG. 12A). As the wiring 316, a film made of an element of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), or silicon (Si) or an alloy film using these elements can be used.

In the case where the wiring 316 has a pattern having corners, it is preferable that the corners be patterned into a rounded shape as in the fifth embodiment.

Next, the insulating layer 314 and the insulating layer 305 are sequentially etched to form second contact holes 317 and 318. The second contact hole 317 is formed to expose the first sacrificial layer 306, and the second contact hole 318 is formed to expose the second sacrificial layer 308 (see FIG. 12B). As the etching process, a dry etching method or a wet etching method can be applied.

In this embodiment mode, second contact holes 317 and 318 are formed by dry etching. The second contact holes 317 and 318 are opened to etch away the first sacrificial layer 306 and the second sacrificial layer 308. For example, the diameter of the second contact holes 317 and 318 is preferably 2 μm or more. The diameter of the contact hole is determined in consideration of the volume of the sacrificial layer to be etched.

In addition, the second contact holes 317 and 318 may be formed as contact holes having a diameter such that the first sacrifice layer 306 and the second sacrifice layer 308 can be easily etched. That is, it is not necessary to form as a small hole as described above, and the second contact holes 317 and 318 are provided so that the entire sacrificial layer is exposed leaving a portion where the insulating layer 314 such as the semiconductor layers 303 and 304 is necessary. May be formed. As a result, the time taken to remove the sacrificial layer can be shortened.

Next, the first sacrificial layer 306 and the second sacrificial layer 308 are removed by etching (see FIGS. 13A to 13C). Here, in FIG. 13, only the microstructure is displayed. For the etching, the sacrificial layer can be removed by etching through the second contact holes 317 and 318 by using a wet etching method suitable for the material of the sacrificial layer or by a dry etching method. Since the first sacrificial layer 306 and the second sacrificial layer 308 are connected, both can be removed by etching through the second contact holes 317 and 318.

For example, when the first sacrificial layer 306 or the second sacrificial layer 308 is tungsten (W), it is immersed in a solution in which 28% ammonia and 31% hydrogen peroxide solution are mixed at a ratio of 1: 2 for about 20 minutes. Etching is performed. In the case where the first sacrificial layer 306 or the second sacrificial layer 308 is silicon dioxide, buffered hydrofluoric acid in which ammonium fluoride is mixed with the hydrofluoric acid 49% aqueous solution 1 at a ratio of 7 is used. In the case where the first sacrificial layer 306 or the second sacrificial layer 308 is silicon, hydroxides of alkali metal elements such as phosphoric acid, KOH, NaOH, CsOH, NH ₄ OH, hydrazine, EPD (ethylenediamine, pyrocatechol, Water mixture), TMAH, IPA, NMD3 solution or the like.

When drying after wet etching, in order to prevent microstructural buckling due to capillary action, rinse with a low-viscosity organic solvent (for example, cyclohexane), or dry under low temperature and low pressure conditions, or both This is done by a combination of

Further, the first sacrificial layer 306 or the second sacrificial layer 308 can be removed by dry etching using F ₂ or XeF ₂ under a high pressure condition such as atmospheric pressure.

  Thus, a space (corresponding to the third space) is generated in the region from which the first sacrificial layer is removed, and a space (corresponding to the fourth space) is generated in the region from which the second sacrificial layer is removed.

Further, in order to prevent buckling of the microstructure due to capillary action occurring in these spaces after the removal of the first sacrificial layer 306 or the second sacrificial layer 308, plasma treatment for imparting water repellency to the surface of the microstructure may be performed. it can. By using such a process, the first sacrificial layer 306 and the second sacrificial layer 308 are removed by etching, so that a space is generated and the microstructure 319 having a movable portion can be manufactured.

In the method for manufacturing the microstructure 319 described above, an appropriate combination of the material for the structural layer 307, the material for the first sacrificial layer 306, the second sacrificial layer 308, and the etchant for removing the sacrificial layer is used. Must be selected. For example, when a specific etching agent is determined, the first sacrificial layer 306 and the second sacrificial layer 308 may be formed using a material having a higher etching rate than the material of the structural layer 307.

Further, when the first sacrificial layer 306 and the second sacrificial layer 308 are formed of different materials and cannot be etched with the same etchant, the sacrificial layer is etched twice. In this case, it is necessary to sufficiently consider a selection ratio with a layer (for example, the structural layer 307, the insulating layer 314, or the like) that is not removed but is in contact with the etching agent.

Further, as in this embodiment, a microstructure including a flexible movable portion with high strength can be manufactured by manufacturing a structure layer of a microstructure with a conductive layer included in a gate electrode.

In the above step, the second sacrificial layer 308 is removed by etching, and the conductive layer included in the second conductive layer 311 is used as the structural layer 307. However, the microstructure is formed without removing the second sacrificial layer 308 by etching. It can also be manufactured (see FIGS. 13D and 13E). In this case, only the first sacrificial layer 306 needs to be removed by etching, and the second contact hole 318 for etching away the second sacrificial layer 308 need not be formed.

In particular, as illustrated in FIG. 13E, when the structural layer 307 and the second sacrificial layer 308 are formed and the sacrificial layer is removed by etching, the insulating layer 314 may remain attached to the tapered portion of the structural layer 307 in some cases. . This can be used as a temporary support for preventing buckling of the structural layer 307 when the microstructure 319 is formed by etching away the sacrificial layer.

When the sacrificial layer is etched away by wet etching, the etching solution enters between the structural layer 307 and the insulating layer 305, and the structural layer 307 and the insulating layer 305 are attached (ie, buckled) by capillary action. In order to prevent this, a support can be formed using the insulating layer 314.

The area where the taper of the structural layer 307 is bonded to the insulating layer 314 is about 100 nm square to 1 μm square, and the above adhesion can be prevented by the support of the insulating layer 314. However, when the structure layer 307 is moved and used, a support is not necessary. Here, when charges having different polarities are applied between the semiconductor layer 303 and the structural layer 307 of the microstructure 319, that is, when a voltage is applied, the structural layer 307 is attracted to the semiconductor layer 303 side due to an electrostatic force and moves downward. Deflection, the support and the structural layer 307 can be separated. This is because the support and the structural layer 307 are bonded to each other with a minute area of about 100 nm square to 1 μm square.

By manufacturing the microstructure 319 using the support in this manner, buckling of the structural layer 307 can be prevented.

Note that this embodiment can be freely combined with the above embodiment.

(Embodiment 9)
By changing part of the steps in the above embodiment modes or adding another step, microstructures and semiconductor elements having various structures can be manufactured. Therefore, in this embodiment, steps different from those in the above embodiment are described.

A second sacrificial layer 321 can be formed over the first sacrificial layer 306 by using the same material as the first sacrificial layer 306, and then a conductive layer 322 can be sequentially stacked (FIG. 14A). B) (see (C)). Then, the first sacrificial layer 306 and the second sacrificial layer 321 are removed by etching, so that a space is generated, and a microstructure in which the conductive layer 322 and the insulating layer 314 serve as a structural layer can be manufactured. Through the above method, a capacitor 324 having a space below, a microstructure 324 having a function of a cantilever, a switch, or the like can be manufactured (see FIGS. 14D and 14E).

At this time, the contact hole 323 for etching the sacrificial layer can be formed at the same time as the first contact hole 315 is formed. Alternatively, the contact hole 323 may be formed after the wiring 316 is formed. The shape of the structure layer constituting the structure body can be determined by the shape of the contact hole 323.

In the above example, the first sacrificial layer 306 and the second sacrificial layer 321 are stacked. For example, a sacrificial layer having a single layer structure is formed without forming the first sacrificial layer 306. It is also possible. Further, in the above example, the first sacrificial layer 306 and the second sacrificial layer 321 are formed of the same material, and the sacrificial layer is etched away at the same time, but the present invention is not limited to this example. For example, the first sacrificial layer 306 and the second sacrificial layer 321 can be formed using different materials, etched in multiple times, and removed.

Note that this embodiment can be freely combined with the above embodiment.

(Embodiment 10)
In order to protect the microstructure, a counter substrate can be attached to the substrate. Therefore, in this embodiment mode, a mode in which a counter substrate is bonded is described.

As shown in FIGS. 15A and 15B, a counter substrate 325 is attached to the substrate 301 in order to protect the microstructure. In the case where the counter substrate 325 is attached, after the wiring 316 is formed, the second insulating layer 326 is formed over the insulating layer 314 (corresponding to the first insulating layer), and etching is performed in an arbitrary shape. At this time, the second insulating layer 326 is patterned so that the sacrificial layer and the structural layer to be a microstructure are exposed. After that, the sacrificial layer is removed by etching, whereby a microstructure having a space can be manufactured. The space shown in FIG. 15A is characterized by having an open area at one end thereof.

Next, the counter substrate 325 will be described. In order to prevent the microstructure from being destroyed by attaching the counter substrate 325, a portion facing the second insulating layer 326 formed over the insulating layer 314 (corresponding to the first insulating layer) A third insulating layer 327 is formed (see FIG. 15A). Since an insulating layer is not formed in a portion facing the microstructure formed over the substrate 301, a gap is formed between the substrates. Therefore, it is preferable that the microstructure is not broken when the substrate 301 and the counter substrate 325 are bonded to each other.

In addition, an antenna 328 which forms a circuit of a semiconductor device can be formed over the counter substrate 325 (see FIG. 15B). In this case, the second wiring 329 for connecting to the wiring 316 (corresponding to the first wiring) is formed over the second insulating layer 326 formed over the insulating layer 314 (corresponding to the first insulating layer). Form. Then, the substrate 301 and the counter substrate 325 can be fixed and bonded so that the second wiring 329 and the antenna 328 are electrically connected to each other.

The substrate 301 and the counter substrate 325 are bonded to each other using an anisotropic conductive material in order to electrically connect the second wiring 329 formed over the substrate and the antenna 328 formed over the counter substrate. It is preferable. An anisotropic conductive material has conductivity only in a specific direction (here, the direction perpendicular to the substrate). For example, an anisotropic conductive paste (ACP: Anisotropic Conductive Paste) is thermally cured or anisotropic. An electroconductive conductive film (ACF: Anisotropic Conductive Film) that has been heat-cured can be used. An anisotropic conductive paste is called a binder layer and has a structure in which particles having a conductive surface (hereinafter referred to as conductive particles) are dispersed in a layer whose main component is an adhesive. The anisotropic conductive film has a structure in which particles having a conductive surface (hereinafter referred to as conductive particles) are dispersed in a thermosetting or thermoplastic resin film. Note that particles having a conductive surface are obtained by plating a spherical resin with nickel (Ni), gold (Au), or the like. Insulating particles made of silica or the like may be mixed in order to prevent an electrical short circuit between the conductive particles at unnecessary portions. In the case where only the insulating layer is formed over the counter substrate 325 and electrical connection of an antenna or the like is not necessary, the substrate 301 and the counter substrate 325 can be bonded to each other using an adhesive having no conductivity. it can.

At this time, similarly to the steps described above, in order to protect the microstructure formed on the substrate 301, a portion that does not face the microstructure and a connection portion between the second conductive layer and the third conductive layer It is preferable to form the third insulating layer 327 so that the counter substrate 325 does not contact the microstructure. Further, the antenna 328 may be formed only above the third insulating layer 327, or may be formed above and below the third insulating layer 327 and electrically connected to each other (FIG. 15). (See (B)).

Note that this embodiment can be freely combined with the above embodiment.

(Embodiment 11)
In this embodiment, a manufacturing process in which the semiconductor device manufactured through the above steps is further separated from the substrate 301 and attached to another substrate or an object will be described. For example, a semiconductor device can be manufactured over a glass substrate and then transferred to a flexible substrate such as a plastic that is thinner and softer than glass.

In the case of peeling the semiconductor device from the substrate 301, the peeling layer 330 is formed when the base film 302 is formed (see FIG. 16A). The peeling layer 330 can be formed below the base film or between the stacked base films. Then, after the wiring 316 is formed as in the above embodiment, the contact hole 331 is formed so that the release layer 330 is exposed. Before forming the contact hole for etching the sacrifice layer, the semiconductor device is preferably peeled off from the substrate. This is because if a contact hole for etching the sacrificial layer is formed, then the sacrificial layer is removed to create a space and then peeled off from the substrate, the space may be destroyed.

An etchant is introduced into the contact hole 331, and the separation layer 330 is partially removed (see FIG. 16B). Next, a substrate 332 for supporting separation from the upper surface direction of the substrate 301 is bonded, and the semiconductor element and the microstructure are separated from the substrate 301 with the separation layer 330 as a boundary. After that, the semiconductor element and the microstructure are transferred to the substrate 332. Next, the flexible substrate 333 is bonded to the side where the semiconductor element and the microstructure are in contact with the substrate 301, that is, the separation surface. Then, the semiconductor element and the microstructure can be transferred by peeling off the substrate 332 for peeling attached from the upper surface direction. In addition, although demonstrated as the board | substrate 332, a film-like thing can also be used.

Then, a contact hole is formed so that the sacrificial layer is exposed, and the sacrificial layer is etched away, whereby a microstructure is manufactured. In addition, a protective film may be formed over the wiring in order to protect the wiring 316 and the like from reacting with the etching agent at the time of peeling.

  After the transfer, in the case where it is necessary to further protect the microstructure, the counter substrate 325 described above can be attached. The counter substrate 325 may be a film.

  In this embodiment mode, a method of transferring the semiconductor element and the microstructure to another flexible substrate 333 after etching the separation layer 330 from the substrate 301 is described; however, the present invention is not limited to this example. . For example, after the peeling layer 330 is removed only by an etching process, the substrate is transferred to another substrate or the like, or the peeling layer 330 is not provided, and a substrate for peeling is attached from the upper surface of the substrate 301 to form a semiconductor element and a microstructure. Is peeled off from the substrate 301. Further, there is a method of polishing the substrate 301 from the back surface to obtain a semiconductor element and a microstructure, and these methods can be combined as appropriate. When a process of transferring the substrate 301 to another flexible substrate 333 using a method other than polishing the substrate 301 from the back surface, there is an advantage that the substrate 301 can be reused.

  As described above, the semiconductor element and the microstructure formed over the substrate 301 are peeled off and attached to a flexible substrate 333 having flexibility, whereby a thin, soft, and small semiconductor device can be manufactured. .

  When crystallization is performed by laser crystallization or a combination of a metal element and a laser as in the above-described process, the crystallization can be performed at a lower temperature than crystallization by heat alone, so that the range of materials that can be used in the process is widened. For example, in the case where the semiconductor layer is crystallized only by heating, it is necessary to perform heating for about 1 hour at a temperature of about 1000 ° C., and a glass substrate that is weak against heat or a metal element having a melting point of 1000 ° C. or less cannot be used. . However, a glass substrate having a strain point of 593 ° C. can be used by the process using the metal element.

  In addition, compared with a semiconductor layer only by thermal crystallization, the semiconductor layer manufactured by the above process has continuous crystal grain boundaries, so that the covalent bond is not interrupted. Therefore, stress concentration caused by unpaired bonds between grain boundaries does not occur, and as a result, the fracture stress becomes higher than that of general polycrystalline silicon.

  Amorphous silicon generally has internal residual stress after film formation. For this reason, it is difficult to form a thick film. On the other hand, in the polycrystalline silicon manufactured by the above process, the internal stress is relaxed and the film can be formed at a lower temperature process, so that a semiconductor layer having an arbitrary thickness can be obtained by repeating the film formation and crystallization. It is also possible to pattern other materials on the semiconductor layer and further form a semiconductor layer thereon.

  Further, it is known that a silicon alloy such as nickel silicide is generally high in strength. By selectively leaving a metal element used for crystallization in the semiconductor layer and applying an appropriate heat treatment, a microstructure that is harder and has higher conductivity can be manufactured. Therefore, as described in this embodiment mode, the semiconductor layer is excellent when used as an electrode under the microstructure.

  In addition, according to the present invention, a microstructure and a semiconductor element are manufactured over the same substrate, so that a semiconductor device that does not require assembly or a package and does not require manufacturing costs can be provided.

  Note that this embodiment mode can be freely combined with the above embodiment modes.

(Embodiment 12)
In this embodiment, specific examples of the structure and use of the semiconductor device described in the above embodiment are described with reference to drawings.

  Here, FIG. 17 illustrates an example of a semiconductor device that is a medical device having functions such as transmitting the detected functional data of a living body by wireless communication, injecting a drug into a diseased affected part, and sampling a diseased cell. It explains using.

  In the medical device 3950 illustrated in FIG. 17A, the semiconductor device 3951 of the present invention is provided in a capsule 3952 coated with a protective layer. A filler 3953 may be filled between the capsule 3952 and the semiconductor device 3951.

  A medical device 3955 shown in FIG. 17B includes a semiconductor device 3951 of the present invention in a capsule 3952 coated with a protective layer. Further, the microstructure 3956 (entire or part of the microstructure) included in the semiconductor device is exposed to the outside of the capsule 3952. A filler 3953 may be filled between the capsule 3952 and the semiconductor device 3951.

  The protective layer provided on the surface of the capsule preferably contains diamond-like carbon (DLC), silicon nitride, silicon oxide, silicon oxynitride, or carbon nitride. Known capsules and fillers can be used as appropriate. By providing the capsule with a protective layer, it is possible to prevent the capsule and the semiconductor device from being dissolved and denatured in the body.

  Furthermore, by making the outermost surface of the capsule round like an oval, it can be used safely without damaging the human body.

  The semiconductor device 3951 that constitutes the medical devices 3950 and 3955 has the structure described in the above embodiment mode, and a sensor, a pump, a sampling structure, and the like are formed using a microstructure. The microstructure includes a sensor that measures physical quantities and chemical quantities to detect biological function data, a pump that injects a drug into the affected area of a disease, a collected body that samples affected cells, and the like.

  Here, when the physical quantity detected by the medical device is pressure, light, sound wave, or the like, a semiconductor device in which the electrode is not exposed to the outside of the capsule as illustrated in FIG. 17A can be used. In addition, when detecting a chemical substance such as a gas component such as temperature, flow rate, magnetism, acceleration, humidity, gas, or a liquid component such as ion, a microstructure 3956 as shown in FIG. It is preferable to use a semiconductor device exposed to the outside. Also in the case of a medical device having a pump for injecting a drug into an affected area or a sampled body for sampling, it is preferable that a microstructure as shown in FIG. 17B is exposed outside the capsule.

In addition, information obtained by the microstructure can be subjected to signal conversion and information processing by an electric circuit. Depending on the configuration of the electric circuit of the semiconductor device, based on the information obtained by the microstructure, the diseased part is searched for and moved, and it is determined whether to inject the drug by observing the affected part. It is also possible to have advanced functions such as.

In addition, information obtained by the microstructure or a signal processed by the electric circuit can be transmitted to the reader / writer by the RF circuit. Furthermore, it is also possible to transmit a control signal by wireless communication to a semiconductor device operating in the body. Since a semiconductor device has an RF circuit and can perform power supply and communication wirelessly, the degree of freedom in medical practice is increased, and pain given to a patient (such as a stomach camera) can be reduced. .

  Note that in the case where the medical device is a device that images the inside of the body, the medical device may be provided with a light emitting device such as an LED (Light Emitting Diode) or an EL. As a result, the inside of the body can be imaged.

  Note that a known battery may be provided in the detection device in order to spontaneously transmit detection result data from the medical device to the reader / writer.

  Next, a method for using the medical device will be described. As shown in FIG. 17C, the subject 3962 swallows the medical device 3950 or 3955, and moves the body cavity 3963. The result detected by the microstructure of the semiconductor device is transmitted to a reader / writer 3961 installed in the vicinity of the subject. The reader / writer receives this result. As a result, it is possible to detect the functional data of the living body of the subject on the spot without collecting the semiconductor device. Moreover, it is possible to image the state of the body cavity and digestive organs.

  In the above example, the example in which the medical device is swallowed and the digestive organ is examined is shown, but the present invention is not limited to this. For example, it is possible to insert a medical device into a blood vessel or an abdominal cavity by making the medical device very small (for example, about several μm to several hundred μm).

  In addition, as shown in FIG. 17D, the medical device 3950 or 3955 is embedded in the body of the subject 3962, and the result of detection of the microstructure of the semiconductor device is transferred to a reader / writer 3964 installed in the vicinity of the subject. send. In this case, the medical device 3955 is embedded so that the electrode 3957 is in contact with the measurement target portion of the subject. The medical device implanted in the body can be fixed at an arbitrary place using a biobond or the like.

  The reader / writer receives this result. It is possible to manage the biological information of the subject by recording and processing the reception result by the biological information management computer. In addition, by providing the reader / writer 3964 on the bed 3960, it is possible to always detect the biological information of the subject whose physical function is incomplete and difficult to move, and to manage the medical condition and health state of the subject. .

Note that this embodiment can be freely combined with the above embodiment.

  In this example, mechanical characteristics relating to a structural layer including a semiconductor layer, such as the structural layer 205 described in Embodiment Mode 4 with reference to FIGS.

For example, as illustrated in FIG. 6B, the structural layer 205 included in the structure is formed by stacking a layer including polycrystalline silicon crystallized using the above steps and a layer including amorphous silicon. Can be formed.
Silicon layers having different crystal states, such as a layer having polycrystalline silicon and a layer having amorphous silicon, are layers having different mechanical characteristics. Therefore, by stacking as in the above example or forming a structural layer in a selective region within the same layer, structures corresponding to various uses can be manufactured.

  In order to investigate the difference in the mechanical properties of silicon layers with different crystal states, the composite elastic modulus and indentation hardness of the layer having amorphous silicon and the layer having polycrystalline silicon formed by CVD are used. Measurements were made. Here, the layer having polycrystalline silicon is obtained by laser crystallization of a layer having amorphous silicon using a metal element.

The layer having amorphous silicon used for the sample was formed by forming a silicon nitride layer with a thickness of 50 nm and a silicon oxide layer with a thickness of 100 nm as a base layer on a quartz substrate by a CVD method. An amorphous silicon layer was formed to a thickness of 66 nm by a CVD method.
The layer having polycrystalline silicon used for the sample was crystallized by using a metal element in a layer having amorphous silicon formed in the same manner as described above by using a continuous wave laser. The energy density of the laser used for crystallization was 9 to 9.5 W / cm ² , and the scanning speed was 35 cm / sec. The thickness of the layer containing polycrystalline silicon crystallized by laser irradiation was about 60 nm due to film shrinkage.

  The mechanical properties were measured by nanoindentation measurement in which a triangular pyramid indenter was pushed into the sample. The measurement condition was a single indentation of the indenter, and the indenter used was a Berkovich indenter made of diamond. Therefore, the indenter has an elastic modulus of about 1000 GPa and a Poisson's ratio of about 0.1.

  The measured composite elastic modulus is an elastic modulus obtained by combining the elastic modulus of the sample and the indenter represented by the following formula (1). In the formula (1), Er is a composite elastic modulus, E is a Young's modulus, and ν is a Poisson's ratio. In addition, the first term (term indicated by sample) in the equation is a term contributed by the elastic modulus of the sample, and the second term (term indicated by indenter) is a term contributed by the elastic modulus of the indenter.

  As shown in the equation, the composite elastic modulus is obtained by the sum of the first term contributed by the elastic modulus of the sample and the second term contributed by the elastic modulus of the indenter. However, since the elastic modulus of the indenter is much larger than that of the sample, the second term can be ignored, and the composite elastic modulus approximately represents the elastic modulus of the sample.

The indentation hardness is hardness measured by an indentation method, and is obtained by dividing the maximum press-fit weight of the indenter by the projected area at the time of maximum press-fit. Here, the projected area at the time of press-fitting is determined by the geometric shape of the indenter and the contact depth when the indenter pushes the sample.
By multiplying this indentation hardness by 76, it can be handled equivalent to the Vickers hardness generally used as an index of hardness.

Table 1 shows the measurement results of the composite elastic modulus and indentation hardness of the layer having polycrystalline silicon and the layer having amorphous silicon.
The result has shown the average value of 3 times of measurement results.

From the results shown in Table 1, the layer having polycrystalline silicon has a higher elastic modulus than the layer having amorphous silicon.
That is, when a bending force is applied to the structural layer, the layer having polycrystalline silicon is more resistant to breakage due to bending than the layer having amorphous silicon.

  Further, the results shown in Table 1 indicate that the layer having polycrystalline silicon is harder than the layer having amorphous silicon.

  By stacking semiconductor layers having different elastic moduli and hardness, it is possible to manufacture a structure that has both flexibility and resistance to bending force. For example, by stacking the above-described layers, even if breakdown occurs from a crystal defect of a layer including polycrystalline silicon, the breakdown is difficult to propagate to the layer including amorphous silicon, and thus the breakdown can be stopped. Thus, the balance between flexibility and hardness can be determined by the ratio of the thicknesses of the layers to be laminated.

  In this way, a structure having a structural layer having desired properties such as flexibility, flexibility, or conductivity by laminating or partially forming silicon layers having different properties or silicon compound layers The body can be made.

It is the figure which showed the semiconductor device of this invention It is the figure which showed the semiconductor device of this invention It is sectional drawing which showed the microstructure with which the semiconductor device of this invention is provided It is sectional drawing which showed the microstructure with which the semiconductor device of this invention is provided It is a figure showing a manufacturing process of a semiconductor device of the present invention. It is the figure which showed the semiconductor device of this invention It is a figure showing a manufacturing process of a semiconductor device of the present invention. It is a figure showing a manufacturing process of a semiconductor device of the present invention. It is a figure showing a manufacturing process of a semiconductor device of the present invention. It is a figure showing a manufacturing process of a semiconductor device of the present invention. It is a figure showing a manufacturing process of a semiconductor device of the present invention. It is a figure showing a manufacturing process of a semiconductor device of the present invention. It is the figure which showed the semiconductor device of this invention It is the figure which showed the semiconductor device of this invention It is a figure showing a manufacturing process of a semiconductor device of the present invention. It is a figure showing a manufacturing process of a semiconductor device of the present invention. It is the figure which showed the utilization form of the semiconductor device of this invention

Claims (30)

Having a microstructure and an electric circuit on an insulating surface;
An antenna provided on the microstructure and the electric circuit;
The antenna and the microstructure are each electrically connected to the electrical circuit;
The microstructure has a structural layer, a space formed between the structural layer and the insulating surface, and a space for moving the structural layer,
The structural layer includes polycrystalline silicon that is thermally crystallized or laser crystallized using a metal element,
The electrical circuit includes the polycrystalline silicon as a semiconductor element. Having a microstructure and an electric circuit on an insulating surface;
An antenna provided on the microstructure and the electric circuit;
The antenna and the microstructure are each electrically connected to the electrical circuit;
The microstructure is a conductive lower layer, a structural layer provided on the lower layer, a space formed between the lower layer and the structural layer, and a space for moving the structural layer And
One of the lower layer or the structural layer has polycrystalline silicon that is thermally crystallized or laser crystallized using a metal element,
The electrical circuit includes the polycrystalline silicon as a semiconductor element. In claim 2,
The lower layer is
A semiconductor device including the metal element, a compound of the metal element, a silicide including the metal element and silicon, or silicon having impurities. In any one of Claims 1 to 3,
2. The semiconductor device according to claim 1, wherein the structural layer has a stacked structure of the polycrystalline silicon and amorphous silicon. In any one of Claim 1 thru | or 3,
The structure layer has a stacked structure of the polycrystalline silicon and a silicide formed of silicon and the metal element. In any one of Claim 1 thru | or 3,
2. The semiconductor device according to claim 1, wherein the structural layer has a stacked structure of silicide composed of the polycrystalline silicon, amorphous silicon, silicon, and the metal element. In any one of Claim 1 thru | or 3,
The structure layer includes a region having the polycrystalline silicon and a region having amorphous silicon in the same layer. In any one of Claim 1 thru | or 3,
The structure layer includes a region having the polycrystalline silicon and a region having a silicide formed of silicon and the metal element in the same layer. In any one of Claim 1 thru | or 3,
The structure layer includes a region having the polycrystalline silicon, a region having amorphous silicon, and a region having a silicide formed of silicon and the metal element in the same layer. In any one of Claims 1 thru | or 9,
The semiconductor device is characterized in that the metal element is one or more of Ni, Fe, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au. In any one of Claims 1 thru | or 10,
The semiconductor device, wherein the antenna is electrically connected to the semiconductor element of the electric circuit. In any one of Claims 1 thru | or 11,
Having a counter substrate on the side facing the insulating surface;
The protective layer over the microstructure is provided in a region of the counter substrate where the microstructure is not provided. In any one of Claims 1 to 12,
In the microstructure, a first space is provided between the structural layer and the insulating surface, and a second space is provided between the structural layer and a layer provided on the structural layer. ,
The semiconductor device, wherein the first space and the second space overlap. In any one of Claims 1 thru | or 13,
The semiconductor device, wherein the polycrystalline silicon is patterned into a polygonal shape with rounded corners when viewed from above. 24. In any one of claims 1 to 23,
2. The semiconductor device according to claim 1, wherein the polycrystalline silicon is formed so that a cross section has a taper angle. Forming a first sacrificial layer only in a first region on the insulating surface;
Forming a layer having silicon on the first sacrificial layer in the first region and in a second region;
The layer having silicon is thermally crystallized or laser crystallized using a metal element,
Patterning the crystallized silicon layer to form a structural layer in the first region and a semiconductor layer in the second region;
Forming a first insulating layer on the structural layer and the semiconductor layer;
Forming a first conductive layer on the first insulating layer;
Patterning the first conductive layer to form a gate electrode in the second region;
A method for manufacturing a semiconductor device, wherein the first sacrificial layer is removed by etching to form a space between the insulating surface and the structural layer. Forming a first sacrificial layer only in a first region on the insulating surface;
Forming a layer having silicon on the first sacrificial layer in the first region and in a second region;
The layer having silicon is thermally crystallized or laser crystallized using a metal element,
Patterning the crystallized silicon layer to form a structural layer in the first region and a semiconductor layer in the second region;
Forming a first insulating layer on the structural layer and the semiconductor layer;
Forming a first conductive layer on the first insulating layer;
Patterning the first conductive layer to form a second sacrificial layer in the first region and a gate electrode in the second region;
Forming a second insulating layer on the second sacrificial layer and the gate electrode;
Forming a first contact hole in the second insulating layer in the second region;
Forming a second conductive layer on the first contact hole and the second insulating layer;
Patterning the second conductive layer to form a wiring electrically connecting the structural layer of the first region and the semiconductor layer of the second region;
Forming a second contact hole exposing the first sacrificial layer and a part of the second sacrificial layer in the second insulating layer;
An etchant is introduced through the second contact hole, the first sacrificial layer and the second sacrificial layer are removed by etching, and a first space between the insulating surface and the structural layer; And forming a second space between the structural layer and the second insulating layer. In claim 16 or claim 17,
Forming a first conductive layer to which a voltage for controlling the movement of the structural layer is applied on the insulating surface;
A method for manufacturing a semiconductor device, wherein the first sacrificial layer is formed over the first conductive layer. Forming a layer having silicon in the first region and the second region on the insulating surface;
The layer having silicon is thermally crystallized or laser crystallized using a metal element,
Patterning the crystallized silicon layer to form a silicide composed of the metal element and silicon as a lower layer in the first region, and forming a semiconductor layer in the second region;
Forming a third sacrificial layer on the lower layer in the first region;
Forming a first insulating layer on the lower layer and the semiconductor layer in the first region and the second region;
In the first region, a first conductive layer is formed on the third sacrificial layer, the first conductive layer is patterned, and a structural layer is formed in the first region, and a second region is formed in the second region. Forming a gate electrode,
A method for manufacturing a semiconductor device, wherein the third sacrificial layer is removed by etching to form a third space between the lower layer and the structural layer. Forming a layer having silicon in the first region and the second region on the insulating surface;
The layer having silicon is thermally crystallized or laser crystallized using a metal element,
Patterning the crystallized silicon layer to form a silicide composed of the metal element and silicon as a lower layer in the first region, and forming a semiconductor layer in the second region;
Forming a first insulating layer on the lower layer and the semiconductor layer in the first region and the second region;
Forming a third sacrificial layer on the first insulating layer in the first region;
Forming a third conductive layer and a fourth conductive layer on the insulating layer and the third sacrificial layer in the first region and the second region,
Patterning the third conductive layer and the fourth conductive layer to form a structural layer and a fourth sacrificial layer in the first region, and forming a gate electrode in the second region;
Forming a second insulating layer on the fourth sacrificial layer and the gate electrode in the first region and the second region;
Forming a first contact hole in the second insulating layer;
Forming a second conductive layer on the second insulating layer and in the first contact hole in the first region and the second region;
Patterning the second conductive layer to form a wiring that electrically connects the structural layer in the first region and the semiconductor layer in the second region;
Forming a second contact hole in the second insulating layer so that a part of the third sacrificial layer and the fourth sacrificial layer are exposed;
An etching agent is introduced through the second contact hole, the third sacrificial layer and the fourth sacrificial layer are removed by etching, and the third space and the second space in contact with the structural layer are respectively formed. A method for manufacturing a semiconductor device, comprising: forming a semiconductor device. In any one of Claims 16 to 20,
The layer having silicon is formed by stacking one or a plurality selected from polycrystalline silicon, amorphous silicon, and a silicide formed of the metal element and silicon. . In any one of Claims 16 to 20,
The method for manufacturing a semiconductor device is characterized in that the layer containing silicon is formed by selectively adding a metal element over amorphous silicon and crystallizing the region to which the metal element is added by laser irradiation. . In any one of Claims 16 to 20,
The layer having silicon is
A method for manufacturing a semiconductor device, wherein a metal element is added and crystallized over amorphous silicon. 24. Any one of claims 16 to 23.
The method for manufacturing a semiconductor device, wherein the metal element is one or more of Ni, Fe, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au. In Claim 17, the first sacrificial layer and the second sacrificial layer are formed using the same material,
A method for manufacturing a semiconductor device, wherein the semiconductor device is removed by etching in the same step. In Claim 20, the third sacrificial layer and the fourth sacrificial layer are formed using the same material,
A method for manufacturing a semiconductor device, wherein the semiconductor device is removed by etching at the same time. In any one of claims 16 to 26,
Any one of the first to fourth sacrificial layers is formed so that the upper surface has a polygonal shape with rounded corners. In any one of claims 16 to 26,
Any one of the first to fourth sacrificial layers is formed so as to have a tapered cross section. In any one of claims 16 to 28,
The method for manufacturing a semiconductor device is characterized in that the structural layer is formed so that the upper surface has a polygonal shape with rounded corners. In any one of claims 16 to 28,
The method for manufacturing a semiconductor device is characterized in that the structural layer is formed to have a tapered cross section.

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