JP2007109949A - Method of forming semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problems of variation in size and shape of a resist pattern and charge-up damage at the same time. <P>SOLUTION: A rectangular frame-like dummy contact hole pattern 35 defines a contact hole pattern 37 in resist pattern formation, and is formed along a side of a chip separation region 17. Contraction of a first resist layer 30 with a pattern per a wafer can be thereby reduced to contraction per a chip. Furthermore, charge generated when a conductor layer is removed can be escaped to a substrate in a chip by a dummy contact formed from the dummy contact hole pattern. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for forming a semiconductor element, and more particularly to a method for forming a contact using a resist pattern.

  As is well known, in the process of forming a semiconductor element, it is necessary to form a connection conductor for electrical connection between electrodes and wirings or between wirings through contact holes formed in an insulating layer on the substrate. . This connection conductor is also called a contact or a contact conductor. These contacts are usually formed by the following method.

  First, a structure obtained by forming an integrated circuit in a chip region partitioned by forming a chip isolation region on a substrate is prepared. An intermediate insulating layer and a resist layer are sequentially formed on the structure so as to cover the chip isolation region and the chip region. Next, a resist pattern, that is, an opening is formed by etching a portion of the resist layer corresponding to the contact formation planned position of the intermediate insulating layer. Using the resist layer having this resist pattern as a mask, the lower intermediate insulating layer is etched to form contact holes. After removing the resist layer, a conductor layer covering the intermediate insulating layer is formed on the entire upper surface of the substrate. Finally, the conductor layer is removed so that the conductor layer remains only in the contact hole.

  By the way, as is well known, when forming a resist pattern, after the resist pattern is formed, a heat treatment is performed to harden the resist layer, so that the resist layer contracts. Due to the tensile stress due to the shrinkage of the resist layer and the decrease in the adhesion between the intermediate insulating layer and the resist layer due to the tensile stress, the size and shape of the resist pattern change. As a result, the finished dimensions and shape of the contacts deviate from the design values.

  In order to suppress the variation in the size and shape of the resist pattern, a method of forming a bowl-shaped dummy pattern so as to surround the outer periphery of the contact resist pattern is conventionally known. According to this method, by providing a dummy pattern, the tensile stress from the region of the resist layer existing outside the dummy pattern, and the tensile stress of the region of the inner resist layer defined by the dummy pattern, Can be divided. Thereby, the tensile stress of the resist layer around the pattern can be reduced (Patent Document 1).

In addition, when the semiconductor element is exposed to an atmosphere such as plasma etching in the process of performing some removal process during the formation of the semiconductor element, charges are accumulated in the conductor layer for forming the contact, and the conductor layer is abnormally formed. There is a possibility that damage due to so-called charge-up occurs. As means for reducing this, a method is known in which electric charges are released to the substrate by electrically connecting the conductor layer and the substrate (Patent Document 2). In this patent document 2, a contact is formed in a region where a semiconductor element is not formed in a peripheral portion of a substrate, that is, a wafer, and the substrate is electrically connected to the conductor layer on the upper side thereof. A method for releasing charge from a layer to a substrate is disclosed.
JP-A-9-97762 JP 2003-282570 A

  However, in order to reduce the above-described charge-up damage, it is not sufficient to simply ground each wafer as disclosed in Patent Document 2, for example.

  Therefore, a method for forming a semiconductor element that can more reliably reduce charge-up damage by losing electric charge for each chip region defined on the wafer during the manufacturing process of the semiconductor element has been desired. It was rare.

  In addition, there has been a demand for a method for forming a semiconductor element that can simultaneously solve variations in the size and shape of a resist pattern and charge-up damage.

  Therefore, in order to solve the above-described problems, a method for forming a semiconductor element according to the present invention includes the following steps from a first step to a seventh step.

  That is, in the first step, the intermediate insulating layer is formed on the entire surface of the substrate having the chip region having the integrated circuit formation region and the chip isolation region surrounding the chip region at the outer periphery of the chip region.

  In the second step, a first resist layer is formed on the entire surface of the substrate.

  In the third step, by etching the first resist layer, a dummy contact hole having a rectangular frame shape is formed at a position directly above the active region in the chip region and along the side of the integrated circuit formation region. A first resist pattern is formed for forming contact holes in the integrated circuit formation region in the chip region.

  In the fourth step, dummy contact holes and contact holes are formed in the intermediate insulating layer by using the first resist pattern.

  In the fifth step, the first resist layer is removed.

  In the sixth step, a first conductor layer is formed in the dummy contact hole, in the contact hole, and on the surface of the intermediate insulating layer.

  In the seventh step, the first conductor layer is removed to leave the first conductor layer only in the dummy contact hole and in the contact hole, thereby forming a dummy contact and a contact.

  According to the method for forming a semiconductor element of the first aspect of the present invention, in the third step, a first resist pattern for a normal contact hole is formed, and a rectangular frame shape is formed along the side of the integrated circuit formation region. A first resist pattern for the dummy contact hole is formed. Thereby, it is possible to reduce the tensile stress in units of chips from the conventional tensile stress due to the shrinkage of the resist layer in units of wafers. As a result, it is possible to suppress variations in the size and shape of the contact due to the shrinkage of the resist layer. In addition, the adhesion between the resist layer and the intermediate insulating layer is improved by reducing the tensile stress.

  Further, according to the method for forming a semiconductor element of the first aspect of the present invention, not only a so-called normal contact but also a dummy contact particularly invented in the present invention is formed on the active region of the substrate. For this reason, in the seventh step, the charge generated when the conductor layer is removed can be released from the dummy contact to the substrate through the conductor layer. Since the dummy contact is formed in a wider area than a normal contact, electric charges can be released more efficiently than in the past.

  In addition, according to the forming method of the present invention, since dummy contacts are provided inside each chip region, as disclosed in Patent Document 2, charges can be efficiently and reliably charged not on a wafer basis but on a chip basis. Can escape.

  According to the method for forming a semiconductor element of the first aspect of the present invention, since the dummy contact is formed simultaneously with the normal contact, it is possible to suppress variations in the size and shape of the intended resist pattern and to charge up damage. Can be achieved at the same time.

  A method for forming a semiconductor device according to the present invention will be described below with reference to the drawings. In addition, each figure has shown only the shape, magnitude | size, and arrangement | positioning relationship of each component only to such an extent that this invention can be understood. Therefore, the configuration of the present invention is not limited to the illustrated configuration example.

<First Embodiment>
In the first embodiment, a method for forming a semiconductor element having dummy contacts on the outer periphery of an integrated circuit formation region will be described. This forming method includes the first to seventh steps. Hereinafter, each step will be described in order from the first step.

  FIG. 1 is a plan view showing a wafer used in this embodiment. A plurality of chip regions 11 are defined by an active chip isolation region 17 on one main surface side of the wafer, and an integrated circuit (not shown) is formed in each chip region 11. In this embodiment, the chip isolation region 17 is made active in order to prevent cracks that may occur during dicing from reaching the chip region 11. Therefore, if this crack is not a problem, a field oxide film may be formed in the chip isolation region 17 without making the chip isolation region 17 active.

  2 and 3 are enlarged views showing one chip region a in FIG. 1, and FIG. 2 shows the first structure of the structure obtained in the third step in this embodiment. 5 is a plan view for explaining a state of a resist pattern 13. FIG. FIG. 3 is a plan view showing the structure obtained in the seventh step.

  4 to 6 are end views showing the structures obtained in the respective formation stages from the first process to the seventh process. Here, FIG. 5A is an end view taken along the line II of FIG. 2, and FIG. 6C is an end view taken along the line II-II of FIG.

  First, a chip region 11 in which the integrated circuit formation region 11a exists and a chip isolation region 17 that surrounds the chip region 11 and that separates the chip regions 11 are formed on the outer periphery of the chip region 11. A substrate 15 is prepared.

  In the first step, an intermediate insulating layer 19 such as an oxide film and a nitride film covering the chip region 11 and the chip isolation region 17 is formed over the entire surface of the substrate 15 (see FIG. 4A). The intermediate insulating layer 19 may be formed by a conventionally known suitable method such as a CVD method. Here, an active region 21 and an element isolation region 23 that electrically isolates the chip region 11 and the chip isolation region 17 are formed in the chip region 11 of the substrate 15. A gate insulating film 25 constituting an integrated circuit and an insulating film 26 under the capacitor are formed at predetermined positions of the active region 21. The gate insulating film 25 is formed between the gate and the substrate, and the insulating film 26 under the capacitor is formed between the capacitor and the substrate. On these insulating films 25 and 26, poly (Poly) silicon 27 is formed as a capacitor or a gate which also constitutes an integrated circuit. The material of the substrate 15 is not particularly limited, but it is particularly preferable to use N-type and P-type silicon substrates from the viewpoint that the effects of the present invention can be remarkably exhibited.

  Next, in the second step in this embodiment, a first resist layer 29 is formed over the entire surface of the substrate 15 above the intermediate insulating layer 19 formed in the first step (see FIG. 4B). ).

  Next, in the third step, the first resist layer 29 is etched to form the first resist pattern 13 in the first resist layer 29 (see FIG. 5A). The first resist layer on which the first resist pattern 13 is formed, that is, the patterned first resist layer 30, as described later, has a contact hole 31 and a dummy contact hole 33 as masks in the next fourth step. Used to form. The dummy contact hole pattern 35 is formed in a rectangular frame shape along the outer periphery of the integrated circuit formation region 11a. The dummy contact hole pattern 35 is formed immediately above the active region 21 provided on the substrate 15. The contact hole pattern 37 is formed in the integrated circuit formation region 11a on the inner side of the frame which is the dummy contact hole pattern 35. Here, the contact hole pattern 37 includes two types of patterns. One pattern is a contact hole pattern 37a formed on the polysilicon 27, and the other pattern is a contact hole pattern formed on the active region 21 where the polysilicon 27 of the substrate 15 is not present. 37b (see FIGS. 2 and 5A).

  Next, in the fourth step, the intermediate insulating layer 19 is etched using the patterned first resist layer 30 formed in the third step as a mask. This etching is usually performed by anisotropic dry etching. By this etching, the dummy contact hole 33 and the contact hole 31 in which the pattern 35, the pattern 37a, and the pattern 37b are respectively transferred to the intermediate insulating layer 19 are formed. Here, the contact hole 31a formed by the pattern 37a is formed on the polysilicon 27, and the contact hole 31b formed by the pattern 37b is formed on the active region 21 where the polysilicon 27 of the substrate 15 does not exist. (See FIG. 5B). Here, the intermediate insulating layer in which the contact holes 31 (31a, 31b) and the dummy contact holes 33 are formed, that is, the intermediate insulating layer with holes is represented by 20.

  Next, in the fifth step, the patterned first resist layer 30 is removed using an etching technique to expose the intermediate insulating layer 20 with holes on the substrate 15 (see FIG. 6A).

  Next, in a sixth step, a first conductor layer 39 is formed on the entire upper surface of the substrate 15 including the exposed intermediate insulating layer 20 with a hole (see FIG. 6B). The formation of the first conductor layer 39 is preferably performed using, for example, a CVD method. Further, as the material of the first conductor layer 39, it is preferable to use a conductive material such as tungsten. The conductive material is embedded in the dummy contact hole 33 and the contact hole 31 and is formed with a uniform thickness on the entire upper surface of the intermediate insulating layer 20 with a hole to form the first conductor layer 39. To do. At this time, the surface of the conductor layer portion 39a formed on the upper surface of the intermediate insulating layer 20 is a flat surface. In addition, a conductor layer portion embedded in each of the holes 31 and 33 is represented by 39b (see FIG. 6B).

  Next, in the seventh step, since the conductor layer portion 39a formed in the sixth step is unnecessary, a removal process is performed on the conductor layer portion 39a. This removal process may be performed by etchback, dry etching, CMP, or any other suitable method. By this removal process, the conductor layer portion 39a is removed up to the upper surface (upper surface) of the intermediate insulating layer 20 with a hole, and only the conductor layer portion 39b embedded in the dummy contact hole 33 and the contact hole 31 remains. Let The remaining conductor layer portion 39b has dummy contacts 41 and contacts 43, that is, contacts 43a formed on the polysilicon 27, and contacts 43b formed on the active region 21 where the polysilicon 27 is not present. Each is formed (see FIG. 3 and FIG. 6C). Here, the conductor layer portion 39b remaining only in the dummy contact hole 33 and the contact hole 31 is hereinafter simply referred to as a conductor 39b.

  As already described, the dummy contact hole pattern 35 formed in the patterned first resist layer 30 in this embodiment is different from the conventional dummy pattern at a location directly above the active region 21. , In a shape surrounding the integrated circuit formation region 11a. Further, the dummy contact 41 in this embodiment is formed as a conductor 39 b inside the chip isolation region 17, similarly to the normal contact 43. Thereby, according to the method for forming a semiconductor element in this embodiment, shrinkage of the patterned first resist layer 30 existing in the chip region 11 can be suppressed during heating when the first resist pattern 13 is formed. The effect is obtained. Furthermore, there is also an effect that the charges generated in the first conductor layer 39 during the removal process of the unnecessary conductor layer portion 39a in the seventh step are released to the substrate 15 via the dummy contact, and thus the conductor layer portion 39b. can get. Accordingly, it is possible to simultaneously achieve the effects of improving the adhesion between the patterned first resist layer 30 and the intermediate insulating layer 19 and reducing the charge-up damage by suppressing the variation in the size and shape of the contact 43 and reducing the tensile stress. it can.

  Further, the dummy contacts 41 in this embodiment are provided on the outer periphery of the individual chip regions 11 of the substrate 15 in a wider range than the normal contacts 43, respectively. Therefore, since the contact area of the dummy contact 41 with the substrate 15 is much larger than that of the contact 43, the electric charge generated in the conductor layer for contact formation can be efficiently and reliably released for each chip region 11. Can do. Therefore, damage to the gate insulating film 25 and the insulating film 26 under the capacitor due to charge-up can be reduced.

  In addition, according to the method for forming a semiconductor element in this embodiment, the dummy contact 41 is formed simultaneously with the normal contact 43 and in the same method, and therefore, the steps required in the conventional method for forming a semiconductor element. The above-mentioned problems can be solved with the same number of steps as the number.

  The method for removing the undesired conductor layer portion 39a in the seventh step is not particularly limited. For example, when a method in which electric charges easily accumulate in the conductor 39b, such as plasma etching, is used. The effects of the present invention described above can be remarkably exhibited.

<Second Embodiment>
In the second embodiment, the semiconductor including the eighth step of forming the first wiring metal 45 on the dummy contact 41 and the contact 43 in the structure formed in the seventh step in the first embodiment. A method for forming the element will be described.

  FIG. 7 is an end view of a semiconductor element obtained by the method for forming a semiconductor element in this embodiment.

  In the eighth step in this embodiment, a first wiring metal 45 such as aluminum is formed immediately above the dummy contact 41 and the contact 43 in the structure obtained in the seventh step in the first embodiment. Form.

  According to the method for forming a semiconductor element in this embodiment, in the process of forming the first wiring metal 45, for example, when plasma etching is performed, the first wiring metal 45 is generated due to the etching process. The charged charges can be released to the substrate 15 through the dummy contacts 41. As a result, damage due to charge-up can be reduced. Further, since the dummy contacts 41 are provided on the outer periphery of each integrated circuit formation region 11a, charges can be efficiently and surely released to the substrate 15 for each chip region 11 as in the first embodiment. Compared with the prior art, damage to the gate insulating film 25 and the insulating film 26 under the capacitor due to the charge-up can be greatly reduced.

<Third Embodiment>
In the third embodiment, formation of a semiconductor element in which the via contact 47 and the dummy via contact 49 are formed immediately above the first wiring metal 45 in the structure formed in the eighth step in the second embodiment. A method will be described. This forming method includes the ninth to fifteenth steps. Hereinafter, each step will be described in order from the ninth step.

  Here, FIGS. 8 to 11 are end views showing the structures obtained in the respective formation stages from the ninth process to the fifteenth process of this embodiment. The plan view is the same as FIG. 2 and FIG. 3 shown in the first embodiment, and will be omitted.

  In the ninth step in this embodiment, first, a second insulating layer 51 such as an oxide film or a nitride film is formed on the entire upper surface of the structure formed in the eighth step in the second embodiment ( (See FIG. 8A).

  Next, in a tenth step, a second resist layer 53 is formed on the entire upper surface of the substrate 15 so as to cover the second insulating layer 51 (see FIG. 8B).

  Next, in an eleventh step, an opening, that is, a second resist pattern 55 is formed by etching the second resist layer 53 as in the case of the first resist layer 29 described above (FIG. 9). (See (A)). The second resist layer on which the second resist pattern 55 is formed is referred to as a patterned second resist layer 54. The patterned second resist layer 54 is used as a mask when the second insulating layer 51 is etched, and is used when the via hole 57 and the dummy via hole 59 are formed. Here, the pattern corresponding to the via hole 57 and the dummy via hole 59 is formed at a position directly above the first wiring metal 45 formed in the eighth step in the second embodiment. Therefore, the dummy via hole pattern 61 corresponding to the first wiring metal 45 formed immediately above the dummy contact 41 is located immediately above the dummy contact 41 formed in the first embodiment, that is, integrated. A rectangular frame is formed along the outer periphery of the circuit forming region 11a. Also, the via hole pattern 63 corresponding to the first wiring metal 45 formed immediately above the normal contact 43 is located directly above the contact 43 formed in the first embodiment, that is, a dummy via hole. It is formed in the integrated circuit formation region 11a which is the inside of the frame which is the pattern 61 for use. Here, a pattern for a via hole formed at a location immediately above the contact 43a is a pattern 63a, and a pattern for a via hole formed at a location immediately above the contact 43b is a pattern 63b.

  Next, in the twelfth step, the second insulating layer 51 is etched in the same manner as the above-described intermediate insulating layer 19 using the patterned second resist layer 54 as a mask (see FIG. 9B). ). Thereby, dummy via holes 59 and via holes 57 are formed in the second insulating layer 51. The second insulating layer 51 in which these via holes are formed is referred to as an insulating layer 52 with via holes. Here, the via hole 57a formed by the pattern 63a is formed at a location directly above the contact 43a, and the via hole 57b formed by the pattern 63b is formed at a location directly above the contact 43b.

  Next, in the thirteenth step, the patterned second resist layer 54 is removed by etching in the same manner as for the patterned first resist layer 30 (see FIG. 10A).

  Next, in a fourteenth step, a second conductor layer 65 made of a highly conductive material such as tungsten and filling the dummy via hole 59 and the via hole 57 is formed (see FIG. 10B). At this time, the second conductor layer 65 includes a conductor layer portion 65a formed on the entire upper surface of the insulating layer 52 with via holes, and a conductor layer portion 65b embedded in the respective via holes 57 and 59. have. Here, the thickness of the conductor layer portion 65a is uniform, and the surface thereof is a flat surface.

  Next, in the fifteenth step, since the formed conductor layer portion 65a is unnecessary, the conductor layer portion 65a is subjected to a removal process by etch back or any other method (see FIG. 11). Thus, only the conductor layer portion 65b in the dummy via hole 59 and the via hole 57 is left, so that the dummy via contact 49 and the via contact 47 are formed. A via contact 47a formed from the via hole 57a is formed at a location directly above the contact 43a, and a via contact 47b formed from the via hole 57b is formed at a location directly above the contact 43b. Here, the conductor layer portion 65b remaining only in the dummy via hole 59 and the via hole 57 is hereinafter simply referred to as a conductor 65b.

  In this embodiment, the dummy via hole pattern 61 formed in the patterned second resist layer 54 includes the dummy contact 41 in the first embodiment and the first wiring metal in the second embodiment. It is formed in a shape surrounding the integrated circuit isolation region 11 a at a location immediately above 45. Further, the dummy via contact 49 in this embodiment has a conductor 65 b inside the chip region 11, similarly to the normal via contact 47. Thus, according to the method for forming a semiconductor element in this embodiment, the second resist with pattern in the chip region 11 is heated during the formation of the second resist pattern 55 as in the first embodiment. The effect that the shrinkage of the layer 54 can be suppressed, and the charge generated in the second conductor layer 65 during the removal process of the unwanted conductor layer portion 65a in the fifteenth step is transferred from the dummy via contact 49 to the first wiring. An effect of escaping to the substrate 15 through the metal 45 and the dummy contact 41 can be obtained. Therefore, the effects of improving the adhesion between the patterned second resist layer 54 and the second insulating layer 51 and reducing the charge-up damage by suppressing the variation in the size and shape of the via contact 47 and reducing the tensile stress are obtained. Can be obtained at the same time.

  In addition, the dummy via contacts 49 in this embodiment are provided on the outer periphery of the individual integrated circuit formation regions 11 a of the substrate 15 in a wider range than the normal via contacts 47. Therefore, the dummy via contact 49 has a larger contact area with respect to the first wiring metal 45 and the substrate 15 than the via contact 47. Therefore, the charges generated in the second conductor layer 65 can be efficiently and reliably released to the substrate 15 for each chip region 11. Therefore, damage to the gate insulating film 25 and the insulating film 26 under the capacitor due to charge-up can be reduced.

  Further, in the method for forming a semiconductor element in this embodiment, since the dummy via contact 49 is formed at the same time as the normal via contact 47 and in the same method, the number of steps is the same as the conventional method for forming a semiconductor element. The problem can be solved.

  Here, the method of removing the undesired conductor layer portion 65a in the fifteenth step is not particularly limited. For example, a method in which charges easily accumulate in the conductor 65b, such as plasma etching, is used. When done, a particularly significant effect can be obtained.

<Fourth embodiment>
In the fourth embodiment, the sixteenth step of forming the second wiring metal 67 immediately above the via contact 47 and the dummy via contact 49 in the structure formed in the fifteenth step in the third embodiment. A method for forming a semiconductor element will be described.

  Here, FIG. 12 is an end view of the semiconductor element obtained by the method of this embodiment.

  In the sixteenth step in this embodiment, a second wiring metal 67 such as aluminum is formed immediately above the via contact 47 and the dummy via contact 49 in the structure formed in the fifteenth step in the third embodiment. Form.

  According to the method for forming a semiconductor element in this embodiment, when the second wiring metal 67 is formed, for example, plasma etching or the like is performed, the generated charges are transferred to the dummy via contact 49, the first wiring metal 45, And it can escape to the substrate 15 through the dummy contact 41. As a result, damage due to charge-up can be reduced. Further, since the dummy contact 41 is provided on the outer periphery of each integrated circuit formation region 11a, similar to the first embodiment, it is possible to efficiently and surely release charges for each chip region 11, and in the related art. In comparison, damage to the gate insulating film 25 and the insulating film 26 under the capacitor due to the charge-up can be greatly reduced.

It is a top view which shows the wafer prepared in 1st Embodiment. FIG. 2 is an enlarged view focusing on one chip region (a) in FIG. 1 and illustrating a state of the first resist pattern of the structure obtained in the third step in the first embodiment. FIG. FIG. 8 is an enlarged view showing one chip region (a) in FIG. 1 and a plan view showing the structure obtained in the seventh step in the first embodiment. It is an end view which shows the structure obtained in each formation step from the 1st process in the 1st Embodiment to the 2nd process. It is an end view which shows the structure obtained in each formation step from the 3rd process in the 1st Embodiment to the 4th process. In particular, FIG. 5A is an end view taken along the line II of FIG. It is an end view which shows the structure obtained in each formation step from the 5th process to the 7th process in 1st Embodiment. In particular, FIG. 6C is an end view taken along the line II-II in FIG. It is an end elevation of the semiconductor element obtained in the second embodiment. It is an end elevation which shows the structure obtained in each formation step from the 9th process in the 3rd embodiment to the 10th process. It is an end elevation which shows the structure obtained in each formation step from the 11th process to the 12th process in 3rd Embodiment. It is an end elevation which shows the structure obtained in each formation step from the 13th process to the 14th process in 3rd Embodiment. It is an end elevation which shows the structure obtained at the 15th process in 3rd Embodiment. It is an end view of the semiconductor element obtained in the fourth embodiment.

Explanation of symbols

11: Chip region 11a: Integrated circuit formation region 13: First resist pattern 15: Substrate 17: Chip isolation region 19: Intermediate insulating layer 20: Intermediate insulating layer with holes 21: Active region 23: Element isolation region 25: Gate insulation Film 26: Insulating film 27 under the capacitor 27: Polysilicon 29: First resist layer 30: Patterned first resist layer 31: Contact hole 31a: formed by pattern 37a Contact hole 31b: formed by pattern 37b Contact hole 33: Dummy contact hole 35: Dummy contact hole pattern 37: Contact hole pattern 37a: Contact hole pattern 37b formed on polysilicon 37b: Contact hole pattern formed on active region 39: 1 conductor layer 39a: conductive layer portion 39 b: a conductor (conductive layer portion)
41: dummy contact 43: contact 43a: contact 43b formed on polysilicon: contact 45b formed on active region 45: first wiring metal 47: via contact 47a: via contact 47b formed from via hole 57a: Via contact 49 formed from via hole 57b: dummy via contact 51: second insulating layer 52: insulating layer with via hole 53: second resist layer 54: second resist layer 55 with pattern: second resist pattern 57 : Via hole 57a: via hole 57b formed by pattern 63a: via hole 59 formed by pattern 63b: dummy via hole 61: pattern for dummy via hole 63: pattern for via hole 63a: position directly above contact 43a Pattern 63b for holes existing in: patterns for via holes located at a position to be directly above the contact 43 b 65: second conductive layer 65a: conductive layer portion 65b: conductor (conductor layer portion)
67: Second wiring metal

Claims (4)

A first step of forming an intermediate insulating layer on the entire surface of the substrate having a chip region having an integrated circuit formation region and a chip isolation region surrounding the chip region at the outer periphery of the chip region;
A second step of forming a first resist layer on the entire surface of the substrate;
By etching the first resist layer, a dummy contact hole having a rectangular frame shape is formed at a position directly above the active region in the chip region and along the outer periphery of the integrated circuit formation region. And a third step of forming a first resist pattern for forming a contact hole in the integrated circuit formation region in the chip region;
A fourth step of forming the dummy contact hole and the contact hole in the intermediate insulating layer by using the first resist pattern;
A fifth step of removing the first resist layer;
A sixth step of forming a first conductor layer in the dummy contact hole, in the contact hole, and on the surface of the intermediate insulating layer;
A seventh step of forming a dummy contact and a contact by removing the first conductor layer and leaving the first conductor layer only in the dummy contact hole and in the contact hole. A method for forming a semiconductor element, comprising:   2. The method of forming a semiconductor element according to claim 1, further comprising an eighth step of forming a first wiring metal immediately above the contact and the dummy contact after the seventh step. . The method for forming a semiconductor element according to claim 2, wherein after the eighth step, a ninth step of forming a second insulating layer on the entire surface of the structure formed by the eighth step;
A tenth step of forming a second resist layer on the entire surface of the structure;
By etching the second resist layer, a dummy via hole is formed at a position directly above the first wiring metal formed immediately above the dummy contact, and the second resist layer is formed immediately above the contact. An eleventh step of forming a second resist pattern for forming a via hole at a position directly above one wiring metal;
A twelfth step of forming the dummy via hole and the via hole in the second insulating layer by using the second resist pattern;
A thirteenth step of removing the second resist layer;
A fourteenth step of forming a second conductor layer in the dummy via hole, in the via hole, and on the surface of the second insulating layer;
A fifteenth step of forming a dummy via contact and a via contact by removing the second conductor layer and leaving the second conductor layer only in the dummy via hole and in the via hole. A method for forming a semiconductor element, comprising:   4. The method of forming a semiconductor element according to claim 3, further comprising a sixteenth step of forming a second wiring metal on the via contact and the dummy via contact after the fifteenth step. Forming method.

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