KR20060008045A - Method for forming inductor of semiconductor device - Google Patents

Method for forming inductor of semiconductor device Download PDF

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KR20060008045A
KR20060008045A KR1020040057700A KR20040057700A KR20060008045A KR 20060008045 A KR20060008045 A KR 20060008045A KR 1020040057700 A KR1020040057700 A KR 1020040057700A KR 20040057700 A KR20040057700 A KR 20040057700A KR 20060008045 A KR20060008045 A KR 20060008045A
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forming
inductor
film
substrate
silicon substrate
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KR101044389B1 (en
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양준석
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 인덕터의 효율을 개선시킬 수 있을 뿐만 아니라, 메인 칩의 오동작을 막을 수 있는 반도체 소자의 인덕터 형성방법을 개시한다. 개시된 본 발명의 방법은, 액티브영역과 필드영역이 정의된 실리콘 기판을 제공하는 단계; 상기 실리콘 기판 상에 상기 기판의 필드영역을 노출시키는 패드산화막 및 패드질화막을 차례로 형성하는 단계; 상기 패드질화막을 식각 장벽으로 이용하여 상기 기판을 식각하여 트렌치를 형성하는 단계; 상기 패드질화막 및 패드산화막을 제거하는 단계; 상기 트렌치 구조를 매립하는 소자분리막을 형성하는 단계; 상기 소자분리막을 선택적으로 식각하여 다수개의 홈을 형성하는 단계; 상기 홈 구조를 매립하는 각각의 도전막 패턴을 형성하는 단계; 상기 도전막 패턴을 포함한 상기 실리콘 기판 상부에 공지의 방식들에 의해 회로 소자를 형성하는 단계; 및 상기 회로 소자가 형성된 기판 상부의 상기 도전막 패턴과 대응되는 부위에 인덕터를 형성하는 단계를 포함한다. The present invention not only improves the efficiency of an inductor, but also discloses a method of forming an inductor of a semiconductor device capable of preventing a malfunction of a main chip. The disclosed method comprises the steps of providing a silicon substrate having active and field regions defined therein; Sequentially forming a pad oxide film and a pad nitride film exposing the field region of the substrate on the silicon substrate; Etching the substrate to form a trench using the pad nitride layer as an etch barrier; Removing the pad nitride film and the pad oxide film; Forming an isolation layer to fill the trench structure; Selectively etching the device isolation layer to form a plurality of grooves; Forming respective conductive film patterns to fill the groove structures; Forming a circuit element on the silicon substrate including the conductive film pattern by known methods; And forming an inductor at a portion corresponding to the conductive layer pattern on the substrate on which the circuit element is formed.

Description

반도체 소자의 인덕터 형성방법{Method for forming inductor of semiconductor device}Method for forming inductor of semiconductor device

도 1은 종래의 기술에 따른 반도체 소자의 인덕터 형성방법을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a method of forming an inductor of a semiconductor device according to the prior art.

도 2는 종래의 기술에 따른 반도체 소자 인덕터의 평면도.2 is a plan view of a semiconductor device inductor according to the prior art.

도 3은 종래의 기술에 따른 문제점을 설명하기 위한 단면도. 3 is a cross-sectional view for explaining a problem according to the prior art.

도 4a 내지 도 4g는 본 발명의 실시예에 따른 반도체 소자의 인덕터 형성방법을 설명하기 위한 공정별 단면도.4A through 4G are cross-sectional views illustrating processes of forming an inductor of a semiconductor device in accordance with an embodiment of the present invention.

-도면의 주요 부분에 대한 부호의 설명-Explanation of symbols on main parts of drawing

20 : 실리콘 기판 21 : 패드산화막20 silicon substrate 21 pad oxide film

22 : 패드질화막 21a : 식각후 잔류된 패드산화막22: pad nitride film 21a: pad oxide film remaining after etching

22a : 식각후 잔류된 패드질화막 23 : 트렌치22a: Pad nitride film remaining after etching 23: Trench

24 : 절연막 24a : 소자분리막24: insulating film 24a: device isolation film

25 : 감광막 패턴 26 : 홈25 photosensitive film pattern 26

27 : 도전막 27a : 도전막 패턴27: conductive film 27a: conductive film pattern

28 : 회로 소자 29 : 최종 금속배선28: circuit element 29: final metal wiring

30 : 인덕터 31 : 보호막 30: inductor 31: protective film

본 발명은 반도체 소자의 인덕터 형성방법에 관한 것으로, 보다 상세하게는, 인덕터의 전기장이 실리콘 기판으로 빠져나가는 것을 막음으로써, 인덕터의 효율을 개선시킬 수 있을 뿐만 아니라, 메인 칩의 오동작을 막을 수 있는 반도체 소자의 인덕터 형성방법에 관한 것이다. The present invention relates to a method for forming an inductor of a semiconductor device, and more particularly, by preventing an electric field of an inductor from escaping to a silicon substrate, not only can improve the efficiency of the inductor, but also prevent the malfunction of the main chip. A method of forming an inductor of a semiconductor device.

통신 산업의 발전, 특히 개인용 휴대 통신의 발전으로 인해 RF(radio frequency) 아날로그(analog) 소자의 개발이 필요함에 따라 수동소자인 인덕터의 집적화가 요구되어 지고 있다. 일반적으로 반도체 소자의 인덕터는 최상층의 금속층을 코일(coil)부로 사용한다. 이 코일은 나선(spiral) 형태로 평면상에 형성된다.Due to the development of the communication industry, in particular, the development of personal mobile communication, the development of radio frequency (RF) analog devices is required. Therefore, integration of passive inductors is required. In general, an inductor of a semiconductor device uses a metal layer of the uppermost layer as a coil part. The coil is formed on a plane in the form of a spiral.

이하, 첨부된 도면을 참고하여 종래 기술의 반도체 소자의 인덕터 형성방법에 대하여 설명하면 다음과 같다. Hereinafter, an inductor forming method of a semiconductor device of the prior art will be described with reference to the accompanying drawings.

도 1은 종래의 기술에 따른 반도체 소자의 인덕터 형성방법을 설명하기 위한 단면도이고, 도 2는 종래의 기술에 따른 반도체 소자 인덕터의 평면도이다. 1 is a cross-sectional view for describing a method of forming an inductor of a semiconductor device according to the prior art, and FIG. 2 is a plan view of the semiconductor device inductor according to the prior art.

도 1에 도시된 바와 같이, 소정의 하부 구조가 구비된 실리콘 기판(10) 상부에 공지의 방식들에 의해 회로 소자(11)를 형성한다. 여기서, 상기 회로 소자(11)는 모스트랜지스터, 층간절연막, 다층 금속배선 등을 포함할 수 있다. 이어서, 상기 회로 소자(11)가 형성된 실리콘 기판(10) 상부에 금속막(미도시)을 증착한 다 음, 상기 금속막을 패터닝하여 동일 평면상에 최종 금속배선(12) 및 인덕터(13)를 형성한다. 이때, 상기 인덕터(13)는 도 2에 도시된 바와 같이, 나선(spiral) 형태를 갖도록 패터닝한다. As shown in FIG. 1, the circuit element 11 is formed on the silicon substrate 10 provided with a predetermined substructure by known methods. Here, the circuit element 11 may include a MOS transistor, an interlayer insulating film, a multilayer metal wiring, or the like. Subsequently, a metal film (not shown) is deposited on the silicon substrate 10 on which the circuit element 11 is formed, and then the metal film is patterned to form the final metal wiring 12 and the inductor 13 on the same plane. Form. In this case, the inductor 13 is patterned to have a spiral shape, as shown in FIG. 2.

이후, 상기 최종 금속배선(12) 및 인덕터(13)가 형성된 기판 결과물 상부에 보호막(14)을 형성한다. Thereafter, the passivation layer 14 is formed on the substrate resulting from the final metallization 12 and the inductor 13.

도 3은 종래의 기술에 따른 문제점을 설명하기 위한 단면도이다. 3 is a cross-sectional view for explaining a problem according to the related art.

그러나, 종래의 기술에서는, 도 3에 도시된 바와 같이, 나선형의 형태로 평면상에 형성된 인덕터(13)와 실리콘 기판(10)의 사이에 전기장이 형성되는데, 이러한 전기장이 실리콘 기판(10)으로 빠져나가게 되어('A' 참조), 전기장의 손실이 일어나, 결국, 인덕터의 효율이 저하된다. 또한, 이렇게 실리콘 기판(10)으로 빠져나간 전기장은 실리콘 기판(10) 내에 전류를 유도하여, 메인 칩으로 원하지 않는 전류가 흐르게 되며('B' 참조), 이는 메인 칩에 영향을 주어 오동작을 유발시킨다. However, in the related art, as shown in FIG. 3, an electric field is formed between the inductor 13 and the silicon substrate 10 formed on the plane in the form of a spiral, and the electric field is transferred to the silicon substrate 10. Escape (see 'A') leads to loss of the electric field, which in turn lowers the efficiency of the inductor. In addition, the electric field exited to the silicon substrate 10 induces a current in the silicon substrate 10, causing unwanted current to flow to the main chip (see 'B'), which affects the main chip and causes a malfunction. Let's do it.

따라서, 본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로서, 인덕터의 전기장이 실리콘 기판으로 빠져나가는 것을 막음으로써, 인덕터의 효율을 개선시킬 수 있을 뿐만 아니라, 상기 실리콘 기판으로 빠져나가는 전기장에 의한 메인 칩의 피해를 감소시킬 수 있는 반도체 소자의 인덕터 형성방법을 제공함에 그 목적이 있다. Accordingly, the present invention has been made to solve the above problems, and by preventing the inductor's electric field from escaping to the silicon substrate, not only can improve the efficiency of the inductor, but also due to the electric field escaping to the silicon substrate. It is an object of the present invention to provide a method of forming an inductor of a semiconductor device capable of reducing damage of a main chip.

상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 인덕터 형성방 법은, 액티브영역과 필드영역이 정의된 실리콘 기판을 제공하는 단계; 상기 실리콘 기판 상에 상기 기판의 필드영역을 노출시키는 패드산화막 및 패드질화막을 차례로 형성하는 단계; 상기 패드질화막을 식각 장벽으로 이용하여 상기 기판을 식각하여 트렌치를 형성하는 단계; 상기 패드질화막 및 패드산화막을 제거하는 단계; 상기 트렌치 구조를 매립하는 소자분리막을 형성하는 단계; 상기 소자분리막을 선택적으로 식각하여 다수개의 홈을 형성하는 단계; 상기 홈 구조를 매립하는 각각의 도전막 패턴을 형성하는 단계; 상기 도전막 패턴을 포함한 상기 실리콘 기판 상부에 공지의 방식들에 의해 회로 소자를 형성하는 단계; 및 상기 회로 소자가 형성된 기판 상부의 상기 도전막 패턴과 대응되는 부위에 인덕터를 형성하는 단계를 포함한다. In order to achieve the above object, an inductor forming method of a semiconductor device of the present invention includes providing a silicon substrate having an active region and a field region defined therein; Sequentially forming a pad oxide film and a pad nitride film exposing the field region of the substrate on the silicon substrate; Etching the substrate to form a trench using the pad nitride layer as an etch barrier; Removing the pad nitride film and the pad oxide film; Forming an isolation layer to fill the trench structure; Selectively etching the device isolation layer to form a plurality of grooves; Forming respective conductive film patterns to fill the groove structures; Forming a circuit element on the silicon substrate including the conductive film pattern by known methods; And forming an inductor at a portion corresponding to the conductive layer pattern on the substrate on which the circuit element is formed.

여기서, 상기 도전막 패턴은 알루미늄막으로 이루어지거나, 또는, 표면에 실리사이드층이 형성된 다결정실리콘막으로 이루어지며, 이때, 상기 실리사이드층은 코발트 실리사이드층이다. Here, the conductive film pattern is made of an aluminum film, or a polysilicon film formed with a silicide layer on the surface, wherein the silicide layer is a cobalt silicide layer.

(실시예)(Example)

이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 4a 내지 도 4g는 본 발명의 실시예에 따른 반도체 소자의 인덕터 형성방법을 설명하기 위한 공정별 단면도이다.4A through 4G are cross-sectional views illustrating processes of forming an inductor of a semiconductor device in accordance with an embodiment of the present invention.

본 발명의 실시예에 따른 반도체 소자의 인덕터 형성방법은, 도 4a에 도시된 바와 같이, 액티브영역(미도시)과 필드영역(미도시)이 정의된 실리콘 기판(20) 상에 패드산화막(21) 및 패드질화막(22)을 차례로 형성한다. In the method of forming an inductor of a semiconductor device according to an embodiment of the present invention, as shown in FIG. 4A, a pad oxide film 21 is formed on a silicon substrate 20 in which an active region (not shown) and a field region (not shown) are defined. ) And the pad nitride film 22 are formed in this order.                     

그런다음, 도 4b에 도시된 바와 같이, 상기 기판(20) 필드영역을 노출시키도록 상기 패드질화막 및 패드산화막을 선택적으로 식각한 후, 상기 식각후 잔류된 패드질화막(22a)을 식각 장벽으로 이용하여 상기 기판(20)을 식각하여 트렌치(23)를 형성한다. 이때, 도 4b에서 미설명된 도면부호 21a는 식각후 잔류된 패드산화막을 나타낸 것이다. 4B, the pad nitride film and the pad oxide film are selectively etched to expose the field region of the substrate 20, and then the pad nitride film 22a remaining after the etching is used as an etching barrier. The substrate 20 is etched to form the trench 23. In this case, reference numeral 21a, which is not described in FIG. 4B, shows the pad oxide film remaining after etching.

이어서, 도 4c에 도시된 바와 같이, 상기 식각후 잔류된 패드질화막 및 패드산화막을 제거하고 나서, 상기 결과의 구조 전면에 상기 트렌치(23) 구조를 매립하도록 절연막(24)을 형성한다. Subsequently, as shown in FIG. 4C, the pad nitride film and the pad oxide film remaining after the etching are removed, and an insulating film 24 is formed to fill the trench 23 structure over the entire structure.

그런후에, 도 4d에 도시된 바와 같이, 상기 기판(20)이 노출될 때까지 상기 절연막을 전면 식각하여 상기 트렌치(23) 구조를 매립하는 소자분리막(24a)을 형성한다. 계속해서, 상기 결과물 상에 홈 형성영역(미도시)을 한정하는 감광막 패턴(25)을 형성한다. Thereafter, as shown in FIG. 4D, the insulating film is etched entirely until the substrate 20 is exposed to form an isolation layer 24a filling the trench 23 structure. Subsequently, a photosensitive film pattern 25 defining a groove forming region (not shown) is formed on the resultant product.

다음으로, 도 4e에 도시된 바와 같이, 상기 감광막 패턴을 식각 장벽으로 이용하여 상기 소자분리막(24a)을 식각하여 다수개의 홈(26)을 형성한 후, 상기 감광막 패턴을 제거한다. 이어서, 상기 결과물 전면에 상기 홈(26) 구조 전체를 매립하도록 도전막(27)을 형성한다. 여기서, 상기 도전막(27)은 알루미늄(Al)막 및 다결정실리콘막 중 어느 하나를 이용하여 형성한다. Next, as illustrated in FIG. 4E, the device isolation layer 24a is etched using the photoresist pattern as an etch barrier to form a plurality of grooves 26, and then the photoresist pattern is removed. Subsequently, a conductive film 27 is formed on the entire surface of the resultant material to fill the entire groove 26 structure. Here, the conductive film 27 is formed using any one of an aluminum (Al) film and a polycrystalline silicon film.

그리고나서, 도 4f에 도시된 바와 같이, 상기 기판(20)이 노출될 때까지 상기 도전막을 전면 식각하여 상기 홈(26) 구조를 매립하는 각각의 도전막 패턴(27a)을 형성한다. 여기서, 상기 도전막 패턴(27a)이 상기 다결정실리콘막으로 형성되었 을 경우에는, 상기 도전막 패턴(27a)의 전기 전도도를 높여주기 위하여, 상기 다결정실리콘막 재질의 도전막 패턴(27a) 표면에 선택적으로 코발트 실리사이드층(Co-silicide)(미도시)을 형성하는 공정을 추가적으로 수행한다. Then, as shown in FIG. 4F, the conductive layer is etched entirely until the substrate 20 is exposed to form respective conductive layer patterns 27a filling the grooves 26. Here, when the conductive film pattern 27a is formed of the polycrystalline silicon film, in order to increase the electrical conductivity of the conductive film pattern 27a, the conductive film pattern 27a is formed on the surface of the conductive film pattern 27a of the polysilicon film material. Optionally, a process of forming a cobalt silicide layer (Co-silicide) (not shown) is additionally performed.

이때, 상기 도전막 패턴(27a)은 알루미늄막 및 표면에 실리사이드층이 형성된 다결정실리콘막 중 어느 하나로 이루어져 있기 때문에, 상기 실리콘 기판(20)에 비해 전기 전도도가 높다. 이와 같은 도전막 패턴(27a)은 이후에 형성될 인덕터의 전기장이 실리콘 기판(20)으로 빠져나가게 되는 것을 막아주는 역할을 하게 된다. At this time, the conductive film pattern 27a is made of any one of an aluminum film and a polysilicon film having a silicide layer formed on the surface thereof, and thus has higher electrical conductivity than the silicon substrate 20. The conductive layer pattern 27a prevents the electric field of the inductor to be formed later from escaping to the silicon substrate 20.

그런후에, 도 4g에 도시된 바와 같이, 상기 도전막 패턴(27a)을 포함한 상기 실리콘 기판(20) 상부에 공지의 방식들에 의해 회로 소자(28)를 형성한다. 여기서, 상기 회로 소자(28)는 모스트랜지스터, 층간절연막, 다층 금속배선 등을 포함할 수 있다. Then, as shown in FIG. 4G, the circuit element 28 is formed on the silicon substrate 20 including the conductive film pattern 27a by known methods. Here, the circuit element 28 may include a MOS transistor, an interlayer insulating film, a multilayer metal wiring, and the like.

그리고나서, 상기 회로 소자(28)가 형성된 실리콘 기판(20) 상부에 금속막(미도시)을 증착한 다음, 상기 금속막을 패터닝하여 동일 평면상에 최종 금속배선(29) 및 인덕터(30)를 형성한다. 이때, 상기 인덕터(30)는 상기 도전막 패턴(27a)과 대응되는 부위에 형성한다. 그리고 나서, 상기 최종 금속배선(29) 및 인덕터(30)가 형성된 기판 결과물 상부에 보호막(31)을 형성한다. Then, a metal film (not shown) is deposited on the silicon substrate 20 on which the circuit element 28 is formed, and then the metal film is patterned to form the final metal wiring 29 and the inductor 30 on the same plane. Form. In this case, the inductor 30 is formed at a portion corresponding to the conductive layer pattern 27a. Then, the passivation layer 31 is formed on the substrate product on which the final metallization 29 and the inductor 30 are formed.

여기서, 상기 인덕터(30)의 작동시에 실리콘 기판(20)쪽을 향해 형성되는 전기장은, 상기 도전막 패턴(27a)쪽으로 집중되어 상기 실리콘 기판(20)을 빠져나가지 못하게 된다. 즉, 상기 도전막 패턴(27a)에 의해 인덕터(30)의 전기장이 손실되는 것을 막을 수 있으며, 이에, 메인 칩으로 전류가 흐르게 되는 것을 차단할 수 있다. 따라서, 인덕터(30)의 효율이 개선되며, 메인 칩의 오동작이 일어나지 않는다.Here, the electric field formed toward the silicon substrate 20 during the operation of the inductor 30 is concentrated toward the conductive layer pattern 27a so as not to escape the silicon substrate 20. That is, the electric field of the inductor 30 may be prevented from being lost by the conductive layer pattern 27a, thereby preventing the current from flowing to the main chip. Therefore, the efficiency of the inductor 30 is improved, and malfunction of the main chip does not occur.

이상에서와 같이, 본 발명은 실리콘 기판에 형성되는 소자분리막에 홈을 형성하고 나서, 상기 홈 구조를 도전막 패턴, 예컨대, 알루미늄막 또는 표면에 실리사이드층이 형성된 다결정실리콘막으로 매립한 후, 상기 도전막 패턴과 대응되는 기판 상부에 인덕터를 형성함으로써, 상기 도전막 패턴에 의해 인덕터의 전기장이 실리콘 기판으로 빠져나가는 것을 방지할 수 있음은 물론, 메인 칩으로 전류가 흐르는 것을 차단할 수 있다. As described above, according to the present invention, after the groove is formed in the device isolation film formed on the silicon substrate, the groove structure is filled with a conductive film pattern, for example, an aluminum film or a polysilicon film having a silicide layer formed on the surface thereof. By forming the inductor on the substrate corresponding to the conductive film pattern, it is possible to prevent the electric field of the inductor from escaping to the silicon substrate by the conductive film pattern, and also to block the flow of current to the main chip.

따라서, 본 발명은 인덕터의 전기장 손실을 막아 인덕터의 효율을 개선시킬 수 있으며, 메인 칩의 오동작을 막을 수 있다.Therefore, the present invention can prevent the inductor electric field loss to improve the efficiency of the inductor, and can prevent the malfunction of the main chip.

Claims (4)

액티브영역과 필드영역이 정의된 실리콘 기판을 제공하는 단계;Providing a silicon substrate in which an active region and a field region are defined; 상기 실리콘 기판 상에 상기 기판의 필드영역을 노출시키는 패드산화막 및 패드질화막을 차례로 형성하는 단계;Sequentially forming a pad oxide film and a pad nitride film exposing the field region of the substrate on the silicon substrate; 상기 패드질화막을 식각 장벽으로 이용하여 상기 기판을 식각하여 트렌치를 형성하는 단계;Etching the substrate to form a trench using the pad nitride layer as an etch barrier; 상기 패드질화막 및 패드산화막을 제거하는 단계;Removing the pad nitride film and the pad oxide film; 상기 트렌치 구조를 매립하는 소자분리막을 형성하는 단계;Forming an isolation layer to fill the trench structure; 상기 소자분리막을 선택적으로 식각하여 다수개의 홈을 형성하는 단계;Selectively etching the device isolation layer to form a plurality of grooves; 상기 홈 구조를 매립하는 각각의 도전막 패턴을 형성하는 단계;Forming respective conductive film patterns to fill the groove structures; 상기 도전막 패턴을 포함한 상기 실리콘 기판 상부에 공지의 방식들에 의해 회로 소자를 형성하는 단계; 및Forming a circuit element on the silicon substrate including the conductive film pattern by known methods; And 상기 회로 소자가 형성된 기판 상부의 상기 도전막 패턴과 대응되는 부위에 인덕터를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 인덕터 형성방법.And forming an inductor in a portion corresponding to the conductive layer pattern on the substrate on which the circuit element is formed. 제 1 항에 있어서, 상기 도전막 패턴은 알루미늄막으로 이루어진 것을 특징으로 하는 반도체 소자의 인덕터 형성방법.The method of claim 1, wherein the conductive layer pattern is formed of an aluminum layer. 제 1 항에 있어서, 상기 도전막 패턴은 표면에 실리사이드층이 형성된 다결정실리콘막으로 이루어진 것을 특징으로 하는 반도체 소자의 인덕터 형성방법.The method of claim 1, wherein the conductive film pattern is formed of a polysilicon film having a silicide layer formed on a surface thereof. 제 3 항에 있어서, 상기 실리사이드층은 코발트 실리사이드층인 것을 특징으로 하는 반도체 소자의 인덕터 형성방법.The method of claim 3, wherein the silicide layer is a cobalt silicide layer.
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KR100842475B1 (en) * 2006-12-28 2008-07-01 동부일렉트로닉스 주식회사 Method of forming the spiral inductor of semiconductor device
KR101299217B1 (en) * 2012-01-17 2013-08-22 전자부품연구원 Semiconductor device and method for manufacturing the same
KR20170029126A (en) 2015-09-07 2017-03-15 전자부품연구원 Passive device and manufacturing method thereof

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KR19990055422A (en) * 1997-12-27 1999-07-15 정선종 Inductor device on silicon substrate and manufacturing method thereof
KR20020014225A (en) * 2000-08-17 2002-02-25 박종섭 Integrated device having insulator layer in trench overlapped with fine inductor and method for foming the same
KR100880794B1 (en) 2002-07-05 2009-02-02 매그나칩 반도체 유한회사 Inductor of secmiconductor device and method for forming the same
KR20050011091A (en) * 2003-07-21 2005-01-29 매그나칩 반도체 유한회사 Method for manufacturing inductor incorporating thereinto shield layer

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KR100842475B1 (en) * 2006-12-28 2008-07-01 동부일렉트로닉스 주식회사 Method of forming the spiral inductor of semiconductor device
KR101299217B1 (en) * 2012-01-17 2013-08-22 전자부품연구원 Semiconductor device and method for manufacturing the same
KR20170029126A (en) 2015-09-07 2017-03-15 전자부품연구원 Passive device and manufacturing method thereof

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