TWI474463B - Semiconductor structure - Google Patents

Description

Semiconductor structure

The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure having a contact pad structure and a protective structure.

With the development of technology and the development of semiconductor technology, electronic components have been successfully applied to various aspects of life. Micro-electro-mechanical system (MEMS) technology is a process for manufacturing micro-mechanical components by a conventional semiconductor process, and a micro-sized mechanical component can be completed by semiconductor technology such as electroplating or etching. Common applications include voltage control components used in inkjet printers, gyroscopes used to detect car tilt in automobiles, or diaphragms used to sense sound in microphones. Since the MEMS technology can integrate the mechanical structure and the electronic circuit, it can be batch-made, and has the advantages of low cost, high quality, and high integration.

Currently, MEMS are integrated on a single wafer using the concept of system on chip (SOC), especially in a standard complementary metal oxide semiconductor (CMOS) process, such as in the same die (die) The MEMS region and the CMOS region are simultaneously formed. In the process of integrating existing CMOS and MEMS systems, many problems may arise. For example, when forming a CMOS area component or a MEMS system, processes between regions may affect each other and interfere with each other.

Please refer to FIG. 1 , which is a schematic plan view of a conventional microelectromechanical region and a non-microelectromechanical region. As shown in FIG. 1, a MEMS region 104 and a non-microelectromechanical region 102 are provided on a die 100. A microelectromechanical element 106 is disposed in the MEMS region 104, such as a diaphragm, a motor, etc.; the non-microelectromechanical region 102 can be a logic region, a memory region, or a peripheral circuit region in which various semiconductor components (not shown) are disposed. For example, various active components or passive components. The surface of the non-microelectromechanical region 102 has a plurality of contact pads 108 that allow external signals to pass through the corresponding contact pads 108 to drive semiconductor components (not shown) in the non-microelectromechanical region 102, or can drive the microelectromechanical regions 104. Microelectromechanical component 106.

Generally, when preparing the microelectromechanical device 106, after completing all kinds of semiconductor processes such as the microelectromechanical device 106, the semiconductor device, and the metal interconnect, the system wafer is subjected to at least one etching process to etch a gas (for example, hydrogen). An etchant such as hydrofluoric acid (HF) or an etching solution removes an inter-metal dielectric layer (IMD) in the microelectromechanical region 104 to form various movable or spatial micro-structured microelectromechanical components 106 in the microelectromechanical region 104. .

In the etching process, many problems often arise. For example, in order to prevent the semiconductor components in the non-microelectromechanical region 102 from being damaged during the etching process, a non-microelectromechanical region 102 is typically covered with a mask layer (not shown) to protect the underlying IMD from being etchant. Remove. The mask layer is typically metal, but if the mask layer is completely covered on the non-microelectromechanical region 102, the contact pads 108 are electrically connected together to create a short circuit. On the other hand, if the contact pads 108 are not covered by the mask layer, the etchant readily enters the non-microelectromechanical region 102 along the periphery of the contact pads 108 to break the internal components. On the other hand, when the contact pad 108 is to drive the semiconductor element or the microelectromechanical element 106, the circuit layout must also be properly considered to avoid mutual short circuit and interference.

Accordingly, the present invention provides a semiconductor structure that avoids the phenomenon of short circuits between the contact pad structures, and also prevents the etchant from penetrating into the non-microelectromechanical region along the contact pad structure, and through various embodiments, the contact pads of the present invention The structure also has excellent electrical conduction quality when connecting semiconductor components or microelectromechanical components.

According to the scope of the patent application, the present invention proposes a semiconductor structure. The semiconductor structure includes a substrate, a dielectric layer, a contact pad structure, and a protective structure. The dielectric layer is disposed on the substrate. The contact pad structure is disposed in the dielectric layer, and includes a plurality of first metal layers and a plurality of plugs electrically connected to each other, wherein the contact pad structure and the substrate do not have a contact plug (contact Plug). The protective structure is disposed in the dielectric layer that surrounds the contact pad structure.

According to the scope of the patent application, the present invention proposes another semiconductor structure. The semiconductor structure includes a substrate, a dielectric layer, a contact pad structure, an insulating structure, and a protective structure. The dielectric layer is disposed on the substrate. The contact pad structure is disposed in the dielectric layer, and includes a plurality of first metal layers and a plurality of plugs electrically connected to each other. The insulating structure is disposed between the substrate and the contact pad structure. The protective structure is disposed in the dielectric layer that surrounds the contact pad structure.

According to the scope of the patent application, the present invention proposes another semiconductor structure. The semiconductor structure includes a substrate, a dielectric layer, a contact pad structure, and a protective structure. The dielectric layer is disposed on the substrate. The contact pad structure is disposed in the dielectric layer, and comprises a plurality of first metal layers and a plurality of plugs electrically connected to each other, wherein the width of the first metal layer of at least one layer and the first metal layer of the other layers The width is different. The protective structure is disposed in the dielectric layer that surrounds the contact pad structure.

The protective structure of the present invention prevents the etchant from entering the non-microelectromechanical region, and the contact pad structure can drive the semiconductor component or the microelectromechanical component as the input and output of the signal. The contact pad structure and the substrate are electrically insulated to have better electrical transmission quality.

Please refer to FIG. 2, which is a schematic plan view of the microelectromechanical region and the non-microelectromechanical region in the present invention. For the convenience of description, the second drawing is illustrated by the symbol of Fig. 1. As shown in FIG. 2, a MEMS region 104 and a non-microelectromechanical region 102 are provided on a die 100. A microelectromechanical element 106 is disposed in the MEMS region 104, such as a diaphragm, a motor, etc.; the non-microelectromechanical region 102 can be a logic region, a memory region, or a peripheral circuit region in which various semiconductor components (not shown) are disposed. For example, various active components or passive components. The surface of the non-microelectromechanical region 102 has a plurality of contact pad structures 114 that allow external signals to pass through the corresponding contact pad structure 114 to drive semiconductor components (not shown) in the non-microelectromechanical region 102, or can drive the microelectromechanical region. Microelectromechanical component 106 in 104.

Please refer to FIG. 3 and FIG. 4, which is a plan view of the semiconductor structure of the present invention, which is an enlarged view of a region C in FIG. Fig. 4 is a schematic cross-sectional view taken along line AA' in Fig. 3. The semiconductor structure of the present invention comprises a substrate 110, a dielectric layer 112, a contact pad structure 114, a protective structure 116, and a mask layer 128. As shown in FIG. 3, the contact pad structure 114 is disposed in the non-microelectromechanical region 102, which may be formed with a wire bonding structure, etc., and the external signal may pass through the contact pad structure 114 to drive the semiconductor device (not shown). Or microelectromechanical component 106.

The mask layer 128 of the present invention, while overlying the non-microelectromechanical region 102, does not overlie the contact pad structure 114 to avoid contact of the mask layer 128 and the contact pad structure 114 as described in the prior art. Short circuit problem. At the same time, in order to prevent the etchant 122 from entering the non-microelectromechanical region 102 from the area around the contact pad structure 114, the present invention will have a protective structure 116 around the contact pad structure 114.

For an introduction to the structure of the details, please refer to Figure 4. Contact pad structure 114 and protective structure 116 are disposed in dielectric layer 112 on substrate 110. The material of the dielectric layer 112 may be yttrium oxide (SiO ₂ ), tetraethoxy decane (TEOS), plasma reinforced tetraethoxy decane (PETEOS) or various interlayer dielectric materials.

As shown in FIG. 4, the contact pad structure 114 includes a plurality of first metal layers 118 and a plurality of plugs 120. Each of the first metal layers 118 is alternately disposed in the dielectric layer 112 and connected up and down by the plugs 120 to form a stack structure. That is, the first metal layers 118 have a layered structure, and the plugs 120 are disposed between the first metal layers 118. Embodiments of the plug 120 can be independent columnars, or separate metal barriers, or patterned metal consisting of a plurality of columnar holes or a plurality of metal walls. Floor. The implementation of the plugs 120 between the first metal layers 118 (i.e., different layers) may be the same or different, and the principles are based on the contact pad structure 114 capable of supporting and stabilizing the stack. In a preferred embodiment of the invention, each plug 120 forms a closed annular structure and surrounds the dielectric layer 112 between each of the first metal layers 118, respectively. In this way, when the etchant 122 such as hydrofluoric acid is introduced, the dielectric layer 112 inside the contact pad structure 114 is not removed, and each plug 120 can effectively contact the first metal layer. 118, and form the most stable structure. The first metal layer 118 and the plug 120 comprise various conductive materials, such as metal tungsten, aluminum or copper, such that each of the first metal layers 118 and the plugs 120 are electrically connected to each other.

In order to ensure that the etchant 122 does not hollow out the dielectric layer 112 during etching, the semiconductor structure of the present invention also has a protective structure 116 and a mask layer 128. The mask layer 128 is disposed over the dielectric layer 112, covering the non-microelectromechanical regions 102, and exposing the contact pad structures 114 and the microelectromechanical regions 104. The material of the mask layer 128 includes various materials of the etch resist 122. For example, when the etchant 122 is hydrofluoric acid, the mask layer 128 is preferably metal aluminum. The protective structure 116 is disposed around the contact pad structure 114 and surrounds the contact pad structure 114. The protective structure 116 will contact the mask layer 128 upwardly and will contact the substrate 110 downwardly to form a top-down complete etch-resistant structure. The protective structure 116 includes a plurality of second metal layers 124 and a plurality of guard rings 126 as seen in detail. Each of the second metal layers 124 has a layered structure, and each of the guard rings 126 is disposed between each of the second metal layers 124. The guard ring 126 is a continuous annular structure, and the material thereof may include metal tungsten, aluminum metal, amorphous silicon or silicon nitride or other etchant capable of resisting hydrofluoric acid (HF). 122 etched material. In this embodiment, the protective structure 116 may have only a single guard ring 126 between the two adjacent second metal layers 124 or, as the case may be, a plurality of guard rings 126 disposed in parallel with each other on the dielectric layer 112. Medium and collectively surround the contact pad structure 114. The planar layout of the guard ring 126 may be a closed structure of various polygons, a circle, etc., and the guard ring 126 of FIG. 3 is illustrated as a square, but is not limited thereto. The shape of each of the guard rings 126 located on the same layer or different layers may be the same or different, in order to be able to close the contact pad structure 114 and substantially contact the second metal layers 124 up and down.

When the contact pad structure 114 and the protective structure 116 are both composed of metal, they can be simultaneously formed by the same metallization process. For example, when any of the first metal layers 118 of the contact pad structure 114 is formed, the second metal layer 124 of the same layer of the protection device 116 is also formed. Next, the plug 120 on which the contact pad structure 114 is formed also forms the guard ring 126 of the protection device 116. Therefore, by using various metal interconnect processes and adjusting the layout of the formed plurality of metal circuit layers and the plurality of plugs connecting the metal layers, the current semiconductor process can be effectively integrated into the metal interconnect. In the wire process, the desired contact pad structure 114 and the protective structure 116 are formed simultaneously. It should be noted, however, that the first metal layer 118 and the plug 120 in the contact pad structure 114 must be electrically insulated from the protection structure 116 to avoid short circuit. However, if the guard ring 126 of the protective structure 116 is formed of an insulating material, such as nitrogen nitride, the contact pad structure 114 may be in contact with the guard ring 126 of the insulating material, but the electrical insulation is generally based on the principle.

On the other hand, in order to prevent the contact pad structure 114 from receiving an input or output current message, the current message may leak through the substrate 110, and the contact pad structure 114 of the present invention is electrically insulated from the substrate 110. In one embodiment of the invention, there is no contact plug between the contact pad structure 114 of the present invention and the substrate 110. That is, there is no contact plug or other similar structure between the first metal layer 118 (usually the first metal layer formed in the semiconductor process, metal one) and the substrate 110 in the lowermost layer of the contact pad structure 114. The lowermost first metal layer 118 and the substrate 110 are electrically connected. There is only a dielectric layer 112 between the contact pad structure 114 and the substrate 110.

In another embodiment of the present invention, the contact pad structure 114 and the substrate 110 of the present invention may further have an insulating structure. Please refer to FIG. 5, which is a schematic view of another embodiment of the semiconductor structure of the present invention. There is an insulating structure between the contact pad structure 114 and the substrate 110. The insulating structure can be, for example, a shallow trench isolation (STI) 130 or other suitable structure. The shallow trench isolation 130 can be completed in conjunction with a general MOS isolation process, such as etching a trench on the substrate 110 and filling the insulating material like yttrium oxide. Contact pad structure 114 is disposed directly on shallow trench isolation 130 and is insulated from substrate 110 by shallow trench isolation 130.

Since the insulating structure of the shallow trench isolation 130 or the like can provide a good insulating effect, in this embodiment, the contact plug 131 can also be disposed between the contact pad structure 114 and the shallow trench isolation 130 so that the contact pad structure 114 can Get better support. As shown in FIG. 5, in the embodiment of the present invention, a material layer 132 may be further disposed on the insulating structure of the shallow trench isolation 130 or the like, for example, a polycrystalline germanium layer prepared by a polysilicon gate process, or may be provided. Good support effect.

Please refer to FIG. 6 , which is a schematic diagram of a third embodiment of the semiconductor structure of the present invention. As shown in FIG. 6, when the etchant 122 is applied, the etchant 122 removes the dielectric layer 112 there along the gap between the contact pad structure 114 and the protective structure 116. In order to prevent the contact pad structure 114 from being unstable due to excessive removal of the dielectric layer 112 around and under the contact pad structure 114, the cross-sectional area, that is, the length or width of each of the first metal layers 118 of the present invention may be identical. As shown in FIG. 6, in the contact pad structure 114, at least one of the first metal layers 118 has a different length or width than the length or width of the first metal layer 118 of the other layers. As such, the path between the etchant 122 entering the contact pad structure 114 and the protective structure 116 is elongated to prevent the etchant 122 from invading and removing the dielectric layer 112 around the underlying pad structure 114. The widened first metal layer 118 is not limited to a single layer, and may be a plurality of layers, which may be arbitrarily arranged. Of course, this embodiment can also be combined with other embodiments, for example, the contact pad structure 114 has a widened first metal layer 118, and has an insulating structure with a shallow trench isolation 130 and the like between the substrate 110, as shown in FIG. Show.

Next, please refer to FIG. 8 , which is a schematic diagram of the contact pad structure being outwardly connected in the present invention. As shown in FIG. 8, the contact pad structure 114 further includes a metal trace 133 as a via for electrically connecting the contact pad structure 114 to other semiconductor components (not shown) or to the microelectromechanical component 106. The metal trace 133 can be connected to an active or passive component in the non-microelectromechanical region 102, or, as shown in FIG. 2, the metal trace 133 can be coupled to the signal input of the MEMS element 106 to drive the MEMS component. 106. As previously mentioned, the contact pad structure 114 and the protective structure 116 must maintain electrical isolation to avoid short circuits. Therefore, the protective structure 116 is provided with an opening 134 corresponding to the passage of the metal wire 133 for the metal wire 133 to pass. Please refer to FIG. 9 for a schematic plan view of the metal wiring and the second metal layer of the same layer in the present invention. As shown in FIG. 9, the protective structure 116 will have an opening 134 in the second metal layer 128 such that the metal line 133 can pass. The opening 134 is preferably disposed in the lower second metal layer 128, such as the lowermost second metal layer 128, to reduce the chance of the etchant 122 entering the non-microelectromechanical region 102 along the opening 134.

In summary, the present invention provides a semiconductor structure that primarily includes a contact pad structure and a protective structure. The protective structure can prevent the etchant from entering the non-microelectromechanical region to destroy the internal components; the contact pad structure can be connected to other semiconductor components or microelectromechanical components as the input and output of the signal, and through various embodiments of the present invention, the contact pad structure It is electrically insulated from the substrate to maintain the electrical transfer quality of the contact pad structure.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧ grain

102‧‧‧Non-micro-electromechanical area

104‧‧‧Microelectromechanical area

106‧‧‧Microelectromechanical components

108‧‧‧Contact pads

110‧‧‧Base

112‧‧‧ dielectric layer

114‧‧‧Contact pad structure

116‧‧‧Protection structure

118‧‧‧First metal layer

120‧‧‧ plug

122‧‧‧ etchant

124‧‧‧Second metal layer

126‧‧‧Protection ring

128‧‧‧mask layer

130‧‧‧Insulation structure

131‧‧‧Contact plug

132‧‧‧ material layer

133‧‧‧Metal connection

134‧‧‧ openings

Figure 1 is a schematic plan view of a conventional microelectromechanical region and a non-microelectromechanical region.

Figure 2 is a schematic plan view of a microelectromechanical region and a non-microelectromechanical region in the present invention.

Figure 3 is a plan view of the semiconductor structure of the present invention.

4 to 7 are schematic views of an embodiment of a semiconductor structure of the present invention.

8 to 9 are schematic views showing the outward connection of the contact pad structure in the present invention.

110. . . Base

112. . . Dielectric layer

114. . . Contact pad structure

116. . . Protective structure

118. . . First metal layer

120. . . Plug

122. . . Etchant

124. . . Second metal layer

126. . . Protection ring

128. . . Mask layer

Claims (20)

A semiconductor structure comprising: a substrate; a dielectric layer disposed on the substrate; a contact pad structure disposed in the dielectric layer, the contact pad structure comprising a plurality of first metal layers and a plurality of plugs ( The plugs are electrically connected to each other, wherein the contact pad structure and the substrate do not have a contact plug; and a protective structure is disposed in the dielectric layer, wherein the protection structure surrounds the contact The pad structure and contacts the substrate downward. The semiconductor structure of claim 1, wherein the contact pad structure is electrically insulated from the protective structure. The semiconductor structure of claim 1, wherein each of the plugs forms a ring structure and surrounds the dielectric layer in the contact pad structure, respectively. The semiconductor structure of claim 1, further comprising a mask layer disposed on the dielectric layer, wherein the protective structure contacts the mask layer upwardly and contacts the substrate downward. The semiconductor structure of claim 1, wherein the protective structure comprises a plurality of second metal layers and a plurality of guard rings connected to each other. A semiconductor structure comprising: a substrate; a dielectric layer disposed on the substrate; a contact pad structure disposed in the dielectric layer, the contact pad structure comprising a plurality of first metal layers and a plurality of plugs ( The plugs are electrically connected to each other; an insulating structure is disposed between the substrate and the contact pad structure; and a protective structure is disposed in the dielectric layer, wherein the protective structure surrounds the contact pad structure and is downward Contact the substrate. The semiconductor structure of claim 6, wherein the insulating structure comprises a shallow trench isolation. The semiconductor structure of claim 6 further comprising a material layer disposed between the insulating structure and the contact pad structure, wherein the material layer comprises polysilicon. The semiconductor structure of claim 6, wherein the contact pad structure is electrically insulated from the protective structure. The semiconductor structure of claim 6, wherein each of the plugs forms a ring structure and surrounds the dielectric layer in the contact pad structure, respectively. The semiconductor structure of claim 6, further comprising a mask layer disposed on the dielectric layer, wherein the protection structure contacts the mask layer upwardly and contacts the base downward bottom. The semiconductor structure of claim 6, wherein the protective structure comprises a plurality of second metal layers and a plurality of guard rings connected to each other. A semiconductor structure comprising: a substrate; a dielectric layer disposed on the substrate; a contact pad structure disposed in the dielectric layer, the contact pad structure comprising a plurality of first metal layers and a plurality of plugs, Electrically connected to each other, wherein at least one of the first metal layers has a cross-sectional area different from that of the other layers; and a protective structure is disposed in the dielectric layer, wherein the protection A structure surrounds the contact pad structure and contacts the substrate downwardly. The semiconductor structure of claim 13, wherein the contact pad structure and the substrate do not have a contact plug. The semiconductor structure of claim 13 further comprising an insulating structure disposed between the substrate and the contact pad structure. The semiconductor structure of claim 15 further comprising a material layer disposed between the insulating structure and the contact pad structure, wherein the material layer comprises polysilicon. The semiconductor structure of claim 13, wherein the contact pad structure is electrically insulated from the protective structure. The semiconductor structure of claim 13, wherein each of the plugs forms a ring structure and surrounds the dielectric layer in the contact pad structure, respectively. The semiconductor structure of claim 13 further comprising a mask layer disposed on the dielectric layer, wherein the protective structure contacts the mask layer upwardly and contacts the substrate downward. The semiconductor structure of claim 13, wherein the protective structure comprises a plurality of second metal layers and a plurality of guard rings connected to each other.