JP2011009515A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2011009515A
JP2011009515A JP2009152261A JP2009152261A JP2011009515A JP 2011009515 A JP2011009515 A JP 2011009515A JP 2009152261 A JP2009152261 A JP 2009152261A JP 2009152261 A JP2009152261 A JP 2009152261A JP 2011009515 A JP2011009515 A JP 2011009515A
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interlayer insulating
conductive pattern
layer
pad
semiconductor device
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Kazuhiro Tashiro
一宏 田代
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Fujitsu Semiconductor Ltd
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Fujitsu Semiconductor Ltd
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Abstract

PROBLEM TO BE SOLVED: To manufacture a reliable semiconductor device efficiently.SOLUTION: This semiconductor device has: a plurality of interlayer insulating films 16, 19, 22 stacked on a semiconductor substrate 1; a pad 25 which is formed on uppermost faces of the plurality of interlayer insulating films 16, 19, 22, and has a probe contact region to which a probe is applied from the outside; wirings 12, 15, and 18 of a plurality of layers formed between the plurality of interlayer insulating films 16, 19, 22; and a stress relaxation 42 which is formed in a region beneath the probe contact region of the pad 25, and has a conductive pattern having at least one of a nonlinear slit and a hole charged with the interlayer insulating film 22.

Description

本発明は、半導体装置に関する。   The present invention relates to a semiconductor device.

近年、電子機器等の高機能化や高性能化が求められており、これに伴って電子機器等に搭載される半導体装置の高集積化や高速化、大容量化が求められている。このため、半導体装置は、外部接続端子の数が増加すると共に、その大きさも縮小する傾向にある。
また、半導体装置の小型化に伴って、外部接続端子の配置間隔が狭くなったり、半導体装置を構成する半導体膜や絶縁膜などの膜厚が薄くなったりしている。さらに、半導体装置に含まれる素子の電気的特性を向上させることを目的として層間絶縁酸化膜に低誘電率膜を採用した場合には、層間絶縁酸化膜の機械的強度が低下することが知られている。 In recent years, there has been a demand for higher functionality and higher performance of electronic devices and the like, and accordingly, there has been a demand for higher integration, higher speed, and larger capacity of semiconductor devices mounted on electronic devices and the like. For this reason, the semiconductor device tends to decrease in size as the number of external connection terminals increases.
Further, with the miniaturization of the semiconductor device, the arrangement interval of the external connection terminals is narrowed, and the film thickness of a semiconductor film, an insulating film, or the like constituting the semiconductor device is reduced. Furthermore, it is known that when a low dielectric constant film is used as an interlayer insulating oxide film for the purpose of improving the electrical characteristics of elements included in the semiconductor device, the mechanical strength of the interlayer insulating oxide film decreases. ing.

ここで、半導体装置の製造工程で実施される検査工程では、半導体装置の外部接続端子に試験用のプローブを所定の圧力で押し当てて、半導体装置と試験装置を電気的に導通状態にする必要がある。
しかしながら、近年の半導体装置では外部接続端子の配置間隔が狭くなっているので、それぞれの外部接続端子にプローブを適切な接触荷重で接触させることが困難になっている。この場合の適切な荷重とは、電気的な接触を得るために必要とされ、接触不良を生じない荷重以上で、且つ半導体装置が機械的に破壊しない程度の荷重である。 Here, in the inspection process performed in the manufacturing process of the semiconductor device, it is necessary to press the test probe against the external connection terminal of the semiconductor device with a predetermined pressure so that the semiconductor device and the test device are in an electrically conductive state. There is.
However, in recent semiconductor devices, since the arrangement interval of the external connection terminals is narrow, it is difficult to bring the probe into contact with each external connection terminal with an appropriate contact load. An appropriate load in this case is a load that is necessary for obtaining electrical contact, is a load that does not cause a contact failure, and that does not mechanically destroy the semiconductor device.

接触荷重が大きくなり過ぎると、外部接続端子の下層の層間絶縁酸化膜にクラックが生じたり、リーク電流が発生したりする原因になる可能性がある。半導体装置の小型化、高集積化に伴って、適切な接触荷重の範囲が狭くなる傾向にあるため、検査工程における接触不良の発生や層間絶縁酸化膜のクラック発生を抑制する必要があった。   If the contact load becomes too large, cracks may occur in the interlayer insulating oxide film below the external connection terminal, or a leakage current may be caused. As a semiconductor device is miniaturized and highly integrated, an appropriate contact load range tends to be narrowed. Therefore, it is necessary to suppress the occurrence of contact failure and the generation of cracks in an interlayer insulating oxide film in an inspection process.

そこで、従来の半導体装置では、導電性の外部接続端子の下部に１層の層間絶縁酸化膜及び導体層をダミーとして設け、さらに下層に存在する本来の層間絶縁酸化膜に生じる衝撃負荷を低減させるように構成していた。さらに、外部接続端子の下層の層間絶縁酸化膜への荷重をより低減させることを目的として、外部接続端子の下層の導体層に同じ形状の開口部を等間隔に配置することで、さらに下層の層間絶縁酸化膜への負荷を低減させるように構成していた。   Therefore, in the conventional semiconductor device, a single interlayer insulating oxide film and a conductor layer are provided as a dummy below the conductive external connection terminal, and the impact load generated in the original interlayer insulating oxide film existing in the lower layer is reduced. It was configured as follows. Furthermore, for the purpose of further reducing the load on the interlayer insulating oxide film under the external connection terminal, by arranging the openings of the same shape in the conductor layer under the external connection terminal at equal intervals, The load on the interlayer insulating oxide film is reduced.

特開平５−６７６４５号公報Japanese Patent Laid-Open No. 5-67645 特開平６−２４４２３５号公報JP-A-6-244235 特開平１０−６４９４５号公報Japanese Patent Laid-Open No. 10-64945 特開２００７−２４２６４４号公報JP 2007-242644 A

しかしながら、外部接続端子の下層の導体層に開口部を有する導電性パターンを採用した場合には、層間絶縁酸化膜と導電性パターンの境界に応力が集中し、ここからクラックが生じ易かった。特に、導電性パターンをＣｕやＡｌ等で形成し、層間絶縁酸化膜をＳｉＯ２で形成した場合には、両者の縦弾性係数や横弾性係数の差が大きいことから、層間絶縁酸化膜と導電性パターンの境界に歪みが生じ易く、応力が集中によるクラックが発生し易かった。
本発明は、このような事情を鑑みてなされたものであり、信頼性の高い半導体装置を効率良く製造できるようにすることを主な目的とする。 However, when a conductive pattern having an opening in the conductor layer under the external connection terminal is employed, stress concentrates on the boundary between the interlayer insulating oxide film and the conductive pattern, and cracks are likely to occur therefrom. In particular, when the conductive pattern is formed of Cu, Al, or the like and the interlayer insulating oxide film is formed of SiO 2 , the difference between the longitudinal elastic modulus and the lateral elastic coefficient is large. The boundary of the sex pattern was likely to be distorted, and cracks due to stress concentration were likely to occur.
The present invention has been made in view of such circumstances, and a main object of the present invention is to enable efficient manufacture of a highly reliable semiconductor device.

本願の一観点によれば、半導体基板と、前記半導体基板上に積層された複数の層間絶縁膜と、前記複数の層間絶縁膜の最上面の上に形成され、外部からプローブが当てられるプローブ接触領域を有するパッドと、前記複数の層間絶縁膜の間に形成される複数層の配線と、前記パッドの前記プローブ接触領域の直下の領域に形成され、前記層間絶縁膜が充填される非直線状スリットと孔の少なくともいずれか一方を有する導電性パターンを有する応力緩和部とを有することを特徴とする半導体装置が提供される。   According to one aspect of the present application, a semiconductor substrate, a plurality of interlayer insulating films stacked on the semiconductor substrate, and a probe contact formed on the top surface of the plurality of interlayer insulating films and to which a probe is applied from the outside A pad having a region, a plurality of layers of wiring formed between the plurality of interlayer insulating films, and a non-linear shape formed in a region immediately below the probe contact region of the pad and filled with the interlayer insulating film There is provided a semiconductor device having a stress relaxation portion having a conductive pattern having at least one of a slit and a hole.

また、本発明の別の観点によれば、半導体基板と、前記半導体基板上に積層された複数の層間絶縁膜と、前記複数の層間絶縁膜の最上面の上に形成され、外部からプローブが当てられるプローブ接触領域を有するパッドと、前記複数の層間絶縁膜の間に形成される複数層の配線と、前記パッドの前記プローブ接触領域の直下の領域の全体に形成され、前記プローブ接触領域よりも広い導電膜、絶縁膜のいずれか一方からなる応力緩和部と、を有することを特徴とする半導体装置が提供される。   According to another aspect of the present invention, a probe is formed on a semiconductor substrate, a plurality of interlayer insulating films stacked on the semiconductor substrate, and an uppermost surface of the plurality of interlayer insulating films. A pad having a probe contact area to be applied; a plurality of layers of wiring formed between the plurality of interlayer insulating films; and an entire area immediately below the probe contact area of the pad. And a stress relaxation portion made of either one of a wide conductive film and an insulating film.

本発明によれば、パッドのプローブ接触領域の直下の領域に非直線状スリットと孔の少なくとも一方を設けることにより、プローブの応力により発生しやすいクラックの箇所を応力緩和部内に特定するとともに、それ以外の領域へのクラックの広がりを防止することができる。
また、パッドのプローブ接触領域の直下の領域の全体に設けられた応力緩和部により、プローブによる応力が配線等の導電性パターンの縁部に加わることを防止し、導電性パターンと絶縁膜、特に絶縁酸化膜の境界におけるクラックの発生を防止できる。 According to the present invention, by providing at least one of a non-linear slit and a hole in a region immediately below the probe contact region of the pad, the location of a crack that is likely to occur due to the stress of the probe is specified in the stress relaxation portion, and It is possible to prevent the crack from spreading to other areas.
In addition, the stress relaxation portion provided in the entire region immediately below the probe contact region of the pad prevents stress due to the probe from being applied to the edge portion of the conductive pattern such as the wiring. Generation of cracks at the boundary of the insulating oxide film can be prevented.

図１は、本発明の第１の実施の形態に係る半導体装置の構成を示す断面図である。FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to the first embodiment of the present invention. 図２は、本発明の図１に示す半導体装置においてパッド部の下層の構造を説明する平面図である。FIG. 2 is a plan view for explaining the structure of the lower layer of the pad portion in the semiconductor device shown in FIG. 1 of the present invention. 図３は、本発明の第１の実施の形態の変形例を示す図である。FIG. 3 is a diagram showing a modification of the first embodiment of the present invention. 図４は、本発明の第２の実施の形態に係る半導体装置においてパッド部の下層の構造を説明する平面図である。FIG. 4 is a plan view for explaining the structure of the lower layer of the pad portion in the semiconductor device according to the second embodiment of the present invention. 図５は、本発明の第３の実施の形態に係る半導体装置の構成を示す断面図である。FIG. 5 is a cross-sectional view showing a configuration of a semiconductor device according to the third embodiment of the present invention. 図６は、本発明の図５に示す半導体装置においてパッド部の下層の構造を説明する平面図である。FIG. 6 is a plan view for explaining the structure of the lower layer of the pad portion in the semiconductor device shown in FIG. 5 of the present invention. 図７は、本発明の第４の実施の形態に係る半導体装置の構成を示す断面図である。FIG. 7 is a cross-sectional view showing a configuration of a semiconductor device according to the fourth embodiment of the present invention. 図８は、本発明の図７に示す半導体装置においてパッド部の下層の構造を説明する平面図である。FIG. 8 is a plan view for explaining the structure of the lower layer of the pad portion in the semiconductor device shown in FIG. 7 of the present invention. 図９は、本発明の第４の実施の形態の変形例に係る半導体装置の構成を示す断面図である。FIG. 9 is a cross-sectional view showing a configuration of a semiconductor device according to a modification of the fourth embodiment of the present invention. 図１０は、本発明の図７に示す半導体装置においてパッド部の下層の構造を説明する平面図である。FIG. 10 is a plan view for explaining the structure of the lower layer of the pad portion in the semiconductor device shown in FIG. 7 of the present invention. 図１１は、本発明の第４の実施の形態の変形例に係る半導体装置においてパッド部の下層の構造を説明する平面図である。FIG. 11 is a plan view for explaining the structure of the lower layer of the pad portion in the semiconductor device according to the modification of the fourth embodiment of the present invention.

発明の目的および利点は、請求の範囲に具体的に記載された構成要素および組み合わせによって実現され達成される。前述の一般的な説明および以下の詳細な説明は、典型例および説明のためのものであって、本発明を限定するためのものではない、と理解すべきである。
以下に、図面を参照して本発明の好ましい実施形態を説明する。図面において、同様の構成要素には同じ参照番号が付されている。 The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not intended to limit the invention.
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the drawings, similar components are given the same reference numerals.

（第１実施の形態）
図１に本実施の形態に係る半導体装置の一部分の断面構造を示す。
半導体装置１は、シリコン等からなる半導体基板２の上に、トランジスタ３や図示を省略するその他の機能素子が形成され、その上に層間絶縁酸化膜と導体層を積層させることで多層配線層が形成されている。 (First embodiment)
FIG. 1 shows a partial cross-sectional structure of a semiconductor device according to this embodiment.
In the semiconductor device 1, a transistor 3 and other functional elements (not shown) are formed on a semiconductor substrate 2 made of silicon or the like, and an interlayer insulating oxide film and a conductor layer are stacked thereon to form a multilayer wiring layer. Is formed.

より詳細には、半導体基板２の上には、半導体基板２に形成されたトランジスタ３のゲート電極４６と第１の導電性パターン１１とそれらを覆う第１層間絶縁酸化膜１２とを含んで第１層１４が形成されている。なお、第１の導電性パターン１１は、素子分離絶縁膜１ａ上にシリコン膜から形成され、配線となる。   More specifically, the semiconductor substrate 2 includes a gate electrode 46 of the transistor 3 formed on the semiconductor substrate 2, a first conductive pattern 11, and a first interlayer insulating oxide film 12 covering them. One layer 14 is formed. The first conductive pattern 11 is formed of a silicon film on the element isolation insulating film 1a and serves as a wiring.

また、第１層１４の上には、第２の導電性パターン１５と第２層間絶縁酸化膜１６を含んで第２層１７が形成されている。以降、第２層１７の上には、第３の導電性パターン１８と第３層間絶縁酸化膜１９を含む第３層２０が、第３層２０の上には、第４の導電性パターン２１と第４層間絶縁酸化膜２２を含む第４層２３が、それぞれ形成されている。そして、最上層には、導体層からなる外部接続端子であるパッド２５と、第４層間絶縁酸化膜２２を保護するカバー膜２６とが形成されている。第２、第３の導電性パターン１５、１８は配線であってもよい。また、第２〜第３の導電性パターン１５、１８、２１と同層には図示しない配線が形成されている。   Further, a second layer 17 including a second conductive pattern 15 and a second interlayer insulating oxide film 16 is formed on the first layer 14. Thereafter, the third layer 20 including the third conductive pattern 18 and the third interlayer insulating oxide film 19 is formed on the second layer 17, and the fourth conductive pattern 21 is formed on the third layer 20. And a fourth layer 23 including the fourth interlayer insulating oxide film 22 are formed. In the uppermost layer, a pad 25 that is an external connection terminal made of a conductor layer and a cover film 26 that protects the fourth interlayer insulating oxide film 22 are formed. The second and third conductive patterns 15 and 18 may be wiring. Further, a wiring (not shown) is formed in the same layer as the second to third conductive patterns 15, 18, and 21.

各層間絶縁酸化膜１２，１６，１９，２２は、例えば、シリコン酸化膜で形成されている。シリコン酸化膜の代わりに、低誘電率絶縁材料や、ＳｉＯＣ、有機絶縁材料等で各層間絶縁酸化膜１２〜２２形成しても良い。各導電性パターン１１，１５，１８，２１は、例えば、ＣｕやＣｕの合金、ＡｌやＡｌの合金を用いて形成されている。カバー膜２６は、例えば、シリコン窒化膜から形成されている。   Each interlayer insulating oxide film 12, 16, 19, and 22 is formed of, for example, a silicon oxide film. Instead of the silicon oxide film, the interlayer insulating oxide films 12 to 22 may be formed of a low dielectric constant insulating material, SiOC, an organic insulating material, or the like. Each of the conductive patterns 11, 15, 18, and 21 is formed using, for example, Cu or Cu alloy, Al or Al alloy. The cover film 26 is made of, for example, a silicon nitride film.

パッド２５は、例えば一辺の長さが４０μｍの正方形を有し、その表面や内部に開口部やスリットは形成されていない。パッド２５の底面の周縁部には、複数のプラグ３１が下から電気的に接続されている。プラグ３１は、第４層間絶縁酸化膜２２に形成したビアホールにＣｕ、Ｗなどの導電性物質を埋め込むことで形成されている。   The pad 25 has, for example, a square having a side length of 40 μm, and no opening or slit is formed on the surface or inside thereof. A plurality of plugs 31 are electrically connected to the peripheral edge of the bottom surface of the pad 25 from below. The plug 31 is formed by burying a conductive material such as Cu or W in a via hole formed in the fourth interlayer insulating oxide film 22.

図２に示すように、第４の導電性パターン２１は、パッド２５の下方に配置される部分に、導電性パターン４１，４２を有し、その中央には応力緩和部であるランド部４３が形成されている。導電性パターン４１，４２は、例えば、図示を省略する他の導電性パターンと電気的に接続されて回路を形成するために設けられている。   As shown in FIG. 2, the fourth conductive pattern 21 has conductive patterns 41 and 42 in a portion disposed below the pad 25, and a land portion 43 that is a stress relaxation portion is at the center thereof. Is formed. The conductive patterns 41 and 42 are provided, for example, to form a circuit by being electrically connected to other conductive patterns not shown.

ランド部４３は、導電性パターン４１，４２との間に間隔を持たせて配置されており、電気的には接続されていない。ランド部４３と導電性パターン４１，４２の間には、第４層間絶縁酸化膜２２が埋め込まれている。ランド部４３の平面形状は、例えば直径が１０μｍ〜４０μｍの円形又はこれとほぼ同じ外形を有する楕円形になっている。ランド部４３は、図２の領域Ａで示されるような検査装置のプローブの先端がパッド２５と接触する面の面積より大きくなるように形成されている。   The land portion 43 is disposed with a space between the conductive patterns 41 and 42 and is not electrically connected. A fourth interlayer insulating oxide film 22 is embedded between the land portion 43 and the conductive patterns 41 and 42. The planar shape of the land portion 43 is, for example, a circle having a diameter of 10 μm to 40 μm or an ellipse having substantially the same outer shape. The land portion 43 is formed such that the tip of the probe of the inspection apparatus as shown by the region A in FIG. 2 is larger than the area of the surface in contact with the pad 25.

また、第２及び第３の導電性パターン１５，１８は、パッド２５の下方に配置され、同じ層には図示を省略するその他の導電性パターンを有する。パッド２５の下方に配置される導電性パターンは、回路の一部をなす導電性パターンであっても良いし、ダミーのパターンであっても良い。   The second and third conductive patterns 15 and 18 are disposed below the pad 25 and have other conductive patterns not shown in the same layer. The conductive pattern disposed below the pad 25 may be a conductive pattern forming a part of a circuit or a dummy pattern.

ここで、第３層２０の第３層間絶縁酸化膜１９には、第３の導電性パターン１８と第４の導電性パターン２１を電気的に接続するプラグ３２が形成されている。同様に、第２層１７の第２層間絶縁酸化膜１６には、第２の導電性パターン１５と第３の導電性パターン１８を電気的に接続するプラグ３３が形成されている。第１層１４の第１層間絶縁酸化膜１２には、第１の導電性パターン１１と第２の導電性パターン１５を電気的に接続するプラグ３４が形成されている。   Here, plugs 32 for electrically connecting the third conductive pattern 18 and the fourth conductive pattern 21 are formed in the third interlayer insulating oxide film 19 of the third layer 20. Similarly, a plug 33 that electrically connects the second conductive pattern 15 and the third conductive pattern 18 is formed in the second interlayer insulating oxide film 16 of the second layer 17. A plug 34 for electrically connecting the first conductive pattern 11 and the second conductive pattern 15 is formed in the first interlayer insulating oxide film 12 of the first layer 14.

次に、半導体装置１の製造方法について説明する。
最初に、半導体基板２の表面にトランジスタ３のゲート電極４６を含む第１層１４を形成する。トランジスタ３を形成する工程では、半導体基板２に例えばｐ型不純物としてボロンを導入してｐウェル１３を形成する。さらに、半導体基板２の表面を熱酸化させてゲート絶縁膜４５を形成する。ゲート絶縁膜４５の上に非晶質又は多結晶のシリコン膜を形成し、レジスト膜を用いたドライエッチングによりシリコン膜をパターニングしてゲート電極４６を形成するとともに、第１の導電性パターン１１を形成する。 Next, a method for manufacturing the semiconductor device 1 will be described.
First, the first layer 14 including the gate electrode 46 of the transistor 3 is formed on the surface of the semiconductor substrate 2. In the step of forming the transistor 3, for example, boron is introduced as a p-type impurity into the semiconductor substrate 2 to form the p well 13. Further, the gate insulating film 45 is formed by thermally oxidizing the surface of the semiconductor substrate 2. An amorphous or polycrystalline silicon film is formed on the gate insulating film 45, the silicon film is patterned by dry etching using a resist film to form the gate electrode 46, and the first conductive pattern 11 is formed. Form.

続いて、ゲート電極４６をマスクにしてイオン注入を行い、ゲート電極４６の両側の半導体基板２の表層にｎ型不純物、例えばリンを導入し、ソース／ドレインエクステンション４７を形成する。
この後、ゲート電極４６を含む半導体基板２の上側全面に絶縁膜を形成し、その絶縁膜をエッチバックしてゲート電極４６の両側部分のみを残して絶縁性サイドウィオール４８を形成する。絶縁膜には、例えばＣＶＤ法により形成された酸化シリコン膜が用いられる。 Subsequently, ion implantation is performed using the gate electrode 46 as a mask, and an n-type impurity such as phosphorus is introduced into the surface layer of the semiconductor substrate 2 on both sides of the gate electrode 46 to form source / drain extensions 47.
Thereafter, an insulating film is formed on the entire upper surface of the semiconductor substrate 2 including the gate electrode 46, and the insulating film is etched back to form an insulating sidewall 48 leaving only both side portions of the gate electrode 46. For the insulating film, for example, a silicon oxide film formed by a CVD method is used.

続いて、絶縁性サイドウォール４８とゲート電極４６をマスクにして半導体基板２の表層に砒素等のｎ型不純物を再びイオン注入し、各ゲート電極４６の両側方の半導体基板２に高濃度不純物拡散領域のソース／ドレイン領域４９を形成する。
さらに、ゲート電極４６を含む半導体基板２の上側全面に金属膜をスパッタ法により形成してから加熱することで、金属シリサイド層５０を形成する。 Subsequently, n-type impurities such as arsenic are ion-implanted again into the surface layer of the semiconductor substrate 2 using the insulating sidewall 48 and the gate electrode 46 as a mask, and high-concentration impurity diffusion is performed in the semiconductor substrate 2 on both sides of each gate electrode 46. A source / drain region 49 of the region is formed.
Further, a metal film is formed on the entire upper surface of the semiconductor substrate 2 including the gate electrode 46 by sputtering, and then heated, thereby forming the metal silicide layer 50.

そして、図示を省略するその他の回路を形成すると、第１の導電性パターン１１が完成する。この後、第１の導電性パターン１１と、半導体基板２の露出している部分の全面に第１層間絶縁酸化膜１２を形成する。第１層間絶縁酸化膜１２は、例えば、プラズマ励起型化学気相成長（ＰＥＣＶＤ）法により形成される。   When other circuits not shown are formed, the first conductive pattern 11 is completed. Thereafter, a first interlayer insulating oxide film 12 is formed on the entire surface of the first conductive pattern 11 and the exposed portion of the semiconductor substrate 2. The first interlayer insulating oxide film 12 is formed by, for example, a plasma enhanced chemical vapor deposition (PECVD) method.

さらに、第１層間絶縁酸化膜１２の所定位置に、ビアホールをドライエッチング法により第１の導電性パターン１１に達するまで形成する。その後、ビアホールにＴａ、ＴｉＮやＴｉ等からなるバリアメタル膜をスパッタリングにより形成する。さらにその上に、導電膜としてＣｕやＷをスパッタリングすると、プラグ３４が形成される。このプラグ３４は、第２層１７が形成されたとき、第２の導電性パターン１５と電気的に接続される。
なお、トランジスタ３は、パッド２５の下方から外れた位置に形成しても良い。また、第１層１４では、トランジスタ３以外の素子を形成しても良い。 Further, via holes are formed at predetermined positions of the first interlayer insulating oxide film 12 until the first conductive pattern 11 is reached by dry etching. Thereafter, a barrier metal film made of Ta, TiN, Ti or the like is formed in the via hole by sputtering. Further, when Cu or W is sputtered as a conductive film, a plug 34 is formed thereon. The plug 34 is electrically connected to the second conductive pattern 15 when the second layer 17 is formed.
Note that the transistor 3 may be formed at a position off the lower side of the pad 25. In the first layer 14, elements other than the transistor 3 may be formed.

次に、第２層１７から第４層２３の形成方法について説明する。
第２層１７から第４層２３の各導電性パターン１５，１８，２１は、シングルダマシン
法、デュアルダマシン法等により形成される。
例えば、第２層１７では、層間絶縁酸化膜１６Ａを例えば、ＰＥＣＶＤ法により所定の厚さに形成する。その後、ドライエッチングを行って層間絶縁酸化膜１６Ａの所定位置に溝を形成し、この溝内に第２の導電性パターン１５を形成する導電性物質、例えばＴａバリア層、Ｃｕ層を順に埋め込む。この後、化学機械研磨（ＣＭＰ）法による研磨で、余分な導電性物質を除去すると、第２の導電性パターン１５が形成される。なお、第２の導電性パターン１５には、回路を形成する配線やパッド、素子などが必要に応じて含まれるものとする。 Next, a method for forming the second layer 17 to the fourth layer 23 will be described.
The conductive patterns 15, 18, and 21 of the second layer 17 to the fourth layer 23 are formed by a single damascene method, a dual damascene method, or the like.
For example, in the second layer 17, the interlayer insulating oxide film 16A is formed to a predetermined thickness by, for example, PECVD. Thereafter, dry etching is performed to form a groove at a predetermined position of the interlayer insulating oxide film 16A, and a conductive material that forms the second conductive pattern 15, for example, a Ta barrier layer and a Cu layer is buried in the groove in this order. Thereafter, by removing excess conductive material by chemical mechanical polishing (CMP), the second conductive pattern 15 is formed. Note that the second conductive pattern 15 includes wirings, pads, elements, and the like that form a circuit as necessary.

続いて、層間絶縁酸化膜１６Ａ及び第２の導電性パターン１５の上に、さらに図示しない薄い銅拡散防止膜を下地として有する層間絶縁酸化膜１６Ｂを例えば、ＰＥＣＶＤ法により所定の厚さに形成する。これら層間絶縁酸化膜１６Ａ，１６Ｂ等によって第２層間絶縁酸化膜１６が形成される。銅拡散防止膜としては、例えばシリコン窒化膜を形成する。
そして、第２層間絶縁酸化膜１６の所定位置にもプラグ３３を前記のプラグ３４と同様にして形成する。このプラグ３３は、その上に形成される第３の導電性パターン１８と電気的に接続される。 Subsequently, an interlayer insulating oxide film 16B having a thin copper diffusion prevention film (not shown) as a base is formed on the interlayer insulating oxide film 16A and the second conductive pattern 15 to have a predetermined thickness by, for example, PECVD. . A second interlayer insulating oxide film 16 is formed by these interlayer insulating oxide films 16A and 16B. For example, a silicon nitride film is formed as the copper diffusion preventing film.
Then, a plug 33 is formed at a predetermined position of the second interlayer insulating oxide film 16 in the same manner as the plug 34. The plug 33 is electrically connected to the third conductive pattern 18 formed thereon.

第３層２０及び第４層２３は、第２層１７と同様な工程で形成される。なお、第３層２０の第３層間絶縁酸化膜１９は、層間絶縁酸化膜１９Ａに第３の導電性パターン１８を埋め込んだ後、その上に図示しない薄い銅拡散防止膜を介して層間絶縁酸化膜１９Ｂを形成することで得られる。第４層２３の第４層間絶縁酸化膜２２は、層間絶縁酸化膜２２Ａに第４の導電性パターン２１を埋め込んだ後、その上に図示しない薄い銅拡散防止膜を介して層間絶縁酸化膜２２Ｂを形成することで得られる。   The third layer 20 and the fourth layer 23 are formed in the same process as the second layer 17. Note that the third interlayer insulating oxide film 19 of the third layer 20 is formed by interposing the third insulating pattern 19A in the interlayer insulating oxide film 19A and then interposing the interlayer insulating oxide film via a thin copper diffusion prevention film (not shown) thereon. It is obtained by forming the film 19B. The fourth interlayer insulating oxide film 22 of the fourth layer 23 is formed by embedding the fourth conductive pattern 21 in the interlayer insulating oxide film 22A and then interposing an interlayer insulating oxide film 22B via a thin copper diffusion prevention film (not shown) thereon. Can be obtained by forming

最上層のパッド２５を形成するときは、第４層間絶縁酸化膜２２上にレジストパターンを形成し、レジストパターンの開口部内に金属膜、例えばＡｌを例えばスパッタ法にて堆積させる。このパッド２５は、その周縁部分においてプラグ３１で電気的に接続される。   When forming the uppermost pad 25, a resist pattern is formed on the fourth interlayer insulating oxide film 22, and a metal film, for example, Al is deposited in the opening of the resist pattern by, for example, sputtering. The pad 25 is electrically connected by a plug 31 at the peripheral portion.

パッド２５の形成は、Ａｌを含む多層構造金属膜を形成した後に、レジストパターンをマスクにして多層構造金属膜をエッチングする方法であってもよい。
その後、第４層間絶縁酸化膜２２の上及びパッド２５の上にカバー膜２６を、例えばＰＥＣＶＤにより形成し、ドライエッチングでパッド２５上のカバー膜２６を除去し、パッド２５の上面の中央部分を露出させる。 The formation of the pad 25 may be a method of forming a multilayer structure metal film containing Al and then etching the multilayer structure metal film using a resist pattern as a mask.
Thereafter, a cover film 26 is formed on the fourth interlayer insulating oxide film 22 and the pad 25 by, for example, PECVD, the cover film 26 on the pad 25 is removed by dry etching, and a central portion on the upper surface of the pad 25 is formed. Expose.

このようにして製造した半導体装置１の検査を行うときは、検査装置のプローブをパッド２５に所定の圧力で押し当てる。１つの半導体装置１に対してパッド２５は複数形成されているので、複数のプローブでパッド２５に電圧を印加したり、パッド２５の電位を測定したりすることで、半導体装置１の動作を検査する。   When the semiconductor device 1 manufactured in this way is inspected, the probe of the inspection device is pressed against the pad 25 with a predetermined pressure. Since a plurality of pads 25 are formed for one semiconductor device 1, the operation of the semiconductor device 1 is inspected by applying a voltage to the pad 25 with a plurality of probes or measuring the potential of the pad 25. To do.

この際、プローブは、パッド２５の中央部に押し当てられるように制御される。このため、プローブを押し当てたときに生じる荷重は、主にパッド２５の中央部に作用する。パッド２５の中央部の下方には、ランド部４３が形成されており、しかもランド部４３の面積は、プローブがパッド２５に接触する領域Ａの面積より大きい。したがって、パッド２５の下の第４層２３において、プローブが押し当てられた部分に相当する領域には、第４の導電性パターン２１と層間絶縁酸化膜２２との境界が存在しない。このため、第４層２３に作用する荷重は、主にランド部４３の内側に作用する。その結果、第４層２３において応力が集中することがなくなって、クラックが生じなくなる。   At this time, the probe is controlled so as to be pressed against the center portion of the pad 25. For this reason, the load generated when the probe is pressed mainly acts on the center portion of the pad 25. A land portion 43 is formed below the center portion of the pad 25, and the area of the land portion 43 is larger than the area of the region A where the probe contacts the pad 25. Therefore, in the fourth layer 23 under the pad 25, there is no boundary between the fourth conductive pattern 21 and the interlayer insulating oxide film 22 in the region corresponding to the portion where the probe is pressed. For this reason, the load acting on the fourth layer 23 mainly acts on the inner side of the land portion 43. As a result, stress does not concentrate in the fourth layer 23, and cracks do not occur.

なお、プローブをパッド２５に押し付ける位置は、予め調整されているので、パッド２５の中央から大きくずれることはない。ランド部４３は、プローブの位置ずれも考慮した
大きさに形成されているので、第４層２３における応力集中を効果的に防止できる。 The position where the probe is pressed against the pad 25 is adjusted in advance, so that it does not deviate greatly from the center of the pad 25. Since the land portion 43 is formed in a size that takes into account the positional deviation of the probe, stress concentration in the fourth layer 23 can be effectively prevented.

このように、この実施の形態では、パッド２５の下方に応力緩和部４３として導電性パターンからなるランド部４３を設けてプローブとパッド２５の接触部分の直下に第４の導電性パターン２１と層間絶縁酸化膜２２の双方が形成されないようにしたので、導電性パターンの周縁と層間絶縁膜の境界に応力が集中することがなくなってクラックの発生が防止される。   As described above, in this embodiment, the land portion 43 made of the conductive pattern is provided as the stress relaxation portion 43 below the pad 25, and the fourth conductive pattern 21 and the interlayer are directly below the contact portion between the probe and the pad 25. Since both of the insulating oxide films 22 are not formed, stress is not concentrated on the boundary between the periphery of the conductive pattern and the interlayer insulating film, and the generation of cracks is prevented.

ここで、この実施の形態の変形例について図３を参照して説明する。
この変形例では、パッド２５の下方の第４層２３の第４の導電性パターン２１に、プローブの接触部分の直下の領域に導電性パターンを設けないことで応力緩和部５１を形成している。第４の導電性パターン２１のその他の領域には、導電性パターン４１，４２が形成されている。図３における応力緩和部５１は、第４層間絶縁膜２２から構成され、その周囲の少なくとも一部は導電パターン４１，４２に囲まれている。 Here, a modification of this embodiment will be described with reference to FIG.
In this modification, the stress relaxation portion 51 is formed by not providing the conductive pattern in the region immediately below the contact portion of the probe in the fourth conductive pattern 21 of the fourth layer 23 below the pad 25. . Conductive patterns 41 and 42 are formed in other regions of the fourth conductive pattern 21. The stress relaxation portion 51 in FIG. 3 is composed of the fourth interlayer insulating film 22, and at least a part of the periphery thereof is surrounded by the conductive patterns 41 and 42.

検査時には、パッド２５の中央部にプローブが押し当てられる、これにより、パッド２５の中央部に荷重が作用し、パッド２５の下方の第４層２３の第４の導電性パターン２１の中央部分に荷重が作用する。第４の導電性パターン２１の中央部分には、導電性物質を有しない応力緩和部５１が形成されているので、この領域には導電性物質と層間絶縁酸化膜２２との境界は存在しない。このため、第４層２３において応力が集中することがなくなって、クラックが生じなくなる。   At the time of inspection, the probe is pressed against the central portion of the pad 25, whereby a load acts on the central portion of the pad 25, and the central portion of the fourth conductive pattern 21 of the fourth layer 23 below the pad 25 is applied. A load acts. Since the stress relaxation portion 51 not having a conductive material is formed in the central portion of the fourth conductive pattern 21, there is no boundary between the conductive material and the interlayer insulating oxide film 22 in this region. For this reason, stress does not concentrate in the fourth layer 23, and cracks do not occur.

なお、図２に示すランド部４３及び図３に示す応力緩和部５１は、第４層２３だけでなく、第３層２０にも設けても良い。また、第４層２３が、パッド２５の下方の領域に導電性物質を有しない構造である場合や、パッド２５の下方の第４の導電性パターン２１に導電性物質と層間絶縁酸化膜２２との境界を有しない構成である場合には、第３層２０のみにランド部４３又は応力緩和部５１を形成しても良い。   The land portion 43 shown in FIG. 2 and the stress relaxation portion 51 shown in FIG. 3 may be provided not only in the fourth layer 23 but also in the third layer 20. Further, when the fourth layer 23 has a structure that does not have a conductive material in a region below the pad 25, or the fourth conductive pattern 21 below the pad 25 has a conductive material, an interlayer insulating oxide film 22, and the like. If the configuration does not have the boundary, the land portion 43 or the stress relaxation portion 51 may be formed only in the third layer 20.

（第２の実施の形態）
図４に、本実施の形態の半導体装置の第４層の平面図を示す。なお、この半導体装置の多層配線の構造は、図１と同様である。
第４層２３の第４の導電性パターン２１は、パッド２５の下方に配置されており、導電性パターン４１，４２が形成されている。さらに、導電性パターン４１，４２の一部を、他の部分より細かい、又は複雑な形状の導電性パターン４１Ａ、４２Ａにすることで応力緩和部６１が形成されている。 (Second Embodiment)
FIG. 4 is a plan view of the fourth layer of the semiconductor device of this embodiment. The structure of the multilayer wiring of this semiconductor device is the same as that shown in FIG.
The 4th conductive pattern 21 of the 4th layer 23 is arranged under pad 25, and conductive patterns 41 and 42 are formed. Furthermore, the stress relaxation part 61 is formed by making a part of the conductive patterns 41 and 42 conductive patterns 41A and 42A having finer or complicated shapes than the other parts.

応力緩和部６１は、２つの導電性パターン４１Ａ，４２Ａの櫛歯状の縁部が層間絶縁酸化膜２２を介して互いに噛み合わされた構成を有する。換言すれば、櫛歯状の縁部の間の平面形状は非直線状、例えば波形状のスリットとなり、そのスリット内に層間絶縁酸化膜２２が充填されている。そのスリットは、配線間の間隔よりも狭く形成されている。
応力緩和部６１を形成する導電性パターン４１Ａ、４２Ａは、同じ電位になるもの、又は導電性パターン４１，４２同士が短絡しても半導体装置１の機能に影響を与えないパターンが用いられる。 The stress relaxation portion 61 has a configuration in which comb-like edges of the two conductive patterns 41A and 42A are engaged with each other via the interlayer insulating oxide film 22. In other words, the planar shape between the comb-shaped edges is a non-linear, for example, wave-shaped slit, and the interlayer insulating oxide film 22 is filled in the slit. The slit is formed narrower than the interval between the wirings.
As the conductive patterns 41A and 42A forming the stress relaxation portion 61, those having the same potential or patterns that do not affect the function of the semiconductor device 1 even when the conductive patterns 41 and 42 are short-circuited are used.

ここで、応力緩和部６１は、プローブによって生じる応力を緩和するのに十分な大きさで形成されている。例えば、応力緩和部６１の長さは、外部のプローブがパッド２５に接触する領域Ａのうち一方向の長さに略等しい。
なお、応力緩和部６１は、応力が集中し易いことから、プローブがパッド２５に接触する領域Ａの長さより小さくても良い。また、応力緩和部６１の形成位置は、パッド２５の中央部に相当する位置、つまり第４の導電性パターン２１の中央部であっても良いが、応
力が集中し易いことから第４の導電性パターン２１の中央部からはずれた位置に形成しても良い。なお、第４層２３の下層である第３層２０では、応力緩和部６１の下方に相当する領域に電源配線やグラウンド配線等の導電性パターンは形成されない。 Here, the stress relaxation part 61 is formed in a sufficient size to relieve the stress generated by the probe. For example, the length of the stress relaxation portion 61 is substantially equal to the length in one direction in the region A where the external probe contacts the pad 25.
The stress relaxation portion 61 may be smaller than the length of the region A where the probe contacts the pad 25 because the stress tends to concentrate. The stress relaxation portion 61 may be formed at a position corresponding to the central portion of the pad 25, that is, the central portion of the fourth conductive pattern 21, but the fourth conductive pattern is formed because stress is easily concentrated. Alternatively, it may be formed at a position deviated from the center of the pattern 21. In the third layer 20, which is the lower layer of the fourth layer 23, conductive patterns such as power supply wiring and ground wiring are not formed in a region corresponding to the lower part of the stress relaxation portion 61.

検査時には、パッド２５の中央部にプローブが押し当てられる。これにより、パッド２５の下方の第４層２３の第４の導電性パターン２１の中央部分に荷重がかかる。第４層２３には、縦弾性係数や横弾性係数の差が大きい導電性パターン４１Ａ、４２Ｂと層間絶縁酸化膜２２が形成されているので、同じ荷重がかかったときに両者の変形量が異なり、歪が生じ易くなっている。   At the time of inspection, the probe is pressed against the center portion of the pad 25. As a result, a load is applied to the central portion of the fourth conductive pattern 21 of the fourth layer 23 below the pad 25. The fourth layer 23 is formed with the conductive patterns 41A and 42B and the interlayer insulating oxide film 22 having a large difference between the longitudinal elastic modulus and the transverse elastic modulus, and therefore, when the same load is applied, the deformation amounts of both are different. , Distortion is likely to occur.

特に、第４の導電性パターン２１に形成された応力緩和部６１は、他の領域より微細な導電性パターン４１Ａ、４２Ａの間にスリットが形成されているので、変形量の差に起因して生じる応力が集中し易い。このため、応力緩和部６１以外の領域の導電性パターン４１、４２と層間絶縁酸化膜２２との境界に作用する応力が低減される。   In particular, the stress relaxation portion 61 formed in the fourth conductive pattern 21 is formed with slits between the conductive patterns 41A and 42A that are finer than other regions. The stress that occurs is easy to concentrate. For this reason, the stress acting on the boundary between the conductive patterns 41 and 42 in the region other than the stress relaxation portion 61 and the interlayer insulating oxide film 22 is reduced.

応力が集中する応力緩和部６１は、前記したように、同じ電位になるもの、又は導電性パターン４１Ａ、４２Ａ同士が短絡しても半導体装置１の機能に影響を与えないパターンなので、クラックが発生しても、スリット内でクラックが止まって外部に広がらないので、半導体装置１に故障が生じることはない。   As described above, the stress relaxation portion 61 where the stress is concentrated has the same potential, or is a pattern that does not affect the function of the semiconductor device 1 even if the conductive patterns 41A and 42A are short-circuited. However, since the crack stops in the slit and does not spread outside, the semiconductor device 1 does not fail.

従って、第４層２３の特定箇所で優先的にクラックが生じることで、その下の第３層２０の第３の導電性パターン１８の縁から第３層間絶縁膜１９にクラックが生じることはない。なお、プローブによって生じる応力が小さい場合には、応力緩和部６１にクラックが生じないこともある。   Therefore, a crack is preferentially generated at a specific portion of the fourth layer 23, so that no crack is generated in the third interlayer insulating film 19 from the edge of the third conductive pattern 18 of the third layer 20 therebelow. . When the stress generated by the probe is small, the stress relaxation portion 61 may not crack.

このように、この実施の形態では、応力緩和部６１として、応力が集中し易い領域に導電性パターン４１Ａ，４２Ａを形成したので、検査時に他の領域に応力が集中してクラックが生じることを防止できる。応力緩和部６１は、クラックが生じた場合であっても、半導体装置１の故障を防止できる。   As described above, in this embodiment, since the conductive patterns 41A and 42A are formed as the stress relaxation portion 61 in the region where the stress is easily concentrated, the stress is concentrated in the other region at the time of inspection, and cracks are generated. Can be prevented. Even if the stress relaxation part 61 is a case where a crack arises, failure of the semiconductor device 1 can be prevented.

なお、応力緩和部６１を形成するパターンは、導電性パターン４１Ａ、４２Ｂと第４層間絶縁酸化膜２２の境界が他の領域より長く、且つ微細に入り組んでいれば良く、図４の形状に限定されない。例えば、Ｌ字形のパターンや、円弧状のパターンを近接して配置することで応力緩和部６１を形成しても良い。また、回路を形成する導電性パターン４１，４２と電気的に接続されないパターンを用いて応力緩和部６１を形成しても良い。   The pattern for forming the stress relieving portion 61 is not limited as long as the boundary between the conductive patterns 41A and 42B and the fourth interlayer insulating oxide film 22 is longer than the other regions and finely interlaced. Not. For example, the stress relaxation portion 61 may be formed by arranging an L-shaped pattern or an arc-shaped pattern close to each other. Further, the stress relaxation portion 61 may be formed using a pattern that is not electrically connected to the conductive patterns 41 and 42 forming the circuit.

（第３の実施の形態）
図５に、本実施の形態の半導体装置の多層配線の構造を示し、図６に第４層の平面図を示す。なお、図６では第３層間絶縁膜１９を省略して描いている。
第４層２３の第４の導電性パターン２１には、少なくとも１つのピラー７１が形成されている。ピラー７１は、第４の導電性パターン２１を貫通する貫通孔７２を形成し、ここに層間絶縁酸化膜２２Ｂを埋め込むことで形成されている。 (Third embodiment)
FIG. 5 shows the structure of the multilayer wiring of the semiconductor device of this embodiment, and FIG. 6 shows a plan view of the fourth layer. In FIG. 6, the third interlayer insulating film 19 is omitted.
At least one pillar 71 is formed in the fourth conductive pattern 21 of the fourth layer 23. The pillar 71 is formed by forming a through hole 72 penetrating the fourth conductive pattern 21 and embedding the interlayer insulating oxide film 22B therein.

その下の第３層２０の第３の導電性パターン１８には、第３の導電性パターン１８として配線パターン７３，７４，７５が形成されている。これら配線パターン７３〜７５は、平面視でピラー７１の直下に拡張部７３Ａ，７４Ａ，７５Ａが形成され、その面積はピラー７１の面積より大きくなっている。これら拡張部７３Ａ〜７５Ａと、ピラー７１によって応力緩和部７７が形成されている。   Below the third conductive pattern 18 of the third layer 20, wiring patterns 73, 74, and 75 are formed as the third conductive pattern 18. These wiring patterns 73 to 75 have extended portions 73 </ b> A, 74 </ b> A, and 75 </ b> A formed directly below the pillar 71 in plan view, and the area thereof is larger than the area of the pillar 71. A stress relaxation portion 77 is formed by the expanded portions 73 </ b> A to 75 </ b> A and the pillar 71.

検査時には、パッド２５の中央部のパッド接触領域にプローブが押し当てられる、これ
により、パッド２５の中央部にかかった荷重が、パッド２５の直下の第４層２３内の第４の導電性パターン２１に作用する。第４層２３には、ピラー７１が設けられており、ピラー７１の外周によって導電性材料と層間絶縁酸化膜２２との境界が形成されている。そして、この境界の存在によって応力が発生し易くなっている。 At the time of inspection, the probe is pressed against the pad contact area at the center of the pad 25, whereby the load applied to the center of the pad 25 is caused by the fourth conductive pattern in the fourth layer 23 immediately below the pad 25. Act on 21. A pillar 71 is provided in the fourth layer 23, and a boundary between the conductive material and the interlayer insulating oxide film 22 is formed by the outer periphery of the pillar 71. The presence of this boundary makes it easy for stress to occur.

ここで、ピラー７１の直下に配置される第３層２０内の第３の導電性パターン１８では、配線パターン７３〜７５にピラー７１の面積より大きい拡張部７３Ａ〜７５Ａが設けられている。つまりピラー７１の直下には、導電性パターンと第３層間絶縁酸化膜１９の境界が配置されていない。
このように、ピラー７１の直下に、変形し難い導電性パターンからなる拡張部７３Ａ〜７５Ａを配置することで、第４層２３における第４の導電性パターン２１と第４層間絶縁酸化膜２２の間の歪みの差が減少させられる。その結果、その直下の第３層２０及び第４層２３におけるクラックの発生が抑制される。 Here, in the third conductive pattern 18 in the third layer 20 arranged immediately below the pillar 71, the wiring patterns 73 to 75 are provided with extended portions 73 </ b> A to 75 </ b> A that are larger than the area of the pillar 71. That is, the boundary between the conductive pattern and the third interlayer insulating oxide film 19 is not disposed immediately below the pillar 71.
As described above, the extended portions 73 </ b> A to 75 </ b> A made of a conductive pattern that is difficult to deform are arranged directly under the pillar 71, so that the fourth conductive pattern 21 and the fourth interlayer insulating oxide film 22 in the fourth layer 23 are arranged. The difference in distortion between them is reduced. As a result, the occurrence of cracks in the third layer 20 and the fourth layer 23 immediately below the same is suppressed.

この実施の形態では、第４の導電性パターン２１にピラー７１を設けることで、クラックが生じ易くなった構造において、ピラー７１の直下に導電性パターン１８と第３層間絶縁酸化膜１９の境界が配置されないよう導電性パターンを形成したので、検査時のクラックの発生を防止できる。これにより、半導体装置１の故障が防止される。   In this embodiment, in the structure in which the pillar 71 is provided in the fourth conductive pattern 21 so that cracks are likely to occur, the boundary between the conductive pattern 18 and the third interlayer insulating oxide film 19 is located immediately below the pillar 71. Since the conductive pattern is formed so as not to be disposed, the occurrence of cracks during inspection can be prevented. Thereby, failure of the semiconductor device 1 is prevented.

（第４の実施の形態）
図７に、本実施の形態の半導体装置の多層配線の構造を示し、図８に第４層の平面図を示す。なお、図８では、第３層間絶縁酸化膜１９を省略して描いている。
第４層２３の第４の導電性パターン２１には貫通孔７２が複数形成され、それぞれの貫通孔７２には第４の層間絶縁酸化膜２２を埋め込んだピラー７１が形成されている。貫通孔７２の上面での対角線の長さ、即ち外径は、第３の実施形態と同様に、配線間隔よりも狭く形成される。 (Fourth embodiment)
FIG. 7 shows the structure of the multilayer wiring of the semiconductor device of this embodiment, and FIG. 8 shows a plan view of the fourth layer. In FIG. 8, the third interlayer insulating oxide film 19 is omitted.
A plurality of through holes 72 are formed in the fourth conductive pattern 21 of the fourth layer 23, and pillars 71 in which the fourth interlayer insulating oxide film 22 is embedded are formed in the respective through holes 72. The length of the diagonal line on the upper surface of the through-hole 72, that is, the outer diameter is formed narrower than the wiring interval, as in the third embodiment.

さらに、第４の導電性パターン２１では、ピラー７１が他の領域より集中して配置された所定の領域、つまり隣り合うピラー７１同士の配置間隔が他の領域のピラー７１の配置間隔より狭い領域があり、この領域が第１の応力緩和部８１になっている。第１の応力緩和部８１の直下の領域の第３層２０では、電源やグラウンド等の導電性パターンは形成されず、第１の応力緩和部８１の一部となっている。   Further, in the fourth conductive pattern 21, a predetermined region in which the pillars 71 are concentrated from other regions, that is, a region in which the spacing between adjacent pillars 71 is narrower than the spacing between the pillars 71 in the other regions. This region is the first stress relaxation portion 81. In the third layer 20 in the region immediately below the first stress relaxation portion 81, a conductive pattern such as a power source or ground is not formed, and is a part of the first stress relaxation portion 81.

一方、第４の導電性パターン２１において、第１の応力緩和部８１以外の領域のピラー７１と、このピラー７１の直下の導電性パターン８２，８３，８４の拡張部８２Ａ，８３Ａ，８４Ａとによって、第２の応力緩和部８５が形成されている。第２の応力緩和部８５を構成する導電性パターン８２〜８４の拡張部８２Ａ〜８４Ａは、ピラー７１の直下に形成され、平面視における面積がピラー７１の面積より大きくなっている。
なお、第４層２３の第４の導電性パターン２１に形成されたピラー７１は、第１の応力緩和部８１又は第２の応力緩和部８５のいずれかを形成しているが、第４の導電性パターン２１はこれら応力緩和部８１，８５を形成しないピラー７１を有しても良い。 On the other hand, in the fourth conductive pattern 21, the pillar 71 in a region other than the first stress relaxation portion 81 and the extended portions 82 </ b> A, 83 </ b> A, 84 </ b> A of the conductive patterns 82, 83, 84 directly below the pillar 71. A second stress relaxation portion 85 is formed. The extended portions 82A to 84A of the conductive patterns 82 to 84 constituting the second stress relaxation portion 85 are formed immediately below the pillar 71, and the area in plan view is larger than the area of the pillar 71.
The pillar 71 formed on the fourth conductive pattern 21 of the fourth layer 23 forms either the first stress relaxation portion 81 or the second stress relaxation portion 85. The conductive pattern 21 may have pillars 71 that do not form the stress relaxation portions 81 and 85.

検査時には、パッド２５の中央部の領域にプローブが押し当てられる、これにより、パッド２５の中央部にかけられた荷重が、パッド２５の下方の第４層２３の第４の導電性パターン２１に作用する。第４層２３では、第４の導電性パターン２１とピラー７１の境界に応力が生じる。第１の応力緩和部８１では、ピラー７１が密集して配置されており、導電性物質と層間絶縁酸化膜２２Ｂの境界が密集している。このため、第１の応力緩和部８１においてクラックの発生が優先的に誘発される。これにより、他の領域に生じる応力を低減させられる。
また、第２の応力緩和部８５では、応力がその下層の第３層２０の第３の導電性パター
ン１８にも作用する。第３層２０のピラー７１の直下の領域及びその周辺には、導電性物質と層間絶縁酸化膜１９の境界が配置されていないので、クラックが生じることはない。 At the time of inspection, the probe is pressed against the central region of the pad 25, whereby the load applied to the central portion of the pad 25 acts on the fourth conductive pattern 21 of the fourth layer 23 below the pad 25. To do. In the fourth layer 23, stress is generated at the boundary between the fourth conductive pattern 21 and the pillar 71. In the first stress relaxation portion 81, the pillars 71 are densely arranged, and the boundary between the conductive material and the interlayer insulating oxide film 22B is dense. For this reason, the occurrence of cracks is preferentially induced in the first stress relaxation portion 81. Thereby, the stress which arises in another field can be reduced.
In the second stress relaxation portion 85, the stress also acts on the third conductive pattern 18 of the third layer 20 below the second stress relaxation portion 85. Since the boundary between the conductive material and the interlayer insulating oxide film 19 is not arranged in the region immediately below the pillar 71 of the third layer 20 and its periphery, no cracks are generated.

この実施の形態では、第４の導電性パターン２１にピラー７１を形成した構成において、第１の応力緩和部８１によってクラックの発生を誘発することで他の領域にクラックを生じ難くしたので、検査時の大きなクラックの発生を防止できる。さらに、第２の応力緩和部８５を設けて、ピラー７１の直ぐ下の層に導電性物質と層間絶縁酸化膜１９の境界が配置されないようしたので、検査時のクラックの発生を防止できる。これらにより、半導体装置１のクラックによる故障が防止される。なお、半導体装置１は、第１の応力緩和部８１のみを設けても良い。   In this embodiment, in the configuration in which the pillars 71 are formed in the fourth conductive pattern 21, it is difficult to generate cracks in other regions by inducing the generation of cracks by the first stress relaxation portion 81. The generation of large cracks at the time can be prevented. Furthermore, since the second stress relaxation portion 85 is provided so that the boundary between the conductive material and the interlayer insulating oxide film 19 is not disposed in the layer immediately below the pillar 71, generation of cracks during inspection can be prevented. As a result, failure due to cracks in the semiconductor device 1 is prevented. Note that the semiconductor device 1 may be provided with only the first stress relaxation portion 81.

ここで、図９及び図１０を参照して本実施の形態の変形例について説明する。
この半導体装置１において、第４層２３の第４の導電性パターン２１には複数のピラー７１，９１が形成されている。第１の応力緩和部９２を形成するピラー９１は、第４の導電性パターン２１における他の領域のピラー７１よりも平面視における面積が小さくなっている。 Here, a modification of the present embodiment will be described with reference to FIGS. 9 and 10.
In the semiconductor device 1, a plurality of pillars 71 and 91 are formed on the fourth conductive pattern 21 of the fourth layer 23. The pillar 91 that forms the first stress relaxation portion 92 has a smaller area in plan view than the pillar 71 in another region of the fourth conductive pattern 21.

また、第１の応力緩和部９２におけるピラー９１の配置間隔は、第４の導電性パターン２１における他の領域のピラー７１同士の配置間隔より狭い。さらに、ピラー９１の配置間隔は、図８に示す第１の応力緩和部８１におけるピラー７１の配置間隔より狭い。さらに、他の領域のピラー７１と、その下層の配線パターン８２〜８４の拡張部８２Ａ〜８４Ａとの間には、第２の応力緩和部８５が形成されている。   Further, the arrangement interval of the pillars 91 in the first stress relaxation portion 92 is narrower than the arrangement interval of the pillars 71 in other regions in the fourth conductive pattern 21. Furthermore, the arrangement interval of the pillars 91 is narrower than the arrangement interval of the pillars 71 in the first stress relaxation portion 81 shown in FIG. Furthermore, a second stress relaxation portion 85 is formed between the pillar 71 in another region and the extended portions 82A to 84A of the wiring patterns 82 to 84 below the other region.

第１の応力緩和部９２では、導電膜と層間絶縁酸化膜２２との境界が、より細かく配置されているので、クラックの発生を図８に示す構成よりさらに誘発し易い。このため、検査時の大きなクラックの発生をさらに防止できる。   In the first stress relaxation portion 92, since the boundary between the conductive film and the interlayer insulating oxide film 22 is arranged more finely, it is easier to induce the generation of cracks than the configuration shown in FIG. For this reason, generation | occurrence | production of the big crack at the time of a test | inspection can further be prevented.

なお、第１の応力緩和部９２の形成位置は、プローブが押し当てられるパッド２５の中央部の直下に形成しても良いし、中央部から外れた位置でも良い。これは、第１の応力緩和部９２は応力を集中させ易いので、必ずしも第４の導電性パターン２１の導電性パターン２１Ａの中央部に配置しなくても良いためである。また、第１の応力緩和部９２がプローブにより生じる応力を十分に緩和できる大きさの場合には、第２の応力緩和部８５を形成しなくても良い。   Note that the first stress relaxation portion 92 may be formed immediately below the center portion of the pad 25 against which the probe is pressed, or may be positioned away from the center portion. This is because the stress is easily concentrated in the first stress relieving portion 92, and therefore it is not always necessary to place the first stress relieving portion 92 in the central portion of the conductive pattern 21A of the fourth conductive pattern 21. In addition, when the first stress relaxation part 92 is large enough to relieve the stress generated by the probe, the second stress relaxation part 85 may not be formed.

また、図１１に示すように、第４の導電性パターン２１のうち大きさが異なる２種類のピラー７１，９５を２つの領域に分けて形成し、それぞれの領域においてピラー７１，９５を略等間隔に配置しても良い。この場合には、平面視における面積が小さいピラー９５が配置された領域が第１の応力緩和部９６になる。   Further, as shown in FIG. 11, two types of pillars 71 and 95 having different sizes in the fourth conductive pattern 21 are formed in two regions, and the pillars 71 and 95 are substantially equal in each region. It may be arranged at intervals. In this case, a region where the pillar 95 having a small area in plan view is arranged becomes the first stress relaxation portion 96.

図１１の例では、第１の応力緩和部９６を形成するピラー９５の配置間隔は、第２の応力緩和部の領域のピラー７１より小さい。しかしながら、ピラー９５の配置間隔とピラー７１の配置間隔を略同じにしても良い。さらに、第１の応力緩和部９６は、ピラー７１を狭い間隔で配置することで形成しても良い。   In the example of FIG. 11, the arrangement interval of the pillars 95 forming the first stress relaxation part 96 is smaller than the pillar 71 in the region of the second stress relaxation part. However, the arrangement interval of the pillars 95 and the arrangement interval of the pillars 71 may be substantially the same. Further, the first stress relaxation portion 96 may be formed by arranging the pillars 71 at a narrow interval.

なお、上記した各実施形態において、第４の導電パターン２１の上に他の導電パターンが形成されてもよい。また、プローブ接触による亀裂の発生を防止するためには、第４の導電性パターン２１は、パッド２５を含めて上から二層目又は三層目の導電パターンであることが好ましい。   In each embodiment described above, another conductive pattern may be formed on the fourth conductive pattern 21. In order to prevent the occurrence of cracks due to probe contact, the fourth conductive pattern 21 is preferably the second or third layer conductive pattern from the top including the pad 25.

ここで挙げた全ての例および条件的表現は、発明者が技術促進に貢献した発明および概
念を読者が理解するのを助けるためのものであり、ここで具体的に挙げたそのような例および条件に限定することなく解釈すべきであり、また、明細書におけるそのような例の編成は本発明の優劣を示すこととは関係ない。本発明の実施形態を詳細に説明したが、本発明の精神および範囲から逸脱することなく、それに対して種々の変更、置換および変形を施すことができると理解すべきである。 All examples and conditional expressions given here are intended to help the reader understand the inventions and concepts that have contributed to the promotion of technology, such examples and It should be construed without being limited to the conditions, and the organization of such examples in the specification is not related to showing the superiority or inferiority of the present invention. Although embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions and variations can be made thereto without departing from the spirit and scope of the present invention.

以下に、実施の形態の特徴を付記する。
（付記１） 半導体基板と、前記半導体基板上に積層された複数の層間絶縁膜と、前記複数の層間絶縁膜の最上面の上に形成され、外部からプローブが当てられるプローブ接触領域を有するパッドと、前記複数の層間絶縁膜の間に形成される複数層の配線と、前記パッドの前記プローブ接触領域の直下の領域に形成され、前記層間絶縁膜が充填される非直線状スリットと孔の少なくともいずれか一方を有する導電性パターンを有する応力緩和部とを有することを特徴とする半導体装置。
（付記２） 前記孔の直下には、前記孔よりも大きな導電パターンが形成されていることを特徴とする付記１に記載の半導体装置。
（付記３） 前記導電パターンは、前記配線の一部であることを特徴とする付記２に記載の半導体装置。
（付記４） 前記孔は、前記導電パターンから１層下の前記配線と、該１層下の前記配線と同じ層の他の導電パターンに重ならない領域に集合して複数形成されていることを特徴とする付記１に記載の半導体装置。
（付記５） 前記孔は密度分布が異なる状態に複数形成されていることを特徴とする付記１に記載の半導体装置。
（付記６） 前記スリットの平面形状は、波形状であることを特徴とする付記１に記載の半導体装置。
（付記７） 半導体基板と、前記半導体基板上に積層された複数の層間絶縁膜と、前記複数の層間絶縁膜の最上面の上に形成され、外部からプローブが当てられるプローブ接触領域を有するパッドと、前記複数の層間絶縁膜の間に形成される複数層の配線と、前記パッドの前記プローブ接触領域の直下の領域の全体に形成され、前記プローブ接触領域よりも広い導電膜、絶縁膜のいずれか一方からなる応力緩和部と、を有することを特徴とする半導体装置。
（付記８） 前記応力緩和部は、外周が絶縁膜に囲まれた導電膜であることを特徴とする付記７に記載の半導体装置。
（付記９） 前記応力緩和部は、外周の少なくとも一部が導電膜に囲まれた絶縁膜であることを特徴とする付記７に記載の半導体装置。
（付記１０） 前記応力緩和部は、上から二層目又は三層目の導電パターンと同層であることを特徴とする付記１乃至付記９のいずれか１つに記載の半導体装置。 The features of the embodiment will be added below.
(Additional remark 1) The pad which has a probe contact area | region which is formed on the uppermost surface of a semiconductor substrate, the several interlayer insulation film laminated | stacked on the said semiconductor substrate, and the said several interlayer insulation film, and a probe is applied from the outside A plurality of layers of wiring formed between the plurality of interlayer insulating films, and a non-linear slit and a hole formed in a region immediately below the probe contact region of the pad and filled with the interlayer insulating film A semiconductor device comprising: a stress relaxation portion having a conductive pattern having at least one of them.
(Supplementary note 2) The semiconductor device according to supplementary note 1, wherein a conductive pattern larger than the hole is formed immediately below the hole.
(Additional remark 3) The said conductive pattern is a part of said wiring, The semiconductor device of Additional remark 2 characterized by the above-mentioned.
(Supplementary Note 4) A plurality of the holes are formed in a region that does not overlap with the wiring that is one layer below the conductive pattern and the other conductive pattern in the same layer as the wiring that is one layer below the conductive pattern. The semiconductor device according to appendix 1, which is characterized.
(Supplementary Note 5) The semiconductor device according to Supplementary Note 1, wherein a plurality of the holes are formed in different density distributions.
(Additional remark 6) The planar shape of the said slit is a wave shape, The semiconductor device of Additional remark 1 characterized by the above-mentioned.
(Appendix 7) A semiconductor substrate, a plurality of interlayer insulating films stacked on the semiconductor substrate, and a pad formed on the uppermost surface of the plurality of interlayer insulating films and having a probe contact region to which a probe is applied from the outside And a plurality of layers of wiring formed between the plurality of interlayer insulating films, and a conductive film and an insulating film formed over the entire region immediately below the probe contact region of the pad and wider than the probe contact region. A semiconductor device comprising: a stress relaxation portion made of either one.
(Supplementary note 8) The semiconductor device according to supplementary note 7, wherein the stress relaxation portion is a conductive film having an outer periphery surrounded by an insulating film.
(Additional remark 9) The said stress relaxation part is an insulating film with which at least one part of outer periphery was surrounded by the electrically conductive film, The semiconductor device of Additional remark 7 characterized by the above-mentioned.
(Supplementary Note 10) The semiconductor device according to any one of Supplementary notes 1 to 9, wherein the stress relaxation portion is in the same layer as a second or third conductive pattern from above.

１ 半導体装置
２ 半導体基板
３ トランジスタ
１１，１５，１８，２１ 導電性パターン
１２ 第１層間絶縁酸化膜
１４ 第１層
１６ 第２層間絶縁酸化膜
１７ 第２層
１９ 第３層間絶縁酸化膜
２０ 第３層
２２ 第４層間絶縁酸化膜
２３ 第４層
２５ パッド
４１，４１Ａ，４２，４２Ａ，７３，７４，７５，８２，８３，８４ 導電性パターン
４３ ランド部（応力緩和部）
５１，６１，７７，９５ 応力緩和部
７１，９１ ピラー
７２ 貫通孔
７３Ａ，７４Ａ，７５Ａ，８２Ａ，８４Ａ 部分
８１，９２，９５ 第１の応力緩和部
８５ 第２の応力緩和部 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor substrate 3 Transistor 11, 15, 18, 21 Conductive pattern 12 1st interlayer insulation oxide film 14 1st layer 16 2nd interlayer insulation oxide film 17 2nd layer 19 3rd interlayer insulation oxide film 20 3rd Layer 22 Fourth interlayer insulating oxide film 23 Fourth layer 25 Pad 41, 41A, 42, 42A, 73, 74, 75, 82, 83, 84 Conductive pattern 43 Land portion (stress relaxation portion)
51, 61, 77, 95 Stress relaxation part 71, 91 Pillar 72 Through-hole 73A, 74A, 75A, 82A, 84A Part 81, 92, 95 1st stress relaxation part 85 2nd stress relaxation part

Claims (5)

半導体基板と、
前記半導体基板上に積層された複数の層間絶縁膜と、
前記複数の層間絶縁膜の最上面の上に形成され、外部からプローブが当てられるプローブ接触領域を有するパッドと、
前記複数の層間絶縁膜の間に形成される複数層の配線と、
前記パッドの前記プローブ接触領域の直下の領域に形成され、前記層間絶縁膜が充填される非直線状スリットか孔の少なくとも一方を有する導電性パターンを有する応力緩和部と
を有することを特徴とする半導体装置。 A semiconductor substrate;
A plurality of interlayer insulating films stacked on the semiconductor substrate;
A pad formed on an uppermost surface of the plurality of interlayer insulating films and having a probe contact region to which a probe is applied from the outside;
A plurality of layers of wiring formed between the plurality of interlayer insulating films;
And a stress relieving part having a conductive pattern formed in a region immediately below the probe contact region of the pad and having at least one of a non-linear slit or a hole filled with the interlayer insulating film. Semiconductor device. 前記孔の直下には、前記孔よりも大きな導電パターンが形成されていることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein a conductive pattern larger than the hole is formed immediately below the hole. 前記孔は、前記導電パターンから１層下の前記配線と、該１層下の前記配線と同じ層の他の導電パターンに重ならない領域に集合して複数形成されていることを特徴とする請求項１に記載の半導体装置。   The hole is formed in a plural number in a region that does not overlap the wiring that is one layer below the conductive pattern and the other conductive pattern in the same layer as the wiring that is one layer below the conductive pattern. Item 14. The semiconductor device according to Item 1. 前記スリットの平面形状は、波形状であることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein a planar shape of the slit is a wave shape. 半導体基板と、
前記半導体基板上に積層された複数の層間絶縁膜と、
前記複数の層間絶縁膜の最上面の上に形成され、外部からプローブが当てられるプローブ接触領域を有するパッドと、
前記複数の層間絶縁膜の間に形成される複数層の配線と、
前記パッドの前記プローブ接触領域の直下の領域の全面に形成され、前記プローブ接触領域よりも広い導電膜、絶縁膜のいずれか一方からなる応力緩和部と、
を有することを特徴とする半導体装置。 A semiconductor substrate;
A plurality of interlayer insulating films stacked on the semiconductor substrate;
A pad formed on an uppermost surface of the plurality of interlayer insulating films and having a probe contact region to which a probe is applied from the outside;
A plurality of layers of wiring formed between the plurality of interlayer insulating films;
A stress relieving portion formed on the entire surface of a region immediately below the probe contact region of the pad and made of either one of a conductive film and an insulating film wider than the probe contact region;
A semiconductor device comprising:
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WO2020103875A1 (en) * 2018-11-21 2020-05-28 Changxin Memory Technologies, Inc. Distribution layer structure and manufacturing method thereof, and bond pad structure
CN112687662A (en) * 2019-10-18 2021-04-20 南亚科技股份有限公司 Semiconductor element and method for manufacturing the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103295999A (en) * 2013-06-03 2013-09-11 上海宏力半导体制造有限公司 Lead wire welding disc and integrated circuit
WO2020103875A1 (en) * 2018-11-21 2020-05-28 Changxin Memory Technologies, Inc. Distribution layer structure and manufacturing method thereof, and bond pad structure
US11587893B2 (en) 2018-11-21 2023-02-21 Changxin Memory Technologies, Inc. Distribution layer structure and manufacturing method thereof, and bond pad structure
CN112687662A (en) * 2019-10-18 2021-04-20 南亚科技股份有限公司 Semiconductor element and method for manufacturing the same
CN112687662B (en) * 2019-10-18 2024-03-15 南亚科技股份有限公司 Semiconductor element and method for manufacturing the same

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