JP2007096126A - Transistor and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve charge matching performance and grid matching performance on a channel layer interface in a transistor using zinc oxide as a channel layer. <P>SOLUTION: Zinc oxide is epitaxial grown on a buffer layer 3 formed on a substrate 2, and a channel layer is formed. Furthermore, Mg<SB>1-x</SB>Ca<SB>x</SB>O is epitaxially grown on the channel layer 4 so that an interface modification layer 7 can be formed, and a gate insulating layer 8 and a gate electrode 9 are formed through the interface modification layer 7. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a transistor having an active layer of zinc oxide (ZnO), and relates to a transistor suitable for a switching element used in an electronic device and an electronic device using the transistor.

  In recent years, the use of thin display devices (flat panel display; FPD) such as liquid crystal display devices and organic EL (electroluminescence) display devices has been rapidly developed. Among these thin display devices, amorphous silicon TFTs (thin film transistors), polysilicon TFTs, and the like are used for active matrix display devices capable of high-quality display.

  However, since these materials have photoconductivity in the visible light region, when light is irradiated, carriers are generated, the resistance is lowered, and the display quality is lowered. Therefore, the light resistance is prevented by blocking the light with a light shielding layer such as a metal coating, but this reduces the effective display area, so it is necessary to brighten the backlight, and the energy utilization efficiency is low. turn into.

Therefore, there is a demand for a transparent transistor that does not have photoconductivity in the visible light region. Examples of the material of the transparent channel layer for forming such a transistor include zinc oxide (ZnO), magnesium zinc oxide (Mg _x Zn _1-x O), and cadmium zinc oxide (Cd _x Zn _1-x O). ), Cadmium oxide (CdO), and the like. Among these, a transistor using ZnO is attracting attention because it is a semiconductor that exhibits relatively good physical properties even at low temperature.

  For example, Patent Document 1 describes that a transparent semiconductor such as ZnO is used for a channel layer of a transistor and a transparent insulating oxide is used for a gate insulating layer to make the transistor transparent.

Further, in Patent Document 2, in order to eliminate lattice mismatch between ZnO and the substrate, a channel layer made of ZnO is formed on a substrate made of ScAlMgO ₄ or ZnO single crystal, so that ZnO is used as the channel layer. It is described that the performance of the thin film transistor can be improved.

By the way, in order to further improve the performance of a transistor based on ZnO, it is indispensable to develop an insulating layer material capable of realizing a good interface with ZnO. Thus, for example, Non-Patent Document 1 proposes a heterostructure using β-LiGaO ₂ as an insulating layer material.

Non-Patent Document 2 describes Mg _1-x Ca _x O as a material having good lattice matching with ZnO, and the Ca concentration x in the Mg _1-x Ca _x O is x = 0.7. It is described that lattice matching with ZnO can be achieved.

Non-Patent Document 3 describes forming Mg _1-x Ca _x O on an MgO substrate. Patent Document 3 describes that niobium nitride (NbN) is epitaxially grown on a solid solution of MgO and CaO.

  Patent Document 4 discloses a Si substrate and a buffer layer of a metal oxide having a NaCl structure made of at least one of MgO, CaO, SrO, BaO, or a solid solution containing these formed on the Si substrate. And a conductive oxide layer including a metal oxide having a perovskite structure formed by epitaxial growth in a cubic (100) orientation or a pseudocubic (100) orientation on the buffer layer. ing.

Patent Document 5 discloses a buffer layer of a metal oxide having an NaCl structure made of at least one of MgO, CaO, SrO, BaO, or a solid solution containing these on a substrate having an amorphous surface, and the buffer. There is disclosed a substrate for an electronic device having a conductive oxide layer containing a metal oxide having a perovskite structure formed on the layer.
JP 2000-150900 A (publication date: May 30, 2000) JP 2002-277534 A (publication date: October 6, 2000) US Pat. No. 4,768,069 JP 2003-163176 A (publication date June 6, 2003) JP 2004-002150 A (publication date January 8, 2004) I, Ohkubo et al, "Heteroepitaxial growth of β-LiGaO2 thin films on ZnO", J. Appl. Phys. Volume 92, number9, p.5587, 2002 J. Nishii, M. Kawasaki, et al, "High-throughput Synthesis and Characterization of Mg1-xCaxO film as a Lattice and Valence-matched Gate Dielectric for ZnO Based Field Effect Transistors", The Third Japan-US Workshop on Combinational Materials Science , 2004 ESHellman, EHHartford, Jr, "Epitaxial solid-solution films of immiscible MgO and CaO", Appl.Phys.Lett.64 (11), p.1341, 14 March 1994

  However, in the technique of Non-Patent Document 1, sufficient transistor characteristic improvement effect cannot be obtained due to charge mismatch at the heterointerface.

Non-Patent Document 2 discloses using Mg _1-x Ca _x O as a gate insulating layer. However, since Mg _1-x Ca _x O hardly dissolves under thermal equilibrium, Mg _1-x Ca _x O can be obtained only as a thin film. For this reason, it may be difficult to use Mg _1-x Ca _x O alone as a gate insulating layer of a transistor.

  Non-Patent Document 3 and Patent Documents 3 to 5 do not describe any lattice matching of ZnO.

  The present invention has been made in view of the above problems, and an object of the present invention is to improve the charge matching and lattice matching at the interface of the channel layer in a transistor using ZnO as the channel layer, thereby improving the transistor performance. The goal is to improve performance.

In order to solve the above problems, a transistor of the present invention has a gate insulating layer between a substrate, a channel layer made of ZnO, a source electrode and a drain electrode connected to the channel layer, and the channel layer. And a gate electrode provided through the interface, wherein the interface on the side of the gate insulating layer in the channel layer is an interface modification made of Mg _1-x Ca _x O (0.2 <x <0.8). It is characterized by a quality layer.

In general, Mg _1-x Ca _x O hardly forms a solid solution under thermal equilibrium, and can only be formed as a thin film. For this reason, it may be difficult to use Mg _1-x Ca _x O alone as a gate insulating layer. Therefore, in the above configuration, Mg _1-x Ca _x O is used as the interface modification layer of the channel layer, and the gate insulating layer is formed through this interface modification layer. Thereby, the lattice matching and charge matching of the interface on the gate insulating layer side in the channel layer can be improved. As a result, the S value of the transistor (rate at which the Schottky barrier height changes with respect to the work function of the metal), field effect mobility, and off current (current flowing between the source electrode and the drain electrode when no gate voltage is applied) ), On / Off ratio (current amplification factor between source electrode and drain electrode by application of gate voltage) can be improved.

Incidentally, the interface reforming layer is preferably Mg _0.42 Ca _0.58 O.

In Non-Patent Document 2, it is said that perfect lattice matching with ZnO can be achieved by setting the composition of Mg _1-x Ca _x O to x = 0.7. However, as a result of detailed examination by the inventors of the present application, it is not possible to achieve perfect lattice matching at x = 0.7. To achieve perfect lattice matching with ZnO, x = 0.58 or a value in the vicinity thereof is required. It became clear that it was necessary. Therefore, the lattice matching with the channel layer made of ZnO can be improved by setting the Ca concentration x in Mg _1-x Ca _x O to 0.58.

  The transistor may have a structure in which a channel layer, a gate insulating layer, and a gate electrode are arranged in this order when viewed from the substrate side, that is, a top gate structure.

  In the case of a top gate structure, a buffer layer may be formed between the substrate and the channel layer, and the channel layer may be formed on the buffer layer.

  According to the above structure, by forming ZnO as a channel layer on the buffer layer, the crystallinity of ZnO can be improved and the characteristics of the transistor can be further improved.

  Moreover, it is preferable that the said buffer layer can improve the crystallinity of ZnO and has a high electrical resistance value. As such a buffer layer, for example, annealed MgZnO can be used.

The transistor may have a structure in which a gate electrode, a gate insulating layer, and a channel layer are arranged in this order when viewed from the substrate side, that is, a bottom gate structure. In the above structure, the channel layer is formed on the interface modified layer in the transistor manufacturing process. In this case, the interface modification layer can function as ZnO orientation control means. Thereby, the interface modified layer made of Mg _1-x Ca _x O improves the lattice matching and charge matching at the interface of the channel layer, and improves the orientation of ZnO formed on the interface modified layer. be able to.

When the bottom gate structure is adopted, the second interface modification made of Mg _1-x Ca _x O (0.2 <x <0.8) is formed on the interface of the channel layer opposite to the gate insulating layer. It is good also as a structure provided with the quality layer.

  Thus, charge matching at the interface opposite to the gate insulating layer side in the channel layer can be improved, and the performance of the transistor can be further improved.

  The channel layer may be single crystal ZnO or polycrystalline ZnO.

  The electronic device of the present invention includes any of the transistors described above. Thereby, the performance of the electronic device can be improved.

The electronic device may be a display device or an image reading device, and the transistor may be connected to the pixel electrode in order to control writing or reading of an image signal to the pixel electrode. For example, when the electronic device is an active matrix display device (for example, a liquid crystal display device or an organic EL display device), the transistor is turned on when an image signal is written from the driver circuit to the pixel electrode. In the case where the electronic device is an image reading device such as an image sensor, the transistor is turned on when reading out a pixel signal taken into the pixel electrode. As described above, by using the transistor in an electronic device for image display or image reading, high performance of these electronic devices can be achieved. Further, by providing a high-performance transistor using ZnO that is transparent to visible light as a channel layer and Mg _1-x Ca _x O as an interface modification layer, the display area of the display device or the image reading device The image reading area can be expanded.

As described above, in the transistor of the present invention, the interface modification layer made of Mg _1-x Ca _x O (0.2 <x <0.8) is provided at the interface on the gate insulating layer side in the channel layer. ing.

  As a result, the lattice matching and charge matching at the interface on the gate insulating layer side in the channel layer can be improved, thereby improving characteristics such as the S value, field effect mobility, off current, and on / off ratio of the transistor. Can be made.

  In addition, by applying the above transistor to an electronic device, the performance of the electronic device can be improved.

Embodiment 1
An embodiment of the present invention will be described. FIG. 1 is a cross-sectional view showing a schematic configuration of a transistor (field effect transistor; FET) 1 which is a semiconductor device according to the present embodiment.

  As shown in this figure, the transistor 1 includes a substrate 2, a buffer layer 3 formed on the substrate 2, a channel layer (semiconductor layer) 4 formed on the buffer layer 3, and a predetermined layer on the channel layer 4. The source electrode 5 and the drain electrode 6 formed with a gap therebetween, the interface modification layer 7 formed in a region other than the source electrode 5 and the drain electrode 6 on the channel layer 4, and the source electrode 5 and the drain electrode 6 , A gate insulating layer 8 formed on the interface modification layer 7 and a gate electrode 9 formed on the gate insulating layer 8. The transistor 1 has a channel width W of 50 μm and a channel length L of 20 μm.

As the substrate 2, ScAlMgO ₄ (SCAM) is used. The substrate thickness is not particularly limited, but a substrate of about 100 μm is used in this embodiment. Since ScAlMgO ₄ has high lattice matching with ZnO (zinc oxide), ZnO can be epitaxially grown with high quality on the substrate 2 made of ScAlMgO ₄ . Note that substantially the same effect can be obtained by using single crystal ZnO instead of ScAlMgO ₄ . Further, the substrate 2 is not limited to ScAlMgO ₄ or single crystal ZnO, and a substrate made of another material may be used.

  The buffer layer 3 is formed by annealing ZnO epitaxially grown on the substrate 2 so as to be (0001) oriented, and is formed with a thickness of 20 nm. The annealing process was performed in the atmosphere at an annealing temperature of 1000 ° C. and an annealing time of 1 hour.

  The channel layer 4 is made of ZnO (single crystal ZnO) epitaxially grown on the buffer layer 3 so as to be (0001) oriented, and is formed to a thickness of 200 nm.

The interface modification layer 7 is made of Mg _1-x Ca _x O having a thickness of 200 nm epitaxially grown on ZnO as the channel layer 4 so as to be (111) -oriented. Here, x is a value representing the Ca concentration in Mg _1-x Ca _x O, and in the transistor 1, x = 0.58. That is, in this embodiment, Mg _0.42 Ca _0.58 O is used as the interface modification layer 7.

As the source electrode 5, the drain electrode 6, and the gate electrode 9, an alloy of aluminum Al and titanium Ti is used. However, the material of the source electrode 5, the drain electrode 6, and the gate electrode 9 is not limited to this, and may be appropriately changed. For example, a transparent conductor such as In ₂ O ₃ , SnO ₂ , or (In—Sn) O _x may be used. In that case, a transistor having a wider area of a transparent portion with respect to visible light can be formed. .

  The gate insulating layer (gate insulating film) 8 is made of amorphous aluminum oxide a-AlOx having a thickness of 500 nm, and is formed on the source electrode 5, the drain electrode 6, and the interface modification layer 7. The gate insulating layer 8 is not limited to this, and various insulating film materials can be used.

  Next, a method for manufacturing the transistor 1 will be described.

First, ZnO with a thickness of 20 nm is epitaxially grown on the substrate 2 made of (0001) -oriented ScAlMgO ₄ with a thickness of 50 nm so as to be (0001) -oriented by the laser MBE method. FIG. 2 is a cross-sectional view showing a schematic configuration of the laser MBE apparatus used in the present embodiment. The growth conditions are not particularly limited. In this embodiment, the target is a ZnO crystal, the growth temperature is 700 ° C., the laser repetition frequency is 5 Hz, the laser power is 1 J / cm ² , and the oxygen partial pressure is 1 × 10 ⁻⁶ Torr. did. Note that a KrF excimer laser having a wavelength λ = 248 nm was used as the laser.

  Next, the buffer layer 3 is formed by annealing (heat treatment) the substrate 2 on which ZnO is epitaxially grown as described above.

  Next, the channel layer 4 is formed on the buffer layer 3 by epitaxial growth of ZnO having a thickness of 200 nm so as to be (0001) -oriented by the laser MBE method. The growth conditions are the same as those of the ZnO epitaxially grown to form the buffer layer 3.

Next, a resist is formed in a predetermined region on the channel layer 4 (a region where the source electrode 5 and the drain electrode 6 are not formed) by a photolithography process, and etching is performed using Ar ⁺ or the like. Pattern into shape.

  Next, the source electrode 5 and the drain electrode 6 made of Al (thickness 30 nm) and Ti (thickness 20 nm) are formed by using electron beam evaporation and lift-off techniques. Alternatively, it may be formed by RF magnetron sputtering or the like.

Next, a resist is formed on the source electrode 5 and the drain electrode 6, and Mg _0.42 Ca _0.58 O having a thickness of 200 nm is epitaxially grown on the channel layer 4 by the laser MBE method so as to be (111) -oriented, thereby modifying the interface. Layer 7 is formed. In this embodiment, a target obtained by mixing and sintering MgO powder and CaO powder is used. The growth temperature is 400 ° C., the laser repetition frequency is 10 Hz, the laser power is 1 J / cm ² , and the oxygen partial pressure is 1 × 10 ⁻⁶ Torr. Mg _0.42 Ca _0.58 O under the growth conditions was epitaxially grown. The same laser as that used in the formation of ZnO was used.

Thereafter, a gate insulating layer 8 made of a-Al ₂ O ₃ is formed on the interface modification layer 7, and a gate electrode 9 made of Au (thickness 100 nm) and Ti (thickness 10 nm) is further formed thereon. Thus, the transistor 1 is completed.

In general, it is known that Mg _1-x Ca _x O hardly dissolves under thermal equilibrium. For this reason, said sintered compact target phase-separated into MgO and CaO. However, in the thin film, a (111) -oriented single-phase solid solution (Mg _0.42 Ca _0.58 O) was obtained on ZnO (0001).

FIG. 3 is a graph showing the results of X-ray diffraction measurement (XRD) of a substrate obtained by epitaxially growing ZnO on a substrate made of ScAlMgO ₄ and further epitaxially growing Mg _1-x Ca _x O thereon. In addition, the broken line shown in the figure has shown the result of the X-ray-diffraction measurement of the sintered compact (it mixed Si as a standard sample) which mixed MgO and CaO in the ratio of 50%, respectively. As shown in this figure, the diffraction peak attributed to MgO and CaO was not found in the result of X-ray diffraction measurement of the substrate on which ZnO and Mg _1-x Ca _x O were epitaxially grown on ScAlMgO ₄ .

FIG. 4 is a graph showing the results of X-ray diffraction measurement when the Ca concentration x in Mg _1-x Ca _x O is 0.64 and 0.50. As shown in this figure, there is an Mg _1-x Ca _x O diffraction peak whose diffraction angle changes depending on the Ca concentration x between the MgO (111) diffraction peak and the CaO (111) diffraction peak. Expressed. This indicates that the lattice constant of Mg _1-x Ca _x O can be changed by adjusting the Ca concentration.

FIG. 5 shows a target (MgO—CaO layer) using a sample obtained by epitaxially growing 20 nm of ZnO on a sapphire (c-sapphire) substrate and epitaxially growing 200 nm of Mg _1-x Ca _x O thereon. is a graph showing the results of examining the relationship between the Ca concentration and Mg _1-x Ca _x O Ca concentrations of a thin film of a sintered body target). Specifically, the laser repetition frequency for each of the case where the growth temperature is set to room temperature and the case where the growth temperature is set to 400 ° C. using three sintered body targets having Ca concentrations of 0.38, 0.48, and 0.56. Epitaxial growth was performed by a laser MBE method under the growth conditions of 10 Hz, laser power 1 J / cm ² , oxygen partial pressure 1 × 10 ⁻⁶ Torr. In the example shown in FIG. 5, the composition of the target was identified by ICP (Inductivity coupled plasma atomic emission spectroscopy).

As shown in this figure, although a slight compositional deviation was observed, the composition of each Mg _1-x Ca _x O thin film almost coincided with the composition of the target. In addition, the growth rate of each thin film was almost the same. From this, it is considered that Mg and Ca reevaporation hardly occurs during film formation.

FIG. 6 shows the results of X-ray diffraction measurement of an Mg _1-x Ca _x O thin film (composition gradient film) epitaxially grown while changing the Ca concentration x on ZnO according to the position on the substrate, and the Mg ₁ it is a graph showing a lattice constant of _-x Ca _x O thin film. In addition, the lattice constant was calculated from the data of the X-ray diffraction measurement result in the plane (normal direction of the substrate surface). In addition, as shown in FIG. 7, the composition gradient film is formed by placing a movable mask between the target and the substrate and performing laser MBE while moving the movable mask as appropriate.

As shown in this figure, a (111) mono-oriented Mg _1-x Ca _x O thin film was obtained in the range of 0.2 <x <0.8. Moreover, the result that a lattice constant increases continuously according to the increase in Ca concentration was obtained. In addition, precipitation of a heterogeneous phase and MgO and CaO was not recognized.

FIG. 8A is a model diagram showing the crystal structure of Mg _1-x Ca _x O, and FIG. 8B is a model diagram showing the crystal structure of ZnO. As shown in these figures, Mg _1-x Ca _x O has a rock-salt crystal structure, and ZnO has a wurtzite crystal structure. Further, Mg ²⁺ in _{Mg 1-x Ca x O,} Ca 2+ is present, since Zn ²⁺ is present in the ZnO, electric charge matching ZnO and Mg _1-x Ca x O. In addition, the lattice constant a _{WZ of} ZnO is 3.250 格子, and the lattice constant a _RS of Mg _1-x Ca _x O varies between 4.21Å and 4.811 応 じ depending on the Ca concentration x.

FIG. 8C is an explanatory view showing the state of an interface when Mg _1-x Ca _x O is epitaxially grown on ZnO. As shown in this figure, the (111) plane of Mg _1-x Ca _x O is disposed on the (0001) plane of ZnO. Therefore, if the value obtained by multiplying the lattice constant a _RS of Mg _1-x Ca _x O by √2 / 2, that is, a _RS × √2 / 2 matches the lattice constant of ZnO, ZnO and Mg _1-x Ca _x O can be lattice-matched.

FIG. 9 is a graph showing the relationship between the value of Ca concentration x in Mg _1-x Ca _x O and (√2 / 2) a _RS . As shown in this figure, the value of (√2 / 2) a _RS is proportional to the Ca concentration x. In calculation, when x = 0.64, the value of (√2 / 2) a _RS coincides with the lattice constant of 3.250Ｏ of ZnO, and the lattice mismatch rate (Lattice mismatch) becomes 0%.

FIG. 10 shows the result of reciprocal lattice space mapping for each Mg _1-x Ca _x O with Ca concentration x = 0.58, 0.53, 0.43. Here, a sample was used in which ZnO with a thickness of 20 nm was epitaxially grown on a sapphire (c-sapphire) substrate, and Mg _1-x Ca _x O with a thickness of 200 nm was epitaxially grown thereon.

As shown in this figure, when x = 0.58, the Qx (rlu) of ZnO (105), Mg _1-x Ca _x O (242), and Mg _1-x Ca _x O (331) match, In-plane lattice matching is obtained. In the case of x = 0.53 and 0.43, the in-plane lattice matching decreased as the difference in x from x = 0.58 was increased. Based on this result, in the transistor 1, the Ca concentration x of Mg _1-x Ca _x O in the interface modification layer 7 is set to 0.58.

  Next, the characteristics of the transistor 1 will be described in comparison with the characteristics of the transistor 1a, which is a modified example of the semiconductor device according to the present embodiment, and the comparison transistor 101.

FIG. 11 is a cross-sectional view showing a schematic configuration of the transistor 1a. As shown in this figure, the transistor 1a has the same element configuration as that of the transistor 1 except that the buffer layer 3 is not provided. However, in the transistor 1a, the composition (Ca concentration x) of Mg _1-x Ca _x O formed as the interface modification layer 7 is not identified. Further, the film thickness, channel width W, and channel length L of each layer are different from those of the transistor 1. Specifically, the transistor 1a has a width W = 60 nm and a length L = 220 nm, the channel layer 4 (ZnO) has a film thickness of 200 nm, and the interface modification layer 7 (Mg _1-x Ca _x O) film. The thickness is 50 nm, and the thickness of the gate insulating layer 8 (a-AlO _x ) is 500 nm.

  FIG. 12 is a cross-sectional view showing a schematic configuration of the comparison transistor 101. As shown in this figure, the comparison transistor 101 has the same configuration as that of the transistor 1a except that the interface modification layer 7 is not provided. That is, the comparison transistor 101 does not include the buffer layer 3 and the interface modification layer 7.

13 (a) to 13 (c) are graphs showing transfer characteristics of the transistor 1, the transistor 1a, and the comparison transistor 101, respectively. The horizontal axis represents the gate voltage Vg (V), and the vertical axis (left side). Id (A), Ig (A), and the vertical axis (right side) indicate Id ^1/2 (× 10 ⁻³ A ^1/2 ).

  14A is a graph showing the output characteristics of the transistors 1 and 1a, and FIG. 14B is a graph showing the output characteristics of the comparison transistor 101. FIG. The horizontal axis represents the drain-source voltage Vds (V), and the vertical axis represents the drain current Id (μA).

  Table 1 is a table summarizing the characteristics of the transistor 1, the transistor 1a, and the comparison transistor 101.

As shown in Table 1, the S value (subthreshold coefficient; subthreshold voltage swing) of the transistors 1 and 1a is reduced to 1/3 or less of the S value of the comparison transistor 101. Therefore, by forming Mg _1-x Ca _x O as the interface modification layer 7 on the ZnO as the channel layer 4, the lattice matching and charge matching at the ZnO interface can be improved, and the S value can be increased. It can be seen that it can be greatly improved.

  The S value is a value representing the rising characteristic in the subthreshold region. The drain current characteristic when the gate voltage is lower than the threshold voltage and the inversion state on the semiconductor surface is weak is called the subthreshold characteristic, and the subthreshold coefficient is used as a parameter for evaluating the goodness of the subthreshold characteristic. The S value is a gate voltage necessary for changing the digit current of the drain current, and is defined by S = dVg / dlog (Id) (unit: volt / decade).

Further, by setting the Ca concentration x in Mg _1-x Ca _x O to x = 0.58 (or by making x close to 0.58), ZnO and Mg _1-x Ca _x O It can be seen that the lattice matching can be further improved and the S value can be further improved.

Further, the Ca concentration x in Mg _1-x Ca _x O is set to x = 0.58 (or x is set to a value close to 0.58), and the substrate 2 and the channel layer 4 (ZnO) By providing the buffer layer 3 therebetween, mobility (field effect mobility) can be improved. This is considered to be because the crystallinity of ZnO could be improved by providing the buffer layer 3.

Further, in the transistor 1a, by providing the interface modification layer 7 made of Mg _1-x Ca _x O, the off current (drain current when the channel is closed) is reduced more than the comparison transistor 101, and the On / The Off ratio (On current is the current value at the operating voltage of the transistor) can be increased.

  In the transistor 1, the Off current is larger than that of the transistor 1a, and the On / Off ratio is lowered accordingly. This is considered due to the fact that the resistance value of the buffer layer 3 (annealed ZnO) is low and that the transistor 1 has a smaller element size than the transistor 1a.

Therefore, a buffer layer 3 made of annealed MgZnO is formed on a substrate made of ScAlMgO ₄ , and ZnO having a film thickness of 200 nm is epitaxially grown thereon to form a channel layer 4, and an interface modification layer 7 formed thereon. A plurality of transistors 1 in which Mg _0.42 Ca _0.58 O having a thickness of 100 nm was epitaxially grown were prepared by changing the values of width W and length L, and their characteristics were examined. Note that the annealing treatment applied to the MgZnO was performed at an annealing temperature of 1000 ° C. and an annealing time of 1 hour in the atmosphere.

Specifically, as shown in FIG. 15, (W × L) = (15 × 5), (15 × 20), (15 × 50), (50 × 5), (50 × 20), (50 A plurality of six types of transistors 1 of × 50) were prepared and their characteristics were examined. In FIG. 15, x indicates an element (transistor) broken in the manufacturing process (process), ▲ indicates an unstable element, and ● indicates a mobility of 100 cm ² / V · s or more and less than 200 cm ² / V · s. Elements marked with ▪ indicate elements with a mobility of 200 cm ² / V · s or higher. As shown in this figure, when annealed MgZnO (having a higher resistance value than ZnO) is used as the buffer layer 3, a mobility of 200 cm ² / V · s or more can be realized depending on the element size.

FIG. 16A is a graph showing the transfer characteristics of the transistor 1 in which MgZnO annealed as the buffer layer 3 is formed. FIG. 16B shows the gate voltage characteristics of the field effect mobility in the transistor 1. It is a graph to show. As shown in this figure, the characteristics of S = 0.2, Off current 10 ⁻¹¹ A, On / Off ratio 10 ⁷ were obtained. Therefore, the buffer layer 3 is preferably made of a material that can improve the crystallinity of ZnO epitaxially grown on the buffer layer 3 and has high resistance.

  The buffer layer 3 is not limited to the above-described ZnO and MgZnO. For example, an element that can be dissolved in ZnO, has high lattice matching with ZnO, and has a high band gap (high resistance) can be used. For example, MgCaO may be used as the buffer layer.

In the transistors 1 and 1a according to the present embodiment, the interface modification layer 7 is formed in the region where the source electrode 5 and the drain electrode 6 are not formed on the channel layer 4, but the present invention is not limited to this. . For example, as shown in FIG. 17, ZnO as the channel layer 4 and Mg _1-x Ca _x O as the interface modification layer 7 are continuously formed, and the source electrode 5 and the drain electrode 6 are formed thereon. It may be formed.

  In this embodiment, the transistors 1 and 1a having a top gate structure (a structure in which a gate electrode is provided on the side far from the substrate 2, that is, the surface side) have been described, but the present invention is not limited to this. For example, as illustrated in FIG. 18, a transistor 1b having a bottom gate structure (a structure in which a gate electrode is provided on the substrate 2 side) may be used.

In the example shown in FIG. 18, the gate electrode 9 is formed in a predetermined shape on the substrate 2, the gate insulating layer 8 is provided so as to cover the substrate 2 and the gate electrode 9, and the gate insulating layer is formed in the region on the gate electrode 9. 8, Mg _1-x Ca _x O is provided as the interface modification layer 7. Further, ZnO is epitaxially grown as the channel layer 4 on the interface modification layer 7. A source electrode 5 and a drain electrode 6 are provided at both ends of the channel layer 4.

In this configuration, the interface modification layer 7 is preferably formed so as to be (111) oriented. Thereby, Mg _1-x Ca _x O as the interface modification layer 7 can function as an alignment film for controlling the alignment of ZnO.

  In this configuration, the substrate 2 only needs to have heat resistance that can withstand a growth temperature of 700 ° C. for epitaxial growth of ZnO, and it is not always necessary to consider lattice matching with ZnO. Therefore, the selectivity of the substrate material can be expanded.

In the case of a bottom gate transistor, the interface modification layer is formed not only on the substrate side surface (channel surface) of the channel layer 4 but also on the surface of the channel layer 4 opposite to the substrate 2 (back channel side). As an example, an Mg _1-x Ca _x O film may be provided. FIG. 19 is a cross-sectional view showing the configuration of the transistor 1c in which the interface modification layer 7a is also provided on the back channel side as described above. Thus, by providing the interface reforming layer 7a on the back channel side, the charge matching can be improved.

In this embodiment, the case where single crystal ZnO is mainly used as the channel layer 4 has been described, but the present invention is not limited to this. For example, in each of the transistors (1, 1a to 1c) described above, polycrystalline ZnO may be used as the channel layer 4, and in that case, polycrystalline ZnO as the channel layer 4 and the interface modified layers 7, 7a may be used. Mg _1-x Ca _x O may be formed at 300 ° C. or lower.

  In addition, each of the transistors according to the present embodiment can be used as a switching element provided in each pixel of an active matrix display device (for example, a liquid crystal display device, an organic EL display device, etc .; an electronic device). FIG. 20 is a block diagram illustrating a schematic configuration of a liquid crystal display device 200 in which the transistor 1 is provided in each pixel (PIX) 37. FIG. 21 is an equivalent circuit diagram showing the configuration of each pixel in the liquid crystal display device 200.

   HYPERLINK "JP-A-2005-33172.files / 000014.gif" As shown in FIG. 20, the liquid crystal display device 200 is an active matrix type liquid crystal display device, and includes a pixel array 31, a source driver 32, A gate driver 33, a control circuit 34, and a power supply circuit 35 are provided.

  The pixel array 31, the source driver 32, and the gate driver 33 are formed monolithically on the substrate 36. The substrate 36 is made of an insulating and translucent material such as glass. The pixel array 31 includes source lines SL, gate lines GL, and pixels 37.

In the pixel array 31, a large number of gate lines GL _j , GL _{j + 1} ,... And a large number of source lines SL _i , SL _{i + 1} ,. A pixel (PIX) 37 is provided for each part surrounded by the two source lines SL and SL adjacent to the gate lines GL and GL. In this way, the pixels 37 are arranged in a matrix in the pixel array 31, and one source line SL is assigned per column, and one gate line GL is assigned per row. Yes.

For a liquid crystal display, each pixel 31, as shown in FIG. 21, the transistor 1 is a switching element is constituted by a pixel capacitor C _P including a liquid crystal capacitance C _L. In general, the pixel capacitance C _P in an active matrix type liquid crystal display, in order to stabilize the display, and a storage capacitance C _S which is added in parallel with liquid crystal capacitance C _L. The auxiliary capacitor C _S includes a liquid crystal capacitor C _L , a leakage current of the transistor 1, a gate-source capacitance of the transistor 1, a variation in pixel potential due to parasitic capacitance such as a pixel electrode / signal line capacitance, and display data of the liquid crystal capacitor C _L. It works to minimize the influence of dependencies.

The gate of the transistor 1 is connected to the gate line GL _j . One electrode of the liquid crystal capacitor C _L and the auxiliary capacitor C _S is connected to the source line SL _j through the drain and source of the transistor 1. Electrode of the liquid crystal capacitance C _L is connected to the drain forms the pixel electrode 37a. The other electrode of the liquid crystal capacitor C _L is connected to the counter electrode across the liquid crystal cell, and the other electrode of the auxiliary capacitor C _S is a common electrode line (not shown) common to all pixels (in the case of the Cs on Common structure), Alternatively, it is connected to an adjacent gate line GL (in the case of a Cs on Gate structure).

Many gate lines GL _j , GL _{j + 1} ... Are connected to the gate driver 33, and many data signal lines SL _i , SL _{i + 1} . The gate driver 33 and the source driver 32 are driven by different power supply voltages V _GH and V _GL and power supply voltages V _SH and V _SL , respectively.

The source driver 32 samples the image signal DAT given by the control circuit 34 based on the synchronization signal CKS and the start pulse SPS from the control circuit 34, and connects the source lines SL _i and SL _{i +} connected to the pixels of each column. ₁ … is output. The gate driver 33 generates gate signals to be applied to the gate lines GL _j , GL _{j + 1} ... Connected to the pixels 37... Of each row based on the synchronization signal CKG · GPS and the start pulse SPG from the control circuit 34. It has become.

The power supply circuit 35 is a circuit that generates power supply voltages V _SH , V _SL , V _GH , V _GL , a ground potential COM, and a voltage V _BB . The power supply voltages V _SH and V _SL are voltages having different levels, and are supplied to the source driver 32. The power supply voltages V _GH and V _GL are voltages having different levels, and are _{supplied to} the gate driver 33. The ground potential COM is applied to a common electrode line (not shown) provided on the substrate 36.

When the transistor 1 is turned on by a gate signal supplied from the gate driver 33 via the gate line GL _j , an image signal supplied from the source driver 32 via the source line SL _{i + 1} is written to the pixel 37 (pixel electrode 37a). .

  In the liquid crystal display device 200, the transistors 1a to 1c may be used instead of the transistor 1. The channel layer 4 may be made of single crystal ZnO or polycrystalline ZnO.

  Further, when the transistors (1, 1a to 1c) according to the present embodiment are used as the transistors included in each pixel of the display device, the interface modification layers 7, 7a, the gate electrode 9, the source electrode 5, and the drain electrode 6 Any one or more of them may be formed of an electrode material that is transparent to visible light. Thereby, a transparent area | region with respect to visible light can be expanded, and the transmittance | permeability of a display apparatus can be improved.

  The transistor according to the present embodiment is not limited to an active matrix display device, and can be used as a switching element provided in an image reading device (electronic device) such as an image sensor, for example. In this case, the switching element is turned on when reading the pixel signal taken into the pixel electrode. Further, the transistor according to the present embodiment is applicable not only to a display device and an image reading device but also to various electronic devices.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims. That is, embodiments obtained by combining technical means appropriately changed within the scope of the claims are also included in the technical scope of the present invention.

  The present invention can be applied to a transistor using zinc oxide as a channel layer.

It is sectional drawing which shows schematic structure of the transistor concerning one Embodiment of this invention. It is sectional drawing which shows schematic structure of the laser MBE apparatus used in one Embodiment of this invention. The ZnO on a substrate made of ScAlMgO ₄ is epitaxially grown, is a graph indicating a result of the on Mg _1-x Ca _x O epitaxially grown X-ray diffraction measurement of the substrate. When ZnO is epitaxially grown on a substrate made of ScAlMgO ₄ and Mg _1-x Ca _x O is further epitaxially grown at a Ca concentration x = 0.64, and when epitaxial growth is performed at x = 0.50 It is a graph which shows the result of a X-ray-diffraction measurement. The relationship between the Ca concentration of the target and the Ca concentration of the Mg _1-x Ca _x O thin film was investigated when the Mg _1-x Ca _x O thin film was epitaxially grown by laser MBE using a sintered body of MgO and CaO as a target. It is a graph which shows a result. Mg _1-x Ca _x O compositionally graded film results of X-ray diffraction measurements, and is a graph showing the Mg _1-x Ca _x O lattice constant of the thin film. Is an explanatory view showing a manufacturing method of Mg _1-x Ca _x O compositionally graded film shown in FIG. (A) is a model diagram showing the crystal structure of _{Mg 1-x Ca x O,} (b) is a model diagram showing the crystal structure of ZnO. (C) is an explanatory view showing the state of the interface when epitaxially growing a Mg _1-x Ca _x O on ZnO. The value of the Ca concentration x in mg _1-x Ca _x O, which is a graph showing the relationship between (√2 / 2) a _RS. Note that a _RS is a lattice constant of Mg _1-x Ca _x O. It is a graph which shows the result of reciprocal space mapping of Mg _1-x Ca _x O. It is sectional drawing which shows the modification of the transistor concerning one Embodiment of this invention. It is explanatory drawing which shows schematic structure of the transistor for a comparison used for the characteristic comparison with the transistor of this invention shown in FIG. 1 and FIG. (A) is a graph showing the transfer characteristics of the transistor shown in FIG. 1, (b) is a graph showing the transfer characteristics of the transistor shown in FIG. 11, and (c) is a transfer characteristic of the comparison transistor shown in FIG. It is a graph to show. (A) is a graph which shows the output characteristic of the transistor shown in FIG. 1 and FIG. 11, (b) is a graph which shows the output characteristic of the transistor for a comparison shown in FIG. It is explanatory drawing which showed the relationship between the channel width W and the channel length L, and the measurement result of mobility in the transistor concerning one Embodiment of this invention. (A) is a graph showing transfer characteristics when annealed MgZnO is used as a buffer layer in the transistor structure shown in FIG. 1, and (b) is a graph showing gate voltage characteristics of mobility in the transistor. It is. It is sectional drawing which shows the modification of the transistor concerning one Embodiment of this invention. It is sectional drawing which shows the modification of the transistor concerning one Embodiment of this invention. It is sectional drawing which shows the modification of the transistor concerning one Embodiment of this invention. It is a block diagram which shows schematic structure of the liquid crystal display device (electronic device) provided with the transistor concerning one Embodiment of this invention. FIG. 21 is an equivalent circuit diagram illustrating a configuration of each pixel in the liquid crystal display device illustrated in FIG. 20.

Explanation of symbols

1, 1a, 1b, 1c Transistor 2 Substrate 3 Buffer layer 4 Channel layer 5 Source electrode 6 Drain electrode 7 Interface modification layer 7a Interface modification layer 8 Gate insulating layer 9 Gate electrode a _RS Mg _1-x Ca _x O lattice Constant a _wz ZnO lattice constant x Mg _1-x Ca _x O or Mg concentration in the sintered body of MgO-CaO

Claims (11)

A transistor comprising a substrate, a channel layer made of ZnO, a source electrode and a drain electrode connected to the channel layer, and a gate electrode provided with a gate insulating layer between the channel layer. ,
A transistor characterized in that an interface modification layer made of Mg _1-x Ca _x O (0.2 <x <0.8) is provided at the interface on the gate insulating layer side in the channel layer. The transistor according to claim 1, wherein the interface modification layer is Mg _0.42 Ca _0.58 O.   3. The transistor according to claim 1, wherein a channel layer, a gate insulating layer, and a gate electrode are arranged in this order when viewed from the substrate side. A buffer layer is formed between the substrate and the channel layer;
The transistor according to claim 3, wherein the channel layer is formed on the buffer layer.   The transistor according to claim 4, wherein the buffer layer is annealed MgZnO.   3. The transistor according to claim 1, wherein a gate electrode, a gate insulating layer, and a channel layer are arranged in this order when viewed from the substrate side. A second interface modification layer made of Mg _1-x Ca _x O (0.2 <x <0.8) is provided on the interface of the channel layer opposite to the gate insulating layer side. The transistor according to claim 6.   The transistor according to claim 1, wherein the channel layer is single crystal ZnO.   The transistor according to claim 1, wherein the channel layer is polycrystalline ZnO.   An electronic device comprising the transistor according to claim 1. The electronic device is a display device or an image reading device,
11. The electronic device according to claim 10, wherein the transistor is connected to the pixel electrode in order to control writing or reading of an image signal to the pixel electrode.