JP2007073312A - Sputtering target, and method of forming thin film using the target - Google Patents

Sputtering target, and method of forming thin film using the target Download PDF

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JP2007073312A
JP2007073312A JP2005258273A JP2005258273A JP2007073312A JP 2007073312 A JP2007073312 A JP 2007073312A JP 2005258273 A JP2005258273 A JP 2005258273A JP 2005258273 A JP2005258273 A JP 2005258273A JP 2007073312 A JP2007073312 A JP 2007073312A
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amorphous oxide
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JP5058469B2 (en
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Susumu Hayashi
享 林
Masafumi Sano
政史 佐野
Katsumi Abe
勝美 安部
Hideya Kumomi
日出也 雲見
Hisato Yabuta
久人 薮田
Tatsuya Iwasaki
達哉 岩崎
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Canon Inc
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a sputtering target for obtaining high reproducibility and yield when forming an amorphous oxide film by sputtering. <P>SOLUTION: The oxide sputtering target is a sintered compound target used when forming a film by sputtering the amorphous oxide film containing at least In, Zn, and Ga. The target containing In, Zn, and Ga as its constituent has a relative density of 75% or higher and a resistivity ρ of 50 Ωcm or less. The target is a sintered compound of polycrystalline oxide showing crystal structure of homologous phase. The amorphous oxide film having electron carrier density of less than 10<SP>18</SP>/cm<SP>3</SP>is formed at a temperature of not less than room temperature and not higher than 450°C by the sputtering method. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、スパッタリングターゲット、特にアモルファス酸化物膜の形成に適したスパッタリングターゲットおよび該ターゲットを用いた薄膜の形成方法に関する。   The present invention relates to a sputtering target, particularly a sputtering target suitable for forming an amorphous oxide film, and a method for forming a thin film using the target.

近年、ZnOを主成分として用いた透明伝導性酸化物多結晶薄膜を透明電極のみならず、チャネル層に用いたTFTの開発が活発に行われている。上記薄膜は、低温で成膜でき、かつ可視光に透明であるため、プラスチック板やフィルムなどの基板上にフレキシブルな透明TFTを形成することが可能であるとされている。その形成手段として、大面積にわたり均一な薄膜を形成可能なスパッタリング法が有望である。   In recent years, TFTs using a transparent conductive oxide polycrystalline thin film containing ZnO as a main component not only for a transparent electrode but also for a channel layer have been actively developed. Since the thin film can be formed at a low temperature and is transparent to visible light, it is said that a flexible transparent TFT can be formed on a substrate such as a plastic plate or a film. As a forming means, a sputtering method capable of forming a uniform thin film over a large area is promising.

例えば、特許文献1には、ZnOを主成分として用いた透明伝導性酸化物多結晶薄膜をチャネル層に用いたTFTが開示されている。また、特許文献2には、非晶質酸化物膜でであるZnIn(x+3y/2+3z/2)を透明電極に用いることが記載されている(Mは、Al及びGaのうち少なくとも一つの元素であり、比率x/yが0.2〜12の範囲であり、比率z/yが0.4〜1.4の範囲にある)。 For example, Patent Document 1 discloses a TFT using a transparent conductive oxide polycrystalline thin film containing ZnO as a main component for a channel layer. Patent Document 2 describes that an amorphous oxide film of Zn x M y In z O (x + 3y / 2 + 3z / 2) is used for a transparent electrode (M is a combination of Al and Ga). And at least one element, the ratio x / y is in the range of 0.2 to 12, and the ratio z / y is in the range of 0.4 to 1.4).

これらの透明伝導性酸化物膜の形成手段として、大面積にわたり均一な薄膜を形成可能なスパッタリング法が有望である。
特開2004−103957号公報 特開2000−044236号公報
As a means for forming these transparent conductive oxide films, a sputtering method capable of forming a uniform thin film over a large area is promising.
JP 2004-103957 A Japanese Patent Laid-Open No. 2000-044236

ZnOを主成分とした伝導性透明酸化物では、酸素欠陥が入りやすく、キャリア電子が多数発生し、電気伝導度を小さくすることが難しい。更にスパッタリング法による成膜の際に、異常放電が発生し、成膜の安定性が損なわれ、得られる膜の均一性及び再現性が低下する。このために、例えばTFT(薄膜トランジスタ)の活性層(チャネル層)として使用する際にゲート電圧無印加時でも、ソース端子とドレイン端子間に大きな電流が流れてしまい、TFTのノーマリーオフ動作を実現できない。また、トランジスタのオン・オフ比を大きくすることも難しい。   In the conductive transparent oxide containing ZnO as a main component, oxygen defects are likely to occur, a large number of carrier electrons are generated, and it is difficult to reduce the electrical conductivity. Furthermore, abnormal discharge occurs during film formation by sputtering, and the stability of the film formation is impaired, and the uniformity and reproducibility of the resulting film are reduced. For this reason, for example, when it is used as an active layer (channel layer) of a TFT (thin film transistor), a large current flows between the source terminal and the drain terminal even when no gate voltage is applied, thereby realizing a normally-off operation of the TFT. Can not. It is also difficult to increase the on / off ratio of the transistor.

また、特許文献2に記載されている相対密度40%更には70%以上の混晶焼結体もしくはホモロガスの焼結体をスパッタリング法に用いた場合、スパッタリング成膜における不安定要素が顕在化する場合がある。そして作製したTFTの再現性及び歩留まりが低いものとなる場合がある。そのためTFTのチャンネル層に適した電子キャリア濃度が1018/cm未満の膜を安定して得ることが難しかった。 Further, when a mixed crystal sintered body or a homologous sintered body having a relative density of 40% or 70% or more described in Patent Document 2 is used in the sputtering method, unstable elements in the sputtering film formation become apparent. There is a case. In some cases, the reproducibility and yield of the manufactured TFT may be low. Therefore, it has been difficult to stably obtain a film having an electron carrier concentration less than 10 18 / cm 3 suitable for a TFT channel layer.

解析の結果、その不安定要素の原因は、ITOなどの透明導電膜の成膜では許容できる程度の微小なアーキングと呼ばれる異常放電や異常放電に伴い発生するノジュールと呼ばれる針状突起の発生、黒化等ターゲット表面の酸化状態の変化に起因するものであった。   As a result of the analysis, the cause of the unstable factors is the occurrence of abnormal discharge called micro-arcing that is acceptable for film formation of a transparent conductive film such as ITO, acicular protrusions called nodules that occur with abnormal discharge, black This was caused by a change in the oxidation state of the target surface such as crystallization.

本発明者らの知見によれば、これらの変化はアモルファス酸化物薄膜の電子キャリア濃度にも変化を与える。そして電子キャリア濃度の変化はTFTの電気特性に直接影響を与えるため、TFTの均一性及び歩留まりに悪影響を及ぼす。そのためTFTのチャンネル層に適した電子キャリア濃度が1018/cm未満の膜を安定して得ることが困難である。 According to the knowledge of the present inventors, these changes also change the electron carrier concentration of the amorphous oxide thin film. Since the change in the electron carrier concentration directly affects the electrical characteristics of the TFT, it adversely affects the uniformity and yield of the TFT. Therefore, it is difficult to stably obtain a film having an electron carrier concentration less than 10 18 / cm 3 suitable for a TFT channel layer.

そこで、本発明の目的は、これらの課題を解決し、アモルファス酸化物膜をスパッタリング成膜する際に高い再現性と歩留まりを得るためのスパッタリングターゲットを提供することにある。   Therefore, an object of the present invention is to solve these problems and provide a sputtering target for obtaining high reproducibility and yield when an amorphous oxide film is formed by sputtering.

本発明者らは、InGaO(ZnO)の膜及びこれに関する膜の成長条件に関する研究開発を精力的に進めた結果、スパッタリングターゲットの組成、抵抗値、及び密度を所定の範囲内に調整することにより前記課題を解決できるという知見を得た。 As a result of intensive research and development on the growth conditions of the InGaO 3 (ZnO) m film and related films, the present inventors adjust the composition, resistance value, and density of the sputtering target within a predetermined range. The knowledge that the said subject can be solved was obtained.

具体的には、スパッタリング成膜時の諸条件に加え、酸化物焼結体スパッタリングターゲットとして相対密度が75%以上、且つ抵抗値ρが50Ωcm以下に調整するものである。このような特定のターゲットを使用することにより、電子キャリア濃度の制御性を改善し電子キャリア濃度が1018/cm未満のアモルファス酸化物薄膜を安定して作製することが可能となる。 Specifically, in addition to various conditions during sputtering film formation, the oxide sintered compact sputtering target is adjusted to have a relative density of 75% or more and a resistance value ρ of 50 Ωcm or less. By using such a specific target, it becomes possible to improve the controllability of the electron carrier concentration and stably produce an amorphous oxide thin film having an electron carrier concentration of less than 10 18 / cm 3 .

ここで本発明における上記ターゲットの抵抗値とは、「バルク抵抗値」とも呼ばれる。そしてバルク形状(抵抗値を測定する際に抵抗値に影響を与えない程度に十分大きい大きさを有する)の試料において、例えば4端子法により抵抗値を求めることができる。   Here, the resistance value of the target in the present invention is also referred to as “bulk resistance value”. In a sample having a bulk shape (having a sufficiently large size that does not affect the resistance value when measuring the resistance value), the resistance value can be obtained by, for example, a four-terminal method.

本発明は、上記のInGaO(ZnO)膜の形成に適したスパッタリングターゲット及び該ターゲットを用いた薄膜の形成方法を提供するものである。 The present invention provides a sputtering target suitable for forming the above InGaO 3 (ZnO) m film and a method for forming a thin film using the target.

以下、具体的に本発明について説明する。   The present invention will be specifically described below.

本発明によるアモルファス酸化物膜の形成に適したスパッタリングターゲットは、少なくともIn、Zn、Gaを含むアモルファス酸化物膜をスパッタリング成膜する際に用いられる焼結体ターゲットに関する。そして、(1)その組成にIn、Zn、Gaを含み、相対密度が75%以上、且つ抵抗値ρが50Ωcm以下であることを特徴とする。   The sputtering target suitable for the formation of the amorphous oxide film according to the present invention relates to a sintered body target used when sputtering an amorphous oxide film containing at least In, Zn, and Ga. (1) The composition contains In, Zn, and Ga, the relative density is 75% or more, and the resistance value ρ is 50 Ωcm or less.

また本発明は、(2)少なくともIn、Zn、Gaを含むアモルファス酸化物膜をスパッタリング成膜する際に用いられる焼結体ターゲットが、ホモロガス相の結晶構造を示す多結晶酸化物焼結体であることが好ましい。   In the present invention, (2) a sintered compact target used when sputtering an amorphous oxide film containing at least In, Zn, and Ga is a polycrystalline oxide sintered body having a homologous crystal structure. Preferably there is.

また本発明は、(3)アモルファス酸化物膜をスパッタリング成膜する際に用いられる焼結体ターゲットが多結晶酸化物焼結体であり、原子数比がIn:Ga:Zn=1:x(0.1≦x≦10):m(m<6)であることが好ましい。   In the present invention, (3) the sintered compact target used when sputtering the amorphous oxide film is a polycrystalline oxide sintered body, and the atomic ratio is In: Ga: Zn = 1: x ( 0.1 ≦ x ≦ 10): m (m <6) is preferable.

本発明によるスパッタリングターゲットを用いた薄膜の形成方法は、アモルファス酸化物膜をスパッタリング成膜する際に用いられる焼結体ターゲットに関する。そして、上記(1)〜(3)のいずれかに記載されるスパッタリングターゲットを用いて電子キャリア濃度が、1018/cm未満のアモルファス酸化物膜を室温以上450℃以下の成膜温度でスパッタリング成膜することを特徴とする。 The thin film formation method using the sputtering target according to the present invention relates to a sintered compact target used when an amorphous oxide film is formed by sputtering. Then, using the sputtering target described in any one of (1) to (3) above, an amorphous oxide film having an electron carrier concentration of less than 10 18 / cm 3 is sputtered at a deposition temperature of room temperature to 450 ° C. It is characterized by forming a film.

本発明は、相対密度が75%以上、且つ抵抗値ρが50Ωcm以下のスパッタリングターゲットを構成している。このような高密度、且つ低抵抗なターゲットを用いると、アモルファス酸化物膜のスパッタリング成膜の際に、不安定要素の原因となる微小なアーキングと呼ばれる異常放電が大幅に抑制される。そして異常放電に伴い発生するノジュールと呼ばれる針状突起の発生、及び黒化等ターゲット表面の酸化状態の変化も大幅に抑制される。   The present invention constitutes a sputtering target having a relative density of 75% or more and a resistance value ρ of 50 Ωcm or less. When such a high-density and low-resistance target is used, abnormal discharge called minute arcing that causes unstable elements is significantly suppressed during sputtering of an amorphous oxide film. And generation | occurrence | production of the acicular protrusion called nodule which generate | occur | produces with abnormal discharge, and the change of the oxidation state of the target surface, such as blackening, are also suppressed significantly.

これらの変化は、スパッタリング成膜で得られるアモルファス酸化物薄膜の電子キャリア濃度にも変化を与える。このため、アモルファス酸化物薄膜をTFTのチャネル層として用いた場合、TFTの電気特性に直接影響を与え、TFTの均一性及び歩留まり改善に非常に有効である。このために、アモルファス酸化物薄膜をTFTの活性層として使用する際に、TFTのノーマリーオフ動作を確実に実現できる。また、トランジスタのオン・オフ比を10以上にすることも可能となる。 These changes also change the electron carrier concentration of the amorphous oxide thin film obtained by sputtering film formation. For this reason, when an amorphous oxide thin film is used as a channel layer of a TFT, it directly affects the electrical characteristics of the TFT and is very effective in improving the uniformity and yield of the TFT. For this reason, when the amorphous oxide thin film is used as the active layer of the TFT, the normally-off operation of the TFT can be reliably realized. In addition, the on / off ratio of the transistor can be increased to 10 6 or more.

本発明によれば、例えばTFTのチャネル層に好適に用いられるアモルファス酸化物薄膜の電子キャリア濃度制御性を改善できる。さらに電子キャリア濃度が1018/cm未満のアモルファス酸化物薄膜を高い再現性と歩留まりで実現できるスパッタリングターゲットの提供が可能となる。 According to the present invention, for example, the electron carrier concentration controllability of an amorphous oxide thin film suitably used for a TFT channel layer can be improved. Furthermore, it is possible to provide a sputtering target capable of realizing an amorphous oxide thin film having an electron carrier concentration of less than 10 18 / cm 3 with high reproducibility and yield.

以上説明したように、本発明によれば、アモルファス酸化物膜をスパッタリング成膜する際に高い再現性と歩留まりを得るためのスパッタリングターゲットを提供することができる。   As described above, according to the present invention, it is possible to provide a sputtering target for obtaining high reproducibility and yield when sputtering an amorphous oxide film.

以下、本発明に係るアモルファス酸化物膜の形成に適したスパッタリングターゲットおよび該ターゲットを用いた薄膜の形成方法を実施するための最良の形態について、図面を参照して具体的に説明する。   The best mode for carrying out a sputtering target suitable for forming an amorphous oxide film according to the present invention and a method for forming a thin film using the target will be specifically described below with reference to the drawings.

本発明によるアモルファス酸化物膜形成に適したスパッタリングターゲット(以下、酸化物スパッタリングターゲット)は、少なくともIn、Zn、Gaを含むアモルファス酸化物膜をスパッタリング成膜する際に用いられる焼結体ターゲットである。このターゲットにおいて、その組成にIn、Zn、Gaを含み、相対密度が75%以上、且つ抵抗値ρが50Ωcm以下であることを特徴とする。好ましくは、その相対密度が90%以上、且つ抵抗値ρが0.5Ωcm以下であることが望ましい。また、さらに好ましくは、その相対密度が95%以上、且つ抵抗値ρが0.1Ωcm以下であることが望ましい。   A sputtering target (hereinafter referred to as an oxide sputtering target) suitable for forming an amorphous oxide film according to the present invention is a sintered body target used when an amorphous oxide film containing at least In, Zn, and Ga is formed by sputtering. . This target is characterized in that its composition contains In, Zn, and Ga, the relative density is 75% or more, and the resistance value ρ is 50 Ωcm or less. Preferably, the relative density is 90% or more and the resistance value ρ is 0.5 Ωcm or less. More preferably, the relative density is 95% or more and the resistance value ρ is 0.1 Ωcm or less.

本発明において、上記相対密度は大きいほど良いため、上限値は存在しない(理想的には100%)。また同様に、抵抗値も小さいほど良いため、下限値は存在しない(理想的には0Ωcm)。   In this invention, since the said relative density is so good that it is large, there is no upper limit (ideally 100%). Similarly, the smaller the resistance value, the better. Therefore, there is no lower limit value (ideally 0 Ωcm).

本発明において、「相対密度」とは、例えば所望のInGaO(ZnO)ターゲットがホモロガス相の単結晶構造を採ったときの密度を100%として規格化する。そして、「実際に作製したInGaO(ZnO)スパッタリングターゲットの密度を所望のInGaO(ZnO)ターゲットがホモロガス相の単結晶構造を採ったときの計算から求めた理想的な密度で割り、規格化したもの」と定義する。 In the present invention, the “relative density” is normalized by setting the density when a desired InGaO 3 (ZnO) m target has a homologous single crystal structure as 100%, for example. And, “the density of the actually produced InGaO 3 (ZnO) m sputtering target is divided by the ideal density obtained from the calculation when the desired InGaO 3 (ZnO) m target has a single crystal structure of the homologous phase, “Standardized”.

前述のように、スパッタリングの際にアーキングと呼ばれる異常放電が発生、また、ターゲット表面にノジュールと呼ばれる針状突起が発生しやすい。その抑制には、ターゲットの密度を可能な限り高く、また抵抗値を斑なく均一に低抵抗化することが求められる。焼結体ターゲットでは、抵抗値ρはその構成組成によって変化するが、スパッタリングの際の安定性には、抵抗値ρの絶対値が最も効果的な制御因子であった。   As described above, abnormal discharge called arcing occurs during sputtering, and acicular protrusions called nodules are likely to occur on the target surface. In order to suppress this, it is required to make the density of the target as high as possible and to reduce the resistance value uniformly and uniformly. In the sintered body target, the resistance value ρ varies depending on the composition, but the absolute value of the resistance value ρ is the most effective control factor for the stability during sputtering.

ターゲットの高密度・低抵抗化のためには、ホットプレス法を用いる場合がある。しかし、大面積成膜を可能とするためのターゲットの大型化に伴い、コストの面から一般にコールドプレス法と呼ばれる製造工程を取ることが望ましい。コールドプレス法とは、酸化物膜の原材料である酸化物粉末の混合体を常温でプレス成形し、酸素含有雰囲気中にて1250℃〜1650℃で焼結し、さらに機械加工を施したものである。その際の焼結温度は、1400℃以上が好ましい。   A hot press method may be used for high density and low resistance of the target. However, it is desirable to take a manufacturing process generally called a cold press method from the viewpoint of cost as the target size for enabling large-area film formation increases. The cold press method is a method in which a mixture of oxide powder, which is a raw material of an oxide film, is press-molded at room temperature, sintered at 1250 ° C to 1650 ° C in an oxygen-containing atmosphere, and further machined. is there. The sintering temperature at that time is preferably 1400 ° C. or higher.

本発明におけるIn、Zn、Gaを含むアモルファス酸化物膜をスパッタリング成膜する際に用いられる焼結体ターゲットは、ホモロガス相の結晶構造を示すものであることが好ましい。本発明における「ホモロガス相の結晶構造」とは、異なる物質の結晶層を何層か重ね合わせた長周期を有する「自然超格子」構造から成る結晶である。結晶周期ないし各薄膜層の厚さが、ナノメーター程度の場合、これら各層の化学組成や層の厚さの組み合わせによって、単一の物質あるいは各層を均一に混ぜ合わせた混晶の性質とは異なる固有の特性が得られる。そして、ホモロガス相の結晶構造は、例えばターゲットを粉砕したパウダーにおけるX線回折パターンが、組成比から想定されるホモロガス相の結晶構造X線回折パターンと一致することから確認できる。具体的には、JCPDS(Joint Committee of Powder Diffraction Standards)カードから得られるホモロガス相の結晶構造X線回折パターンと一致することから確認することができる。   It is preferable that the sintered compact target used when sputtering the amorphous oxide film containing In, Zn, and Ga in the present invention has a homologous phase crystal structure. The “crystal structure of the homologous phase” in the present invention is a crystal having a “natural superlattice” structure having a long period in which several crystal layers of different substances are stacked. When the crystal cycle or thickness of each thin film layer is on the order of nanometers, depending on the combination of the chemical composition of these layers and the thickness of the layers, it differs from the properties of a single substance or a mixed crystal in which each layer is uniformly mixed. Unique characteristics can be obtained. The crystal structure of the homologous phase can be confirmed, for example, because the X-ray diffraction pattern of the powder obtained by pulverizing the target matches the crystal structure X-ray diffraction pattern of the homologous phase assumed from the composition ratio. Specifically, it can be confirmed from the coincidence with the crystal structure X-ray diffraction pattern of the homologous phase obtained from a JCPDS (Joint Committee of Powder Diffraction Standards) card.

本発明によるスパッタリングターゲットは、In、Zn、Gaを含む多結晶酸化物焼結体である。そして原子数比がIn:Ga:Zn=1:x:m(0.1≦x≦10、m<6)の範囲に調整することが好ましい。   The sputtering target according to the present invention is a polycrystalline oxide sintered body containing In, Zn, and Ga. The atomic ratio is preferably adjusted to a range of In: Ga: Zn = 1: x: m (0.1 ≦ x ≦ 10, m <6).

本発明のスパッタリングターゲットの作製は、例えば出発原料としてIn、Ga、ZnO(各4N試薬)を所定の比率で湿式混合し、仮焼、乾式粉砕、本焼結(1400℃)することで作製できる。結晶状態における組成がInGaO(ZnO)(mは6未満の自然数)で表されるアモルファス酸化物薄膜は、mの値が6未満の場合は、800℃以上の高温まで、アモルファス状態が安定に保たれる。しかし、mの値が大きくなるにつれ、すなわち、InGaOに対するZnOの比が増大して、ZnO組成に近づくにつれ、結晶化しやすくなる。 For producing the sputtering target of the present invention, for example, In 2 O 3 , Ga 2 O 3 and ZnO (each 4N reagent) as starting materials are wet-mixed at a predetermined ratio, calcined, dry pulverized, and finally sintered (1400 ° C. ). An amorphous oxide thin film whose composition in the crystalline state is represented by InGaO 3 (ZnO) m (m is a natural number less than 6) is stable in an amorphous state up to a high temperature of 800 ° C. or higher when the value of m is less than 6. To be kept. However, as the value of m increases, that is, the ratio of ZnO to InGaO 3 increases, and as it approaches the ZnO composition, it becomes easier to crystallize.

従って、アモルファス酸化物TFTのチャネル層としては、mの値が6未満であることが好ましい。また、アモルファス酸化物薄膜のキャリアである電子は、ITOなどの透明導電性酸化膜と同様に酸素欠陥に由来すると考えられるので、スパッタ成膜条件である酸素ガス分圧や印加電力密度の調整により制御できる。   Therefore, the value of m is preferably less than 6 for the channel layer of the amorphous oxide TFT. In addition, the electrons that are carriers of the amorphous oxide thin film are thought to originate from oxygen defects as in the case of a transparent conductive oxide film such as ITO. Therefore, by adjusting the oxygen gas partial pressure and the applied power density, which are sputtering film formation conditions, Can be controlled.

さらに、Inに対するGaの比率によっても、電子キャリア濃度の制御が可能である。Ga組成比10以上では、スパッタ成膜条件である酸素ガス分圧を0にしても電子キャリア濃度が低く、電界効果移動度が小さいものになる。つまり、TFT作製条件として制御因子を1つ失うことになり、再現性の低いものになった。また、Ga組成比0.1未満の場合は、Zn組成比であるmの値によらず結晶化しやすくなる。   Furthermore, the electron carrier concentration can also be controlled by the ratio of Ga to In. When the Ga composition ratio is 10 or more, the electron carrier concentration is low and the field effect mobility is small even when the oxygen gas partial pressure, which is the sputter film formation condition, is zero. That is, one control factor was lost as a TFT manufacturing condition, and the reproducibility was low. Further, when the Ga composition ratio is less than 0.1, crystallization is facilitated regardless of the value of m which is the Zn composition ratio.

アモルファス酸化物薄膜の電子キャリア濃度の制御は、アモルファス酸化物薄膜の材料、組成比、スパッタリング成膜条件により制御する。しかし、その再現性及び大面積にわたる均一性は、ターゲット特性によるところが大きい。本発明のターゲットを用いたスパッタリング成膜は、電子キャリア濃度の制御性に優れ、電子キャリア濃度が1018/cm未満のアモルファス酸化物薄膜を安定して作製することができる。 The electron carrier concentration of the amorphous oxide thin film is controlled by the material, composition ratio, and sputtering film forming conditions of the amorphous oxide thin film. However, the reproducibility and uniformity over a large area largely depend on the target characteristics. Sputtering film formation using the target of the present invention is excellent in controllability of the electron carrier concentration, and can stably produce an amorphous oxide thin film having an electron carrier concentration of less than 10 18 / cm 3 .

通常のITOなどの透明導電性酸化膜では、電子キャリア濃度が1021/cmである。それに対し、TFTのチャネル層に適用するアモルファス酸化物薄膜では、電子キャリア濃度が1018/cm未満、さらに好ましくは1014/cm以上1016/cm以下の範囲にすることが好ましい。 An ordinary transparent conductive oxide film such as ITO has an electron carrier concentration of 10 21 / cm 3 . On the other hand, in the amorphous oxide thin film applied to the channel layer of the TFT, the electron carrier concentration is preferably less than 10 18 / cm 3 , more preferably 10 14 / cm 3 or more and 10 16 / cm 3 or less.

本発明者らは、このアモルファス酸化物薄膜は、伝導電子数の増加と共に、電子移動度が大きくなるという特異な特性を見出した。そして、その膜を用いてTFTを作成し、オン・オフ比、ピンチオフ状態での飽和電流、スイッチ速度などのトランジスタ特性が更に向上することを見出した。そして、アモルファス酸化物膜を薄膜トランジスタのチャネル層として用いることにより、電子移動度が1cm/(V・秒)以上、好ましくは5cm/(V・秒)以上に設定することができる。 The present inventors have found that the amorphous oxide thin film has a unique characteristic that the electron mobility increases as the number of conduction electrons increases. Then, a TFT was formed using the film, and it was found that transistor characteristics such as an on / off ratio, a saturation current in a pinch-off state, and a switch speed were further improved. Then, by using the amorphous oxide film as a channel layer of the thin film transistor, the electron mobility can be set to 1 cm 2 / (V · sec) or more, preferably 5 cm 2 / (V · sec) or more.

さらに上記条件に加えて電子キャリア濃度が1018/cm未満に設定することができる。そして好ましくは、1014/cm以上1016/cm以下のときは、オフ時(ゲート電圧無印加時)のドレイン・ソース端子間の電流を、10マイクロアンペア未満、好ましくは0.1マイクロアンペア未満にすることができる。 In addition to the above conditions, the electron carrier concentration can be set to less than 10 18 / cm 3 . Preferably, when it is 10 14 / cm 3 or more and 10 16 / cm 3 or less, the current between the drain and source terminals at the time of off (when no gate voltage is applied) is less than 10 microamperes, preferably 0.1 micron Can be less than amperes.

また該薄膜を用いれば、電子移動度が1cm/(V・秒)以上、好ましくは5cm/(V・秒)以上の時は、ピンチオフ後の飽和電流を10マイクロアンペア以上にでき、オン・オフ比を10以上とすることができる。 When the thin film is used, when the electron mobility is 1 cm 2 / (V · sec) or more, preferably 5 cm 2 / (V · sec) or more, the saturation current after pinch-off can be 10 microamperes or more and -Off ratio can be 10 3 or more.

TFTでは、ピンチオフ状態では、ゲート端子に高電圧が印加され、チャネル中には高密度の電子が存在している。したがって、本発明によれば、電子移動度が増加した分だけ、より飽和電流値を大きくすることができる。この結果、オン・オフ比の増大、飽和電流の増大、スイッチング速度の増大など、ほとんど全てのトランジスタ特性が向上する。なお、通常の化合物中では、電子数が増大すると、電子間の衝突により、電子移動度は減少する。   In the TFT, in a pinch-off state, a high voltage is applied to the gate terminal, and high-density electrons exist in the channel. Therefore, according to the present invention, the saturation current value can be further increased by the amount of increase in electron mobility. As a result, almost all transistor characteristics such as an increase in on / off ratio, an increase in saturation current, and an increase in switching speed are improved. In a normal compound, when the number of electrons increases, electron mobility decreases due to collisions between electrons.

本発明において、アモルファス酸化物膜とは、実質的にアモルファス構造を有すれば良く、膜全体がアモルファス構造を有するものだけでなく、その膜中に微結晶又は多結晶を含んでも良いものとする。   In the present invention, the amorphous oxide film only needs to have a substantially amorphous structure, and not only the whole film has an amorphous structure but also the film may contain microcrystals or polycrystals. .

本発明者らの知見によれば、特許文献2に記載されている相対密度40%更には70%以上の混晶焼結体又はホモロガスの焼結体をスパッタリング法に用いた場合、得られるアモルファス酸化物薄膜の電子キャリア濃度が次第にずれる場合がある。   According to the knowledge of the present inventors, when a mixed crystal sintered body or a homologous sintered body having a relative density of 40% or 70% or more described in Patent Document 2 is used in the sputtering method, an amorphous material is obtained. In some cases, the electron carrier concentration of the oxide thin film gradually shifts.

結晶状態における組成がInGaO(ZnO)(mは6未満の自然数)で表されるアモルファス酸化物薄膜を特定の酸素分圧を有する雰囲気中で成膜することにより、電気伝導度を制御できる。具体的には、酸素分圧が1×10−3Pa以上、望ましくは1×10−2Pa以上の雰囲気中で成膜することにより、電気伝導度を10S/cm未満に低下させることができる。この場合、基板の温度は意図的に加温しない状態で、ほぼ室温に維持されている。ガラス基板を用いる際には、基板温度を450℃以下の低温に制御することが望ましい。また、プラスチックフィルムなどの耐熱性の低い材料を基板として使用するためには、基板温度は200℃以下に制御することが好ましい。さらに好ましくは100℃未満に保つことが好ましい。酸素分圧をさらに大きくすることにより、電子キャリア数を低下させることができる。 Electrical conductivity can be controlled by forming an amorphous oxide thin film whose composition in the crystalline state is represented by InGaO 3 (ZnO) m (m is a natural number less than 6) in an atmosphere having a specific oxygen partial pressure. . Specifically, the electrical conductivity can be lowered to less than 10 S / cm by forming a film in an atmosphere having an oxygen partial pressure of 1 × 10 −3 Pa or higher, preferably 1 × 10 −2 Pa or higher. . In this case, the temperature of the substrate is maintained at substantially room temperature without intentionally heating. When using a glass substrate, it is desirable to control the substrate temperature to a low temperature of 450 ° C. or lower. In order to use a low heat-resistant material such as a plastic film as the substrate, the substrate temperature is preferably controlled to 200 ° C. or lower. More preferably, it is preferably kept below 100 ° C. By further increasing the oxygen partial pressure, the number of electron carriers can be reduced.

そして、本発明の上記アモルファス酸化物膜を用い、ノーマリーオフで、かつオン・オフ比を10以上のトランジスタを構成することができる。また、そのTFT特性の均一性及び再現性が向上し、高い歩留まりを実現できる。 A transistor having a normally-off and an on / off ratio of 10 6 or more can be formed using the amorphous oxide film of the present invention. Further, the uniformity and reproducibility of the TFT characteristics are improved, and a high yield can be realized.

上記アモルファス酸化物膜を用いた薄膜トランジスタにおいて、Al,Y、HfO、又はそれらの化合物を少なくとも二つ以上含む混晶化合物をゲート絶縁膜とすることが好ましい。ゲート絶縁薄膜とチャネル層薄膜との界面に欠陥が存在すると、電子移動度の低下及びトランジスタ特性にヒステリシスが生じる。また、ゲート絶縁膜の種類により、リーク電流が大きく異なる。このために、チャネル層に適合したゲート絶縁膜を選定する必要がある。Al膜を用いれば、リーク電流を低減できる。また、Y膜を用いれば、ヒステリシスを小さくできる。さらに、高誘電率のHfO膜を用いれば、電子移動度を大きくすることができる。また、これらの膜の混晶を用いて、リーク電流、ヒステリシスが小さく、電子移動度の大きなTFTを形成できる。また、ゲート絶縁膜形成プロセス及びチャネル層形成プロセスは、室温で行うことができるので、TFT構造として、スタガ構造及び逆スタガ構造のいずれも形成することができる。 In the thin film transistor using the amorphous oxide film, a gate insulating film is preferably formed using a mixed crystal compound containing at least two of Al 2 O 3 , Y 2 O 3 , HfO 2 , or a compound thereof. If there is a defect at the interface between the gate insulating thin film and the channel layer thin film, the electron mobility is lowered and the transistor characteristics are hysteresis. Further, the leakage current varies greatly depending on the type of the gate insulating film. For this purpose, it is necessary to select a gate insulating film suitable for the channel layer. If an Al 2 O 3 film is used, leakage current can be reduced. In addition, the hysteresis can be reduced by using a Y 2 O 3 film. Further, if a high dielectric constant HfO 2 film is used, the electron mobility can be increased. Further, by using mixed crystals of these films, a TFT with small leakage current and hysteresis and high electron mobility can be formed. In addition, since the gate insulating film formation process and the channel layer formation process can be performed at room temperature, both a staggered structure and an inverted staggered structure can be formed as the TFT structure.

薄膜トランジスタ(Thin Film Transistor:TFT)は、ゲート端子、ソース端子、及び、ドレイン端子を備えた3端子素子である。セラミックス、ガラス、もしくはプラスチックなどの絶縁基板上に成膜した半導体薄膜を、電子またはホールが移動するチャネル層として用いる。そのチャンネル層に流れる電流をゲート端子に印加する電圧により制御し、ソース端子とドレイン端子間の電流をスイッチングする機能を有するアクティブ素子である。   A thin film transistor (TFT) is a three-terminal element including a gate terminal, a source terminal, and a drain terminal. A semiconductor thin film formed over an insulating substrate such as ceramic, glass, or plastic is used as a channel layer through which electrons or holes move. The active element has a function of switching the current between the source terminal and the drain terminal by controlling the current flowing through the channel layer by the voltage applied to the gate terminal.

以下、実施例により本発明をさらに詳細に説明するが、本発明はこれらの実施例によって何ら限定されるものではない。   EXAMPLES Hereinafter, although an Example demonstrates this invention further in detail, this invention is not limited at all by these Examples.

(実施例1:酸化物スパッタリングターゲットの作製)
まず、出発原料としてIn、Ga、ZnO(各4N試薬)を1:1:1の比率で湿式混合し、仮焼、乾式粉砕、本焼結を行うことにより、InGaO(ZnO)組成を有する酸化物スパッタリングターゲットを作製した。(本工程は一般にコールドプレスと呼ばれている。)本実施例で作製した酸化物スパッタリングターゲットは、本発明品A、本発明品B、比較品Cの3種類である。この本発明品A、本発明品B、比較品Cについて、相対密度(%)と抵抗値ρ(Ωcm)を測定した。その関係を図1に示す(横軸:ターゲット相対密度(%)、縦軸:ターゲット抵抗値(Ωcm))。
(Example 1: Production of oxide sputtering target)
First, In 2 O 3 , Ga 2 O 3 , and ZnO (each 4N reagent) as a starting material are wet-mixed at a ratio of 1: 1: 1, and calcined, dry pulverized, and main-sintered to perform InGaO 3 An oxide sputtering target having a (ZnO) 4 composition was prepared. (This process is generally called a cold press.) There are three types of oxide sputtering targets prepared in this example: Invention product A, Invention product B, and Comparison product C. With respect to this product A, product B and comparative product C, the relative density (%) and the resistance value ρ (Ωcm) were measured. The relationship is shown in FIG. 1 (horizontal axis: target relative density (%), vertical axis: target resistance value (Ωcm)).

これによると、本発明品Aは、相対密度が96.9%、抵抗値ρが1.3×10−2Ωcm、本発明品Bは、相対密度が75.0%、抵抗値ρが5.0×10Ωcmであった。これに対して比較品Cは、相対密度が66.0%、抵抗値ρが2.9×10Ωcmであった(後述の表1参照)。 According to this, the product A of the present invention has a relative density of 96.9% and a resistance value ρ of 1.3 × 10 −2 Ωcm, and the product B of the present invention has a relative density of 75.0% and a resistance value ρ of 5 0.0 × 10 Ωcm. On the other hand, the comparative product C had a relative density of 66.0% and a resistance value ρ of 2.9 × 10 6 Ωcm (see Table 1 described later).

(実施例2:スパッタ法によるIn−Zn−Ga−O系アモルファス酸化膜の成膜)
酸素とアルゴンの混合ガスを雰囲気とした高周波スパッタ法により、ガラス基板(コーニング社製1737)上にIn−Zn−Ga−O系アモルファス酸化物膜を堆積させた。その際、前述のInGaO(ZnO)組成を有する本発明品A、本発明品B、比較品Cの3種類の多結晶焼結体をターゲットとして用いた。基板温度は25℃である。
(Example 2: Formation of an In-Zn-Ga-O-based amorphous oxide film by sputtering)
An In—Zn—Ga—O-based amorphous oxide film was deposited over a glass substrate (Corning Corp., 1737) by a high-frequency sputtering method using a mixed gas of oxygen and argon as an atmosphere. At that time, three types of polycrystalline sintered bodies of the invention product A, the invention product B, and the comparison product C having the above-described InGaO 3 (ZnO) 4 composition were used as targets. The substrate temperature is 25 ° C.

得られた膜に関し、膜面に対して入射角0.5度でX線を入射させ、X線回折を行った。その結果、明瞭な回折ピークは検出されず、作製したIn−Zn−Ga−O系膜は、いずれもアモルファス膜であることが確認された。   The obtained film was subjected to X-ray diffraction by making X-rays incident on the film surface at an incident angle of 0.5 degree. As a result, a clear diffraction peak was not detected, and it was confirmed that all the produced In—Zn—Ga—O-based films were amorphous films.

次に、本発明品Bを対象として、成膜時の雰囲気の酸素分圧(Pa)を変化させ、得られたアモルファス酸化物膜の電気伝導度(S/cm)を測定した。その結果を図2に示す(横軸:酸素分圧(Pa)、縦軸:電気伝導度(S/cm))。   Next, for the product B of the present invention, the oxygen partial pressure (Pa) of the atmosphere during film formation was changed, and the electrical conductivity (S / cm) of the obtained amorphous oxide film was measured. The results are shown in FIG. 2 (horizontal axis: oxygen partial pressure (Pa), vertical axis: electrical conductivity (S / cm)).

これによると、酸素分圧が1.8×10−2Pa以上の酸素とアルゴンの混合ガス雰囲気中で成膜することにより、電気伝導度を10−5S/cm程度にすることができた(図2のグラフの右側から2つ目の測定値参照)。電子移動度は、約5cm/V・秒で、電子キャリア濃度は1018/cm未満であった。この場合、基板の温度は、意図的に加温しない状態でほぼ室温に維持されている。得られたアモルファス酸化物膜の表面は平坦であった。 According to this, it was possible to make the electric conductivity about 10 −5 S / cm by forming a film in a mixed gas atmosphere of oxygen and argon having an oxygen partial pressure of 1.8 × 10 −2 Pa or more. (Refer to the second measured value from the right side of the graph of FIG. 2). The electron mobility was about 5 cm 2 / V · sec, and the electron carrier concentration was less than 10 18 / cm 3 . In this case, the temperature of the substrate is maintained at substantially room temperature without intentionally heating. The surface of the obtained amorphous oxide film was flat.

さらに、酸素分圧を1×10−1Paまで増加させると、電気伝導度を10−10S/cm未満にまで低下させることができた(この測定値は、図2に示すグラフの範囲外に位置し、図示されていない)。この場合、電子移動度は測定できなかったが、電子キャリア濃度が大きな膜での値から外挿して、電子移動度は、約1cm/V・秒と推定された。 Furthermore, when the oxygen partial pressure was increased to 1 × 10 −1 Pa, the electrical conductivity could be reduced to less than 10 −10 S / cm (this measured value is outside the range of the graph shown in FIG. 2). Not shown). In this case, although the electron mobility could not be measured, the electron mobility was estimated to be about 1 cm 2 / V · second by extrapolating from the value in the film having a high electron carrier concentration.

なお、ガラス基板の代わりに厚さ200μmのポリエチレン・テレフタレート(PET)フィルムを用いた場合にも、得られたInGaO(ZnO)アモルファス酸化物膜は、上記と同様の特性を示した。 Even when a polyethylene terephthalate (PET) film having a thickness of 200 μm was used instead of the glass substrate, the obtained InGaO 3 (ZnO) 4 amorphous oxide film exhibited the same characteristics as described above.

(実施例3:In−Zn−Ga−O系アモルファス酸化物膜を用いたTFTパネルの作製(ガラス基板))
1)TFTパネルの作製
本実施例のアモルファス酸化物をチャネル層としたTFT素子として、図3に示すトップゲート型TFT素子を作製した。
(Example 3: Production of TFT panel using In-Zn-Ga-O-based amorphous oxide film (glass substrate))
1) Fabrication of TFT Panel A top gate TFT device shown in FIG. 3 was fabricated as a TFT device using the amorphous oxide of this example as a channel layer.

まず、12cm×12cmの大きさのガラス基板1上に、酸素分圧1.8×10−2Paの条件で、In−Ga−Zn−O系アモルファス酸化物膜をRFスパッタ法により、チャネル層2として、120nmの厚さに形成した。その際、前述のInGaO(ZnO)組成を有する本発明品A、本発明品B、比較品Cの3種類の多結晶焼結体をターゲットとして用いた。 First, an In—Ga—Zn—O-based amorphous oxide film is formed on the glass substrate 1 having a size of 12 cm × 12 cm under the condition of an oxygen partial pressure of 1.8 × 10 −2 Pa by an RF sputtering method. 2 to a thickness of 120 nm. At that time, three types of polycrystalline sintered bodies of the invention product A, the invention product B, and the comparison product C having the above-described InGaO 3 (ZnO) 4 composition were used as targets.

さらにその上に、金膜を30nm積層し、フォトリゾグラフィー法とリフトオフ法により、ドレイン端子5及びソース端子6を形成した。最後にゲート絶縁膜3として用いるY膜を電子ビーム蒸着法により成膜(厚み:90nm、比誘電率:約15、リーク電流密度:0.5MV/cm印加時に10−3A/cm)した。 Further thereon, a gold film having a thickness of 30 nm was laminated, and a drain terminal 5 and a source terminal 6 were formed by a photolithography method and a lift-off method. Finally, a Y 2 O 3 film used as the gate insulating film 3 is formed by electron beam evaporation (thickness: 90 nm, relative dielectric constant: about 15, leakage current density: 10 −3 A / cm when 0.5 MV / cm is applied) 2 ).

その上に金を成膜し、フォトリソグラフィー法とリフトオフ法により、ゲート端子4を形成した。チャネル長は、10μmで、チャネル幅は、150μmであった。基板内には10×10=100個のTFTを等間隔で配列して形成した。   A gold film was formed thereon, and a gate terminal 4 was formed by a photolithography method and a lift-off method. The channel length was 10 μm and the channel width was 150 μm. In the substrate, 10 × 10 = 100 TFTs were arranged at equal intervals.

2)TFTパネルの特性評価
図4に、室温下で測定したTFT素子の電流−電圧特性を示す(横軸:ドレイン電圧VDS(V)、縦軸:ドレイン電流IDS(A))。
2) Characteristic Evaluation of TFT Panel FIG. 4 shows current-voltage characteristics of a TFT element measured at room temperature (horizontal axis: drain voltage V DS (V), vertical axis: drain current I DS (A)).

これによると、ドレイン電圧VDSの増加に伴い、ドレイン電流IDSが増加したことからチャネルがn型伝導であることが分かる。IDSは、VDS=6V程度で飽和(ピンチオフ)する典型的な半導体トランジスタの挙動を示した。利得特性を調べたところ、VDS=6V印加時におけるゲート電圧VGSの閾値は、約1.4Vであった。また、V=6V時には、IDS=2.3×10−4Aの電流が流れた。これは、ゲートバイアスにより絶縁体のIn−Ga−Zn−O系アモルファス酸化物膜内にキャリアを誘起できたことに対応する。トランジスタのオン・オフ比は、10程度であった。また、出力特性から電界効果移動度を算出したところ、飽和領域において約11.5cm(Vs)−1の電界効果移動度が得られた。 According to this, it can be understood that the channel is of n-type conduction because the drain current I DS increases with the increase of the drain voltage V DS . I DS shows the behavior of a typical semiconductor transistor that saturates (pinch off) at about V DS = 6V. When the gain characteristic was examined, the threshold value of the gate voltage V GS when V DS = 6 V was applied was about 1.4V. Further, when V G = 6 V, a current of I DS = 2.3 × 10 −4 A flowed. This corresponds to the fact that carriers can be induced in the insulator In—Ga—Zn—O-based amorphous oxide film by the gate bias. The on / off ratio of the transistor was about 10 8 . Further, when the field effect mobility was calculated from the output characteristics, a field effect mobility of about 11.5 cm 2 (Vs) −1 was obtained in the saturation region.

また、TFTパネル内100個の素子の特性をすべて評価した。ゲートの短絡の見られた2個を除き、電界効果移動度は、8〜11.5cm/(V・秒)の範囲に、VGSの閾値は0.5〜2.0Vの範囲に収まった。特に隣接するTFT素子の間では特性の差が殆ど見られなかった。 Moreover, all the characteristics of 100 elements in the TFT panel were evaluated. The field effect mobility is in the range of 8 to 11.5 cm 2 / (V · sec), and the threshold value of V GS is in the range of 0.5 to 2.0 V, except for two gate short circuits. It was. In particular, there was almost no difference in characteristics between adjacent TFT elements.

こうして得られたTFTパネルの特性の変化について、本発明品A、本発明品B、比較品Cのターゲット3種類のそれぞれを用いて、連続5バッチ分、TFTを作製し、得られたTFTを対象としてTFT特性の均一性および再現性を評価した。   Regarding the change in the characteristics of the TFT panel thus obtained, TFTs were prepared for 5 continuous batches using each of the three types of targets of the present product A, the present product B, and the comparative product C. As an object, the uniformity and reproducibility of TFT characteristics were evaluated.

ここで、TFT特性の均一性の評価については、同一パネル内のVg=6Vにおけるオン電流の最大値と最小値の比(最大値/最小値)を測定した。その結果、TFT特性の均一性の良い方から順に、1.05以内:◎、1.10以内:○、1.20以内:△、1.20より大:×として、4段階で評価した。   Here, for the evaluation of the uniformity of TFT characteristics, the ratio (maximum value / minimum value) of the maximum value and the minimum value of the on-current at Vg = 6 V in the same panel was measured. As a result, the TFT characteristics were evaluated in four stages in order from the better uniformity of TFT characteristics: within 1.05: ◎, within 1.10: ◯, within 1.20: Δ, greater than 1.20: x.

また、TFT特性の再現性の評価については、連続5バッチ分における第1バッチと第5バッチの平均電界効果移動度の比(第1バッチ/第5バッチ)を測定した。その結果、TFT特性の再現性の良い方から順に、1.10以内:◎、1.20以内:○、1.50以内:△、1.50より大:×として、4段階で評価した。   Moreover, about evaluation of the reproducibility of TFT characteristics, ratio (1st batch / 5th batch) of the average field effect mobility of the 1st batch and 5th batch in continuous 5 batches was measured. As a result, the TFT characteristics were evaluated in four stages in order from those with good reproducibility of TFT characteristics: 1.10 or less: 、, 1.20 or less: ○, 1.50 or less: Δ, greater than 1.50: x.

表1に、本発明品A、本発明品B、比較品Cについて、その相対密度、抵抗値ρ、そのターゲットを用いて作製したTFTの均一性、そのターゲットを用いて作製したTFTの再現性を示す。   Table 1 shows the relative density, resistance value ρ, uniformity of TFTs produced using the target, and reproducibility of TFTs produced using the target for the inventive product A, the inventive product B, and the comparative product C. Indicates.

これによると、相対密度が95%以上で抵抗値ρが0.1Ωcm以下の本発明品Aを用いて作製したTFTは、TFT特性の均一性および再現性の評価結果がいずれも◎であった。また、相対密度が75%で抵抗値ρが50Ωcmの本発明品Bを用いて作製したTFTは、TFT特性の均一性および再現性の評価結果がいずれも○であった。これに対し、相対密度が75%未満で抵抗値ρが50Ωcmを超えている比較品Cを用いて作製したTFTは、TFT特性の均一性および再現性の評価結果が△および×であった。このことから、TFT特性の均一性および再現性に関しては、相対密度が75%以上で抵抗値ρが50Ωcm以下の酸化物スパッタリングターゲットを用いて作製することが有効であることが確認された。   According to this, the TFT produced using the product A of the present invention having a relative density of 95% or more and a resistance value ρ of 0.1 Ωcm or less had both excellent evaluation results of TFT characteristic uniformity and reproducibility. . In addition, the TFT produced using the product B of the present invention having a relative density of 75% and a resistance value ρ of 50 Ωcm had a good evaluation result of uniformity and reproducibility of TFT characteristics. On the other hand, the TFT produced using the comparative product C having a relative density of less than 75% and a resistance value ρ exceeding 50 Ωcm had Δ and x evaluation results of uniformity and reproducibility of TFT characteristics. From this, it was confirmed that it is effective to use an oxide sputtering target having a relative density of 75% or more and a resistance value ρ of 50 Ωcm or less in terms of uniformity and reproducibility of TFT characteristics.

図5に、本発明品Aおよび本発明品Bのターゲットを粉砕したパウダーから得られるX線回折パターンと、JCPDSカードから得られるホモロガス相の結晶構造X線回折パターンとを示す。(横軸:2θ(degrees:度)、縦軸:強度(arbitrary units:任意単位))図5から明らかなように、本発明品A、本発明品Bは、いずれもホモロガス相の結晶構造X線回折パターンを示していることが確認された。   FIG. 5 shows an X-ray diffraction pattern obtained from powder obtained by pulverizing the targets of the present invention product A and the present product product B, and a homologous phase crystal structure X-ray diffraction pattern obtained from a JCPDS card. (Horizontal axis: 2θ (degrees: degree), vertical axis: intensity (arbitrary units: arbitrary unit)) As is clear from FIG. 5, both of the products A and B of the present invention have a crystal structure X of a homologous phase. It was confirmed that a line diffraction pattern was shown.

なお、上記の実施例では、アモルファス酸化物薄膜をTFTのチャネル層を使用する場合に主眼をおいて説明したが、本発明はこのようにアモルファス酸化物薄膜をTFTのチャネル層に使用する場合に限定されるものではない。TFTのチャネル層以外の応用としては、例えば、光センサー素子等を挙げることができる。   In the above-described embodiments, the amorphous oxide thin film has been mainly described when the TFT channel layer is used. However, the present invention is applied when the amorphous oxide thin film is used for the TFT channel layer. It is not limited. As an application other than the channel layer of the TFT, for example, an optical sensor element can be cited.

本発明に係るスパッタリングターゲットは、TFTのチャネル層に好適に用いられるアモルファス酸化物薄膜の成膜に利用できる。さらに、LCDや有機ELディスプレイのスイッチング素子として利用できる。また、プラスチックフィルムをはじめとするフレキシブル素材に半導体の薄膜を形成したフレキシブル・ディスプレイをはじめ、ICカードやIDタグなどにも幅広く応用できる。   The sputtering target according to the present invention can be used for the formation of an amorphous oxide thin film suitably used for a channel layer of a TFT. Furthermore, it can be used as a switching element for LCDs and organic EL displays. In addition, it can be widely applied to IC cards and ID tags, as well as flexible displays in which semiconductor thin films are formed on flexible materials such as plastic films.

本発明の実施例1で作製したスパッタリングターゲット(本発明品A、本発明品B、比較品C)の相対密度と抵抗値ρの関係を示すグラフである。It is a graph which shows the relationship between the relative density and resistance value (rho) of the sputtering target (this invention product A, this invention product B, comparative product C) produced in Example 1 of this invention. 実施例1で作製した本発明のスパッタリングターゲット(本発明品B)を用いて、スパッタ法で成膜したIn−Ga−Zn−O系アモルファス膜の電気伝導度と成膜中の酸素分圧の関係を示すグラフである。Using the sputtering target of the present invention (Product B of the present invention) produced in Example 1, the electrical conductivity of the In—Ga—Zn—O-based amorphous film formed by sputtering and the oxygen partial pressure during film formation It is a graph which shows a relationship. 本発明の実施例3で作製したトップゲート型MISFET素子構造を示す模式図である。It is a schematic diagram which shows the top gate type MISFET element structure produced in Example 3 of this invention. 本発明の実施例3で作製したトップゲート型MISFET素子の電流−電圧特性を示すグラフである。It is a graph which shows the current-voltage characteristic of the top gate type MISFET element produced in Example 3 of this invention. 実施例1で作製した本発明のスパッタリングターゲット(本発明品Aおよび本発明品B)を粉砕したパウダーから得られるX線回折パターンと、JCPDSカードから得られるホモロガス相の結晶構造X線回折パターンとを示すグラフである。An X-ray diffraction pattern obtained from a powder obtained by pulverizing the sputtering target of the present invention (Invention product A and Invention product B) produced in Example 1, and a homologous phase crystal structure X-ray diffraction pattern obtained from a JCPDS card It is a graph which shows.

符号の説明Explanation of symbols

1 基板
2 チャネル層
3 ゲート絶縁膜
4 ゲート電極(ゲート端子)
5 ドレイン電極(ドレイン端子)
6 ソース電極(ソース端子)
1 Substrate 2 Channel layer 3 Gate insulating film 4 Gate electrode (gate terminal)
5 Drain electrode (drain terminal)
6 Source electrode (source terminal)

Claims (5)

少なくともIn、Zn、Gaを含む焼結体ターゲットであって、その組成にIn、Zn、Gaを含み、相対密度が75%以上、且つ抵抗値ρが50Ωcm以下であることを特徴とするスパッタリングターゲット。   A sputtering target comprising at least In, Zn, and Ga, the composition comprising In, Zn, and Ga, a relative density of 75% or more, and a resistance value ρ of 50 Ωcm or less. . 前記ターゲットがホモロガス相の結晶構造を示す多結晶酸化物焼結体であることを特徴とする請求項1に記載のスパッタリングターゲット。   The sputtering target according to claim 1, wherein the target is a polycrystalline oxide sintered body having a homologous phase crystal structure. 前記ターゲットが多結晶酸化物焼結体であり、原子数比がIn:Ga:Zn=1:x:m(0.1≦x≦10、m<6)であることを特徴とする請求項1または2に記載のスパッタリングターゲット。   The target is a polycrystalline oxide sintered body, and the atomic ratio is In: Ga: Zn = 1: x: m (0.1 ≦ x ≦ 10, m <6). The sputtering target according to 1 or 2. 請求項1から3のいずれか1項に記載のスパッタリングターゲットを用いて、電子キャリア濃度が1018/cm未満のアモルファス酸化物膜を室温以上450℃以下の成膜温度でスパッタリング法により形成することを特徴とする薄膜の形成方法。 Using the sputtering target according to claim 1, an amorphous oxide film having an electron carrier concentration of less than 10 18 / cm 3 is formed by a sputtering method at a deposition temperature of room temperature to 450 ° C. A method for forming a thin film. 前記アモルファス酸化物膜を薄膜トランジスタのチャネル層として形成することを特徴とする請求項4記載の薄膜の形成方法。   5. The method for forming a thin film according to claim 4, wherein the amorphous oxide film is formed as a channel layer of a thin film transistor.
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