JP2007093318A - Inspection signal generator and semiconductor inspection device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inspection signal generator, which can be easily designed and can be operated at a high frequency; and to provide a semiconductor inspection device equipped with the same signal generator. <P>SOLUTION: This inspection signal generator 10 is structured so as to include format data generating circuits 11a and 11b provided in parallel, buffers 12a and 12b provided so as to correspond thereto, a buffer selector 13 for switching between the buffers 12a and 12b to be connected to an inspection signal generating circuit 15, and a buffer choice control circuit 14 for choosing between the buffers 12a and 12b and controlling the buffer selector 13. Pattern data generated by the generating circuits 11a and 11b are stored in the corresponding buffers 12a and 12b, respectively. The pattern data stored in the buffers 12a and 12b are alternately input into an inspection signal generating circuit 15 by the control of the control circuit 14. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an inspection signal generation device that generates an inspection signal to be applied to an inspection target such as an IC (Integrated Circuit) or LSI (Large Scale Integraton), and an inspection target using the signal generated by the inspection signal generation device The present invention relates to a semiconductor inspection apparatus for inspecting semiconductor devices.

  A semiconductor inspection apparatus gives an inspection signal (test pattern) to an object to be inspected (hereinafter referred to as a DUT (Device Under Test)) such as an IC or LSI, and a signal output from the DUT matches a predetermined expected value. It is judged whether the quality is good or not. There are several formats (waveform formats) in the test pattern given to the DUT by the semiconductor inspection apparatus. Typical examples of this format include RZ (Return to Zero), NRZ (Non Return to Zero), etc. There is. The semiconductor inspection apparatus includes an inspection signal generation apparatus that generates a test pattern of such a format.

  FIG. 7 is a block diagram showing a configuration of a conventional inspection signal generation apparatus. As shown in FIG. 7, the conventional inspection signal generation apparatus 100 includes a format data generation circuit 101, a buffer 102, and an inspection signal generation circuit 103. A test pattern is generated by the input rate signal S101 and timing signal S102. An inspection signal S103 is output. Here, the rate signal S101 is a signal that defines the frequency of the inspection signal, and the timing signal S102 is a signal that has substantially the same frequency as the frequency of the rate signal S101 and that defines the output timing of the inspection signal S103.

  The format data generation circuit 101 generates pattern data D101 necessary for generating a waveform format in synchronization with the input rate signal S101. Although not shown in FIG. 7, a control signal is input to the format data generation circuit 101 and the inspection signal generation circuit 103, and the waveform format of the inspection signal S103 is set by this control signal. The buffer 102 temporarily stores the pattern data D101 output from the format data generation circuit 101. The buffer 102 is a first-in first-out (FIFO) memory. The write timing of the pattern data D101 is controlled by the rate signal S101, and the read timing is controlled by the timing signal S102. The inspection signal generation circuit 103 generates an inspection signal S103 from the read pattern data D102 read from the buffer 102 and the timing signal S102.

  In the above configuration, when DUT inspection is performed, first, a control signal is output to the inspection signal generation circuit 103 from an inspection program (not shown) provided in the semiconductor inspection apparatus, and the waveform format of the inspection signal S103 is set. Is done. Next, a control signal is output from the inspection program or the like to the format data generation circuit 101, whereby pattern data D101 necessary for waveform format generation is generated and output. The pattern data D101 from the format data generation circuit 101 is sequentially stored in the buffer 102 in synchronization with the rate signal S101. Next, when the timing signal S102 is input, the pattern data D101 temporarily stored in the buffer 102 is read in synchronization with the timing signal S102 and output to the inspection signal generation circuit 103 as read pattern data D102.

The inspection signal generation circuit 130 generates and outputs an inspection signal S103 from the input read pattern data D102 and the timing signal S102. Thereafter, the inspection signal S103 is sequentially generated based on the pattern data D101 from the format data generation circuit 101. For details of the conventional semiconductor inspection apparatus, see, for example, Patent Documents 1 to 3 below.
Japanese translation of PCT publication No. 2003-505697 JP 2002-131393 A Japanese Patent Laid-Open No. 5-196689

  By the way, in the conventional inspection signal generation apparatus 100 shown in FIG. 7, the pattern data D101 is generated by the format data generation circuit 101 every time the rate signal S101 is input, and the pattern data D101 and the timing signal S102 are used. An inspection signal S103 is generated. Therefore, in order to continuously generate the inspection signal S103, the frequency of the timing signal S102 that defines the output timing of the inspection signal S103 is equal to the frequency of the rate signal S101 that defines the timing of generating the pattern data D101. There must be.

  Here, the frequency of the rate signal S101 and the timing signal S102 need not be exactly the same, but the difference needs to be within a range that can be absorbed by the buffer 102. For this reason, for example, when the maximum frequency of the timing signal S102 is 100 MHz, the maximum frequency of the rate signal S101 needs to be around 100 MHz.

  Incidentally, in recent years, since the operating frequency of the DUT has been improved, there is a need to increase the maximum frequency of the inspection signal S103 given to the DUT. In the inspection signal generation device 100 shown in FIG. 7, for example, when the maximum frequency of the timing signal S102 is changed to 200 MHz in order to set the maximum frequency of the inspection signal S103 to 200 MHz, the maximum frequency of the rate signal S101 is also changed to around 200 MHz. Furthermore, it is necessary to redesign the internal circuit of the test signal generation apparatus 100 so that it operates at a maximum frequency of 200 MHz. As described above, the conventional test signal generation apparatus 100 shown in FIG. 7 needs to be designed so that all of the internal circuits operate at the maximum frequency, and requires a great amount of design man-hours when the operating frequency increases. It was.

  In order to solve this problem, it is conceivable that two systems of format data generation circuits are provided in parallel to suppress an increase in operating frequency. FIG. 8 is a diagram illustrating a modification of the conventional inspection signal generation device 100. 8 includes format data generation circuits 111a and 111b provided in parallel in place of the format data generation circuit 101 shown in FIG. 7, and a format in place of the buffer 102 shown in FIG. A buffer 112 that receives the outputs of the data generation circuits 111a and 111b is provided. Further, in place of the inspection signal generation circuit 103 shown in FIG. 7, an inspection signal generation circuit 113 capable of higher speed operation is provided.

  Here, in the test signal generation device 110 shown in FIG. 8, since the format data generation circuits 111a and 111b are provided in parallel, the maximum operating frequency of the format data generation circuits 111a and 111b is set to the same as the conventional one (for example, 100 MHz). However, pattern data can be obtained at substantially twice the frequency. However, each time the rate signal S101 is input, two pattern data D111a and D111b are stored in the buffer 112. Therefore, the maximum operating frequency on the output side of the buffer 112 is set to the maximum operating frequency of the format data generating circuits 111a and 111b. 2 times (for example, 200 MHz), which is considered to cause a rise in design man-hours.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide an inspection signal generation device that is easy to design and can operate at a high frequency, and a semiconductor inspection device including the inspection signal generation device. .

In order to solve the above-described problem, the inspection signal generation device of the present invention specifies a first control signal (S11) that defines the frequency of the inspection signal (S13) to be given to the object to be inspected, and the output timing of the inspection signal. In the inspection signal generator (10, 20, 30) that generates the inspection signal using the second control signal (S12), pattern data that defines the waveform of the inspection signal in synchronization with the first control signal A plurality of generation circuits (11a, 11b, 21a to 21d) to be generated and the pattern data generated by the generation circuit corresponding to the generation circuits are synchronized with the first control signal. A plurality of buffers (12a, 12b, 22a to 22d) to be temporarily stored and one of the plurality of buffers are selected in synchronization with the second control signal, and the selected buffer is selected. Selective reading means (13, 14, 23, 24, 33a to 33c, 34) for reading the pattern data temporarily stored from the memory, the pattern data read by the selective reading means, and the second An inspection signal generation circuit (15) for generating the inspection signal from the control signal is provided.
According to the present invention, the pattern data generated by each of the generation circuits is temporarily stored in the corresponding buffer in synchronization with the first control signal. Then, any one of the buffers is selected by the selective reading means, and the pattern data stored in the selected buffer is read out and input to the inspection signal generation circuit to generate the inspection signal.
In the inspection signal generation device of the present invention, the frequency of the first control signal is set to a frequency obtained by dividing the frequency of the inspection signal given to the inspection target by the number of the generation circuits. It is characterized by.
In the inspection signal generation device according to the present invention, the selective reading means includes selectors (13, 23, 33a to 33c) connected to the output ends of the plurality of buffers and the input ends of the inspection signal generation circuit, A selection control device (14, 24, 34) that selects a buffer from which the pattern data is read from the plurality of buffers, and controls the selector to input the pattern data read from the selected buffer to the inspection signal generation circuit. ).
Furthermore, in the inspection signal generation device of the present invention, the selector includes a plurality of first selectors (33a, 33b) connected to the plurality of buffers, an output terminal of the first selector, and an input of the inspection signal generation circuit. A second selector (33c) connected to the end is provided.
A semiconductor inspection apparatus according to the present invention is a semiconductor inspection apparatus that inspects an object to be inspected. The inspection object is inspected using a signal obtained by giving the object.

According to the present invention, since the selection of the buffer by the selective reading means is performed in synchronism with the second control signal, the operating frequency of each buffer can be made lower than the frequency of the second control signal. There is an effect that the design of the signal generation device becomes simple.
In addition, according to the present invention, there is an effect that it is possible to operate at a high frequency in which the frequency of the inspection signal is increased only by increasing the number of parallel generation circuits and buffers.
Furthermore, according to the present invention, if the number of selector stages is increased, there is an effect that the operating frequency of the selector (first selector) connected to the buffer can be reduced.

  Hereinafter, an inspection signal generation device and a semiconductor inspection device according to an embodiment of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram showing a configuration of an inspection signal generation apparatus according to the first embodiment of the present invention. As shown in FIG. 1, the test signal generation apparatus 10 according to the first embodiment of the present invention includes format data generation circuits 11a and 11b, buffers 12a and 12b, a buffer selector 13, a buffer selection control circuit 14, and a test signal generation circuit 15. It is comprised including. Here, the rate signal S11 and the timing signal S12 are input to the inspection signal generation device 10, and the inspection signal generation device 10 operates in synchronization with these signals and outputs the inspection signal S13.

  Here, the rate signal S11 is a signal that defines the frequency of the inspection signal S13, and the timing signal S12 is a signal that defines the output timing of the inspection signal S13. In the present embodiment, it is assumed that the maximum frequency of the inspection signal S13 is set to 200 MHz. Further, it is assumed that the frequency of the rate signal S11 is set to 100 MHz, which is a half frequency of the inspection signal S13, and the frequency of the timing signal S12 is set to substantially the same frequency (200 MHz) as the inspection signal S13.

  Here, the frequency of the rate signal S11 is set to a frequency (frequency-divided frequency) obtained by dividing the frequency of the inspection signal S13 by the number of format data generation circuits (format data generation circuits 11a and 11b). In addition, the timing signal S12 is a signal that defines the output timing of the inspection signal S13, and the time position within one cycle of the rate signal S11 may change and the frequency may not be constant. The expression “almost the same frequency” is used.

  The format data generation circuits 11a and 11b generate pattern data D11a and D11b necessary for generating the waveform format in synchronization with the input rate signal S11. Although not shown in FIG. 1, a control signal is input to the format data generation circuit 11 and the inspection signal generation circuit 15, and the waveform format of the inspection signal S13 is set by this control signal.

  The buffers 12a and 12b are provided corresponding to the format data generation circuits 11a and 11b, and temporarily store pattern data D11a and D11b output from each. The buffers 12a and 12b are FIFO (First-In First-Out) memories, the write timing of the pattern data D11a and D11b is controlled by the rate signal S11, and the read timing is the buffer from the buffer selection control circuit 14. Controlled by a switching signal SL.

  The buffer selector 13 is connected to each of the output ends of the buffers 12a and 12b and the input end of the inspection signal generation circuit 15, and based on the buffer switching signal SL output from the buffer selection control circuit 14, the output of the buffers 12a and 12b. One of the pattern data output from the end is selected and output to the inspection signal generation circuit 15. The buffer selection control circuit 14 operates in synchronization with the timing signal S12, and outputs a buffer switching signal SL for selecting one of the buffers 12a and 12b.

  Here, the buffer switching signal SL is output to both of the buffers 12a and 12b. However, as shown in FIG. 1, the input terminal of the buffer switching signal SL in the buffer 12b is an inverting input. The buffers 12a and 12b are alternately selected. The buffer selector 13 is controlled by the buffer switching signal SL so that the pattern data output from the output terminal of the selected buffer of the buffers 12a and 12b is input to the input terminal of the inspection signal generation circuit 15.

  FIG. 2 is a diagram illustrating an example of a circuit configuration of the buffer selection control circuit 14. As shown in FIG. 2, the buffer selection control circuit 14 includes a D flip-flop 16. The timing signal S 12 is input to the clock input terminal, the inverted output terminal is connected to the D input terminal, and the output from the output terminal is connected. Is a buffer switching signal SL. Thus, a toggle flip-flop is configured, and the level of the buffer switching signal SL is “H (high)”, “L (low)”, “H”, “L” each time the timing signal S12 is input. Change in order. Returning to FIG. 1, the inspection signal generation circuit 15 generates the inspection signal S13 from the selection data D13 selected by the buffer selector 13 and the timing signal S12 among the read pattern data D12a and 12b read from the buffers 12a and 12b. Generate.

  In the above configuration, when performing a DUT inspection, first, a control signal is output to the inspection signal generation circuit 15 from an inspection program (not shown) provided in the semiconductor inspection apparatus, and the waveform format of the inspection signal S13 is set. Is done. Next, a control signal is output from the inspection program or the like to the format data generation circuits 11a and 11b, thereby generating and outputting pattern data D11a and D11b necessary for waveform format generation, respectively. The pattern data D11a and D11b from the format data generation circuits 11a and 11b are sequentially stored in the buffers 12a and 12b in synchronization with the rate signal S11.

  FIG. 3 is a diagram for explaining pattern data stored in each of the buffers 12a and 12b. The pattern data D11a, D11b generated by the format data generation circuits 11a, 11b are (A), (B), (C), (D), (E), (F), (G), (H),. As shown in FIG. 3, these are alternately stored in the buffers 12a and 12b, so that (A), (C), (E), (G ),... Are stored in the order, and the buffer 12b stores the pattern data in the order of (B), (D), (F), (H),.

  Next, the reading operation of the pattern data stored in each of the buffers 12a and 12b will be described. FIG. 4 is a timing chart for explaining an operation of reading pattern data from the buffers 12a and 12b. Assume that the level of the buffer switching signal SL output from the buffer selection control circuit 14 is “L”. Further, as shown in FIG. 3, the oldest pattern data stored in the buffer 12a is “(A)”, and the oldest pattern data stored in the buffer 12b is “( B) ". In this state, since the level of the buffer switching signal SL is “L”, the buffer 12a is selected. Therefore, the select data D13 is the oldest pattern data “(A)” stored in the buffer 12a.

  When the timing signal S12 is input to the buffer selection control circuit 14 in this state, the buffer switching signal SL rises and the level becomes “H”. When the buffer switching signal SL is input to the buffers 12a and 12b, the read pattern data D12a read from the buffer 12a changes to the second pattern data “(C)”. On the other hand, the read pattern data D12b read from the buffer 12b does not change and remains the pattern data “(B)”. When the buffer switching signal SL is input to the buffer selector 13, the select data D13 becomes the oldest pattern data “(B)” stored in the buffer 12b (time t11).

  When the next timing signal S12 is input to the buffer selection control circuit 14, the buffer switching signal SL falls and the level becomes "L". When the buffer switching signal SL is input to the buffers 12a and 12b, the read pattern data D12b read from the buffer 12b changes to the second pattern data “(D)”. On the other hand, the read pattern data D12a read from the buffer 12a does not change and remains the pattern data “(C)”. When the buffer switching signal SL is input to the buffer selector 13, the select data D13 becomes the pattern data “(C)” from the buffer 12a (time t12).

  Further, when the next timing signal S12 is input to the buffer selection control circuit 14, the buffer switching signal SL rises and the level becomes “H”. When the buffer switching signal SL is input to the buffers 12a and 12b, the read pattern data D12a read from the buffer 12a changes to the third pattern data “(E)”. On the other hand, the read pattern data D12b read from the buffer 12b does not change and remains the pattern data “(D)”. When the buffer switching signal SL is input to the buffer selector 13, the select data D13 becomes the pattern data “(D)” from the buffer 12b (time t13).

  Thereafter, the same operation is repeated, and the pattern data is sequentially read from the buffers 12a and 12b. The read pattern data D12a and D12b read from each of the buffers 12a and 12b are input to the inspection signal generation circuit 15 as select data D13 via the buffer selector 12. Since the selection data D13 and the timing signal S12 are input to the inspection signal generation circuit 15, the inspection signal S13 is generated and output using them.

  In the inspection signal generation device 10 of the present embodiment described above, the buffer selector 13, the buffer selection control circuit 14, and the inspection signal generation circuit 15 need to be operated at a frequency equivalent to the frequency of the timing signal S12. However, referring to FIG. 4, the frequency of the buffer switching signal SL input to the buffers 12a and 12b is half that of the timing signal S12, and the buffers 12a and 12b are alternately selected according to the timing signal S12. The operating frequencies (output-side operating frequencies) of the buffers 12a and 12b can be set to the same frequency as the rate signal S11. The buffer selector 13 can be realized by, for example, a two-to-one multiplexing circuit, and the buffer selection control circuit 14 can be realized by a toggle flip-flop as shown in FIG. From the above, the test signal generation device 10 of the present embodiment is easy to design and can operate at a high frequency.

[Second Embodiment]
FIG. 5 is a block diagram showing a configuration of the inspection signal generation apparatus according to the second embodiment of the present invention. The inspection signal generation device 20 of the present embodiment is mainly different from the inspection signal generation device 10 shown in FIG. 1 in the number of parallel format data generation circuits and buffers. As shown in FIG. 5, the inspection signal generation device 20 of the present embodiment includes format data generation circuits 21a to 21d, buffers 22a to 22d, a buffer selector 23, a buffer selection control circuit 24, and an inspection signal generation circuit 15. Thus, the parallel number of the format data generation circuits 21a to 21d and the buffers 22a to 22d is “4”. The inspection signal generation circuit 15 is the same as that shown in FIG.

  Also in this embodiment, it is assumed that the maximum frequency of the inspection signal S13 is set to 200 MHz. In the present embodiment, since the four format data generation circuits 21a to 21d and the four buffers 22a to 22d are provided, the frequency of the rate signal S11 is set to 50 MHz that is a quarter of the frequency of the inspection signal S13. The frequency of the timing signal S12 is set to substantially the same frequency (200 MHz) as the inspection signal S13. Here, when the frequency of the rate signal S11 that defines the operating frequency of the format data generation circuits 21a to 21d is set to 100 MHz as in the first embodiment, the highest frequency of the inspection signal S13 and the frequency of the timing signal S12 are set to 400 MHz. And higher speed operation is possible.

  The buffers 22 a to 22 d have their input ends connected to the output ends of the format data generation circuits 21 a to 21 d, respectively, and their output ends connected to the buffer selector 23. The buffer selection control circuit 24 supplies a buffer selection signal BS to the buffers 22 a to 22 d and supplies a buffer switching signal SL to the buffer selector 23. The buffer selection signal BS is output to any one of the buffers 22a to 22d, and is used to select any one of the buffers 22a to 22d and read the pattern data stored in the selected buffer.

  Here, since the number of parallel buffers is “2”, the test signal generator 20 shown in FIG. 1 inputs the buffer switching signal SL to each of the buffers, thereby selecting this buffer as the pattern data. Can be shared with the signal for reading out (buffer selection signal). However, since the buffer switching signal SL cannot be shared in the present embodiment, the buffer selection signal BS is supplied from the buffer selection control circuit 24 to each of the buffers 22a to 22d.

  In the above configuration, the pattern data generated by the format data generation circuits 21a to 21d is stored in the buffers 22a to 22d, respectively, as in the first embodiment. Then, the buffer selection control circuit 24 sequentially supplies the buffer selection signal BS in the order of the buffer 22a, buffer 22b, buffer 22c, buffer 22d, buffer 22a,... And selects one of the buffers 22a to 22d and stores it. Read pattern data. In addition, in response to the supply of the buffer selection signal BS, the buffer switch signal SL is supplied to the buffer selector 23 to cause the inspection signal generation circuit 15 to output the pattern data read from the selected buffer as the select data D23. The inspection signal generation circuit 15 generates and outputs an inspection signal S13 using the input select data D23 and the timing signal S12.

  According to the inspection signal generation device 20 of the present embodiment, the operating frequencies of the format data generation circuits 21a to 21d and the buffers 22a to 22d can be further reduced. Alternatively, the operation frequency of the format data generation circuits 21a to 21d and the buffers 22a to 22d can be made the same as in the first embodiment, and the frequency of the inspection signal S13 can be made higher. In the example shown in FIG. 5, the configuration in which the parallel number of the format data generation circuit and the buffer is “4” is illustrated, but the parallel number is arbitrary.

[Third Embodiment]
FIG. 6 is a block diagram showing a configuration of the inspection signal generation apparatus according to the third embodiment of the present invention. The inspection signal generation device 30 of the present embodiment is different from the inspection signal generation device 20 shown in FIG. 5 in the configuration of the buffer selector and the buffer selection control circuit. As shown in FIG. 6, the inspection signal generation device 30 of this embodiment includes format data generation circuits 21 a to 21 d, buffers 22 a to 22 d, buffer selectors 33 a to 33 c, a buffer selection control circuit 34, and an inspection signal generation circuit 15. Consists of. The format data generation circuits 21a to 21d, the buffers 22a to 22d, and the inspection signal generation circuit 15 are the same as those shown in FIG.

  In the present embodiment, it is assumed that the highest frequency of the inspection signal S13 is set to 200 MHz as in the second embodiment shown in FIG. Also in this embodiment, since the four format data generation circuits 21a to 21d and the four buffers 22a to 22d are provided, the frequency of the rate signal S11 is 50 MHz that is a quarter of the frequency of the inspection signal S13. The frequency of the timing signal S12 is set to substantially the same frequency (200 MHz) as the inspection signal S13. Further, as in the second embodiment, when the frequency of the rate signal S11 that defines the operating frequency of the format data generation circuits 21a to 21d is set to 100 MHz as in the first embodiment, the highest frequency of the inspection signal S13 and the timing signal S12. Can be set to 400 MHz, and higher speed operation is possible.

  The input end of the buffer selector 33a is connected to the output ends of the buffers 22a and 22b, and the input end of the buffer selector 33b is connected to the output ends of the buffers 22c and 22d. The buffer selector 33c has its input terminal connected to the output terminals of the buffer selectors 33a and 33b, and its output terminal connected to the input terminal of the inspection signal generation circuit 15. Thus, in this embodiment, the buffer selector has a multistage configuration. The reason for this configuration is to reduce the operating frequency of the buffer selector. In the configuration shown in FIG. 6, the operating frequency of the buffer selector 33c is 200 MHz, which is the same as the frequency of the test signal S13, but the operating frequencies of the buffer selectors 33a and 33b are 100 MHz, which is a half of the operating frequency.

  The buffer selection control circuit 34 supplies buffer switching signals SL11 to SL13 to the buffer selectors 33a to 33c, respectively, and the pattern data read from the buffer selected by the supply of the buffer selection signal BS generates the test signal. Control to input to the circuit 15.

  According to the test signal generation device 30 of the present embodiment, the operating frequencies of the format data generation circuits 21a to 21d and the buffers 22a to 22d can be further reduced, as with the test signal generation device 20 of the second embodiment. Alternatively, the operation frequency of the format data generation circuits 21a to 21d and the buffers 22a to 22d can be made the same as in the first embodiment, and the frequency of the inspection signal S13 can be made higher. In the example shown in FIG. 6, a configuration in which the number of stages of the buffer selector is two (the buffer selectors 33a and 33b are the first stage and the buffer selector 33c is the second stage) is illustrated. However, the number of stages is arbitrary, and it is desirable to set appropriately according to the parallel number of buffers.

  Although the inspection signal generation apparatus according to the embodiment of the present invention has been described above, the semiconductor inspection apparatus of this embodiment includes the above inspection signal generation apparatus. Then, the inspection signal generated by the inspection signal generator is applied to the DUT, the expected value of the signal output from the DUT when the inspection signal is applied to the DUT is obtained, and the expected value and the actual output from the DUT are obtained. Is compared with the received signal to determine whether the DUT is good or bad.

It is a block diagram which shows the structure of the test | inspection signal production | generation apparatus by 1st Embodiment of this invention. 3 is a diagram illustrating an example of a circuit configuration of a buffer selection control circuit 14. FIG. It is a figure for demonstrating the pattern data memorize | stored in each of the buffer 12a, 12b. 6 is a timing chart for explaining an operation of reading pattern data from buffers 12a and 12b. It is a block diagram which shows the structure of the test | inspection signal production | generation apparatus by 2nd Embodiment of this invention. It is a block diagram which shows the structure of the test | inspection signal generation apparatus by 3rd Embodiment of this invention. It is a block diagram which shows the structure of the conventional test | inspection signal production | generation apparatus. It is a figure which shows the modification of the conventional test | inspection signal production | generation apparatus 100. FIG.

Explanation of symbols

10 Inspection Signal Generation Device 11a, 11b Format data generation circuit (generation circuit)
12a, 12b Buffer 13 Buffer selector (selective reading means, selector)
14 Buffer selection control circuit (selection reading means, selection control device)
DESCRIPTION OF SYMBOLS 15 Inspection signal generation circuit 20 Inspection signal generation apparatus 21a-21d Format data generation circuit (generation circuit)
22a to 22d buffer 23 buffer selector (selection reading means, selector)
24 Buffer selection control circuit (selection reading means, selection control device)
30 Inspection signal generator 33a, 33b Buffer selector (selection reading means, selector, first selector)
33c Buffer selector (selection reading means, selector, second selector)
S11 Rate signal (first control signal)
S12 Timing signal (second control signal)
S13 Inspection signal

Claims (5)

In an inspection signal generation device that generates the inspection signal using a first control signal that defines a frequency of an inspection signal to be given to an object to be inspected and a second control signal that defines an output timing of the inspection signal,
A plurality of generation circuits for generating pattern data defining a waveform of the inspection signal in synchronization with the first control signal;
A plurality of buffers provided corresponding to the generation circuits, and temporarily storing the pattern data generated by the corresponding generation circuit in synchronization with the first control signal;
Selection reading means for selecting one of the plurality of buffers in synchronization with the second control signal and reading the pattern data temporarily stored from the selected buffer;
An inspection signal generation device comprising: an inspection signal generation circuit that generates the inspection signal from the pattern data read by the selective reading means and the second control signal.   2. The inspection signal according to claim 1, wherein the frequency of the first control signal is set to a frequency obtained by dividing the frequency of the inspection signal given to the inspection target by the number of the generation circuits. Generator. The selective reading means includes a selector connected to an output end of the plurality of buffers and an input end of the inspection signal generation circuit;
A selection control device that selects a buffer that reads the pattern data from the plurality of buffers, and controls the selector to input the pattern data read from the selected buffer to the inspection signal generation circuit. The inspection signal generation device according to claim 1 or 2. The selector includes a plurality of first selectors connected to the plurality of buffers;
The inspection signal generation device according to claim 3, further comprising: a second selector connected to an output terminal of the first selector and an input terminal of the inspection signal generation circuit. In semiconductor inspection equipment that inspects the inspection target,
5. The inspection signal generation device according to claim 1, wherein the inspection signal is generated using a signal obtained by applying the inspection signal generated by the inspection signal generation device to the inspection target. A semiconductor inspection apparatus for inspecting an inspection object.

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