JP2007088171A - Semiconductor device and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is made to be thinner by performing mounting and laminating on a circuit substrate in the single body state of an electric circuit. <P>SOLUTION: The semiconductor device is obtained by combining, on a silicon wafer 7, the circuit substrate 5 with not less than two unit semiconductor devices 1, where an electric circuit 2 by the thin film growth of metal and silicon crystal is arranged at the side of an isolation layer 8 with electrodes 3, 4 are at the opposite side of the isolation layer 8 via the isolation layer 8. One of the unit semiconductor devices 1 is joined by facing-down with the circuit substrate 5 by the electrode 4 at the opposite side of the isolation layer 8. When the unit semiconductor device 1 joined by facing-down with the circuit substrate 5 is adopted as the lowest layer, the upper layer side unit semiconductor device 1 is joined by facing-down with the exposure surface of the electric circuit part 2, where the side of the isolation layer 8 is removed in the lower layer side unit semiconductor device 1. Then the plurality of unit semiconductor devices 1 are laminated on the circuit substrate 5. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a semiconductor structure in which an electronic circuit is formed on a silicon wafer by thin film growth of a metal / silicon crystal or a manufacturing method using the same. is there.

  In recent years, as seen in signal processing semiconductor devices such as system LSIs and memory cards for mobile phones, the number of elements has increased along with higher performance and higher functionality. The space to implement is a problem.

  Conventionally, so-called flip chip mounting, in which an IC chip or the like is directly mounted on a circuit board, has been generalized in order to realize high functionality, high performance, and downsizing of such electronic devices, and a stacked package has been made thereby. .

  For example, a stacked package of a semiconductor device such as a system LSI or a memory includes a package on package (POP) as shown in FIG. In this POP, a normal unit semiconductor device c composed of a base part a and an electric circuit part b of a silicon substrate is laminated on a circuit board d for a mother board via a circuit board e for an interposer. A unit semiconductor device c is mounted on the interposer circuit board e by bonding between the electrodes f and g, and the interposer circuit board e and the motherboard circuit board d on which the unit semiconductor device c is mounted. Are solder-bonded between the mutual electrodes j and k via the copper balls l, and the interposer circuit board e is solder-bonded between the mutual electrodes j and j via the copper balls l.

  Here, the electrode f of the unit semiconductor device c is formed by, for example, forming a protrusion by wire bonding on an aluminum electrode, and is brought into contact with a gold-plated copper electrode g of a circuit board e for an interposer to be bonded between metals. Implemented. For example, the metal-to-metal bonding between the electrodes f and g of the unit semiconductor device c and the circuit board e for interposer is performed by removing contaminants on the surface of the electrode g using plasma and applying pressure while applying ultrasonic energy. This is achieved by removing contaminants on each gold, and the reliability of the joint is enhanced by sealing the periphery of the joint with an epoxy resin h.

  Also, solder bonding of the electrodes f and g between the circuit board d for the motherboard and the circuit board e for the interposer, and the electrodes j and k between the circuit boards e for the interposer via the copper balls l is performed respectively. The solder solder joint copper ball l is heated on the upper side of the electrode j of the circuit board e for interposer via the high melting point cream solder m provided with printing, and the cream solder m is heated at a peak of 250 to 270 ° C. Pre-joined with reflow in the furnace, this pre-joined solder ball l is connected to the circuit board d for the motherboard and the electrode j, k on the side of the circuit board e for the interposer facing the solder ball l. Join them with reflow of only the cream solder n in the heating path whose peak temperature is lower than the above case, through the low melting point cream solder n printed in advance on them. It is achieved by.

  Also, the electrical connection between the circuit board d for the motherboard, the circuit board e for the interposer, and the circuit board e for the interposer is filled in the through-holes of the insulating layer interposed between them, so-called via holes. There are also known a method of performing via via posts and a lamination method of bonding with a conductive adhesive (for example, see Patent Document 1).

  On the other hand, there is a substrate having a strained silicon layer as a substrate for forming a semiconductor device with high speed and low power consumption. In the proposed one, a large amount of oxygen ions are implanted into the silicon substrate and buried in the silicon substrate. In the method of forming a film, a large number of crystal defects are generated in the silicon substrate, and there is a problem that the quality of the oxide film formed in the silicon substrate is not sufficient, whereas a separation layer is formed on the silicon substrate, A silicon layer, a SiGe layer, a silicon layer, and an insulating layer are formed thereon in order to produce a first substrate, and the first substrate is bonded to the second substrate on the insulating layer side to be integrated. Then, the SiGe in the SiGe layer below is diffused by hydrogen annealing into the silicon layer which is separated into two at the separation layer and becomes the exposed layer on the second substrate side, and the second substrate side A technique is known in which a strained SOI substrate having a SiGe layer on an insulating layer and a strained silicon layer thereon can be obtained with good yield and quality (see, for example, Patent Document 2). Also discloses a method of manufacturing a semiconductor member having a circuit element step of forming a circuit element on the strained silicon layer.

By the way, Patent Document 2 does not particularly disclose a technique for laminating semiconductor members obtained by manufacturing, but using conventional circuit boards for interposers, copper balls and via posts disposed between them, There is no choice but to select and apply a laminating method for joining via conductive adhesive.
JP 2003-218273 A (see FIG. 4) JP 2002-305293 A

  However, since the conventional semiconductor device has a multi-stage structure in which a unit semiconductor device mounted on a circuit board for an interposer is joined and laminated via a copper ball, a via post, and a conductive adhesive, In addition, the number of wirings and junctions is increased with respect to the electric circuit of the unit semiconductor device that performs signal processing, and the package stacking height increases. In order to stack unit semiconductor devices in four stages as in the conventional example of FIG. 11, a thickness of about 0.9 mm is required, which is a problem for further miniaturization of cellular phones and memory cards.

  An object of the present invention is a semiconductor device suitable for further thinning that can be mounted and stacked on a circuit board in a state of a single electric circuit part, and mounted on a circuit board in a state of a single electric circuit part, or mounted and stacked, It is an object of the present invention to provide a semiconductor device with a thinner thickness and a manufacturing method thereof.

  In order to achieve the above object, the semiconductor device of the present invention is provided with an electric circuit portion on a silicon wafer through a thin film growth of a metal / silicon crystal through a separation layer for mutual insulation and post-separation. Is one of the features.

  In such a configuration, the silicon wafer is formed on the substrate for manufacturing the semiconductor device by forming the electric circuit portion by the thin film growth method of the metal / silicon crystal through the separation layer on the silicon wafer. It works as a substrate that safely and electrically handles the electrical circuit part that is being used, not only for the manufacture of semiconductor devices with the electrical circuit part, but also between the electrodes at the down face to the circuit board of the semiconductor device unit after manufacture While ensuring that mounting and stacking with direct bonding are achieved, the separation layer side of the unit semiconductor device on the lower layer side is removed in the stacked state, so that the unit semiconductor device on the lower layer side can be As a state, a stacked structure is obtained in which unit semiconductor devices on the upper layer side are stacked without a substrate. Whether the semiconductor device is just mounted on the circuit board or positioned on the uppermost layer of the stack and the back surface remains exposed, it is protected by keeping the isolation layer and silicon wafer covered However, if it is removed, the joint with the other can be made bulky.

  Such a semiconductor device includes a step of forming a separation layer on a silicon wafer for mutual insulation and post-separation, and an electronic circuit formed by metal / silicon crystal thin film growth on the separation layer including electrodes. By the method for manufacturing a semiconductor device characterized by comprising the step of:

  The semiconductor device of the present invention also has an electric circuit portion formed by metal / silicon crystal thin film growth on the silicon wafer via a separation layer for mutual insulation and post-separation. A unit semiconductor device provided with an electrode on at least the anti-separation layer side and a circuit board, and the unit semiconductor device faces the circuit board with an electrode on the side opposite to the separation layer side. Another feature is that it is joined down.

  In such a configuration, the unit semiconductor device in which the electric circuit portion is formed on the silicon wafer via the separation layer is used as the semiconductor device mounted on the circuit board, and the electric circuit portion of the unit semiconductor device is formed on the substrate on which the unit circuit is formed. The silicon wafer side can be handled with mechanical and electrical safety, and the electrodes on the anti-separation layer side of the electric circuit part can be used to directly face-down to the circuit board. The electric circuit portion of the later unit semiconductor device can be mechanically and electrically protected by the silicon wafer and the separation layer until the separation layer side is removed for bonding with the other, having an electrode on the back.

  Such a semiconductor device includes a step of forming a separation layer on a silicon wafer for mutual insulation and post-separation, and a separation layer side and an anti-separation layer side by thin film growth of a metal / silicon crystal on the separation layer. Forming a unit semiconductor device by forming an electronic circuit in which at least the electrode on the side of the anti-separation layer protrudes from the surface, and face-down bonding to the circuit board with the electrode on the side of the anti-separation layer of the unit semiconductor device By the method for manufacturing a semiconductor device having another feature that the process is provided, the multilayer structure of the electric circuit portion can be easily achieved.

  In this case, since at least the electrode on the side of the anti-separation layer of the electric circuit portion of the unit semiconductor device protrudes from the surface, the direct bonding with the circuit board has a gap between the surroundings of the bonding portion. It is preferable to achieve contact prevention and insulation with the rest of the electric circuit portion.

  The semiconductor device of the present invention also has an electric circuit portion formed by metal / silicon crystal thin film growth on the silicon wafer via a separation layer for mutual insulation and post-separation. And at least a unit semiconductor device provided so that at least the electrode on the side opposite to the separation layer protrudes from the electric circuit portion, and a circuit board. Electricity that is face-down bonded to the circuit board with the electrode opposite to the layer side, and the unit semiconductor device face-down bonded to the circuit board is the bottom layer, and the separation layer side of the lower unit semiconductor device is removed Another feature is that the upper unit semiconductor device is face-down bonded to the exposed surface of the circuit portion, and a plurality of unit semiconductor devices are stacked on the circuit board.

  In such a configuration, in each unit semiconductor device, a silicon wafer is formed on a substrate for manufacturing a semiconductor device by forming an electric circuit portion by a metal / silicon crystal thin film growth method via a separation layer thereon, and a semiconductor It works as a substrate that safely and electrically handles the electrical circuit part formed in the device, manufactures a unit semiconductor device having the electrical circuit part, and utilizes the electrodes included in the electrical circuit part of the unit semiconductor device While the direct mounting on the circuit board and the stacking can be easily and reliably achieved, the unit semiconductor device on the lower layer side is removed by removing the separation layer side of the unit semiconductor device on the lower layer side when stacking. In this state, the unit semiconductor device on the upper layer side is laminated without interposing the substrate. In addition, even if the semiconductor device is mounted on a circuit board, or even if it is located on the uppermost laminated layer and the back surface is exposed, it can be protected by being covered with the separation layer and the silicon wafer. If it is removed, joining with others can be made bulky. In addition, since at least the electrode on the anti-separation layer side of the electric circuit portion protrudes from the electric circuit portion, direct bonding with the circuit board and the unit semiconductor device has a gap between the surroundings of the bonding portion. This is preferable because it is possible to prevent or insulate the electrical circuit unit from other parts.

  Such a semiconductor device includes a step of forming a separation layer on a silicon wafer for mutual insulation and post-separation, and an electronic circuit formed by thin film growth on the separation layer and electrodes on the separation layer side and the anti-separation layer side. Forming a unit semiconductor device by forming an electronic circuit in which at least the electrode on the side of the anti-separation layer protrudes from the surface, and a step of face-down bonding to the circuit board with the electrode on the side of the anti-separation layer of the unit semiconductor device; The unit semiconductor device face-down bonded to this circuit board is used as the lowermost layer, and the separation layer side of the lower unit semiconductor device is removed to expose the upper unit semiconductor device on the anti-separation layer side electrode. A step of performing face-down bonding at least once, and a step of stacking a plurality of unit semiconductor devices on a circuit board. It can be provided achieving multi-layered film structure of easily.

  In the further structure in which the exposed back surface of the unit semiconductor device that is face-down bonded is removed from the separation layer side, it can be carried out as it is for electrical connection with other layers and stacking of the unit semiconductor devices.

  In this case, according to the method for manufacturing a semiconductor device including the step of removing the separation layer side of the unit semiconductor device finally stacked, leaving a part of the separation layer, the uppermost unit semiconductor layer finally stacked on the circuit board While removing the separation layer side of the back of the device to eliminate the excessive thickness of the semiconductor device having the stacked structure, the back of the electrical circuit portion of the uppermost unit semiconductor device is mechanically and electrically connected to a part of the remaining separation layer. Can be protected.

  Further features and actions of the present invention will become apparent from the detailed description and drawings that follow. Each feature of the present invention can be used alone or in combination in various combinations as much as possible.

  According to the semiconductor device and its manufacturing method of one aspect of the present invention, the electric circuit portion has a multi-layered thin film structure formed by a metal / silicon crystal thin film growth method on a silicon wafer, and the unit semiconductor As a device, various semiconductor devices can be obtained which are handled and secured on a silicon wafer portion with mechanical and electrical safety, and which are easily and surely mounted and stacked on a circuit board with direct bonding between electrodes even at the down face.

  In particular, in the stacked state on the circuit board, the separation layer side of the unit semiconductor device which is the lower layer side is removed and it becomes a state of the electric circuit unit alone, so it becomes significantly lower than before, so high performance, Mobile phones and memory cards with higher functionality can be further miniaturized.

  In addition, even if the back surface of the unit semiconductor device is exposed after mounting or stacking, it is mechanically and electrically protected by removing the separation layer and the silicon wafer, so that it can be removed. Bonding with others can be done low. According to the manufacturing method, a multilayer thin film structure of the electric circuit portion can be easily achieved and provided at a low cost.

  According to another aspect of the present invention, a semiconductor device and a manufacturing method thereof, in particular, a unit semiconductor device having an electric circuit portion having a bulky thin film structure uses an electrode on the side opposite to the electric circuit portion. It can be mounted on a circuit board with direct face-down direct bonding, and can be provided inexpensively as it can be protected mechanically and electrically by a silicon wafer and a separation layer.

  If at least the electrode on the anti-separation layer side of the electric circuit portion of the unit semiconductor device protrudes from the surface, the circuit board and the unit semiconductor devices obtain a direct bonding state with a gap between the bonding portions. Therefore, it is possible to prevent contact and insulation with the rest of the electric circuit section, and to easily perform the joining without failure.

  An electrical circuit unit in which a unit semiconductor device is mounted face-down on a circuit board and stacked, and the unit semiconductor device face-down bonded to the circuit board is used as a lowermost layer, and the separation layer side of the lower unit semiconductor device is removed With a configuration in which the upper-layer unit semiconductor device is repeatedly face-down bonded to the exposed surface, two or more unit semiconductor devices can be stacked as low as necessary on the circuit board.

  In this case, if the separation layer side of the finally stacked unit semiconductor device is removed leaving a part of the separation layer, the excess thickness of the semiconductor device having the stacked structure is eliminated, and the remaining part of the separation layer is the uppermost layer. The back part of the electric circuit part of the unit semiconductor device can be protected mechanically and electrically.

  Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described in detail with reference to the drawings for understanding of the present invention. The following embodiments are specific examples of the present invention and do not limit the technical scope of the present invention.

  The semiconductor device according to the present embodiment is shown in FIG. 5B, and is a single semiconductor device 1 as handled in FIG. 6A, and a circuit board 5 as shown in FIG. Each case shows a semiconductor device 11 on which the device 1 is mounted and a semiconductor device 21 in which a plurality of unit semiconductor devices 1 are stacked on a circuit board 5 as shown in FIG. From the viewpoint of the manufacturing process in which these are obtained, the semiconductor device 1 shown in FIGS. 5B and 6A is a primary semiconductor device obtained in a thin film growth process of a metal / silicon crystal, and FIG. The semiconductor device 11 shown in FIG. 1 is a secondary semiconductor device obtained in the process of mounting the primary semiconductor device as the unit semiconductor device 1 on the circuit board 5, and the semiconductor device 21 shown in FIG. 1 is a secondary semiconductor device of the semiconductor device 11. It can be said that there is a relationship with a tertiary semiconductor device obtained by stacking another unit semiconductor device 1 on the unit semiconductor device 1.

  The unit semiconductor device 1 shown in FIGS. 5 (b) and 6 (a) has an electric circuit formed on a silicon wafer 7 by a thin film growth of a metal / silicon crystal through a separation layer 8 for mutual insulation and post-separation. A portion 2 is provided, which is manufactured by the steps shown in FIGS. In the process of FIG. 2A, the separation layer 8 is formed on the silicon wafer 7 as the base portion. A method of forming the separation layer 8 is generally based on SOI (silicon on insulator) technology as disclosed in Patent Document 2. However, it is not limited to this. The separation layer 8 to be formed is highly brittle as a porous structure by anodizing the silicon wafer 7 in order to facilitate subsequent separation. In the step of FIG. 2B, the electrode 3 is formed on the separation layer 8 by sputtering a metal thin film using a sputter (SPUTTER) method. In the case of the present embodiment, copper was used as the metal of the electrode 3.

  Sputtering here was performed using a sputtering apparatus as shown in FIG. Explaining this, a state in which the degree of vacuum in the reaction chamber 30 is maintained at 0.7 Pa while Ar gas is supplied to the reaction chamber 30 from the gas inlet 31 through 5 SCCM and a part thereof is exhausted through the gas exhaust port 32. As described above, a high frequency of 1000 W is applied from the external DC power source 35 through the lower opening to the electrode 34 that is installed on the lower opening through the insulating ring 33 and has the cooling path 36, and the upper counter electrode 38 in the reaction chamber 30. Plasma is generated between them. Ar gas in the plasma is irradiated onto the electrode 34 and the copper target 37 thereon is sputtered. By this sputtering, sputtered copper particles are deposited on the separation layer 8 on the surface of the silicon wafer 7 on the counter electrode 38 to grow a thin film. The electrode 3 having a thickness of about 1 μm as shown in FIG. 2B is formed with a sputtering time of about 10 minutes.

  In the step of FIG. 2C, the electrode 3 uniformly formed on the separation layer 8 by the sputtering method is applied with a photolithography method (resist coating step and coating) in order to obtain a predetermined pattern as shown in the drawing. After the resist layer is exposed through an exposure mask, the exposed portion is removed by development). By such a process, the shape of the electrode and the electric circuit on the side of the separation layer 8 necessary at that time is created.

For the etching here, an etching apparatus schematically shown in FIG. 10 was used. To illustrate per thereto, from the gas inlet 41 into the reaction chamber 40, 25 SCCM of SiCl ₂ gas, flowing 40SCCM Cl ₂ gas, while a part was evacuated through the gas outlet 42, a vacuum in the reaction chamber 40 With the temperature maintained at 4 Pa, the high-frequency electrode 44 having a cooling path 47 that is installed on the lower opening via the insulating ring 43 and suppresses the temperature rise to 200 ° C. or less is connected to 400 W from the external high-frequency power source 46 through the lower opening. To generate plasma between the upper counter electrode 45 and the reaction chamber 40. The electrode 3 is processed for 15 minutes in a state where plasma is generated. On the surface of the copper film 3 exposed to plasma, chlorine ions existing in the plasma are irradiated and etched to form a predetermined pattern as shown in FIG.

In the step of FIG. 3A, a polycrystalline silicon layer 9 is formed on the separation layer 8 carrying the electrode 3 patterned in FIG. 2C by CVD using a thin film growth of a silicon crystal. . Here, the CVD method is a method in which a reaction gas is introduced during decompression and heated to thermally decompose the reaction gas to form a film. As the film forming conditions, SiH ₄ gas is used and the heating temperature is 600 ° C. and the pressure is 200 Pa.

  In the step of FIG. 3B, the polycrystalline silicon layer 9 is annealed by a laser annealing method to be changed to a single crystalline silicon layer 9a. An excimer laser (XeCl) was used as the laser, and annealing treatment was performed at an output of 200 W.

In the step of FIG. 3 (c), a process such as the photolithography method or the ion implantation method described above is used for the single crystal silicon layer 9a, and a transistor, an electric wiring, or the like is formed by thin film growth to form the electric circuit layer 2a. . Etching by the photolithography method is performed using the etching apparatus shown in FIG. However, in the case of single-crystal silicon layer 9a, C ₄ F ₈ gas flow 100 SCCM SCCM, the SF ₆ gas is performed 0.5 Pa, an RF power 400W, an etching treatment under the conditions are not heated vacuum.

  In the step of FIG. 4A, the copper film 3a is formed by thin film growth by the same method as the steps of FIGS. 2B and 2C to form electrodes and wiring patterns.

  In the process of FIG. 4B, in order to stack the electric circuit inside the unit semiconductor device 1 by thin film growth, the single crystal siliconization and the body film 3a are patterned on the thin film patterned in the process of FIG. The polycrystalline silicon layer 9b is formed by the same thermal CVD method as in FIG.

  In the step of FIG. 4C, the stacked polycrystalline silicon layer 9b is single-crystallized in the same manner as in the step of FIG. 3B, and the electric circuit layer 2a such as a transistor or a wiring is formed in the same manner as in the step of FIG. It is formed by thin film growth of metal / silicon crystals.

  As a result, as shown in FIG. 4C, two-stage electric circuit layers 2a and 2a are formed on the surface of the separation layer 8 on the silicon wafer 7.

  Further, in the step of FIG. 5A, the steps of FIG. 4B and FIG. 4C are repeated a plurality of times to obtain the unit semiconductor device 1 in which the electric circuit layer 2a is formed in multiple layers up to a predetermined number.

  Finally, in the step shown in FIG. 5B, a metal is used to project a predetermined amount of the electrode 4 made of aluminum, copper, or the like on the surface of the uppermost electric circuit layer 2a by using the above-described sputtering method or lithography method. The unit semiconductor device 1 is formed by thin film growth. The electrode 4 may have a nickel or gold layer on the surface by a metal plating method.

  In this way, the unit semiconductor device 1 can be provided in a low-cost, low-yield, low-yield structure with a simple multilayered thin-film structure of the electric circuit section 2. In addition, such a unit semiconductor device 1 is provided with an electric circuit section 2 by thin film growth of a metal / silicon crystal on a silicon wafer 7 via a separation layer 8 for mutual insulation and post-separation. . Here, the silicon wafer 7 is a substrate for manufacturing the unit semiconductor device 1 by forming the electric circuit portion 2 by the metal / silicon crystal thin film growth technique through the separation layer 8 on the silicon wafer 7. The electric circuit unit 2 is used as a substrate for safely and electrically handling the electric circuit unit 2, and the unit semiconductor device 1 having the electric circuit unit 2 is manufactured as well as the unit semiconductor device 1 unit after manufacturing. While ensuring that the mounting and lamination with direct bonding between the electrodes 4 and 6 and the electrodes 4 and 3 in the down face to the circuit board 5 as shown in FIG. In the stacked state as shown in FIGS. 8B and 8C, the unit semiconductor device 1 on the lower layer side is removed so that the unit semiconductor device 1 on the lower layer side is in the state of the electric circuit unit 2 alone. Unit semiconductor device 1 on the side Layered structure interposed without lamination of the circuit board for Da will be obtained. Moreover, even if the unit semiconductor device 1 is only mounted on the circuit board 5 or positioned on the uppermost stacked layer, the separation layer 8 or the silicon wafer 7 is covered even if the back surface remains exposed. By doing so, it is protected until electrical connection with others is achieved, and if it is removed, the connection with others can be made bulky.

  From the above, the electric circuit unit 2 has a low-profile multi-layered thin film structure formed by a metal / silicon crystal thin film growth method on the silicon wafer 7, and the unit semiconductor device 1 is mechanically coupled to the silicon wafer 7 unit. Various semiconductor devices 11 and 21 that are handled and stacked on the circuit board 5 easily and reliably with direct bonding between the electrodes 4 and 6 and the electrodes 4 and 3 even in the down face can be obtained.

  In particular, in the stacked state on the circuit board 5, as shown in FIGS. 1, 8B and 8C, each of the unit semiconductor devices 1 on the lower layer side has the separation layer 8 side removed, and the electric circuit unit 2 alone Therefore, the cellular phone and memory card with higher performance and higher functionality can be further miniaturized.

  Moreover, even if the back surface of the unit semiconductor device 1 is exposed after being mounted or stacked, by keeping the covering state with the separation layer 8 or the silicon wafer 7, it is mechanically and electrically protected, If it is removed, bonding with others can be made bulky.

  In particular, since the electrode 4 is an external electrode protruding from the outermost electric circuit layer 2a, that is, from the electric circuit portion 2, electrical connection with the other can be achieved directly as described above. Specifically, direct bonding with the circuit board 5 and the lower layer unit semiconductor device 1 is achieved with the gap G between the electrodes 4 and 6 and between the electrodes 4 and 3 and around the bonding portion. Therefore, it is preferable to prevent contact and insulation with the rest of the electric circuit portion 2. It is preferable to seal the periphery of the joint with an insulating resin as necessary.

  Next, a process of manufacturing the semiconductor device 11 in which the unit semiconductor device 1 is mounted on a circuit board 5 of a product such as a mobile phone or a memory card will be described with reference to FIG.

  First, in the process of FIG. 6A, the unit semiconductor device 1 is sucked and sucked through the suction hole 13 by the mounting tool 12 provided in the mounting head (not shown) at the base portion 17 formed by the silicon wafer 7 and the separation layer 8. , Hold, handle and mount with mechanical and electrical safety. On the other hand, the circuit board 5 to be mounted is placed in the decompression furnace 10. The mounting tool 12 positions the adsorbed unit semiconductor device 1 with respect to the circuit board 5 in the decompression furnace 10, makes the electrodes 4 and 6 face each other, and keeps a certain distance in the vertical direction. The air in the decompression furnace 10 is discharged until a predetermined pressure, for example, 20 Pa is reached. Next, high-frequency power 13.5 MHz is applied between the electrodes (not shown) in the vacuum furnace 10 to generate plasma. At this time, by plasma ion irradiation, contaminants adhering to the surfaces of the electrodes 4 and 6 and substances that inhibit intermetallic bonding such as oxide films are removed.

  Thereafter, the application of the electric field and the magnetic field is stopped, the air leaks into the decompression furnace 10, and the mounting tool 12 is lowered to bring the electrodes 4 and 6 into contact with each other within 1 minute after returning to the normal atmospheric pressure. Thus, the electrodes 4 and 6 are metal-bonded to complete the face-down mounting, and the semiconductor device 11 as shown in FIG. 6B is obtained. In addition to pressurization, the mounting tool 12 may be given an ultrasonic wave or heated as energy for assisting the metal-to-metal bonding.

  Here, the metal bonding between the electrodes 4 and 6 is preferably the same type of metal bonding such as copper and copper, gold and gold, aluminum and aluminum. However, the present invention is not limited to this, and a dissimilar metal bond such as aluminum and gold or copper and gold can also be used.

  As described above, the electric circuit section 2 formed by metal / silicon crystal thin film growth is formed on the silicon wafer 7 via the separation layer 8 for mutual insulation and post-separation. 8 is a combination of a unit semiconductor device 1 provided with an electrode 4 on at least the anti-separation layer 8 side and a circuit board 5, and the unit semiconductor device 1 is opposite to the separation layer 8 side. A semiconductor device 11 face-down bonded to the circuit board 5 by the side electrode 4 can be provided. According to such a semiconductor device 11, the unit semiconductor device 1 in which the unit semiconductor device 1 in which the electric circuit portion 2 is formed on the silicon wafer 7 via the separation layer 8 is used as the semiconductor device 11 mounted on the circuit substrate 5. 1 is handled on the side of the silicon wafer 7 that forms the base portion 17 that forms the electrical circuit portion 2 with the mechanical and electrical safety as described above, and is on the side of the anti-separation layer 8 of the electrical circuit portion 2. The electrode 4 can be directly face-down bonded to the circuit board 5, and the electric circuit portion 2 of the unit semiconductor device 1 after mounting has the electrode 3 on the back and is bonded to the other. Therefore, the silicon wafer 7 and the separation layer 8 can be mechanically and electrically protected until the separation layer side is removed.

  Finally, the unit semiconductor device 1 is further stacked and mounted on the semiconductor device 11 shown in FIG. 6B, and the semiconductor device 21 shown in FIGS. 1, 8B, and 8C is manufactured. The case will be described with reference to FIGS.

  7A, the separation layer 8 side of the unit semiconductor device 1 mounted on the circuit board 5 is removed. That is, the electric circuit portion 2 and the base portion 17 of the unit semiconductor device 1 are separated at the portion of the separation layer 8 as shown in FIG. Specifically, as shown in FIG. 7A, the separation layer 8 is physically jetted from the side by jetting a liquid 15 in which a minute abrasive is mixed with the water jet head 14 onto the separation layer 8. Destroy. As a result, the base portion 17 is separated from the electric circuit portion 2 and removed as shown in FIG. At this time, a part of the separation layer 8 remains on the back surface of the electric circuit portion 2. That is, the separation layer residual portion 8a remains attached. If this is left as it is, it becomes a protective layer on the back surface of the electric circuit portion 2, so that it is preferable to leave it on the back surface of the electric circuit portion 2 until electrical connection with the other is achieved.

In this example, the unit semiconductor device 1 is removed in order to form a stack for joining. This removal is performed by, for example, a dry etching method. For the dry etching, the etching apparatus of FIG. 10 is used, an etching gas such as CF ₄ gas is introduced into the reaction chamber 40, plasma is generated, and the separation layer remaining portion 8a is subjected to a chemical reaction by fluorine-based radicals in the plasma. Remove. If the etching rate is appropriately managed, only the separation layer residual portion 8a is removed, and the electrode 3 of the electric circuit portion 2 can be exposed as shown in FIG. 7C. Here, the electrode 3 is electrically connected to the electric circuit portion 2 when the electric circuit portion 2 is formed by thin film growth, and this is also a protruding electrode protruding from the electric circuit portion 2. Good.

  Next, in the process of FIG. 8A, in the same pressure reduction furnace 10 as in FIG. 6A, the first electric circuit unit 2 is mounted on the circuit board 5 and the separation layer 8 side is removed to form the first electric circuit unit 2. The second unit semiconductor device 1 is stacked and mounted on the unit semiconductor device 1. Specifically, in the case of FIG. 6A, the electrode 4 of the second unit semiconductor device 1 is opposed to the electrode 3 exposed on the back surface of the electric circuit section 2 of the first unit semiconductor device 1. After removing the adhering foreign matter and oxide film by the same operation as in Fig. 1, the mounting is finished by metal bonding between the electrodes 4 and 3, and the second semiconductor device as shown in Figs. The first separation layer 8 side is removed, the separation layer remaining portion 8a is removed, and the back surface of the electric circuit portion 2 of the second semiconductor device 1, particularly the electrode 3 is exposed.

  By repeating the stacking operation as described above, as illustrated in FIG. 8C, the semiconductor device 21 in which the required number and the predetermined number of unit semiconductor devices 1 are stacked on the circuit board 5 is obtained.

  As described above, the electric circuit section 2 formed by metal / silicon crystal thin film growth is formed on the silicon wafer 7 via the separation layer 8 for mutual insulation and post-separation. 2 or more unit semiconductor devices 1 provided so that at least the electrode 4 on the side opposite to the separation layer of the electrodes 3 and 4 provided on the side protrudes from the electric circuit portion 2, and a circuit board 5, One of the unit semiconductor devices 1 is face-down bonded to the circuit board 5 with the electrode 4 on the side opposite to the separation layer 8 side, and the unit semiconductor device 1 face-down bonded to the circuit board 5 is used as the lowermost layer. A stack in which a plurality of unit semiconductor devices 1 are stacked on a circuit board 5 by face-down bonding the upper layer unit semiconductor device 1 to the exposed surface of the electric circuit portion 2 from which the separation layer 8 side of the lower unit semiconductor device 1 is removed. Structure semiconductor It is possible to provide a location 21.

  According to such a semiconductor device 21, in each unit semiconductor device 1, the silicon wafer 7 forms the electric circuit portion 2 by the metal / silicon crystal thin film growth method via the separation layer 8 thereabove to form the unit semiconductor device. 1, the base part 17, and the electric circuit part 2 formed in the unit semiconductor device 1, which serves as an electric and mechanically safe substrate and base part 17, and has the electric circuit part 2 The manufacturing of the unit semiconductor device 1 and the direct mounting on the circuit board 5 with the metal bonding between the electrodes 4 and 6 of the electric circuit section 2 of the unit semiconductor device 1 and the metal between the electrodes 4 and 3 While making it possible to easily and reliably achieve lamination with bonding, the unit semiconductor device 1 on the lower layer side is removed from the electric circuit portion 2 by removing the separation layer 8 side of the unit semiconductor device 1 that is on the lower layer side during lamination. Stand alone and The unit semiconductor device 1 of the upper layer becomes a layered structure interposed without lamination of the circuit board for interposer Te. In addition, even when the unit semiconductor device 1 is mounted on the circuit board 5 and is located on the uppermost layer that is stacked, the separation layer 8 and the silicon wafer 7 remain covered even if the back surface is exposed. If you remove it, it will be protected. To give a specific example, the thickness of one unit semiconductor device 1 that is a single electric circuit unit 2 varies depending on the number of electric circuit layers 2a of the electric circuit unit 2, but is 0.01 mm in this example. Even in the four-stage laminated structure shown in (c), the thickness of the laminated part is m0.04 mm. Moreover, since at least the electrode 3 on the anti-separation layer 8 side of the electric circuit portion 2 protrudes from the electric circuit portion 2, the electrodes 4 and 6 between the circuit substrate 5 and the unit semiconductor device 1, and between the electrodes 4 and 3. In this case, the direct bonding is achieved with the gap G between the joints, and it is preferable to prevent contact and insulation with the rest of the electric circuit part.

  In addition, the film formation conditions formed by the sputtering method of the copper film 3 are an example, and are not specifically limited. Although the copper film 3 is formed by the sputtering method, it can be formed by the CVD method instead.

  Moreover, the etching conditions of the copper film 3 demonstrated in FIG. 10 are examples, and are not specifically limited.

  Furthermore, the conditions for using the CVD method to form the polycrystalline silicon layer 9 have been described above, but this is merely an example and is not limited.

  Further, the etching conditions for the single crystal silicon layer 9a already described in the description of FIG. 3C are merely examples, and are not particularly limited.

  The present invention relates to a unit semiconductor device having an electric circuit part, a cell phone and a memory card that are mounted on a circuit board and are practically used as a stacked semiconductor device to reduce the bulk, increase performance, and increase functionality. The thickness can be reduced to about 1/25 as an example.

It is sectional drawing which shows one example of the lamination type semiconductor device which concerns on embodiment of this invention. FIG. 2 is a process diagram illustrating a first stage of a manufacturing process of a unit semiconductor device stacked in the semiconductor device of FIG. 1 divided into (a) to (c). FIG. 3 is a process diagram showing a second stage of the manufacturing process of the unit semiconductor device subsequent to FIG. 2 divided into (a) to (c). FIG. 11 is a process diagram illustrating a third stage of the manufacturing process subsequent to FIG. 3 of the unit semiconductor device, which is divided into (a) to (c). FIG. 5A is a process diagram showing a fourth stage of the manufacturing process subsequent to FIG. 4 of the unit semiconductor device, which is divided into (a) and (b). FIG. 6A is a process diagram showing a first stage of a manufacturing process for manufacturing a semiconductor device in a state where the unit semiconductor device manufactured as shown in FIG. 5B is mounted on a circuit board, divided into (a) and (b). FIG. 7 is a process diagram illustrating the latter stage of the semiconductor device manufacturing process following FIG. 6 by dividing the process into (a) to (c). FIG. 8 is a process diagram illustrating a manufacturing process subsequent to the processes of FIGS. 6 and 7 of the stacked type semiconductor device as illustrated in FIG. 1 in (a) to (c). It is sectional drawing which shows an example of the sputtering device used for manufacture of the semiconductor device of this invention. It is sectional drawing which shows an example of the etching apparatus used for manufacture of the semiconductor device of this invention. It is sectional drawing which shows the example of the conventional lamination type semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 11, 21 Semiconductor device 2 Electric circuit part 3, 4, 6 Electrode 5 Circuit board 7 Silicon wafer 8 Separation layer 9 Polycrystalline silicon layer 9a Monocrystalline silicon layer 12 Mounting tool 13 Suction hole 14 Water jet head 15 Abrasive material mixture No water 17 base part

Claims (10)

A semiconductor device comprising an electric circuit portion formed by thin film growth of a metal / silicon crystal on a silicon wafer through a separation layer for mutual insulation and post-separation. On the silicon wafer, through an isolation layer for mutual insulation and post-separation, an electric circuit part by metal / silicon crystal thin film growth is provided with electrodes on at least the anti-separation layer side of the isolation layer side and the anti-separation layer side. The unit semiconductor device comprises a combination of a unit semiconductor device provided and a circuit board, and the unit semiconductor device is face-down bonded to the circuit board with an electrode on the side opposite to the separation layer side. Semiconductor device. At least an anti-separation layer of an electrode having an electric circuit portion on the silicon layer and an anti-separation layer side by means of a thin film growth of a metal / silicon crystal through a separation layer for mutual insulation and post-separation A combination of two or more unit semiconductor devices provided so that the electrode on the side protrudes from the electric circuit section and a circuit board, and one of the unit semiconductor devices is on the side opposite to the separation layer side The unit semiconductor device face-down bonded to the circuit board with the electrodes of the upper layer side is formed on the exposed surface of the electric circuit portion from which the separation layer side of the lower unit semiconductor device is removed with the unit semiconductor device face-down bonded to the circuit board as the lowermost layer. A semiconductor device, wherein unit semiconductor devices are face-down bonded, and a plurality of unit semiconductor devices are stacked on a circuit board. 4. The semiconductor device according to claim 2, wherein the separation layer side is removed from the exposed back surface of the unit semiconductor device that is face-down bonded. 5. A step of forming a separation layer on the silicon wafer for mutual insulation and post-separation, and a step of forming an electronic circuit including an electrode on the separation layer by thin film growth of a metal / silicon crystal. A method for manufacturing a semiconductor device. Forming a separation layer on the silicon wafer for mutual insulation and post-separation, and growing a metal / silicon crystal thin film on the separation layer to at least the anti-separation layer side and the anti-separation layer side And a step of forming an electronic circuit having an electrode. Forming a separation layer on the silicon wafer for mutual insulation and post-separation, and including electrodes on the separation layer side and the anti-separation layer side by thin film growth of a metal / silicon crystal on the separation layer; A step of forming a unit semiconductor device by forming an electronic circuit in which an electrode on the separation layer side protrudes from the surface, and a step of face-down bonding to a circuit board with an electrode on the side opposite to the separation layer of the unit semiconductor device. A method of manufacturing a semiconductor device. Forming a separation layer on the silicon wafer for mutual insulation and post-separation, and including electrodes on the separation layer side and the anti-separation layer side by thin film growth of a metal / silicon crystal on the separation layer; A step of forming a unit semiconductor device by forming an electronic circuit in which an electrode on the separation layer side protrudes on the surface, a step of face-down bonding to a circuit board with an electrode on the side opposite to the separation layer of the unit semiconductor device, And a step of removing the separation layer side of the unit semiconductor device leaving a part of the separation layer. A step of forming a separation layer on the silicon wafer for mutual insulation and post-separation, and an electronic circuit formed by thin film growth on the separation layer including electrodes on the separation layer side and the anti-separation layer side, and at least the anti-separation layer Forming an electronic circuit with a side electrode protruding on the surface to obtain a unit semiconductor device, a step of face-down bonding to the circuit board with an electrode on the anti-separation layer side of the unit semiconductor device, and face down to the circuit board The unit semiconductor device joined is the bottom layer, and the unit semiconductor device on the upper layer side is face-down bonded to the circuit layer exposed by removing the separation layer side of the lower unit semiconductor device with the electrode on the anti-separation layer side. And a step of stacking a plurality of unit semiconductor devices on a circuit board at least once, and a method for manufacturing a semiconductor device. 9. The method of manufacturing a semiconductor device according to claim 8, further comprising a step of removing the separation layer side of the unit semiconductor device finally stacked, leaving a part of the separation layer.

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