JP2000138260A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance connection reliability of flip-chip mounting by filling the surface on the electrode pad side of a semiconductor device with sealing resin, while surrounding the side face of solder bumps formed thereon and making thin the rear surface of a semiconductor substrate, thereby enhancing strength at the joint. SOLUTION: A spherical bump 20 of high melting point solder is formed at each electrode part of individual semiconductor LSIs 11 on a semiconductor wafer 10. The entire surface of the semiconductor wafer 10 is then spin coated with a sealing resin 21, e.g. epoxy resin, which is cured through heat treatment at about 150 deg.C for about 5 hours. Since the periphery of the solder bump 20 is filled with the sealing resin 21 before the semiconductor wafer 10 and a semiconductor substrate 12 are made thin by mechanical grinding, the mechanical strength of the semiconductor substrate 12 is enhanced. Handling of a thin semiconductor substrate 12 is facilitated, and the yield of the semiconductor LSI is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device such as a semiconductor IC and a semiconductor LSI, and more particularly to a method of manufacturing a semiconductor device having a solder bump on an electrode pad portion.

[0002]

2. Description of the Related Art In recent years, portable electronic devices such as digital video cameras, digital cellular phones, and notebook personal computers have become widespread, and such portable electronic devices have been reduced in size, thickness and weight. Demands are growing. In order to reduce the size, thickness, and weight of portable electronic devices, it is important to increase the component mounting density. In particular, semiconductor I
As for semiconductor devices such as C and semiconductor LSI, a high-density mounting technology using a flip-chip type semiconductor device directly mounted on a printed wiring board instead of a conventional package type semiconductor device has been developed and put into practical use. I have.

As a mounting method for mounting such a flip-chip type semiconductor device (flip-chip mounting), for example, a solder bump is formed on an Al electrode pad of a semiconductor LSI, and connection terminals of a chip of the semiconductor LSI are formed. Is brought into contact with the solder bumps and the LSI chip is directly mounted on the printed wiring board. Here, as a method for manufacturing the solder bump, there is a method using electrolytic plating. According to this method, the thickness of the solder formed by electrolytic plating is affected by the slight variations in the surface state and electric resistance of the base material layer, and the height of the solder formed in one IC chip is reduced. There is a problem that it is basically difficult to form a uniform solder bump.

[0004] On the other hand, as a method of manufacturing a solder bump which suppresses variations in the height of the solder bump, there is a method of forming a film by vacuum evaporation and a method of forming a pattern using lift-off of a photoresist film. This method is implemented, for example, as shown in FIG. Here, in FIG. 11A, the electrode portion 1a of the flip-chip type semiconductor LSI 1 has an electrode pad 3 made of an Al—Cu alloy or the like formed on a semiconductor substrate 2 made of silicon or the like by sputtering, etching or the like. A surface protection film 4 made of a silicon nitride film, polyimide, or the like, which is formed so as to cover the entire surface of the semiconductor substrate 2 from above the electrode pad 3; and a surface protection film 4 formed in the region of the electrode pad 3. A metal multilayer film made of, for example, Cr, Cu, Au, or the like, which is formed by sputtering or the like so as to cover the opening 4a and the surface of the electrode pad 3 exposed at the side and bottom of the opening 4a, so-called BLM (Ball Limit)
(Ting Metal) film 5.

[0005] In order to form a solder bump on the electrode portion 1a of the semiconductor LSI 1 having such a configuration, FIG.
As shown in (b), an opening 6 is formed in the region of the BLM film 5.
A resist film 6 having a is formed. Subsequently, FIG.
As shown in (c), a solder vapor deposition film 7 is formed on the entire surface of the semiconductor substrate 2 from above the resist film 6. Thereafter, as shown in FIG. 11D, unnecessary portions of the solder-deposited film 7 are removed by lift-off of the resist film 6, and a desired pattern of the solder-deposited film 7 is formed. Finally, FIG.
As shown in (e), a heat treatment is applied to melt the solder of the solder deposition film 7, thereby forming a substantially spherical solder bump 7a based on the surface tension of the solder. Here, generally, the formation of the solder bumps 7a is performed when the semiconductor LSI 1 is in the state of a semiconductor wafer, that is, each semiconductor LSI
This is performed in a state before cutting into the SI chip 1.

[0006] From the semiconductor LSI 1 in which the solder bumps 7a are formed on the electrode portions 1a in this way, the wafer-like semiconductor substrate 2 is cut out as individual chip-like semiconductor LSIs 1 by dicing or the like. Thereafter, as shown in FIG. 12, the solder bumps 7a of the respective semiconductor LSIs 1 are respectively brought into contact with lands 8a made of Cu or the like as contact portions formed on the printed wiring board 8. Here, the surface of the printed wiring board 8 excluding the land 8a is
b, and the area of the land 8a is pre-coated with the eutectic solder film 8c.

Therefore, the eutectic solder film 8c is melted by the reflow process, enters between the solder bump 7a and the land 8a, and is cooled and hardened. This allows
Each solder bump 7a is soldered to the land 8a and is electrically connected. In the flip-chip mounting performed as described above, the printed wiring board is reduced in size as compared with the mounting of a semiconductor device packaged with a conventional molding resin, so that various electronic devices can be miniaturized. , Which contributes to the realization of weight reduction.

[0008]

By the way, IC cards, mobile phones, PDAs (Personal Digits)
In a portable electronic device such as an al assistant, it is desirable that the mounting space for the semiconductor device be as small as possible. In addition to the two-dimensional miniaturization that has been mainly planned so far, it is possible to reduce the thickness in the height direction. Therefore, there is a strong need to establish a semiconductor device mounting technology. It is desirable to reduce the thickness of the semiconductor device by, for example, thinning the semiconductor wafer after the formation of the semiconductor device. However, when the semiconductor wafer is reduced in thickness, the semiconductor wafer itself is easily broken and the subsequent handling is very difficult. Become. Furthermore, as the diameter of semiconductor wafers is increasing, when thinning semiconductor wafers,
It is an important point to secure the mechanical strength of a semiconductor wafer.

On the other hand, if the semiconductor wafer is thinned after the solder bumps are formed on the electrode portions of the semiconductor device, the solder bumps may be exposed to the outside when the semiconductor wafer is handled or set in various processing apparatuses. Touch,
Frequent occurrence of deformation defects and conduction defects at the joints occurs. Also, the solder bump 7a and the land 8 described above are used.
a, when the ambient temperature changes, the semiconductor L
Since the semiconductor substrate 2 of the SI 1 and the printed wiring board 8 have different coefficients of thermal expansion, they are subjected to thermal stress.

That is, while the coefficient of thermal expansion of silicon constituting the semiconductor substrate 2 is 3.4 ppm / ° C., the coefficient of thermal expansion of a glass epoxy type substrate generally used as the printed wiring board 8 is about 15 ppm. / ° C. Therefore, when thermal stress is repeatedly applied to a solder joint between the solder bump 7a and the land 8a due to a temperature difference generated by turning on and off the semiconductor LSI 1, a crack is generated at the joint and broken, and the electrical connection is made. In some cases, the breakage may cause a so-called breakage failure, and there is a problem in the reliability of the solder joint.

As shown in FIG. 12, a sealing resin 9 is injected between the semiconductor LSI 1 and the printed wiring board 8 in order to suppress the breakage of the solder joint due to such thermal stress. A method is generally adopted in which a stress is received by the entire sealing resin 9 so as to reduce the thermal stress at the solder joint portion and increase the strength against the thermal stress. However, in the above-described configuration using the sealing resin 9, the semiconductor LSI 1 is integrally fixed and held to the printed wiring board 8 by the sealing resin 9. ,
Either the entire printed wiring board 8 on which the semiconductor LSI 1 is mounted is replaced entirely and the defective product is discarded, or the semiconductor LSI 1 is forcibly peeled off from the printed wiring board 8 by a chemical or mechanical external force.

Here, the former replacement of the entire printed wiring board 8 has a problem that the cost is increased, and the latter forced stripping of the semiconductor LSI 1 causes damage to the printed wiring board 8. Become. Therefore, it is difficult to replace defective components when a defect occurs in the semiconductor LSI 1, that is, to perform a so-called rework operation, which is one reason that flip chip mounting is not widely used.

SUMMARY OF THE INVENTION In view of the above, the present invention allows a semiconductor device to be configured to be thinner and to reliably reduce thermal stress between the semiconductor device and a printed wiring board without using a sealing resin. It is an object of the present invention to provide a method of manufacturing a semiconductor device in which the connection is relaxed and the connection reliability in flip-chip mounting is increased by increasing the strength of a bonding portion.

[0014]

According to the present invention, there is provided a semiconductor device comprising: a first step of forming a solder bump on an electrode pad of a semiconductor device; and a step of surrounding a side surface of the solder bump. Achieved by including a second step of filling the surface of the semiconductor device on the electrode pad side with a sealing resin, and a third step of performing a thinning process on the back surface of the semiconductor substrate constituting the semiconductor device. Is done.

According to the above configuration, after the periphery of the root portion of the solder bump is reinforced by filling with the sealing resin,
The thickness of a semiconductor substrate included in a semiconductor device is reduced. Therefore, the thermal stress is reduced by filling the sealing resin, and even if the semiconductor substrate is thinned in the third stage, the mechanical strength is increased by the sealing resin, so that the semiconductor substrate is broken. It is easy to handle. Accordingly, when manufacturing a semiconductor device on the surface of a semiconductor substrate, various processes are performed on a relatively thick semiconductor substrate, and the thinned semiconductor substrate is reinforced by a sealing resin, so that the semiconductor substrate is easily reinforced. It will not be broken. In addition, when the thickness is reduced, the deformation of the solder bump due to the contact between the solder bump and the outside and the conduction failure of the joint do not occur, and the yield of the semiconductor device is improved. With the increase in the diameter of the semiconductor substrate, the productivity of the thin semiconductor device is further improved. This is extremely advantageous for manufacturing a semiconductor device having a high degree of integration, high performance, and high reliability designed based on a fine design rule.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Note that the embodiments described below are preferred specific examples of the present invention,
Although various technically preferable limits are given, the scope of the present invention is not limited to these embodiments unless otherwise specified in the following description.

FIGS. 1 to 5 show a first embodiment of a method of manufacturing a semiconductor device according to the present invention. Here, as shown in FIG. 2A, the semiconductor wafer 10 includes a plurality of flip-chip type semiconductor LSIs 11 arranged side by side. Each of the electrode portions of the flip-chip type semiconductor LSI 11 includes an electrode pad 13 made of an Al—Cu alloy or the like formed on a semiconductor substrate 12 made of silicon or the like by sputtering, etching, or the like. A surface protection film 14 made of a silicon nitride film, polyimide, or the like formed so as to cover the entire surface of
An opening 14a formed in the region of the electrode pad 13 of the surface protective film 14, and a surface formed by sputtering or the like to cover the surface of the electrode pad 13 exposed at the side and bottom of the opening 14a. A metal multilayer film made of Cr, Cu, Au, etc., a so-called BLM film 15;
And a polyimide film 16 formed over the entire surface so as to have an opening 16a in the region of the film 15.

First, in step ST1, a substantially spherical solder made of a high melting point solder is applied to each electrode portion of each semiconductor LSI 11 of the semiconductor wafer 10 having the above-described structure in the same manner as the solder bump 7a shown in FIG. The bump 20 is formed. This solder bump 20 is formed on the polyimide film 16.
Is formed on the BLM film 15 exposed from the opening 16a. The high melting point solder is made of, for example, about 97% of Pb and about 3% of Sn, and has a high melting point and a high elasticity.

Next, in step ST2, as shown in FIG. 2B, a sealing resin 21 such as an epoxy resin is applied to the entire surface of the semiconductor wafer 10 by spin coating or the like, and then substantially cured by curing. The sealing resin 21 is cured by performing a heat treatment at 150 ° C. for about 5 hours. In this case, the thickness of the sealing resin 21 is selected to be approximately the same height as the first solder ball bump 20 or less. This allows the top of the first solder ball bump 20 to protrude from the surface of the sealing resin 21.

Subsequently, in step ST3, FIG.
As shown in (2), a protective tape 22 composed of a tape base material 22a and an adhesive layer 22b is adhered as a protective member over the entire surface of the semiconductor substrate 12 from above the solder bumps 20 and the sealing resin 21. Thereafter, in step ST4, the semiconductor wafer 10 and the semiconductor substrate 12 are changed from the state shown in FIG. 3A to the state shown in FIG. )
The thickness is reduced to the state shown in FIG.

Here, the semiconductor wafer 10 and the semiconductor substrate 12 have a thickness of 200 μm or less by mechanical grinding.
For example, the thickness is reduced to 150 μm. As a result, the flaws 10a unavoidably formed on the back surface of the semiconductor wafer 10 in many processes in the previous process are ground and removed. In this case, since the solder bumps 20 are surrounded by the sealing resin 21 and the entire surface of the semiconductor substrate 11 is covered by the protective tape 22, the solder bumps 20 come into contact with the outside during mechanical grinding, There is no occurrence of deformation failure or conduction failure at the joint.
In FIG. 3, for simplification of the drawing, the semiconductor L
The part of SI11 is omitted.

Next, in step ST5, after the protective tape 22 is removed, in step ST6, FIG.
As shown in FIG. 3, solder balls 23 formed of a eutectic solder film pattern are formed on the tops of the solder bumps 20 by a ball transfer method or the like.
To form Here, the eutectic solder is, for example, 40%
About Pb and about 60% of Sn,
It has a lower melting point of, for example, 200 ° C. or less than the high melting point solder described above.

The solder ball 23 is melted by heat treatment at a temperature in a range where only the eutectic solder melts and the high melting point solder does not melt, for example, 200 ° C. to 250 ° C. The solder bumps 20 are formed in a ball shape and cured.
And joined. As a result, the solder ball bumps 24 having a laminated structure of the solder bumps 20 and the solder balls 23 are formed.
Is formed. Finally, in step ST7, the wafer-like semiconductor substrate 12 is cut out from each of the semiconductor LSIs 11 as individual chip-like semiconductor LSIs 11 by dicing or the like, thereby completing the semiconductor LSIs 11.

Semiconductor LSI manufactured by the above process
11 is mounted on the printed wiring board 30 as described below. That is, as shown in FIG. 5B, each solder ball bump 24 of the flip-chip type semiconductor LSI 11 is opposed to a land 31 made of Cu or the like as a contact portion formed on the printed wiring board 30. Here, the surface of the printed wiring board 30 excluding the lands 31 is covered with the solder resist 32, and the regions of the lands 31 are pre-coated with the eutectic solder film 33.

Then, as shown in FIG. 5C, by bringing the semiconductor LSI 11 closer to the printed wiring board 30, each solder ball bump 24 is brought into contact with the corresponding land 31, and a so-called reflow process is performed. Thus, the eutectic solder film constituting the solder balls 23 and the eutectic solder film 33 pre-coated on the lands 31 of the printed wiring board 30 are melted and joined to each other. As described above, the printed wiring board 3 of the flip-chip type semiconductor LSI 11
0 is completed.

As described above, the sealing resin 21 is filled around the solder bumps 20 before the mechanical grinding for thinning the semiconductor wafer 10 and the semiconductor substrate 12, so that the mechanical strength of the semiconductor substrate 12 is reduced. Will be enhanced. Accordingly, the thinned semiconductor substrate 12 can be easily handled, and the yield of the semiconductor LS111 can be improved. Further, since the solder ball 23 is formed of a eutectic solder film, the wettability between the solder ball 23 and the eutectic solder film 33 pre-coated on the land 31 is good,
Since they are strongly joined by being familiar with each other, they can be reliably soldered.

Furthermore, the solder bump 20 is
The semiconductor substrate 12 and the printed wiring board 3 are fixed and held by the ambient temperature change after mounting.
Even if a thermal stress is generated between the solder resin bumps 0 and 0, the respective solder ball bumps 24 are fixed by the sealing resin 21 and the solder bumps 20 have elasticity. As a result, the solder bumps 20 are elastically deformed, and the thermal stress is reduced. Accordingly, it is possible to prevent the joint portion of the solder ball bump 24 from being broken due to the thermal stress, and it is possible to improve the reliability of the solder ball bump.

As described above, according to the first embodiment,
By reducing the thickness of the semiconductor substrate 12 constituting the semiconductor LSI 11, the thickness of flip-chip mounting can be reduced. This makes it possible to further reduce the size and thickness of portable electronic devices such as an IC card, a mobile phone, and a PDA, for a final product set of various electronic devices using the semiconductor LSI 11.

Here, the mechanical grinding device for performing the mechanical grinding in step ST4 is configured, for example, as shown in FIG. The mechanical grinding device 40 comprises a wafer carrier 41 which is driven to rotate around a vertical axis, and a horizontal upper surface of the wafer carrier 41, that is, the protective tape 22.
Semiconductor wafer 1 placed and fixedly held with
0, the grinding wheel 42 is supported so as to be movable in the horizontal direction and rotatable about the vertical axis.
In such a configuration, the back surface (upper surface) of the semiconductor wafer 10 is mechanically ground by the grindstone 42 moving in the horizontal direction while rotating around the vertical axis. The grinding conditions are, for example, a grinding wheel feed speed of 150 μm /
The grinding wheel rotation speed is 2500 rpm, and the thickness of the semiconductor wafer 10 after grinding is 150 μm (shaving allowance is about 475 μm).

FIGS. 6 to 8 show a second embodiment of the method of manufacturing a semiconductor device according to the present invention. The method of manufacturing the semiconductor device has substantially the same configuration as the method of manufacturing the semiconductor device shown in FIG. 1, and will be described below with reference to the flowchart of FIG. First, in step ST11, FIG.
As shown in FIG. 2A, a solder bump 20 is formed, and in step ST12, a sealing resin 21 is filled as shown in FIG. 2B, and then in step ST13, FIG.
As shown in (1), a protective tape 22 as a protective member is attached to the entire surface of the semiconductor substrate 12.

Next, in step ST14, the back surface of the semiconductor substrate 12 is mechanically ground to
After the thickness of the semiconductor substrate 12 is reduced, the protection tape 22 is removed from the surface of the semiconductor substrate 12 in step ST15. Then, in step ST16, as shown in FIG. 7, the surface of the solder bump 20 protruding from the sealing resin 21 is subjected to a plasma cleaning process. By this plasma cleaning process, the surface of the solder bump 20 is sputter-etched, the components of the sealing resin 21 and the adhesive layer 22b of the protective tape 22 remaining on the surface are removed, and the surface of the solder bump 20 is cleaned. You.

Here, the plasma cleaning process is performed by a discharge plasma of an inert gas, for example, argon gas, using a plasma processing apparatus shown in FIG. 8, for example. The plasma processing apparatus 50 is a so-called triode-type RF plasma processing apparatus having a known configuration, and includes a closed plasma processing chamber 51, an anode plate 52 provided at an upper part in the plasma processing chamber 51, and a lower part provided at a lower part. A stage 53 as a cathode plate, a grid electrode 54 provided between the anode plate 52 and the stage 53, a plasma generation power source 56 connected to the anode plate 52 via a coupling capacitor 55, and a stage 53. And a substrate bias power supply 58 connected via a coupling capacitor 57.

According to the plasma processing apparatus 50 having such a configuration, the semiconductor wafer 10 as a substrate to be processed is mounted on the stage 53, and the substrate is processed in a state in which, for example, argon gas is introduced as an inert gas. A bias voltage is applied between the stage 53 and the grid electrode 54 by the bias power source 58, and a plasma source power is applied between the anode plate 52 and the grid electrode 54 by the plasma generation power source 56. As a result, a discharge plasma 59 of argon gas is generated between the anode plate 52 and the grid electrode 54, and argon ions Ar ⁺ fly out of the anode plate 52 toward the grid electrode 54, pass through the grid electrode 54 and pass through the stage 52. It collides with the upper semiconductor wafer 10. Therefore, the surface of the semiconductor wafer 10, that is, the resin 21
The surface of the solder bump 20 and the projecting surface of the solder bump 20 are etched, and the components of the sealing resin 21 and the adhesive layer 22b of the protective tape 22 remaining on the surface of the solder bump 20 are removed.

In this case, the operating conditions of the plasma processing apparatus 50 are set as follows, for example. Argon gas flow rate 25 sccm Pressure 1.0 Pa Stage 53 temperature Room temperature Plasma source power 700 W (2 MHz) Substrate bias voltage 350 V (13.56 MHz) Processing time 120 seconds Under such operating conditions, the plasma cleaning of the semiconductor wafer 10 is performed. As a result, the sealing resin 21 remaining on the surface of the first solder ball bump 20 was effectively removed by the sputtering action of Ar ⁺ ions, and the surface of the first solder ball bump 20 was cleaned.

Thereafter, in step ST17, solder balls 23 made of eutectic solder are formed on the tops of the solder bumps 20 by a ball transfer method or the like. In step ST18, the semiconductor substrate 12 in the form of a wafer is divided into individual semiconductor chips. The LSI 11 is cut out by dicing to complete the semiconductor LSI 11. The semiconductor LSI 11 manufactured by the above steps is mounted on the printed wiring board 30 as described below. That is, FIG.
As shown in (1), each solder ball bump 24 of the flip-chip type semiconductor LSI 11 is opposed to a land 31 made of Cu or the like as a contact portion formed on the printed wiring board 30.

Here, the land 3 of the printed wiring board 30
The surface except 1 is covered with a solder resist 32, and the region of the land 31 is pre-coated with a eutectic solder film 33. Then, as shown in FIG. 5C, by bringing the semiconductor LSI 11 closer to the printed wiring board 30, each solder ball bump 24 comes into contact with the corresponding land 31, and the solder balls 23 are so-called reflowed. And the eutectic solder film 33 pre-coated on the lands 31 of the printed wiring board 30 are melted and joined together. As described above, the flip-chip mounting of the flip-chip type semiconductor LSI 11 on the printed wiring board 30 is completed.

In this case, as in the first embodiment shown in FIGS. 1 to 5, the semiconductor wafer 10 and the semiconductor substrate 1
2 before the mechanical grinding for thinning,
Is filled with the sealing resin 21 so that the semiconductor substrate 1
The mechanical strength of No. 2 will be increased. Accordingly, the thinned semiconductor substrate 12 can be easily handled, and the yield of the semiconductor LS111 can be improved. In addition, since the solder balls 23 are made of a eutectic solder film, the solder balls 23 and the eutectic solder film 33 pre-coated on the lands 31 have good wettability, and are strongly bonded to each other by being familiar with each other. , And can be reliably soldered.

Furthermore, the solder bump 20 is
The semiconductor substrate 12 and the printed wiring board 3 are fixed and held by the ambient temperature change after mounting.
Even if a thermal stress is generated between the solder resin bumps 0 and 0, the respective solder ball bumps 24 are fixed by the sealing resin 21 and the solder bumps 20 have elasticity. As a result, the solder bumps 20 are elastically deformed, and the thermal stress is reduced. Accordingly, it is possible to prevent the joint portion of the solder ball bump 24 from being broken due to the thermal stress, and it is possible to improve the reliability of the solder ball bump.

Since the tops of the solder bumps 20 are cleaned by plasma cleaning, the sealing resin 21 and the protection tape 2 remaining on the tops of the solder bumps 20 are removed.
The components of the second adhesive layer 22b are completely removed. Then, since the solder balls 23 are formed on the clean surface, the connection resistance at the interface between the solder bumps 20 and the solder balls 23 is reduced, and the solder bumps 24 having lower resistance and higher performance are formed. Can be configured.
As described above, according to the second embodiment, the semiconductor LSI
Reliability and durability in flip-chip mounting of the eleventh printed circuit board 30 are further improved as compared with the first embodiment.

FIGS. 9 and 10 show a third embodiment of the method of manufacturing a semiconductor device according to the present invention. The method of manufacturing the semiconductor device has substantially the same configuration as the method of manufacturing the semiconductor device shown in FIG. 1, and will be described below with reference to the flowchart of FIG. First, in step ST21, FIG.
As shown in FIG. 2A, a solder bump 20 is formed, and in step ST22, a sealing resin 21 is filled as shown in FIG. 2B. Next, in step ST23, the semiconductor wafer 10 and the semiconductor substrate 12 are changed from the state shown in FIG. 3A to the state shown in FIG. The thickness is reduced to the state shown in FIG.

Semiconductor wafer 10 and semiconductor substrate 12
Is thinned by the above etching process until the thickness becomes 200 μm or less, for example, 150 μm. As a result, the flaws 10a inevitably formed on the back surface of the semiconductor wafer 10 in a large number of processes in the previous step are removed by etching. Here, the etching process
For example, using a spin etching apparatus shown in FIG.
For example, it is performed by a mixed solution of hydrofluoric acid and nitric acid. The spin etching apparatus 60 includes a wafer carrier 62 driven to rotate in a process chamber 61, a supply pipe 63 for introducing a chemical solution into the process chamber 61, and an air supply pipe 64 for introducing air (nitrogen) into the process chamber 61. And a discharge pipe 65 for discharging a chemical solution from the process chamber 61, and an exhaust pipe 66 for discharging air from the process chamber 61.

The spin etching apparatus 6 having such a configuration
0, the semiconductor wafer 10 on the wafer carrier 62
Is placed upside down, and in a state where the wafer carrier 62 is rotationally driven, a mixed solution of hydrofluoric acid, nitric acid and water is introduced into the process chamber 51 through the supply pipe 63 as a chemical, and the air supply pipe 64 is connected. Air is introduced through. As a result, the chemical solution having the above-described structure adheres to the back surface, which is the upper surface of the semiconductor wafer 10, and the chemical solution is scattered from the semiconductor wafer 10 by centrifugal force due to the rotation of the semiconductor wafer 10, so that the back surface of the semiconductor wafer 10 becomes uniform. It will be etched.

In this case, the spin etching device 60
Are set, for example, as follows. Wafer carrier rotation speed 2000 rpm Chemical composition HF: HNO ₃ : H ₂ O = 1: 1: 8 Approx. Liquid supply amount 40 l / min Wafer thickness after processing 150 μm (etching allowance 475 μm) Under these operating conditions, semiconductor wafer 10 Was performed, the scratches 10a unavoidably formed on the back surface of the semiconductor wafer 10 were removed by many processes in the previous process, and the semiconductor wafer 10 was thinned.

Thereafter, in step ST24, as shown in FIG. 7, the surface of the solder bump 20 protruding from the sealing resin 21 is subjected to plasma cleaning using an argon gas and a hydrofluoric acid gas using a plasma processing apparatus 50. . Thereby, the surface of the solder bump 20 is sputter-etched, the components of the sealing resin 21 remaining on the surface are removed, and the surface of the solder bump 20 is cleaned.

In this case, the operating conditions of the plasma processing apparatus 50 are set as follows, for example. Flow rate of HF gas 10 sccm Flow rate of argon gas 25 sccm Pressure 1.0 Pa Temperature of stage 53 Room temperature Plasma source power 700 W (2 MHz) Substrate bias voltage 350 V (13.56 MHz) Processing time 120 seconds

The plasma cleaning of the semiconductor wafer 10 was performed under these operating conditions.
In addition to the sputtering action of r ⁺ ions, the reduction action by HF removes the natural oxide film and the deposits adhering to the surface of the solder bump 20 more effectively with the chemical reaction, and the surface of the solder bump 20 becomes more effective. It was further cleaned. Subsequently, in step ST25, a solder ball 23 made of eutectic solder is formed on the top of the solder bump 20 by a ball transfer method or the like, and in step ST26, the wafer-like semiconductor substrate 12 is separated into individual chip-like semiconductor LSs.
I11 is cut out by dicing to obtain a semiconductor L
Complete SI11.

Semiconductor LSI manufactured by the above steps
11 is mounted on the printed wiring board 30 as described below. That is, as shown in FIG. 5B, each solder ball bump 24 of the flip-chip type semiconductor LSI 11 is opposed to a land 31 made of Cu or the like as a contact portion formed on the printed wiring board 30. Here, the surface of the printed wiring board 30 excluding the lands 31 is covered with the solder resist 32, and the regions of the lands 31 are pre-coated with the eutectic solder film 33.

Then, as shown in FIG. 5C, by bringing the semiconductor LSI 11 closer to the printed wiring board 30, each solder ball bump 24 comes into contact with the corresponding land 31, so-called reflow. Eutectic solder film constituting solder ball 23 and eutectic solder film 3 pre-coated on land 31 of printed wiring board 30
3 are melted and joined together. As described above, the printed wiring board 30 of the flip-chip type semiconductor LSI 11
Is completed.

In this case, as in the first and second embodiments, the solder bumps 20 are formed before the semiconductor wafer 10 and the semiconductor substrate 12 are thinned by etching.
Is filled with the sealing resin 21 so that the semiconductor substrate 1
The mechanical strength of No. 2 will be increased. Accordingly, the thinned semiconductor substrate 12 can be easily handled, and the yield of the semiconductor LS111 can be improved. In addition, since the solder balls 23 are made of a eutectic solder film, the solder balls 23 and the eutectic solder film 33 pre-coated on the lands 31 have good wettability, and are strongly bonded to each other by being familiar with each other. , And can be reliably soldered.

Further, the solder bumps 20 are made of a sealing resin 21.
The semiconductor substrate 12 and the printed wiring board 3 are fixed and held by the ambient temperature change after mounting.
Even if a thermal stress is generated between the solder resin bumps 0 and 0, the solder resin bumps 24 are fixed by the sealing resin 21 and the solder bumps 20 have elasticity. As a result, the solder bumps 20 are elastically deformed, and the thermal stress is reduced. Accordingly, it is possible to prevent the joint portion of the solder ball bump 24 from being broken due to the thermal stress, and to improve the reliability of the solder ball bump.

Since the top of the solder bump 20 is cleaned by a plasma cleaning process using an inert gas such as argon gas and HF gas as a reducing gas, the sealing resin 21 remaining on the top of the solder bump 20 and the protective resin 21 are protected. The components of the adhesive layer 22b of the tape 22 are more completely removed. Then, since the solder balls 23 are formed on the clean surface, the connection resistance at the interface between the solder bumps 20 and the solder balls 23 is reduced, and the solder bumps 24 having lower resistance and higher performance are formed. Can be configured. As described above, according to the third embodiment, the reliability and durability in flip-chip mounting of the semiconductor LSI 11 on the printed wiring board 30 are further improved as compared with the first and second embodiments. Will be.

In the above embodiment, the solder bump 2
0 is formed by film formation using a vacuum evaporation film and lift-off of a photoresist, but is not limited thereto, and may be formed by another method using electrolytic plating or the like. In order to reduce the thickness of the semiconductor wafer 10, mechanical grinding by the mechanical grinding device 40 or etching using a chemical solution by the spin etching device 60 is performed, but not limited thereto. For example, chemical mechanical polishing or dry etching. Processing or the like may be performed.

Further, the solder balls 23 are formed by the ball transfer method, but are not limited thereto, and may be formed by not only another printing method and transfer method but also another method such as a plating method. . Further, the case where the solder ball bumps 24 are formed on the electrode pads of the semiconductor LSI 11 has been described. However, the present invention is not limited to this, and the present invention can be applied to electrode pads of other semiconductor devices. Further, the solder ball bump 24 has a laminated structure of the solder bump 20 and the solder ball 23,
However, the present invention is not limited thereto, and the solder bump 20 alone may be used.

Further, as a semiconductor device, a semiconductor LSI 11
Has been described, but the present invention is not limited to this, and the present invention can be applied to a method of manufacturing another semiconductor device such as a semiconductor IC. Further, in the third embodiment, the HF gas is used as the reducing gas. However, the present invention is not limited to this. For example, H ₂ , HCl, or the like may be used. In this case, in the case of a liquid source such as HF or HCl, the liquid source is introduced into the process chamber 61 by a technique such as bubbling with a carrier gas such as He, vaporization by heating or ultrasonic vaporization.

[0055]

As described above, according to the present invention, the semiconductor device can be made thinner and the heat between the semiconductor device and the printed wiring board can be reduced without using a sealing resin. The stress can be surely alleviated, the strength of the joint can be increased, and the connection reliability in flip chip mounting can be increased.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a first embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a schematic sectional view sequentially showing steps up to the attachment of a protective tape in the manufacturing method of FIG. 1;

FIG. 3 is a schematic cross-sectional view of the semiconductor substrate showing states before and after a mechanical grinding step in the manufacturing method of FIG. 1;

FIG. 4 is a schematic perspective view showing a configuration of an example of a mechanical grinding device used in the mechanical grinding step of FIG.

FIG. 5 is a schematic perspective view showing a solder ball forming step in the manufacturing method of FIG. 1 and a state before and after mounting.

FIG. 6 is a flowchart showing a second embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 7 is a schematic sectional view showing a plasma cleaning step in the manufacturing method of FIG. 6;

FIG. 8 is a schematic diagram illustrating a configuration of an example of a plasma processing apparatus used in the plasma cleaning step of FIG. 7;

FIG. 9 is a flowchart showing a third embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 10 is a schematic diagram showing a configuration of an example of a spin etching apparatus used in an etching step in the manufacturing method of FIG. 9;

FIG. 11 is a schematic sectional view sequentially showing steps in an example of a conventional method for manufacturing a semiconductor device.

FIG. 12 is a schematic cross-sectional view showing a state in which a flip-chip type semiconductor LSI manufactured by the method for manufacturing the semiconductor device in FIG. 4 is mounted on a printed wiring board.

[Explanation of symbols]

10: semiconductor wafer, 11: semiconductor LSI, 1
2 ... semiconductor substrate, 13 ... electrode pad, 14 ...
・ Surface protection film, 15 ・ ・ ・ BLM film, 16 ・ ・ ・ Polyimide film, 20 ・ ・ ・ Solder bump (high melting point solder), 2
DESCRIPTION OF SYMBOLS 1 ... Sealing resin, 22 ... Protective tape (protective member), 22a ... Tape base material, 22b ... Adhesive layer, 23 ... Solder ball (eutectic solder), 24 ...
・ Solder bump, 30 ・ ・ ・ Printed wiring board, 31 ・
··· Land, 32: solder resist, 33: eutectic solder film, 40: mechanical grinding device, 41: wafer carrier, 42: grinding stone, 50: plasma processing device, 51 ... plasma processing chamber, 52 ... anode plate,
53: stage, 54: grid electrode, 55, 57
... Coupling capacitor, 56 ... Plasma generation power supply,
58: substrate bias power supply, 60: spin etching apparatus, 61: process chamber, 62: wafer carrier, 63: supply pipe, 64: air supply pipe, 65
..Drain pipes, 66 ... Exhaust pipes

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/304 645 H01L 21/302 M 21/306 21/306 B 21/56 21/92 602K 604H

Claims (10)

[Claims] A first step of forming a solder bump on an electrode pad of the semiconductor device; and filling a sealing resin on a surface of the semiconductor device on an electrode pad side so as to surround a side surface of the solder bump. A method of manufacturing a semiconductor device, comprising: a second step; and a third step of performing a thinning process on a back surface of a semiconductor substrate constituting the semiconductor device. 2. The thinning process in the third step,
The method according to claim 1, wherein the method is performed so that the thickness of the semiconductor substrate is 200 μm or less. 3. The thinning process in the third stage,
2. The method according to claim 1, wherein the method is performed by mechanical grinding or chemical mechanical polishing. 4. The thinning process in the third stage,
2. The method according to claim 1, wherein the method is performed by etching. 5. The semiconductor device according to claim 3, wherein the entire surface of the semiconductor device is covered with a protective member so as to cover the solder bumps and the sealing resin before the thinning in the third step. 2. The method according to claim 1, wherein the protection member is removed. 6. The semiconductor according to claim 1, further comprising a fourth step of cleaning the surface of the solder bump protruding from the surface of the sealing resin after the thinning in the third step. Device manufacturing method. 7. The method according to claim 6, wherein the cleaning in the fourth step is performed by a plasma cleaning process. 8. The method according to claim 7, wherein the plasma cleaning process is a sputter etching process using at least an inert gas discharge plasma. 9. The method according to claim 7, wherein the plasma cleaning process is a sputter etching process using at least a discharge plasma of a reducing gas. 10. The method according to claim 1, wherein at least each of the steps up to the third step is performed on a semiconductor device formed on a semiconductor substrate in a state of a semiconductor wafer.