JP2007068052A - Phase determining apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a phase determining apparatus for correctly determining a phase of a known signal even when the effect of white thermal noises or the like is great. <P>SOLUTION: The phase determining apparatus 100 includes: a reception section 10; a partial signal acquisition section 20; a phase correction section 30; and a buffer 40. The reception section 10 receives a signal sequence to which a known signal is periodically inserted and provides an output to the partial signal acquisition section 20. The partial signal acquisition section 20 acquires a prescribed partial signal and partial signals before and after the prescribed partial signal from the signal sequence received by the reception section 10, and writes the acquired signals to the buffer 40. The phase correction section 30 executes the correction of the phase of the prescribed partial signal written in the buffer 40 on the opportunity of receiving a write end notice informed from the partial signal acquisition section 20. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a signal processing technique, and more particularly to a phase determination device that determines the phase of a radio signal.

In a wireless communication system, a frequency offset occurs due to instability of a signal oscillated from a crystal or the like used in a transmission device and a reception device. In order to reduce the influence of the generated frequency offset, the phase error of the known signal included in the transmitted signal is determined, and the phase of the signal is shifted by the determined phase error. However, a continuous error generally occurs in a radio signal including a known signal due to a fading phenomenon in the transmission path. Due to this influence, the phase of the known signal may not be correctly determined. In such a case, a signal whose frequency offset is corrected based on the phase of the known signal cannot be demodulated. Conventionally, in order to remove a continuous error of a known signal, the error is distributed by interleaving the known signal (see, for example, Patent Document 1). In addition, in order to determine an error in a known signal, the phase is determined using a value obtained by making a hard decision on the known signal or code information of the known signal (see, for example, Patent Document 2).
JP 2002-111756 A (FIG. 1) JP-A-6-276239 (FIG. 1)

  Under such circumstances, the present inventor has come to recognize the following problems. In other words, when a terminal receives a signal with very low received power as in a satellite communication system, the influence of white heat noise generated at the terminal becomes large, and the phase of the known signal can be determined correctly. It is a problem that cannot be done.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a phase determination device that correctly determines the phase of a known signal even when the influence of white thermal noise or the like is large.

  In order to solve the above-described problem, a phase determining apparatus according to an aspect of the present invention includes a receiving unit that periodically receives a signal sequence in which a known signal is inserted, and a plurality of signals included in the signal sequence received by the receiving unit. A partial signal acquisition unit that sequentially acquires a plurality of partial signals each corresponding to a known signal, and a known signal rule that should correspond to each of the partial signals acquired by the partial signal acquisition unit Accordingly, a phase correction unit that performs phase correction on the predetermined partial signal by comparing the predetermined partial signal with the partial signals before and after the predetermined partial signal is provided.

  Here, “a plurality of partial signals to be respectively associated with known signals” includes a portion corresponding to a known signal in a signal series received through a radio channel. In other words, the partial signal is a known signal at the time of reception. The value obtained by hard-decision of the partial signal is a flag indicating whether or not phase correction is performed on the partial signal itself or a data signal subsequent to the partial signal. The “front and rear partial signals” may be not only one partial intelligence signal before and after but also two or more partial signals. The “known signal” includes a signal arranged according to a predetermined rule. The “known signal rule” includes a predetermined known signal arrangement rule. “According to the known signal rule” includes calculating the correlation between the partial signal and the known signal rule corresponding to the partial signal, and using the difference between the two. “Phase correction” includes rotating the phase and the like, and also inverting the sign.

  According to this aspect, it can be determined that a burst error has occurred in a known signal different from the previous and subsequent known signals. Therefore, by correcting the phase, it is possible to reduce the random or burst error in the portion corresponding to the known signal. it can. Further, the performance can be improved by correcting the burst error. Further, it is possible to reduce erroneous correction when a random error occurs in a partial signal.

  Another aspect of the present invention is also a phase determination device. The apparatus includes: a reception unit that receives a signal sequence in which the same known signal is periodically inserted; a partial signal acquisition unit that sequentially acquires a plurality of partial signals from the signal sequence received by the reception unit; A phase correction unit that corrects the predetermined partial signal when the predetermined partial signal is different from the partial signals before and after the acquired partial signal.

  Here, the “front and rear partial signals” may include not only one front and rear partial signal but also two or more partial signals. In addition, “when the predetermined partial signal is different from the preceding and following partial signals” means, for example, when all known signals included in the signal sequence are composed of the same symbol and the phase correction direction is different. including. That is, when a predetermined partial signal is different from the corresponding known signal and either one of the partial signals before and after the predetermined partial signal is different from the corresponding known signal, the predetermined partial signal Is inverted. In other words, if both of the partial signals before and after the predetermined partial signal match the corresponding known signals, even if the predetermined partial signal is different from the corresponding known signal, The known signal is not inverted. “Different” includes the case where the codes of the partial signals do not match. Also, for example, when the known signals included in the signal sequence are composed of different symbols having a certain rule, “when the predetermined partial signal is different from the preceding and succeeding partial signals” refers to the preceding and following partial signals and those This includes a case where the known signal corresponding to is the same and the predetermined partial signal is different from the known signal corresponding thereto. “Perform correction on a predetermined partial signal” means to invert a flag indicating whether or not to perform phase correction on a partial signal itself or a data signal subsequent to the partial signal. Including.

  According to this aspect, it can be determined that a burst error has occurred in a partial signal different from the preceding and succeeding partial signals, and therefore the random or burst error of the partial signal can be reduced by correcting the phase thereof. Further, the performance can be improved by correcting the burst error. Further, it is possible to reduce erroneous correction when a random error occurs in a partial signal.

  The partial signal acquisition unit may include a reliability acquisition unit that acquires the reliability of each partial signal. The phase correction unit may perform correction on the predetermined partial signal by comparing the reliability of the predetermined partial signal with the reliability of the partial signals before and after the predetermined partial signal.

  Here, “partial signal reliability” refers to the likelihood of a partial signal, and includes, for example, the likelihood of a partial signal, a soft decision value, etc., that is, a reception error of a known signal. According to this aspect, since the error determination is performed using the reliability of the partial signal, the determination accuracy can be improved. Further, when the reliability of the predetermined partial signal and the reliability of the partial signals before and after the predetermined partial signal are both equal to or higher than the threshold value, the flag related to the predetermined partial signal is corrected.

  The phase correction unit is a case where the absolute values of the two reliability levels before and after the predetermined partial signal acquired by the partial signal acquisition unit are both larger than the first threshold value, and the reliability of the predetermined partial signal is If the absolute value is greater than a second threshold value that is less than or equal to the first threshold value, a predetermined partial signal modification may be performed. Further, the flag related to the predetermined partial signal may be corrected only on the condition that “the absolute value of the reliability of the predetermined partial signal is larger than the second threshold value”. The flag modified when “the predetermined partial signal is different from the preceding and following partial signals” is further modified when “the absolute value of the reliability of the predetermined partial signal is greater than the second threshold value”. . That is, the flag that should not have been corrected is the same as when the flag related to the predetermined partial signal is not corrected.

  Here, the “first threshold value” and the “second threshold value” are criteria for determining the reliability of the partial signal, and include that both are the same value. According to this aspect, since the error is determined using the threshold value, the determination accuracy can be improved.

  The signal sequence received by the reception unit includes a plurality of data signals before and after each partial signal, and the phase correction unit is a data signal subsequent to the predetermined partial signal, Phase correction may be performed on a data signal existing before a subsequent partial signal together with a predetermined partial signal.

  According to this aspect, since the phase of the data signal at the subsequent stage is also corrected together with the partial signal that is considered to have a random or burst error, the correction capability in error correction can be improved. Further, the performance can be improved by correcting the burst error. Further, it is possible to reduce erroneous correction when a random error occurs in a partial signal.

  Each of the plurality of partial signals included in the signal sequence received by the receiving unit is composed of a plurality of symbols, and the partial signal acquisition unit adds the reliability of the plurality of symbols included in the partial signals, respectively, You may acquire the reliability of a partial signal.

  According to this aspect, since the reliability that is the source of error determination is acquired using the value obtained by adding the reliability of a plurality of symbols, the determination accuracy can be improved.

  It should be noted that any combination of the above-described constituent elements and a conversion of the expression of the present invention between a method, an apparatus, a system, a recording medium, a computer program, etc. are also effective as an aspect of the present invention.

  According to the present invention, the phase of a known signal can be correctly determined even when the influence of fading, white thermal noise, or the like is large.

(Example)
An outline of the present invention will be given before a specific description of embodiments of the present invention. An embodiment of the present invention relates to a receiving apparatus that receives a low CN (Carrier Noise ratio) radio signal, such as an Inmarsat satellite communication system. The receiving apparatus according to the present embodiment uses a known signal periodically inserted into the radio signal in order to determine the phase of the received radio signal. In general, the number of known signals included in a radio signal is very small compared to a data signal. If this small number of known signals are received in error, many data signals that are demodulated based on the known signals will also be erroneous at the same time, and reception performance will deteriorate rapidly. Therefore, it is important to accurately determine an error of a known signal. In this embodiment, the known signals before and after the known signal are used to determine the phase of the known signal and reduce errors. In this embodiment, in order to simplify the description, it is assumed that the modulation method of the radio signal is BPSK (Binary Phase Shift Keying). Further, it is assumed that all known signals included in the signal sequence are composed of the same symbol. Details will be described later.

  FIG. 1 is a diagram illustrating a configuration example of a receiving device 200 according to an embodiment of the present invention. The receiving device 200 includes an antenna 1, an RF unit 2, a high frequency unit 3, an analog / digital (A / D) conversion unit 4, a signal processing unit 5, a phase determination device 100, and a decoding unit 6. Including. The antenna 1 receives a signal sequence transmitted from a partner that is performing communication. The RF unit 2 performs a process of converting the signal sequence received by the antenna 1 into an intermediate frequency band signal using a filter or the like. The high frequency unit 3 performs frequency conversion processing from the intermediate frequency band to the baseband band on the signal sequence processed by the RF unit 2. The A / D conversion unit 4 converts the signal sequence frequency-converted to the baseband into a digital signal. The signal processing unit 5 performs processing such as automatic gain control processing, DC offset correction, phase estimation, carrier reproduction, and frame synchronization on the signal sequence converted into a digital signal by the A / D conversion unit 4. The phase determination device 100 determines the presence / absence of an error in the signal sequence processed by the signal processing unit 5, performs phase correction, and determines the phase. The decoding unit 6 performs error correction decoding processing such as deinterleaving processing and Viterbi decoding on the signal sequence whose phase is determined by the phase determination device 100.

  FIG. 2 is a diagram illustrating a configuration example of the phase determination device 100 of FIG. The phase determination device 100 includes a reception unit 10, a partial signal acquisition unit 20, a phase correction unit 30, and a buffer 40. The receiving unit 10 receives a signal sequence in which known signals are periodically inserted, and outputs the signal sequence to the partial signal acquisition unit 20. The known signal inserted periodically may be composed of a plurality of symbols, or may be composed of only one symbol.

  The signal series processed by the phase determination apparatus 100 has a configuration as shown in FIG. FIG. 3 is a diagram illustrating a configuration example of a signal sequence received by the phase determination apparatus 100 in FIG. The horizontal axis represents time. The receiving unit 10 receives the reception signal shown in FIG. 3, that is, the signal sequence. This signal series includes a known signal 52 and a data signal 54. The known signal 52 is inserted into the signal series for each period L. FIG. 3 shows a case where one known signal 52 is composed of a plurality of symbols, but is not limited to this, and may be composed of one symbol. Note that the number of symbols included in the known signal 52 and the data signal 54 is L. A signal sequence composed of an integral multiple of L is expressed as a frame.

  Further, the known signal 52 received by the receiving unit 10 is generally different from the transmitted known signal due to a continuous error occurring in the transmission path, noise generated in the receiving apparatus 200, or the like. Therefore, in the following description, “known signal 52” will be described as “partial signal corresponding to known signal 52” or simply “partial signal”.

  Returning to FIG. The partial signal acquisition unit 20 acquires a predetermined partial signal and partial signals before and after the predetermined partial signal from the signal sequence received by the receiving unit 10. Specifically, partial signals are acquired over one frame and written to the buffer 40. A data signal may be written into the buffer 40 together with the partial signal. The partial signal acquisition unit 20 writes all the partial signals to the buffer 40 and then notifies the phase correction unit 30 that the writing has been completed.

  In response to the write completion notification notified from the partial signal acquisition unit 20, the phase correction unit 30 corrects the “flag” related to the predetermined partial signal written in the buffer 40 and the phase of the predetermined partial signal itself. Perform correction. Specifically, it is determined whether or not the predetermined partial signal is different from the preceding and following partial signals. In the determination, the buffer 40 may be used as a temporary memory. A “flag” indicating whether or not to correct the phase is stored in the buffer 40. Note that the flag before being corrected is a value obtained by hard-decision of the partial signal. If the predetermined partial signal is different from the preceding and succeeding partial signals, the flag relating to the predetermined partial signal is corrected. Note that the phase of the partial signal itself or the data signal subsequent to the partial signal may be corrected based on the flag or the modified flag. Details will be described later. The predetermined partial signal includes any of the partial signals acquired by the partial signal acquisition unit 20. For example, it may be the first partial signal in one frame or a partial signal existing in the middle. In this embodiment, since the radio signal modulation scheme is BPSK, the symbols included in the signal sequence are expressed as “+1” or “−1” when there is no error. Therefore, “performing the phase correction of the predetermined partial signal” includes inverting the sign.

  Further, “when the predetermined partial signal is different from the preceding and succeeding partial signals” means that the direction of the phase correction is different, for example, the signs of the preceding and following partial signals match, and The case where the code | symbol of a predetermined partial signal does not correspond is included. In this embodiment, all known signals are assumed to be the same symbol, for example, 0. Therefore, all partial signals corresponding to the known signal can be discriminated to some extent by determining the sign.

  The buffer 40 is a memory space in which a partial signal acquired by the partial signal acquisition unit 20 is written. The buffer 40 is also used as a temporary memory when the phase correction unit 30 determines the phase of the partial signal. The buffer 40 may have a different start address for writing for each target to be written. Further, the buffer 40 may not be configured from a single memory.

  FIG. 4 is a diagram illustrating a configuration example of the partial signal acquisition unit 20 of FIG. The partial signal acquisition unit 20 includes a writing unit 22 and a reliability acquisition unit 24. The writing unit 22 writes the signal series received by the receiving unit 10 in the buffer 40. The buffer 40 is a memory and is also called an interleave buffer.

  The reliability acquisition unit 24 acquires reliability of a predetermined partial signal and partial signals before and after the partial signal corresponding to known signals included in the signal sequence received by the reception unit 10, and stores them in the buffer 40. Write. In other words, the partial signals included in the signal sequence received by the receiving unit 10 are sequentially acquired as “predetermined partial signals”. That is, the reliability acquisition unit 24 acquires the reliability of all partial signals included in the signal sequence received by the reception unit 10. Here, the reliability includes a value indicating the probability of the partial signal, and includes, for example, a soft decision value of the partial signal, a value indicating a correlation between the partial signal and the known signal, and the like. When one partial signal is composed of a plurality of symbols, the reliability of the partial signal may be acquired by adding the reliability of the plurality of symbols included in the partial signal.

  Here, the buffer 40 into which the reliability obtaining unit 24 writes a partial signal or the like has a configuration as shown in FIG. FIG. 5 is a diagram illustrating a configuration example of the buffer 40 of FIG. When the partial signal acquisition unit 20 writes a signal series in the buffer 40, the partial signal acquisition unit 20 writes the signal sequence from the upper left of the buffer 40 to the right. The partial signal acquisition unit 20 writes to the next line in the same manner after writing to the end of a certain line of the buffer 40. By setting the size of one row of the buffer 40 to the same L as the known signal insertion period in the signal sequence, the known signals 52 can be positioned in the same column as shown in FIG. In FIG. 5, since it is assumed that the frame is synchronized, the partial signal corresponding to the known signal appears at the head of the column. When frame synchronization is not achieved, the partial signal does not exist in the first column as shown in FIG. 5, but does not change in that it is located in the same column.

  Here, in order to simplify the description, the configuration example of the buffer 40 in FIG. 2 has been described as being two-dimensionally arranged, but the actual buffer 40 may have a one-dimensional configuration. . Each row may be stored in a physically separated memory as long as each row is associated with a pointer or the like.

  FIG. 6 is a diagram illustrating a configuration example of the phase correction unit 30 of FIG. The phase correction unit 30 includes a determination unit 32 and a correction processing unit 34. The determination unit 32 determines whether an error is included in the partial signal corresponding to the known signal written in the buffer 40. The determination is made sequentially for all partial signals. Specifically, among a plurality of partial signals, a certain partial signal is defined as a predetermined partial signal, the reliability codes of the partial signals before and after the predetermined partial signal are the same code, and the code and the predetermined signal When the sign of the reliability of the partial signal is different, it is determined that the flag should be corrected. After the determination is completed for all the partial signals, the phase correction unit 30 notifies the correction processing unit 34 to that effect.

  The correction processing unit 34 corrects the flag determined to be corrected after the determination in the phase correction unit 30 is completed. Thereafter, phase correction processing is performed on the corresponding partial signal in accordance with the flag. Specifically, when the flag indicates that the phase correction should be executed (for example, 1), the phase correction process is performed on the corresponding partial signal. If the reliability code of the predetermined partial signal and the reliability codes of the partial signals before and after the predetermined partial signal are different from each other, it is highly possible that the predetermined partial signal has a locally generated error. Conceivable. Therefore, in such a case, since the flag should not be determined according to the partial signal, correction of the flag related to the predetermined partial signal is executed according to the preceding and following partial signals. Here, the correction of the flag includes reversing the sign. Further, executing the phase correction includes inverting so that the sign of the known signal whose phase is to be inverted is the same as the sign of the known signal before and after that when the modulation scheme of the signal sequence is BPSK. When the signal sequence received by the receiving unit 10 includes a plurality of data signals before and after each known signal, the correction processing unit 34 is a data signal subsequent to the predetermined partial signal. The phase correction may be executed together with the predetermined partial signal for the data signal existing before the partial signal subsequent to the predetermined partial signal.

  7A to 7C are diagrams showing examples of arrangement of partial signals and the like stored in the buffer 40 of FIG. 7A to 7C show different address areas of the buffer 40, respectively. FIG. 7A is a diagram illustrating an arrangement example in the buffer 40 of the partial signal written by the partial signal acquisition unit 20 of FIG. Here, it is assumed that all known signals are “0”. Further, an example in which a partial signal, that is, one known signal is composed of two symbols is shown. Each symbol is stored as a soft decision value represented by any value from −7 to +7 as reliability. Further, it is assumed that “−7” is “1” when a hard decision is made, and “0” when “+7” is a hard decision. That is, in a situation where there is no noise, the reliability of all the partial signals is “+7”. As the reliability approaches “± 0”, the probability of the partial signal decreases, and “reliability = 0” has the lowest reliability. In addition, the sum of the number of partial signals corresponding to known signals included in one frame and the number of data signals is assumed to be 6 × L. However, the number of known signals and data signals included in one frame is not limited to this. May be a multiple of L.

  FIG. 7B is a diagram illustrating an arrangement example in the buffer 40 of the reliability of the partial signal written by the reliability acquisition unit 24 of FIG. The reliability obtaining unit 24 adds the soft decision values of the symbols included in each partial signal for each known signal existing in each row, and stores the result in the buffer 40.

  FIG. 7C is a diagram illustrating an arrangement example of the flag indicating the determination result of the partial signal written by the determination unit 32 in FIG. 2 in the buffer 40. Here, “0” in FIG. 7C is a flag indicating that the known signal corresponding to the row is not inverted. “1” is a flag indicating that the known signal corresponding to the row is inverted. In accordance with this flag, the correction processing unit 34 in FIG. 4 performs phase correction on the partial signal. The correction may be executed not only for the known signal but also for the data signal included in the row.

  Next, an operation example of the phase determination apparatus according to the embodiment of the present invention will be described with reference to FIG. FIG. 8 is a flowchart showing an operation example of the phase determination apparatus 100 of FIG. First, the receiving unit 10 receives a signal sequence in which known signals are periodically inserted as shown in FIG. 3 (S10). Next, the partial signal acquisition unit 20 writes the signal sequence in the buffer 40 in order to acquire the predetermined partial signal and the known signals before and after the predetermined known signal from the signal sequence received by the receiving unit 10 (S12). ). The partial signal acquisition unit 20 calculates the reliability of the symbol included in each partial signal when writing to the buffer 40 and writes the result.

  Next, the partial signal acquisition unit 20 acquires the reliability of each of a plurality of symbols included in the partial signal stored in the buffer 40 and adds them together (S14). Next, using the reliability of the partial signal written in the buffer 40, the phase correction unit 30 determines whether the flag should be corrected line by line. The determination is to be corrected when “a predetermined known signal is different from the preceding and following known signals”, that is, when the phase correction direction is different. This will be described using an example. Here, it is assumed that “ABC” is the result of hard decision on the sum of reliability shown in FIG. B is a hard decision value of the reliability of a predetermined partial signal, that is, a flag. A and C are hard decision values of the reliability of the front and rear partial signals. “ABC” has eight patterns, that is, “000”, “001”, “010”, “011”, “100”, “101”, “110”, and “111”. Among these, “101” and “010” are “the same code as the reliability code of the partial signal before and after the predetermined partial signal, and the code of the reliability of the predetermined partial signal is If it is different, "the flag is corrected. That is, “1” is obtained for “B = 0” of “101”, and “0” is obtained for “B = 1” of “010”. In other words, the flags are not corrected except for these two ways.

  Here, it is determined whether or not the flag should be corrected based on the reliability code of the predetermined partial signal and the reliability codes of the preceding and following partial signals, and whether or not the phase of the corresponding partial signal should be corrected. Is determined (S16). When it is determined that the phase correction should not be performed based on the flag or the corrected flag (N in S16), the phase correction unit 30 sets the correction non-permission flag “0” in the buffer 40 as a line not to be corrected. Remember. On the other hand, when the determination unit 32 determines that the phase should be corrected based on the flag or the corrected flag (Y in S16), the phase correction unit 30 sets the correction permission flag “1” as a line to be corrected. Is stored in the buffer 40. The processing of S16 to S18 is repeatedly executed for each row until the determination is completed for all rows (N in S20, S22).

  When the determination is completed for the known signals of all rows (Y in S20), the phase correction unit 30 performs phase correction on the corresponding partial signals stored in the buffer 40 according to the flags stored in the buffer 40. Correction is executed (S24). The phase correction unit 30 corrects the phase together with the predetermined partial signal with respect to the data signal that is a subsequent data signal of the predetermined partial signal and exists before the partial signal after the predetermined partial signal. May be executed.

  Next, the operation example of the flowchart of FIG. 8 will be described in detail with reference to the arrangement example of the buffer 40 of FIG. 2 shown in FIGS. First, the receiving unit 10 receives a signal sequence in which known signals are periodically inserted as shown in FIG. 3 (S10). Next, the partial signal acquisition unit 20 writes the signal sequence in the buffer 40 in order to acquire a predetermined partial signal and partial signals before and after the predetermined partial signal from the signal sequence received by the receiving unit 10 (S12). ). The partial signal acquisition unit 20 calculates the reliability of the symbol included in each partial signal when writing, and writes the result. Here, it is assumed that data is written in the buffer 40 as in the second configuration example shown in FIG.

  The partial signal acquisition unit 20 acquires the reliability of the partial signal by adding the reliability of the plurality of symbols included in the partial signal, respectively (S14). Specifically, in the arrangement example shown in FIG. 7A, the respective partial signals are sequentially added and written into the buffer 40 as shown in FIG. 7B. That is, for the first line, “9” obtained by adding “5” and “4” is written, and thereafter, the second to sixth lines are calculated in the same manner and sequentially written in the buffer 40. 7 (b) is an example of arrangement.

  Next, the phase correction unit 30 determines whether or not the phase correction should be executed line by line using the reliability of the partial signal written in the buffer 40 as shown in FIG. 7B. Here, since the first row is a predetermined partial signal, the reliability is “9” as shown in FIG. 7B. For the first row, the reliability of the partial signal in the subsequent stage exists as “−4”, but the partial signal in the previous stage does not exist in the same frame. Therefore, the reliability “3” of the last partial signal of the previous frame (not shown) is used as the reliability of the partial signal in the previous stage. Here, when “9” of the predetermined partial signal is hard-decided, it becomes “0”, which matches the corresponding known signal, so that it is determined not to correct the flag. Therefore, since the hard decision value “0” is used as a flag for the first row as it is, it is determined that the phase correction is not performed (N in S16), and as shown in FIG. “0” is written (S17).

  Next, it is determined whether the phase correction should be executed with the partial signal in the second row as a predetermined partial signal (N in S20, S22, and S16). Here, as shown in FIG. 7B, the reliability of the partial signals in the second row is “−4”, and the reliability of the preceding and succeeding partial signals is “9”. Therefore, if they are hard-decided in the column direction, a row of “010” is obtained. However, in this case, since it is determined that the flag should be corrected as described above, the flag is “0”. Therefore, it is determined that the second line is not subjected to phase correction (N in S16), and “0” is written in the second line as shown in FIG. 7C (S17). Similarly, when the hard decision is made in the column direction, the third row is “101”, and in this case as well, it is determined that the flag should be corrected as described above. Accordingly, the correction of the flag “0” is executed, and “1” is written in the third line of FIG. 7C (Y in S16, S18). However, in the third line, the flag may not be corrected by using “001” from the flag after the previous correction. Since the fourth line is “011” and the fifth line is “110”, “1” is written in the fourth and fifth lines in FIG. Y, S18). Since the sixth line is “100”, it is determined that the phase correction is not performed, and “0” is written in the sixth line of FIG. 7C (N in S16, S17). When the partial signal in the sixth row is a predetermined partial signal, the reliability of the first partial signal of the next frame (not shown) is assumed to be “5” as the reliability of the subsequent partial signal.

  When the determination is completed for the partial signals in all rows (Y in S20), the phase correction unit 30 corrects the phases of the corresponding partial signals according to the flags stored in the buffer 40 shown in FIG. Is executed (S24). Specifically, phase correction is performed on the partial signals corresponding to the second and sixth lines, respectively.

  According to the present embodiment, since the phase of the data signal at the subsequent stage is inverted together with the partial signal corresponding to the known signal that is considered to have a burst error, the correction capability in error correction can be improved. Since the burst error is determined using the reliability of the partial signal, the determination accuracy can be improved. Further, since it can be determined that a burst error has occurred in a partial signal different from the preceding and succeeding partial signals, the burst error of the partial signal can be reduced by inverting the phase. In addition, it is possible to cope with repeated phase slips in the demodulator. In addition, since the reliability that is the source of the burst error determination is acquired using the value obtained by adding the reliability of a plurality of symbols, the determination accuracy can be improved. Further, the performance can be improved by correcting the burst error. Further, it is possible to reduce erroneous correction when a random error occurs in a partial signal. Even when the influence of white thermal noise or the like is large, the phase of the partial signal can be determined correctly.

  Next, a modification of the embodiment of the present invention will be shown. A modification of the embodiment of the present invention relates to a receiving device 200 including a phase determination device 100. The difference from the embodiment of the present invention is that a threshold value is used in determining whether to invert the phase of the partial signal. Since the configuration is the same as that of the above-described embodiment, the same reference numerals are used to simplify the description. A receiving apparatus 200 according to a modification of the embodiment of the present invention has an antenna 1, an RF unit 2, a high frequency unit 3, an A / D conversion unit 4, and a signal processing unit 5 similarly to the configuration shown in FIG. And a phase determination device 100 and a decoding unit 6. Similarly to the configuration shown in FIG. 2, the phase determination device 100 includes a reception unit 10, a partial signal acquisition unit 20, a phase correction unit 30, and a buffer 40. Similarly to the configuration shown in FIG. 4, the partial signal acquisition unit 20 includes a writing unit 22 and a reliability acquisition unit 24. Similarly to the configuration shown in FIG. 6, the phase correction unit 30 includes a determination unit 32 and a correction processing unit 34.

  Here, the operation example of the phase determination apparatus according to the modification of the embodiment of the present invention will be described with reference to FIGS. FIG. 9 is a flowchart showing an operation example of the phase determination apparatus according to the modification of the embodiment of the present invention. FIG. 9 is a diagram showing that the process of S26 is performed instead of S16 in the flowchart of FIG. Note that S10 to S24 are the same as those in the flowchart shown in FIG.

  In S <b> 26, the phase correction unit 30 uses the reliability of the partial signal written in the buffer 40 to determine whether or not to correct the flag and to determine whether or not to correct the phase line by line. The determination here is “the absolute value of the reliability before and after the predetermined partial signal is larger than the first threshold value, and the absolute value of the reliability of the predetermined partial signal is larger than the second threshold value. The “case” is a case where the flag is not corrected even if it is determined in S16 in the previous stage that the flag is corrected for the predetermined partial signal. In this case, the absolute value of the reliability of the predetermined partial signal is large, and it can be said that the reliability of the flag is high. As a result, when the corrected flag is “0”, it is determined that the phase is not corrected (N in S26), and the process proceeds to S17. On the other hand, if the corrected flag is “1”, it is determined that the phase is to be corrected (Y in S26), and the process proceeds to S18.

  FIGS. 10A and 10B are diagrams showing an example of the arrangement of flags in the buffer 40 indicating the determination result of partial signals in the buffer 40 according to the modification of the embodiment of the present invention. FIG. 10 (a) corresponds to FIG. 7 (b). FIG. 10B corresponds to FIG. 7C, and shows values written to the buffer 40 by the determination unit 32. Here, the operation example of the phase determination apparatus 100 according to the modification will be specifically described with reference to the arrangement examples illustrated in FIGS. 7A to 7C and FIGS. 10A to 10B. I will do it. Note that S10 to S24 are the same as those in the flowchart shown in FIG.

  In S26, first, determination processing similar to S16 described above is performed for the first to sixth lines shown in FIG. Here, it is assumed that the reliability of the last partial signal of the previous frame (not shown) is “3”. In addition, the reliability of the first partial signal of the subsequent frame is set to “10”. The hard decision values of the respective predetermined partial signals and the preceding and following partial signals are (001) in the first row, and (010), (100), (001), (011), and (110) in order. Therefore, the flags before correction are “0”, “1”, “0”, “0”, “1”, “1” in order. Here, (010) in the second row is a pattern in which the above-described flag is to be corrected, so the flag “1” is corrected to “0”. Then, the corrected flags are “0”, “0”, “0”, “0”, “1”, “1” in order, and the first to fourth lines are determined to be non-phase-inverted lines. The Next, it is determined whether the corrected second line should be corrected again. In this case, since the soft decision value “−10” that uses the second row as the predetermined partial signal exceeds the threshold value, the flag “0” on the second row is further corrected, that is, a determination corresponding to S16. It is determined that the flag should not have been corrected. Then, it is determined that the second line is a line on which phase correction is performed (Y in S26). The fifth and sixth lines are determined to be the lines on which phase correction is performed (Y in S26). Therefore, the final flags are “0”, “1”, “0”, “0”, “1”, “1”, as illustrated in FIG.

  The difference from the above-described embodiment is that the reliability of the predetermined partial signal and the partial signals before and after the predetermined partial signal are the threshold even if it is determined that the flag correction is performed in the same determination as in S16. If it exceeds the value, it is a point to re-correct in order to restore the flag of the line by trusting their reliability.

  According to the modification of the present embodiment, a partial signal having a reliability lower than the threshold value is not desirable as a criterion for determination. Therefore, with respect to a predetermined partial signal having such a partial signal before and after that, Does not perform phase correction. Accordingly, it is possible to prevent erroneous correction from being performed on a partial signal that does not include an error. In addition, since it is considered that a predetermined partial signal having a reliability higher than the threshold has a high probability of not being erroneous, phase correction is performed on such a partial signal. Moreover, the accuracy of determination can be improved by these. Moreover, since these threshold values are determined before the determination, the determination process can be skipped. By skipping the determination process, the phase determination process including the determination can be executed at high speed.

  In the above, this invention was demonstrated based on the Example. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to the combination of each component and each processing process, and such modifications are also within the scope of the present invention. .

  In the present embodiment and the modification, the front and rear partial signals are described as one front and rear partial signal. However, the present invention is not limited to this, and two or more partial signals may be used. Further, the first threshold value and the second threshold value have been described as different values. However, it is not limited to this, and the same value may be used. Further, the reliability has been described as a soft decision value represented by any value from -7 to +7. However, the present invention is not limited to this, and it may be a soft decision value represented by a range having a certain width around 0, such as -127 to +127. Also, the minimum value may be used without setting 0 as the center. For example, it may be a soft decision value represented by any value from 0 to 255.

  Further, in the present embodiment and the modification, it has been described that the modulation scheme of the transmitted signal sequence is BPSK. However, the present invention is not limited to this, and a modulation scheme such as QPSK (Quadrature Phase Shift Keying) or 16QAM (Quadrature Amplitude Modulation) may be used. In such a case, the same effect as described above can be obtained by performing “phase rotation processing” on the portion where “phase correction is performed” in S16 of FIG. Further, the description has been made assuming that all known signals are composed of the same symbols. However, the present invention is not limited to this, and it may be a sequence arranged according to a predetermined rule. In this case, the same effect as described above can be obtained by calculating the correlation with a predetermined rule as the reliability and using the difference between the two.

  In FIG. 1, the RF unit 2 and the high-frequency unit 3 have been described as separate circuits. However, the present invention is not limited to this, and the high frequency unit 3 may be provided inside the RF unit 2 to perform direct conversion. It goes without saying that the same effects as described above can be obtained even in such a configuration.

It is a figure which shows the structural example of the receiver concerning the Example of this invention. It is a figure which shows the structural example of the phase determination apparatus of FIG. It is a figure which shows the structural example of the signal series which the phase determination apparatus of FIG. 2 receives. It is a figure which shows the structural example of the partial signal acquisition part of FIG. It is a figure which shows the structural example of the buffer of FIG. It is a figure which shows the structural example of the phase correction part of FIG. FIG. 7A is a diagram illustrating an arrangement example of the partial signals written by the partial signal acquisition unit in FIG. 2 in the buffer. FIG. 7B is a diagram illustrating an arrangement example in the buffer of the reliability of the partial signal written by the reliability acquisition unit of FIG. FIG. 7C is a diagram illustrating an arrangement example of a flag indicating the determination result of the partial signal written by the determination unit in FIG. 2 in the buffer. 3 is a flowchart illustrating an operation example of the phase determination device in FIG. 2. It is a flowchart which shows the operation example of the phase determination apparatus concerning the modification of the Example of this invention. FIGS. 10A and 10B are diagrams showing an example of the arrangement of flags in the buffer 40 indicating the determination result of partial signals in the buffer 40 according to the modification of the embodiment of the present invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Antenna, 2 RF part, 3 High frequency part, 4 A / D conversion part, 5 Signal processing part, 6 Decoding part, 10 Receiving part, 20 Partial signal acquisition part, 22 Writing part, 24 Reliability acquisition part, 30 Phase Correction unit, 32 determination unit, 34 correction processing unit, 40 buffer, 52 known signal, 54 data signal, 100 phase determination device, 200 reception device.

Claims (5)

A receiving unit for receiving a signal sequence in which known signals are periodically inserted;
A partial signal acquisition unit that sequentially acquires a plurality of partial signals that are included in the signal sequence received by the reception unit and that respectively correspond to the known signals;
The predetermined partial signal is compared with the partial signals before and after the predetermined partial signal, according to the rules of the known signal that should correspond to each of the partial signals acquired by the partial signal acquisition unit. A phase correction unit that performs phase correction,
A phase determination device comprising: The partial signal acquisition unit includes a reliability acquisition unit that acquires the reliability of each partial signal,
The phase correction unit performs correction on the predetermined partial signal by comparing the reliability of the predetermined partial signal with the reliability of the partial signals before and after the predetermined partial signal. The phase determination apparatus as described.   The phase correction unit is a case where the absolute values of the two reliability levels before and after the predetermined partial signal acquired by the partial signal acquisition unit are both greater than a first threshold value, The correction is performed on the predetermined partial signal when the absolute value of the reliability is larger than a second threshold value which is a value equal to or less than the first threshold value. Phase determination device. The signal sequence received by the receiving unit includes a plurality of data signals before and after each partial signal,
The phase correction unit is a data signal subsequent to the predetermined partial signal, and a data signal existing before the partial signal after the predetermined partial signal is phased together with the predetermined partial signal. The phase determination apparatus according to claim 1, wherein correction is performed. Each of the plurality of partial signals included in the signal sequence received by the receiving unit is composed of a plurality of symbols,
The phase determination apparatus according to claim 1, wherein the partial signal acquisition unit acquires the reliability of the partial signal by adding the reliability of a plurality of symbols included in the partial signal.

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