JP2007067379A - Solid state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid state imaging device of excellent image characteristics in which both micronization of pixels and higher optical condensing rate are attained. <P>SOLUTION: A high-concentration p-well layer 5 is partially formed inside a semiconductor substrate 1 with the lower region of STI6 as a center. Photoelectric converters 9a and 9b are so formed as to spread downside of gate electrodes 10a and 10b. Salicide regions 12a and 12b are so formed to cover only a part of the surfaces of gate electrodes 10a and 10b, being deviated to a drain region 13 side. The incident light can enter the photoelectric converters 9a and 9b as well that spread downside of the gate electrodes 10a and 10b through the part in which no salicide regions 12a and 12b are formed among the surfaces of gate electrodes 10a and 10b. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device in which a plurality of pixels are arranged in a matrix.

  In a solid-state imaging device typified by a CCD or MOS type image sensor, it is required to increase the light collection rate in order to improve image characteristics. In order to increase the light collection rate, it is generally known to use a condensing lens.

  In recent years, it has been desired to reduce the size of pixels with the miniaturization of solid-state imaging devices. In order to satisfy such requirements, attempts have been made to make pixels finer by sharing one gate electrode or drain region with a plurality of adjacent pixels. The details will be described below by taking a solid-state imaging device having two cells as one cell (unit) as an example.

  FIG. 9 is a plan view schematically showing a conventional solid-state imaging device. FIG. 9 is a diagram in which a part of the configuration of the solid-state imaging device is projected onto the main surface of the semiconductor substrate.

  The solid-state imaging device shown in FIG. 9 includes a plurality of pixels arranged in a matrix on a semiconductor substrate. In general, an n-type silicon substrate is used as the semiconductor substrate. Two adjacent pixels 102a and 102b constitute one cell C and include a photoelectric conversion unit (not shown) that converts incident light into signal charges. Light receiving regions 103a and 103b that allow light to enter the photoelectric conversion unit are formed in predetermined regions in the pixels 102a and 102b. Each of the light receiving regions 103a and 103b has the same shape and is formed at a predetermined position with reference to the center m of the pixels 102a and 102b.

  Next, with reference to FIGS. 10 and 11, the positional relationship between the pixel 2 and the light receiving region 3 will be described more specifically.

  10 is an enlarged view of the two-dot chain line portion shown in FIG. 9, and FIG. 11 is a cross-sectional view taken along line XI-XI in FIG.

  As shown in FIGS. 10 and 11, the conventional solid-state imaging device includes a semiconductor substrate 101, a low concentration p-well layer 104, a high concentration p-well layer 105, an element isolation region 106, and a p-type injection isolation. Layer 107, p-type photoelectric conversion portions 108a and 108b, n-type photoelectric conversion portions 109a and 109b, gate electrodes 110a and 110b, spacer 111, salicide regions 112a and 112b, drain region 113, and Vt. A control layer 114, a barrier control layer 115, an insulating film 116, a light shielding film 117, a color filter 118, and a condenser lens 119 are provided.

  The pixel 102a is mainly configured by photoelectric conversion portions 108a and 109a constituting a photodiode, a gate electrode 110a, a salicide region 112a formed on the surface of the gate electrode 110a, and an element isolation region 106. Similarly, the pixel 102b is configured around the photoelectric conversion units 108b and 109b, the gate electrode 110b, the salicide region 112b formed on the surface of the gate electrode 110b, and the element isolation region 106.

  The insulating film 116 is formed so as to cover the surface of the semiconductor substrate 101 on which the gate electrodes 110a and 110b are formed. On the insulating film 116, a light shielding film 117 having an opening in a predetermined region on the photoelectric conversion portions 109a and 109b is formed. The openings provided in the light shielding film 117 form light receiving regions 103a and 103b for receiving incident light to the photoelectric conversion units 109a and 109b.

  Further, a color filter 118 and a plurality of condenser lenses 119 provided corresponding to each of the pixels 102 a and 102 b are formed above the light shielding film 117. The condensing lens 119 uses the area occupied by each pixel 102a and 102b with respect to the main surface of the semiconductor substrate 101 as effectively as possible in order to condense as much light as possible onto the pixels 102a and 102b. Are arranged as follows. That is, the condensing lens 119 is arranged so that the optical axis Ax passes through the center m of the pixels 102a and 102b.

In the conventional solid-state imaging device, two pixels 102a and 102b share one drain region 113 to form one cell, thereby miniaturizing the pixels.
Japanese Patent Application No. 8-316448

  However, in a conventional solid-state imaging device in which a plurality of pixels constitute one cell, the light collection rate of the solid-state imaging device as a whole is reduced. As a result, the image sensitivity decreases and varies, color shading failure, and sensitivity shading. There is a problem that defects and the like occur.

  Hereinafter, problems of the conventional solid-state imaging device will be described in detail with reference to FIGS.

  As shown in FIG. 9, the centers m of the pixels 102a and 102b are arranged at a constant interval in a direction parallel to the main surface of the semiconductor substrate. On the other hand, in one cell C, the two pixels 102 a and 102 b share one drain region 113. Therefore, the centers p of the light receiving regions 103a and 103b in the pixels 102a and 102b are arranged in a state shifted from the center m of the pixels 102a and 102b in a direction parallel to the main surface of the substrate. As a result, the arrangement pitch of the centers m of the pixels 102a and 102b is constant, whereas the arrangement pitch of the centers p of the light receiving regions 103a and 103b is not constant.

  Further, as described above, the condensing lens 119 covers as much as possible the area occupied by each pixel 102a and 102b with respect to the main surface of the semiconductor substrate 101 in order to collect light as much as possible in the pixels 102a and 102b. Is arranged. That is, the condensing lens 119 is arranged so that the optical axis Ax passes through the center m of the pixels 102a and 102b. 9 to 11, the condensing lenses 119 are arranged in an array corresponding to the light receiving regions 103a and 103b of the pixels 102a and 102b, and are formed so that the outer circumferences of adjacent lenses are in contact with each other. ing.

  The light incident on the pixels 102a and 102b is collected by the condenser lens 119, and enters the optical axis Ax direction of the condenser lens 119, that is, toward the center m of the pixels 102a and 102b. However, when the center m of the pixels 102a and 102b and the center p of the light receiving regions 103a and 103b are shifted in the main surface direction of the semiconductor substrate 101, they are incident toward the center m of the pixels 102a and 102b. The light deviates from the center p of the light receiving regions 103a and 103b. Therefore, the light receiving sensitivity in the photoelectric conversion units 109a and 109b is lowered.

  In view of this, a shift between the center m of the pixels 102a and 102b and the center p of the light receiving regions 103a and 103b is considered in advance, and the light axis of the condenser lens 119 passes through the center p of the light receiving regions 103a and 103b. It is also conceivable to increase the light collection rate by arranging them.

  However, when one cell C is configured by the two pixels 102a and 102b, the centers p of the light receiving regions 103a and 103b are not arranged at equal intervals on the semiconductor substrate 101 as described above. Therefore, if the optical axis of the condensing lens 119 and the center p of the light receiving regions 103a and 103b are made to coincide, there arises a problem that the layout of the condensing lens 119 becomes complicated.

  If the condensing lens 19 is arranged corresponding to the position of the center p of the light receiving regions 103a and 103b, the size of the condensing lens 119 needs to be reduced, so that the areas of the pixels 102a and 102b are effectively used. Can not do it. As a result, condensing rate is reduced.

  Therefore, an object of the present invention is to provide a solid-state imaging device that achieves both miniaturization of pixels and a high light collection rate and is excellent in image characteristics such as image sensitivity, color shading, and sensitivity shading.

  The present invention is directed to a solid-state imaging device. The solid-state imaging device includes a semiconductor substrate and a plurality of pixels that are arranged on the semiconductor substrate and include a light receiving region that receives incident light. The predetermined number of pixels are grouped to form one pixel unit, and each of the light receiving regions is formed such that the center thereof coincides with the center of each pixel in a direction parallel to the main surface of the semiconductor substrate. Is done.

  Each of the pixels may include a photoelectric conversion region and a gate electrode, and the photoelectric conversion region may be formed to extend below the gate electrode.

  The solid-state imaging device according to the present invention is formed on the surface of the first semiconductor region and the first semiconductor region formed from the surface of the semiconductor substrate to a predetermined depth, and separates each pixel unit. An isolation region; and a second semiconductor region formed inside the first semiconductor region, partially formed around the lower part of the isolation region, and having a higher impurity concentration than the first semiconductor region. Each includes a photoelectric conversion region, and the photoelectric conversion region may be formed to extend between the second semiconductor regions.

  Each pixel includes a photoelectric conversion region, a surface region formed on the surface of the semiconductor substrate, and a gate electrode, and the surface region may be formed to have a predetermined gap between the gate electrode. good.

  Each of the pixels may further include a condensing lens, and the condensing lens may be arranged so that its optical axis passes through the center of the pixel.

  The pixel unit includes a drain region, and each pixel includes a photoelectric conversion region, a gate electrode, and a salicide region formed on the surface of the gate electrode, and a predetermined number of pixels included in each pixel unit. May share the drain region, and the salicide region may be formed in a part of the surface of the gate electrode that is biased toward the drain region.

  Moreover, it is preferable that the light receiving region forms the same pattern for each pixel unit.

  In this case, the pixel unit includes two adjacent pixels and a drain region, and the two pixels included in each pixel unit may have a line-symmetric layout with respect to the center line of the pixel unit. .

  Alternatively, the pixel unit includes four pixels arranged in a 2 × 2 matrix and a drain region, and the four pixels included in each pixel unit have a point-symmetric layout with respect to the center of the pixel unit. You may have.

  Alternatively, the pixel unit includes four pixels arranged in a 2 × 2 matrix and a drain region, and the four pixels included in each pixel unit are point-symmetric with respect to the center of the pixel unit, and The layout may be axisymmetric with respect to the center line of the pixel unit.

  The solid-state imaging device according to the present invention is preferably an amplification type solid-state imaging device.

  Since the solid-state imaging device according to the present invention is formed so that the center of the pixel coincides with the center of the light receiving region, a high light collection rate can be obtained. Therefore, according to the present invention, a solid-state imaging device with good image characteristics can be realized.

(First embodiment)
Hereinafter, the solid-state imaging device according to the first embodiment of the present invention will be described with reference to the drawings, taking as an example a solid-state imaging device in which two pixels are configured as one cell. In each drawing, for convenience of explanation, the positional relationship is shown using a broken line, a chain line, or the like.

  FIG. 1 is a plan view schematically showing a solid-state imaging device according to the first embodiment of the present invention. In FIG. 1, for convenience of illustration, some pixel components are shown by projection onto the main surface of a semiconductor substrate (not shown).

  The solid-state imaging device shown in FIG. 1 includes a plurality of pixels 2a and 2b arranged in a two-dimensional matrix on a semiconductor substrate (not shown). The pixels 2a and 2b include a photoelectric conversion unit (not shown) that converts incident light into signal charges. Points m (hereinafter referred to as “pixel centers”) obtained by projecting the centers of the plurality of pixels 2a and 2b onto a semiconductor substrate (not shown) are spaced apart in a direction parallel to the main surface of the semiconductor substrate. Is arranged in.

  Each of the pixels 2a and 2b includes light receiving regions 3a and 3b for receiving incident light, gate electrodes 10a and 10b, and salicide regions 12a and 12b, respectively.

  Two adjacent pixels 2a and 2b constitute one cell C (pixel unit). The cells constitute a predetermined number of arrangement patterns of the light receiving regions 3a and 3b as one group, and each cell has the same configuration. In the present embodiment, the pixels 2a and 2b included in the cell C have a line-symmetric layout around the center line of the cell (the boundary line between the pixels 2a and 2b in FIG. 1). In the following, only one cell C will be described in detail.

  Next, the positional relationship between the pixel 2 and the light receiving region 3 will be described more specifically with reference to FIGS. 2 and 3.

  2 is an enlarged view of the cell C shown in FIG. 1, and FIG. 3 is a cross-sectional view taken along line III-III shown in FIG.

  As shown in FIGS. 2 and 3, the solid-state imaging device according to the present embodiment includes a semiconductor substrate 1, a low concentration p-well layer 4, and a high concentration p− having a higher impurity concentration than the low concentration p-well layer 4. well layer 5, STI 6, p-type STI active layer 7, p-type photoelectric conversion units 8a and 8b, n-type photoelectric conversion units 9a and 9b, gate electrodes 10a and 10b, spacers 11a and 11b, salicide The regions 12a and 12b, the drain region 13, the Vt control layer 14, the barrier control layer 15, the insulating film 16, the light shielding film 17, the color filter 18, and the condenser lens 19 are provided.

  The pixel 2a is mainly configured by photoelectric conversion units 8a and 9a constituting a photodiode and a gate electrode 10a. Similarly, the pixel 2b is configured around the photoelectric conversion units 8b and 9b, the drain region 13, and the gate electrode 10b. In particular, in the present embodiment, the photoelectric conversion portions 8a and 8b are formed so as to have a gap between the gate electrodes 10a and 10b. Note that the cell C constituted by the pixels 2a and 2b is separated from each other by the STI 6.

  As shown in FIG. 3, in the present embodiment, the high concentration p-well layer 5 is formed around the region below the STI 6 and is not formed below the gate electrodes 10a and 10b. Instead, the photoelectric conversion portions 9a and 9b are formed so as to extend below the gate electrodes 10a and 10b. Further, the salicide regions 12a and 12b are formed only on part of the surfaces of the gate electrodes 10a and 10b. More specifically, the salicide regions 12a and 12b are formed so that each length (the length in the left-right direction in FIG. 3) is shorter than the gate length of the gate electrodes 10a and 10b. The salicide regions 12a and 12b are formed so as to be biased toward the drain region 13 in the surfaces of the gate electrodes 10a and 10b.

  An insulating film 16 is formed on the gate electrodes 10a and 10b. On the insulating film 16, a light shielding film 17 having an opening in a predetermined region above the photoelectric conversion portions 9a and 9b is formed. Further, a color filter 18 is formed on the light shielding film 17, and a plurality of condenser lenses 19 are arranged on the color filter 18.

  In order to collect as much light as possible on the corresponding pixel 2, the condenser lens 19 is disposed so as to cover as much as possible the area occupied by each pixel 2 a and 2 b on the main surface of the semiconductor substrate. That is, the condensing lens 19 is arranged so that its optical axis passes through the center m of the pixels 2a and 2b. In the present embodiment, as shown in FIG. 3, the plurality of condenser lenses 19 are arranged in an array corresponding to each of the plurality of pixels 2a and 2b. They are formed so that they touch each other.

  As shown in FIG. 3, the light receiving regions 3 a and 3 b in the present embodiment are the regions occupied by the openings of the light shielding film 17 and the photoelectric conversion units 9 a and 9 b (that is, photoelectric conversion to the main surface of the semiconductor substrate 1). Projection of the portions 9a and 9b) and a region of the main surface of the semiconductor substrate 1 through which incident light can be transmitted. The region on the main surface of the semiconductor substrate 1 through which incident light can be transmitted varies depending on the positions and dimensions of the salicide regions 12a and 12b.

  In general, in a solid-state imaging device having two pixels as one cell, two adjacent pixels share one drain region 13, so that the center m of the two adjacent pixels 2a and 2b, the light receiving region 3a, The center p of 3b is arranged at a position shifted in the main surface direction of the substrate. Therefore, in the conventional solid-state imaging device, the pitch of the center m of each pixel 2a and 2b is constant on the semiconductor substrate 101, whereas the pitch of the center p of the light receiving region 3 is not constant.

  On the other hand, as shown in FIG. 1, the solid-state imaging device according to the present embodiment is configured such that the center m of the pixels 2a and 2b and the center p of the light receiving regions 3a and 3b substantially coincide. Yes.

  Specifically, as shown in FIG. 3, the high-concentration p-well layer 5 is not formed below the gate electrodes 10a and 10b, but partially inside the semiconductor substrate 1 with the region below the STI 6 as the center. Is formed. Accordingly, the photoelectric conversion portions 9a and 9b are formed so as to extend below the gate electrodes 10a and 10b. Furthermore, the salicide regions 12a and 12b cover only part of the surfaces of the gate electrodes 10a and 10b and are formed at positions that are biased toward the drain region 13 side. Since it is configured in this manner, incident light passes through a portion of the surfaces of the gate electrodes 10a and 10b where the salicide regions 12a and 12b are not formed and spreads below the gate electrodes 10a and 10b. It can also enter 9a and 9b.

  Further, in the solid-state imaging device according to the present embodiment, the condenser lens 19 is disposed so that the optical axis thereof passes through the center m of the pixels 2a and 2b. Therefore, the light L incident on the pixels 2a and 2b is collected by the condenser lens 19 and incident toward the center m of the pixels 2a and 2b. As described above, the center m of the pixels 2a and 2b and the center p of the light receiving regions 3a and 3b are formed so as to substantially coincide with each other in the main surface direction of the semiconductor substrate 1. The condensed light can enter the center p of the light receiving regions 3a and 3b.

  As described above, the solid-state imaging device according to the present embodiment is configured to overlap the center m of the pixels 2a and 2b and the center p of the light receiving regions 3a and 3b. Therefore, according to the present embodiment, it is possible to allow the light traveling toward the center m of the pixels 2a and 2b to enter the center p of the light receiving regions 3a and 3b without changing the arrangement of the condenser lens 19. A high light collection rate can be obtained. As a result, a decrease in sensitivity, variation in image sensitivity, color shading failure, sensitivity shading failure, and the like are suppressed, and a solid-state imaging device with good image characteristics can be realized.

  Here, a method for manufacturing the solid-state imaging device according to the present embodiment will be described.

  4A to 4K are cross-sectional views for explaining the outline of the manufacturing method of the solid-state imaging device according to the first embodiment of the present invention.

First, as shown in FIG. 4A, a low-concentration p-well layer 4 (impurity concentration: 1 × 10 ¹⁴ to 1 × 10 ¹⁵ cm ⁻³ ) is formed inside the n-type semiconductor substrate 1. It is formed to a depth of about 3 μm from the surface.

Next, as shown in FIG. 4B, the high concentration p-well layer 5 (impurity concentration: 1 × impurity concentration) higher than that of the low concentration p-well layer 4 at the position where the pixel isolation region is to be formed in the semiconductor substrate 1. 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻³ ) so that the concentration peak position is 0.9 μm deep from the surface of the semiconductor substrate 1.

Next, as shown in FIG. 4C, the STI 6 is formed from the main surface of the semiconductor substrate 1 to a predetermined depth. More specifically, first, a trench T is formed by dry etching in a region where an element isolation portion is to be formed. The depth of the groove T is about 0.3 μm. Thereafter, ion implantation is performed with low energy toward the inner surface of the groove T. Specifically, boron (B) ions are implanted into the inner surface of the groove T under the conditions of 30 KeV and 3.2 × 10 ¹³ / cm ² . As a result, the p ⁺ -type inner surface film 7 is formed on the inner surface of the groove T. Next, an insulating film such as an oxide film is buried in the trench T in which the inner surface film 7 is formed, and then the surface is flattened. The STI 6 is formed through the above steps.

  Next, as illustrated in FIG. 4D, the p-type Vt control layer 14 and the barrier control layer 15 are formed inside the low concentration p-well layer 4. The concentration peak position of the Vt control layer is 0.3 μm deep from the surface of the semiconductor substrate 1, and the concentration peak position of the barrier control layer 15 is 0.8 μm deep from the surface of the semiconductor substrate.

Next, as shown in FIG. 4E, p-type photoelectric conversion units 8a and 8b and n-type photoelectric conversion units 9a and 9b are formed. More specifically, in accordance with a conventionally known method, a resist pattern having openings is provided in regions (regions determined by design) where the photoelectric conversion portions 9a and 9b on the main surface of the semiconductor substrate 1 are to be formed. Then, using this resist pattern as a mask, arsenic (As), which is an n-type impurity, is ion-implanted with high energy. Specifically, As ions are implanted under the conditions of 600 KeV and 2.2 × 10 ¹² / cm ² . As a result, photoelectric conversion portions 9 a and 9 b are formed inside the semiconductor substrate 1. The depth of the concentration peaks of the photoelectric conversion portions 9a and 9b from the surface of the semiconductor substrate 1 is about 0.3 μm.

  Next, photoelectric conversion portions 8a and 8b are formed by selectively introducing p-type impurities into the surface of the semiconductor substrate 1 according to a known method. In the present embodiment, p-type impurities are introduced into a region on the surface of the semiconductor substrate 1 that is a predetermined distance away from a region (a region determined by design) where the gate electrodes 10a and 10b are to be formed. As a result, the state where the n-type photoelectric conversion portions 9 a and 9 b extend to the lower portions of the gate electrodes 10 a and 10 b on the surface layer of the semiconductor substrate 1 is maintained.

  Next, as shown in FIG. 4F, gate electrodes 10a and 10b are formed. More specifically, a polysilicon film is deposited on the surface of the semiconductor substrate 1 by a CVD method so as to have a thickness of 200 nm. Then, the deposited polysilicon film is patterned by photolithography processing, dry etching processing, or the like, thereby forming gate electrodes 10a and 10b.

Next, in FIG. 4G, the drain region 13 is formed on the main surface of the semiconductor substrate 1. More specifically, n-type impurities are ion-implanted into a portion of the main surface of the semiconductor substrate 1 exposed from between the gate electrodes 10a and 10b using the formed gate electrodes 10a and 10b as a mask. Specifically, arsenic (As) ions are ion-implanted under the conditions of 50 KeV and 2.0 × 10 ¹⁵ / cm ² , thereby forming the drain region 13 on the main surface of the semiconductor substrate 1.

  Next, as shown in FIG. 4H, an oxide film is deposited on the surface of the semiconductor substrate 1 by a CVD method so as to have a thickness of 150 nm. Then, the deposited oxide film is patterned by a photolithography process, a dry etching process, or the like to form a spacer 11 along the side walls of the opposing gate electrodes 10a and 10b.

Next, as shown in FIG. 4I, part of the surface of the gate electrodes 10a and 10b is salicided. More specifically, a compound such as CoSi ₂ is deposited on a part of the surface of the gate electrodes 10a and 10b by sputtering. Since the incident light can pass through the non-salicide regions (portions where the salicide region 12 is not formed) on the surfaces of the gate electrodes 10a and 10b, the photoelectric conversion portions 9a and 9b formed to spread below the gate electrodes 10a and 10b. It is possible to capture light into the light.

  Next, as shown in FIG. 4J, an insulating film 16 made of a silicon oxide film is deposited by a CVD method so as to cover the gate electrodes 10a and 10b. Although the insulating film 16 includes a wiring layer, the description here is omitted for the sake of simplicity. Subsequently, a light shielding film 17 is formed so as to cover the insulating film 16. Specifically, a thin film is formed using tungsten, copper, aluminum or the like so as to cover the insulating film 16 by PVD or CVD. Then, the part located in the upper part of the photoelectric conversion parts 9a and 9b is selectively removed by dry etching among the formed thin films. As a result, as shown in FIG. 4J, openings are formed in the light shielding film 17 at positions corresponding to the photoelectric conversion portions 9a and 9b, and the light receiving regions 3a and 3b are formed.

  Then, as shown in FIG. 4K, the color filter 18 and the condenser lens 19 are formed on the light shielding film 17. The condenser lens 19 is a microlens that is formed by heat reflow transfer of a heat-soluble transparent resin or a resist, and is arranged in an array corresponding to each of the light receiving regions 3 of each pixel 2. Thereby, a solid-state imaging device having a structure as shown in FIG. 7K is completed.

  As described above, according to the manufacturing method according to the present embodiment, the solid-state imaging device can be manufactured such that the centers of the light receiving regions 3a and 3b overlap the center m of the pixels 2a and 2b. According to the manufacturing method according to the present embodiment, a high light collection rate can be obtained without changing the arrangement of the condenser lens 19. Therefore, it is possible to manufacture a solid-state imaging device with good image characteristics.

  In this embodiment, the solid-state imaging device having a structure in which two pixels are one cell has been described as an example. However, the present invention is, for example, a solid-state imaging device in which three pixels are one cell, and four pixels are one cell. The present invention can be similarly applied to a solid-state imaging device having a light-receiving region in which one cell is composed of a plurality of pixels.

(Second Embodiment)
FIG. 5 is a plan view schematically showing a solid-state imaging device according to the second embodiment of the present invention.

  In the solid-state imaging device according to the present embodiment, four pixels 2 a to 2 d are configured as one cell C. The pixels 2a to 2d included in the cell C have a point-symmetric layout with respect to the center of the cell C.

  More specifically, as shown in FIG. 5, in the pixels 2 a to 2 d having a substantially rectangular shape, each of the light receiving regions 3 a to 3 d is formed to extend in the diagonal direction of each pixel. In the cell C, the light receiving regions 3b and 3c of the pair of pixels 2b and 2c arranged on the diagonal line are arranged along the diagonal line of the cell and share one drain region 13 formed at the center of the cell. .

  FIG. 6 is a plan view showing an example of a conventional solid-state imaging device configured with four pixels as one cell.

  Similar to the first embodiment, in the conventional solid-state imaging device having a 4-pixel 1-cell configuration, the light receiving region 103 is formed such that the center p is shifted from the center m of the pixel 102. On the other hand, from the viewpoint of improving the light collection efficiency, the condensing lens (not shown) is usually arranged so that its optical axis passes through the center m of the pixel 102. Therefore, also in the conventional solid-state imaging device shown in FIG. 9, the light condensed by the condenser lens (not shown) enters the position shifted from the center p of the light receiving region 103, and thus the light collection efficiency is high. descend.

  On the other hand, the solid-state imaging device according to the present embodiment is formed so that the photoelectric conversion unit (not shown) extends below the gate electrodes 10a to 10d, as in the first embodiment. The salicide regions 12a to 12d are formed only in a part of the surfaces of the gate electrodes 10a to 10d on the drain region 13 side. Therefore, according to the present embodiment, the solid-state imaging device having the layout of four pixels and one cell as shown in FIG. 5 is configured such that the center m of the pixels 2a to 2d and the center p of the light receiving regions 3a to 3d overlap. can do. Therefore, it is possible to realize a solid-state imaging device with good image characteristics.

(Third embodiment)
FIG. 7 is a plan view schematically showing a solid-state imaging device according to the third embodiment of the present invention.

  In the solid-state imaging device according to this embodiment, four pixels 2a to 2d having a substantially rectangular shape constitute one cell C, as in the second embodiment. In each of the pixels 2a to 2d, each of the light receiving regions 3a to 3d is formed so as to extend in the diagonal direction of each pixel. However, the pixels 2a to 2d included in the cell C are different from the second embodiment in that the pixels 2a to 2d have a layout that is point-symmetric with respect to the center of the cell C and line-symmetric with respect to the center line of the cell C. . Specifically, two pixels 2 a and 2 b adjacent in the row direction share one drain region 13.

  FIG. 8 is a plan view showing another example of a conventional solid-state imaging device configured with four pixels as one cell.

  Similar to the second embodiment, in the conventional solid-state imaging device having a 4-pixel 1-cell configuration, the light-receiving region 3 is formed such that the center p of the light-receiving region 3 is shifted from the center m of the pixel 2. . Therefore, the light condensed by the condensing lens (not shown) is incident on the position shifted from the center p of the light receiving region 3 and the condensing efficiency is lowered.

  On the other hand, according to the solid-state imaging device according to the present embodiment, the photoelectric conversion unit (not shown) is formed so as to extend below the gate electrodes 10a to 10d, as in the first embodiment. At the same time, the salicide regions 12a to 12d are formed only in a part on the drain region 13 side on the gate electrodes 10a to 10d. Therefore, it is possible to realize a solid-state imaging device with improved light collection efficiency and good image characteristics. .

  In each of the embodiments described above, only the case where one cell is composed of two pixels or four pixels has been described. However, the number of pixels constituting one cell is not particularly limited.

  Further, in each of the above embodiments, the configuration of the cell is specified, but the cell may be any cell as long as a predetermined number of arrangement patterns of the light receiving area are configured as one group.

  Further, in each of the above embodiments, the MOS type solid-state imaging device has been described as an example. However, the present invention may be applied to a CCD solid-state imaging device.

  The present invention can be applied to, for example, an amplification type solid-state imaging device, particularly a MOS solid-state imaging device having a trench isolation structure. More specifically, the present invention can be used for a solid-state imaging device used for a camera-equipped mobile phone, a video camera, a digital still camera, and the like, a line sensor used for a printer, and the like.

1 is a plan view schematically showing a solid-state imaging device according to a first embodiment of the present invention. Enlarged view of cell C shown in FIG. Sectional view along the III-III line shown in FIG. Sectional drawing explaining the outline of the manufacturing method of the solid-state imaging device which concerns on the 1st Embodiment of this invention. Sectional drawing explaining the process following FIG. 4A Sectional drawing explaining the process following FIG. 4B. Sectional drawing explaining the process of following FIG. 4C Sectional drawing explaining the process of following FIG. 4D Sectional drawing explaining the process following FIG. 4E. Sectional drawing explaining the process of following FIG. 4F Sectional drawing explaining the process following FIG. 4G. Sectional drawing explaining the process following FIG. 4H Sectional drawing explaining the process following FIG. 4I. Sectional drawing explaining the process following FIG. 4J. The top view which shows typically the solid-state imaging device concerning the 2nd Embodiment of this invention The top view which shows an example of the conventional solid-state imaging device which comprises 4 pixels as 1 cell. The top view which shows typically the solid-state imaging device which concerns on 3rd Embodiment of this invention. The top view which shows another example of the conventional solid-state imaging device which comprises 4 pixels as 1 cell. A plan view schematically showing a conventional solid-state imaging device Enlarged view of the two-dot chain line portion shown in FIG. Sectional drawing which follows the XI-XI line of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Pixel 3 Light-receiving area 4 Low concentration p-well layer 5 High concentration p-well layer 6 STI
7 p-type STI active layer 8 photoelectric conversion part (p-type)
9 Photoelectric conversion part (n-type)
10 Gate electrode 11 Spacer 12 Salicide region 13 Drain region 14 Vt control layer 15 Barrier control layer 16 Insulating film 17 Light shielding film 18 Color filter 19 Condensing lens 20 Incident light C Cell m Center of pixel p Center of light receiving area Ax Optical axis L Incident light

Claims (11)

A solid-state imaging device,
A semiconductor substrate;
A plurality of pixels arranged on the semiconductor substrate and including a light receiving region for receiving incident light;
A predetermined number of pixels are grouped to form one pixel unit,
Each of the light receiving regions is a solid-state imaging device formed such that the center thereof coincides with the center of each of the pixels in a direction parallel to the main surface of the semiconductor substrate. Each of the pixels includes a photoelectric conversion region and a gate electrode,
The solid-state imaging device according to claim 1, wherein the photoelectric conversion region is formed so as to extend below the gate electrode. A first semiconductor region formed from the surface of the semiconductor substrate to a predetermined depth;
An isolation region formed on a surface of the first semiconductor region and separating each of the pixel units;
A second semiconductor region formed inside the first semiconductor region, partially formed around the lower part of the isolation region, and having a higher impurity concentration than the first semiconductor region;
Each of the pixels includes a photoelectric conversion region,
The solid-state imaging device according to claim 1, wherein the photoelectric conversion region is formed so as to extend between the second semiconductor regions. Each of the pixels includes a photoelectric conversion region, a surface region formed on the surface of the semiconductor substrate, and a gate electrode.
The solid-state imaging device according to claim 1, wherein the surface region is formed to have a predetermined gap between the surface region and the gate electrode. Each of the pixels further includes a condenser lens;
The solid-state imaging device according to claim 1, wherein the condenser lens is disposed so that an optical axis thereof passes through a center of the pixel. The pixel unit includes a drain region,
Each of the pixels includes a photoelectric conversion region, a gate electrode, and a salicide region formed on the surface of the gate electrode,
The predetermined number of pixels included in each of the pixel units share the drain region;
The solid-state imaging device according to claim 1, wherein the salicide region is formed in a part of the surface of the gate electrode that is biased toward the drain region.   The solid-state imaging device according to claim 1, wherein the light receiving region forms the same pattern for each pixel unit. The pixel unit includes two adjacent pixels and a drain region,
The solid-state imaging device according to claim 7, wherein the two pixels included in each pixel unit have a line-symmetric layout with respect to a center line of the pixel unit. The pixel unit includes four pixels arranged in a 2 × 2 matrix and a drain region,
The solid-state imaging device according to claim 7, wherein the four pixels included in each of the pixel units have a point-symmetric layout with respect to a center of the pixel unit. The pixel unit includes four pixels arranged in a 2 × 2 matrix and a drain region,
The four pixels included in each pixel unit have a layout that is point-symmetric with respect to the center of the pixel unit and line-symmetric with respect to a center line of the pixel unit. The solid-state imaging device according to 7.   The solid-state imaging device according to claim 1, wherein the solid-state imaging device is an amplification type solid-state imaging device.

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