JP2014090088A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method of the same, which inhibits deterioration in accuracy of the size and a shape of a pattern, which is caused because a parting line lies during a plurality of times of exposure processes.SOLUTION: A semiconductor device comprises: a semiconductor substrate SUB; and a plurality of light-receiving elements TMI arranged on a principal surface of the semiconductor substrate SUB. A plurality of regions where the plurality of light-receiving element TMI are arranged in a matrix are arranged on the principal surface of the semiconductor substrate SUB on which the plurality of light-receiving element TMI are arranged. A pitch P2 in a second direction crossing a first direction between the adjacent light-receiving elements across a parting line SPL which serves as a border between regions extending along the first direction along which the plurality of light-receiving elements TMI are arranged is greater than a repetition pitch P1 between the adjacent light-receiving elements in the regions.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having an image sensor and a manufacturing method thereof.

  Since it is difficult to form the pattern of a large-sized chip solid-state imaging device in a single exposure process, a pattern is generally formed by performing a plurality of exposure processes using a plurality of masks.

  As miniaturization of a plurality of light receiving elements constituting a solid-state image sensor progresses, it is difficult to set the position of a dividing line as a boundary portion of an area to be exposed in each of a plurality of exposure processes. The dividing line is located on the outer periphery of the mask. When the distance between the outer peripheral portion of the mask and the edge of the pattern formed by the mask is shortened, the accuracy such as the size and shape of the formed pattern is deteriorated. If the accuracy of the pattern to be formed, that is, the size and shape of the light receiving element deteriorates, the image quality of the light receiving element deteriorates. In order to suppress deterioration due to the shortening of the distance between the dividing line and the pattern edge as described above, the dividing line is positioned so as to be located as far as possible from the edge of the pattern.

  For example, Japanese Patent Application Laid-Open No. 2005-183600 (Patent Document 1) and Japanese Patent Application Laid-Open No. 2005-223707 (Patent Document 2) disclose that the accuracy of the size and shape of the pattern formed in the vicinity of the dividing line is deteriorated. Has been.

JP-A-2005-183600 JP 2005-223707 A

  In order to locate the dividing line as far as possible from the edge of the pattern, for example, a plurality of exposure methods have been attempted by positioning the dividing line in the center of the light receiving element as a pixel. However, if the miniaturization of the light receiving element proceeds rapidly, there are cases where the above method does not lead to a fundamental solution.

  In each of the above-mentioned patent documents, countermeasures are taken on the premise that deterioration in accuracy such as the dimension and shape of the pattern occurs due to the location of the dividing line in a plurality of exposure processes, but the accuracy deterioration itself is suppressed. This technology is neither disclosed nor suggested.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a semiconductor device includes a semiconductor substrate and a plurality of light receiving elements. The light receiving element is disposed on the main surface of the semiconductor substrate. A region where the plurality of light receiving elements are arranged in a matrix is divided into a plurality of regions by a dividing line extending along the first direction in which the plurality of light receiving elements are arranged. The pitch between the light receiving elements adjacent to each other across the dividing line is larger than the repetitive pitch between the plurality of light receiving elements adjacent to each other in the second direction that does not cross the dividing line and intersects the first direction.

  According to another embodiment, in a method for manufacturing a semiconductor device, first, a plurality of light receiving elements arranged in a matrix in the first region of the main surface of the semiconductor substrate are formed by exposure. A plurality of light receiving elements arranged in a matrix form is exposed and formed in a second area arranged adjacent to the first area on the main surface. In the step of exposing and forming the light receiving element in the second region, a dividing line that is a boundary between the first region and the second region and extends along the first direction in which the plurality of light receiving elements are arranged. Is located. In a region where a plurality of light receiving elements are arranged in a matrix, the pitch between adjacent light receiving elements across the dividing line does not cross the dividing line and is adjacent to the second direction intersecting the first direction. It is larger than the repetitive pitch between a plurality of light receiving elements.

  In the semiconductor device according to one embodiment and the semiconductor device manufacturing method according to another embodiment, the distance between the edge of the pattern of the light receiving element and the dividing line in the region straddling the dividing line SPL is suppressed. The deterioration of the accuracy of the pattern of the light receiving element is suppressed, and the deterioration of the image quality due to the deterioration of the accuracy is suppressed.

1 is a schematic plan view showing a state of a wafer in a semiconductor device according to the present invention. FIG. 2 is a schematic enlarged plan view of a region II surrounded by a dotted line in FIG. 1. 1 is a schematic plan view illustrating a configuration of a solid-state imaging element as a semiconductor device according to a first embodiment. FIG. 6 is a schematic cross-sectional view showing a first step of a plurality of exposure steps, which is a method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a schematic cross-sectional view showing a second step of the multiple exposure steps, which is a method for manufacturing the semiconductor device of the first embodiment. FIG. 7 is a schematic cross-sectional view showing a third step of the plurality of exposure steps, which is a method for manufacturing the semiconductor device of the first embodiment. FIG. 7 is a schematic cross-sectional view showing a fourth step following FIG. 6, which is the method for manufacturing the semiconductor device of the first embodiment. It is a schematic plan view which shows the structure of the area | region which each figure of FIGS. 9-22 shows. FIG. 6 is a schematic cross sectional view showing a first step of the method for manufacturing the semiconductor device in the first embodiment. FIG. 6 is a schematic cross sectional view showing a second step of the method for manufacturing the semiconductor device in the first embodiment. FIG. 6 is a schematic cross sectional view showing a third step of the method for manufacturing the semiconductor device in the first embodiment. FIG. 10 is a schematic cross sectional view showing a fourth step of the method for manufacturing the semiconductor device in the first embodiment. FIG. 10 is a schematic cross sectional view showing a fifth step of the method for manufacturing the semiconductor device in the first embodiment. FIG. 10 is a schematic cross sectional view showing a sixth step of the method for manufacturing the semiconductor device in the first embodiment. FIG. 10 is a schematic cross sectional view showing a seventh step of the method for manufacturing the semiconductor device in the first embodiment. FIG. 10 is a schematic cross sectional view showing an eighth step of the method for manufacturing the semiconductor device in the first embodiment. FIG. 10 is a schematic cross sectional view showing a ninth step of the method for manufacturing the semiconductor device in the first embodiment. FIG. 10 is a schematic cross sectional view showing a tenth step of the method for manufacturing the semiconductor device in the first embodiment. FIG. 11 is a schematic cross sectional view showing an eleventh step of the method for manufacturing a semiconductor device in the first embodiment. FIG. 10 is a schematic cross sectional view showing a twelfth step of the method for manufacturing the semiconductor device in the first embodiment. FIG. 24 is a schematic cross sectional view showing a thirteenth step of the method for manufacturing the semiconductor device in the first embodiment. It is a schematic sectional drawing which shows the 14th process of the manufacturing method of the semiconductor device in Embodiment 1. FIG. 4 is a schematic cross-sectional view (A) of a portion along line XXIIIA-XXIIIA in FIG. 3 and a schematic cross-sectional view (B) of a portion along line XXIIIB-XXIIIB in FIG. 3. It is a schematic plan view which shows the structure of the solid-state image sensor as a semiconductor device of a 1st comparative example. It is the schematic sectional drawing (A) of the part which follows the XXVA-XXVA line | wire of FIG. 24, and the schematic sectional drawing (B) of the part which follows the XXVB-XXVB line | wire of FIG. It is a schematic plan view which shows the structure of the solid-state image sensor as a semiconductor device of a 2nd comparative example. It is the schematic sectional drawing (A) of the part which follows the XXVIIA-XXVIIA line of FIG. 26, and the schematic sectional drawing (B) of the part which follows the XXVIIB-XXVIIB line of FIG. FIG. 6 is a schematic plan view showing a configuration of a solid-state imaging element as a semiconductor device according to a second embodiment. Schematic sectional view (A) of the portion along the line XXIXA-XXIXA in FIG. 28 and schematic sectional view of the portion along the line XXIXB-XXIXB in FIG. And. FIG. 6 is a schematic plan view showing a configuration of a solid-state imaging element as a semiconductor device according to a third embodiment. Schematic sectional view (A) of the portion along the XXXIA-XXXIA line of FIG. 30 and schematic sectional view of the portion along the XXXIB-XXXIB line of FIG. 30 which also serve as the method of manufacturing the semiconductor device of the third embodiment. And. FIG. 10 is a schematic plan view showing a configuration of a solid-state imaging element as a semiconductor device of a first example of the fourth embodiment. 32 is a schematic cross-sectional view (A) of a portion along the line XXXIIIA-XXXIIIA in FIG. 32 and a schematic cross-section of a portion along the line XXXIIIB-XXXIIIB in FIG. 32, which also serves as a method of manufacturing the semiconductor device of the first example of the fourth embodiment. (B). FIG. 10 is a schematic plan view showing a configuration of a solid-state imaging element as a semiconductor device of a second example of the fourth embodiment. Schematic sectional view (A) of the portion along the XXXVA-XXXVA line in FIG. 34 and the schematic sectional view of the portion along the XXXVB-XXXVB line in FIG. 34, which also serve as a manufacturing method of the semiconductor device of the second example of the fourth embodiment. (B). FIG. 10 is a schematic plan view showing a configuration of a solid-state imaging element as a semiconductor device of a third example of the fourth embodiment. 36 is a schematic cross-sectional view (A) of a portion along the line XXXVIIA-XXXVIIA in FIG. 36 and a schematic cross-section of a portion along the line XXXVIIB-XXXVIIB in FIG. 36, which also serves as a method of manufacturing the semiconductor device of the third example of the fourth embodiment. (B). FIG. 10 is a schematic plan view showing a configuration of a solid-state imaging element as a semiconductor device of a first example of Embodiment 5. FIG. 10 is a schematic plan view showing a configuration of a solid-state imaging element as a semiconductor device of a second example of the fifth embodiment. FIG. 10 is a schematic plan view showing a configuration of a solid-state imaging element as a semiconductor device according to a sixth embodiment. 40 is a schematic cross-sectional view (A) of the portion along the XLIA-XLIA line of FIG. 40 and a schematic cross-sectional view of the portion along the XLIB-XLIB line of FIG. 40, which also serves as a method of manufacturing the semiconductor device of the second embodiment. And. It is the schematic plan view which extracted the principal point of one Embodiment. It is the schematic plan view which extracted the principal point of one Embodiment.

Hereinafter, an embodiment will be described with reference to the drawings.
(Embodiment 1)
First, a semiconductor device in a wafer state will be described as an embodiment.

  With reference to FIG. 1, a plurality of chip regions IMC for solid-state imaging elements are formed on a semiconductor wafer SW. Each of the plurality of chip regions IMC has a rectangular planar shape and is arranged in a matrix.

  With reference to FIG. 1 and FIG. 2, a solid-state imaging device composed of a plurality of light receiving elements is formed in each of the plurality of chip regions IMC. However, in the vicinity of the outer periphery of each chip region IMC, a peripheral circuit for controlling a light receiving element such as a photodiode is formed. The peripheral circuit is formed as a so-called CMOS (Complementary Metal Oxide Semiconductor) transistor circuit in an outer peripheral region of a region where a plurality of light receiving elements are formed in the chip region IMC, for example.

  In the semiconductor wafer SW, a dicing line region DLR is formed between the plurality of chip regions IMC. When the semiconductor wafer SW is diced in the dicing line region DLR, the semiconductor wafer SW is divided into a plurality of semiconductor chips.

  A mark MK (alignment mark or misalignment inspection mark) used when a semiconductor device such as a solid-state image sensor is formed is usually formed on the dicing line region DLR. However, the mark MK may be formed on the chip area IMC. When the mark MK is formed on the chip region IMC, the mark MK is preferably formed in the vicinity of the end of the chip region IMC.

  Referring to FIG. 3, each of a plurality of chip regions IMC, that is, diced semiconductor chips, is configured as a semiconductor substrate made of, for example, silicon. However, for example, germanium may be used instead of silicon, and a semiconductor substrate made of a different semiconductor material may be used depending on the wavelength of incident light when the solid-state imaging device is used. A plurality of light receiving elements TMI are arranged on the main surface of the chip area IMC.

  In the chip region IMC, a plurality of light receiving elements TMI are arranged in both the vertical direction (first direction) in the drawing and the horizontal direction (second direction) in the drawing that intersects (for example, substantially orthogonal) to the chip region IMC. That is, a plurality of light receiving elements TMI are arranged in a matrix in the chip area IMC.

  On the main surface of the chip region IMC, a reset transistor RMI, a selection transistor SMI, and an amplification transistor AMI are arranged as other transistors in the vicinity of each of the light receiving elements TMI. In addition to these, a large number of peripheral circuits PMI are arranged on the main surface of the chip area IMC. Since the light receiving elements TMI are arranged in a matrix as described above, it is preferable that these transistors RMI, SMI, and AMI are also arranged in a matrix.

  The light receiving element TMI includes a part of the photodiode PD as a photoelectric conversion region. Here, a part of the photodiode PD means a region constituted by a pn junction of a p-type region and an n-type region in contact with the p-type region, as will be described later. The photodiode PD is used to convert received light into an electric signal, that is, an electric charge such as an electron, by a pn junction. In other words, the light receiving element TMI is connected to the photodiode PD, thereby converting the charge converted by the photodiode PD into a voltage and then transferring it to another transistor (such as the amplification transistor AMI). Function.

  Specifically, the light receiving element TMI includes a photodiode PD, a transfer transistor gate electrode TGE, and a capacitance region FD. Since a part of the photodiode PD is a region that supplies light by receiving light, it corresponds to a source region of a so-called MOS (Metal Oxide Semiconductor) transistor. The transfer transistor gate electrode TGE corresponds to the gate electrode of a general MOS transistor, and has the same function as the gate electrode of a general MOS transistor. The capacitor region FD corresponds to a drain region of a general MOS transistor because the charge supplied from the photodiode PD is converted into an electric signal (voltage) and transferred to another transistor. For this reason, the light receiving element TMI as a whole can be considered as a transfer transistor having the same configuration as the MOS transistor.

  The reset transistor RMI, the selection transistor SMI, and the amplification transistor AMI all have the same configuration as a general MOS transistor, and in FIG. 3, the activity corresponding to the source region, drain region, and channel region of each of these transistors. The areas ACR are arranged in a straight line. In FIG. 3, there are a reset transistor gate electrode RGE which is a gate electrode of the reset transistor RMI, a selection transistor gate electrode SGE which is a gate electrode of the selection transistor SMI, and an amplification transistor gate electrode AGE which is a gate electrode of the amplification transistor AMI. They are arranged in a straight line.

  The reset transistor RMI has a function of resetting the electric charge supplied to the capacitor region FD, and the selection transistor SMI selects any one row or one column among the rows and columns in which the plurality of light receiving elements TMI are arranged. It is a transistor for doing. The amplification transistor AMI is used to read a voltage applied to the drain region of the amplification transistor AMI by the selection circuit SMI or the booster circuit as the peripheral circuit PMI as an amplified signal from the source region of the amplification transistor AMI. The peripheral circuit PMI can be used as a general MOS transistor, for example, as in the other cases.

  In particular, when forming a chip region IMC as a large-sized solid-state imaging device, a plurality of exposure steps are performed using a plurality of masks having different patterns. That is, in the chip region IMC, a plurality of, for example, three regions A, B, and C formed by exposure at different times are formed. Next, with reference to FIGS. 4-7, the procedure and aspect of a multiple times of exposure process are demonstrated in detail.

  Referring to FIG. 4, specifically, thin film FLM for forming a pattern is formed on the main surface of semiconductor substrate SUB made of, for example, a silicon single crystal constituting chip region IMC. Here, polycrystalline silicon or silicon oxide film for forming a pattern is collectively expressed as a thin film FLM. Next, a photoresist PHR as a photosensitive material is applied on the thin film FLM.

Next, using the mask MK _A mask pattern MP _A is formed, the area A (first area) only to the normal exposure step of the main surface of the semiconductor substrate SUB is made. By this processing, for example, the photoresist PHR in the region A becomes a state having the photosensitive portion PHR _A and the non-photosensitive portion PHR _B. Note for exposure in this time region B (second region) and the region C is not done, photoresist PHR of these regions maintains the initial state as the untreated section PHR _C.

Referring to FIG. 5, next, a normal exposure process is performed only on region B (first region) of the main surface of semiconductor substrate SUB, using mask MK _B on which mask pattern MP _B is formed. The By this processing, for example, the photoresist PHR in the region B has a photosensitive portion PHR _A and a non-photosensitive portion PHR _B, and the photoresist PHR in the region C (second region) is still an unprocessed portion PHR _C. Maintained.

Referring to FIG. 6, next, a normal exposure process is performed only on region C of the main surface of semiconductor substrate SUB using mask MK _C on which mask pattern MP _C is formed, so that region C is obtained. The photoresist PHR has a photosensitive portion PHR _A and a non-photosensitive portion PHR _B.

  Referring to FIG. 7, all the photoresists in region A, region B, and region C are formed as a resist pattern (not shown) by a normal development process, and the pattern of thin film FLM is formed by normal etching using this resist pattern. Are formed as a pattern FLP.

  In FIG. 3, the peripheral circuits PMI for the regions A, B, and C are all different from each other so that the masks for forming the regions A, B, and C can be easily understood. It is shown. The same applies to FIGS. 4 to 7.

  In one embodiment, in the region where the plurality of light receiving elements TMI are arranged in a matrix, the region A and the region B, and the region including the boundary between the region B and the region C are related to the horizontal direction in the figure. The pitch P2 of the light receiving elements TMI is larger than the repetitive pitch P1 of the light receiving elements TMI in the left and right directions in the region other than the region including the boundary portion.

  Here, the repetition pitch P1 in the left-right direction in the figure is, for example, any one point A that constitutes one light-receiving element TMI among a plurality of light-receiving elements TMI in the region A, one light-receiving element TMI, and the left-right direction in the figure In other light receiving elements TMI adjacent to each other, the distance in the left-right direction in the drawing with respect to another point B corresponding to the same location as the point A is meant. Therefore, the distance between the point B and the point C in the figure in the left-right direction also corresponds to the repetition pitch P1.

  The region A and the region B are disposed adjacent to each other, and the region B and the region C are disposed adjacent to each other. Here, it is considered that there is a dividing line SPL extending along the vertical direction in the figure at the boundary between the region A and the region B and at the boundary between the region B and the region C. At this time, within a region where the plurality of light receiving elements TMI are arranged in a matrix, a pitch P2 of the pair of light receiving elements TMI adjacent to each other with respect to the horizontal direction in the figure crossing the dividing line SPL is The pair of light receiving elements TMI adjacent to each other in the horizontal direction in the figure that does not cross the dividing line SPL is larger than the repetition pitch P1 in the horizontal direction in the figure.

  In other words, the distance between point B and point C in FIG. 3 is larger than the distance between point A and point B in FIG. Hereinafter, when considering the repetitive pitch, an area defined by a pitch including (crossing) the dividing line SPL is referred to as a pitch (for example, P2 in FIG. 3) straddling the dividing line SPL, and does not include the dividing line SPL (crossing or the like). A region defined by the pitch in the region) is a repetitive pitch (for example, P1 in FIG. 3), in other words, a pitch P1 that does not straddle the dividing line SPL.

  Next, consider the interval between a pair of light receiving elements TMI adjacent to each other in the horizontal direction in the figure. Here, the interval refers to the element isolation region SPT (see FIG. 7) sandwiched between the edges EDG (see FIG. 7) that are the outer peripheral portions of one light receiving element and another light receiving element adjacent thereto. It means the minimum width (in the horizontal direction). In the element isolation region SPT sandwiched between the edges EDG, patterns such as the light receiving element TMI and the active region ACR are not formed.

  At this time, in the region where the plurality of light receiving elements TMI are arranged in a matrix, a distance d2 between the pair of light receiving elements TMI adjacent to each other with respect to the horizontal direction in the figure crossing the dividing line SPL is The distance between the pair of light receiving elements TMI adjacent to each other in the horizontal direction in the figure that does not cross the dividing line SPL is larger than the interval d1 in the horizontal direction in the figure. Hereafter, when considering the above-mentioned distance, the distance in the area defined by the distance including (crossing) the dividing line SPL is referred to as the distance (for example, d2 in FIG. 3) across the dividing line. For example, the dividing line in the area A An interval that does not include SPL (does not cross) (for example, d1 in FIG. 3), in other words, is distinguished from an interval d1 that does not straddle the dividing line SPL.

  Referring to FIG. 3 again, the distance d2 in the horizontal direction of the figure in the region straddling the dividing line is more preferably twice or more the distance d1 in the horizontal direction of the figure in region A. For example, when the distance d1 is 1 μm, the distance d2 is more preferably 2 μm or more. Actually, the dividing line SPL corresponds to a boundary line between two exposure areas formed at different times, and the dividing line SPL is formed as a so-called dividing line SPL on the main surface of the chip area IMC. It is possible to verify the dividing line from the chip area IMC of the product. A step on the surface is formed on the dividing line, and this step can also be confirmed when crossing the dividing line in the horizontal direction of the figure.

  Next, a method for manufacturing a semiconductor device according to an embodiment will be described with reference to FIGS. Referring to FIG. 8, each of FIGS. 9A to 22A shows a portion along the line AA in FIG. 8, that is, an aspect of each process in which the light receiving element TMI is formed. Each of FIGS. 9B to 22B shows a portion along the line BB in FIG. 8, that is, each step in which the reset transistor RMI, the selection transistor SMI, and the amplification transistor AMI are formed. An embodiment is shown.

  Referring to FIGS. 9A and 9B, first, a semiconductor substrate SUB having a main surface is prepared. The semiconductor substrate SUB is preferably a semiconductor wafer SW (see FIG. 1) made of, for example, a single crystal of silicon having n-type impurities. Next, in order to reduce the generation of stress and protect the main surface of the semiconductor substrate SUB, a silicon oxide film OX is formed as a pad oxide film by, for example, a thermal oxidation method. Further, for example, a silicon nitride film NF is laminated on the silicon oxide film OX by a CVD (Chemical Vapor Deposition) method.

  Next, a photoresist PHR made of photosensitive organic molecules is applied on the silicon nitride film NF, and the silicon nitride film NF in a region where the element isolation region SPT is to be formed is removed by a normal photolithography technique and etching. Etching may be performed so that the silicon oxide film OX immediately below the removed silicon nitride film NF becomes slightly thin.

Referring to FIGS. 10A and 10B, after the photoresist PHR is oxidized and decomposed and removed to carbon dioxide CO ₂ , the silicon oxide film OX in the region where the silicon nitride film NF is removed is oxidized. As a result of this oxidation, the silicon oxide film OX grows to increase its thickness, thereby forming an element isolation region SPT. The element isolation region SPT is to electrically isolate regions where the light receiving element TMI and other transistors are formed.

  Since the oxygen atmosphere used for this oxidation does not pass through the silicon nitride film NF, the silicon oxide film OX immediately below the silicon nitride film NF is not oxidized. Thereafter, the silicon nitride film NF and the silicon oxide film OX immediately below the silicon nitride film NF are removed by etching.

  With reference to FIGS. 11A and 11B, first, a pattern of a photoresist PHR is formed so as to cover the surface of the element isolation region SPT by a general photolithography technique. Next, using this photoresist PHR pattern, a p-type well region PWL such as boron is formed in the semiconductor substrate SUB by a normal ion implantation technique and heat treatment.

  Next, an impurity having a conductivity type opposite to that of the p-type well region PWL, that is, an n-type impurity is thinner than that of the p-type well region PWL by a normal ion implantation technique on almost the entire surface of the p-type well region PWL. Injected to a concentration. The region into which the n-type impurity is implanted is a relatively shallow region indicated by “X” in the drawing and near the surface of the p-type well region PWL. This process is so-called channel doping, and is a process for adjusting the threshold value of the formed transistor.

  Referring to FIGS. 12A and 12B, a silicon oxide film, for example, is formed on the main surface of the semiconductor substrate SUB by a normal thermal oxidation method, and is covered by a normal CVD method so as to cover the silicon oxide film. A polycrystalline silicon film is formed. Next, these silicon oxide film and polycrystalline silicon film are patterned so as to remain in a desired region by a normal photolithography technique using a photoresist PHR and etching. As a result, these become the gate insulating film GI and the transfer transistor gate electrode TGE, respectively, in the region where the light receiving element is formed. In the region where the reset transistor is formed, the gate insulating film GI and the gate electrode RGE for the reset transistor are respectively formed. In the region where the selection transistor is formed, the gate insulating film GI and the gate electrode SGE for the selective transistor are formed. In the region to be formed, the gate insulating film GI and the amplification transistor gate electrode AGE are formed.

  Note that these gate electrodes TGE and the like are preferably formed as a polycrystalline silicon film containing conductive impurities.

Referring to FIGS. 13A and 13B, particularly in the region where the photodiode PD is formed in the region where the light receiving element of FIG. Then, an n-type impurity region NWL such as arsenic or phosphorus is formed by using a normal photolithography technique and ion implantation technique. The impurity concentration of n-type impurity region NWL is preferably an n ⁻ region lower than that of p-type well region PWL. Thus, as described above, the photodiode PD is formed as a photoelectric conversion region by a pn junction between the p-type well region PWL (p-type region) and the n-type impurity region NWL (n-type region).

  Referring to FIGS. 14A and 14B, the surface of the semiconductor substrate SUB in the p-type well region PWL is called a so-called LDD (Light Doped Drain) using a normal photolithography technique and ion implantation technique. A low concentration n-type region NR1 is formed.

  Referring to FIGS. 15A and 15B, first, for example, a silicon oxide film and a silicon nitride film are laminated and deposited in this order on the entire main surface of semiconductor substrate SUB. Thereafter, the silicon oxide film and the silicon nitride film remain on the side walls of the gate electrode TGE and the like by normal etch back, and the silicon oxide film and the silicon oxide film in other regions are removed. As a result, a sidewall insulating film SWI including a sidewall insulating film SWI1 of a silicon oxide film and a sidewall insulating film SWI2 of a silicon nitride film is formed on the sidewall of the gate electrode TGE and the like.

Referring to FIGS. 16A and 16B, in the region where the capacitance region of the light receiving element is formed, and in the region where the source region and the drain region (active region ACR in FIG. 3) such as the reset transistor RMI are formed. On the other hand, the n-type region NR2 is formed by ordinary photolithography and ion implantation techniques. In addition to the photoresist pattern formed by the photolithography technique described above, the n-type region NR2 is formed by using the sidewall insulating film SWI as a processing mask. The n-type region NR2 is an n ⁺ region having a higher impurity concentration than the low-concentration n-type region NR1.

  A region NR that is a combination of the low-concentration n-type region NR1 and the n-type region NR2 in FIG. 16A becomes the capacitance region FD of the light receiving element TMI. In addition, a region NR that is a combination of the low-concentration n-type region NR1 and the n-type region NR2 in FIG. 16B becomes an active region ACR in which a source region and a drain region such as a reset transistor RMI are formed.

  Referring to FIGS. 17A and 17B, an interlayer insulating film II made of a silicon oxide film is formed by using, for example, a CVD method.

  Referring to FIGS. 18A and 18B, interlayer insulating film II is polished so as to have a flat upper surface by a chemical mechanical polishing method called CMP (Chemical Mechanical Polishing). When the interlayer insulating film II contains impurities such as boron and phosphorus, the upper surface thereof may be planarized by heat treating the interlayer insulating film II instead of CMP. Further, via holes VA are formed in the interlayer insulating film II so as to reach the n-type region NR by a normal photolithography technique and etching technique.

  Next, a contact CT made of, for example, tungsten is filled in the via hole VA. In this process, for example, a CVD method is used, and a tungsten thin film is also formed on the interlayer insulating film II. However, the tungsten film on the interlayer insulating film II is removed by CMP. Thereafter, a thin film made of, for example, titanium nitride (TiN) and a thin film made of aluminum copper (AlCu) are formed on interlayer insulating film II by, for example, sputtering. Then, metal wiring Al1 made of titanium nitride and aluminum copper is formed so as to cover the upper surface of contact CT by ordinary photolithography and etching. However, the configuration of the metal wiring Al1 is not limited to this, and may be a configuration including only a single aluminum thin film, for example.

  Referring to FIGS. 19A and 19B, the interlayer insulating film II is formed again on the interlayer insulating film II and the metal wiring Al1, and after the surface is planarized in the same manner as described above, a desired region is obtained. A via hole VA is formed (on the metal wiring Al1). The interlayer insulating film II and the via hole VA are formed by the same procedure as the interlayer insulating film II and the via hole VA formed in the step of FIG. Since the etching selectivity between the interlayer insulating film II and the metal wiring Al1 is different from each other, the etching of the interlayer insulating film II from the upper side to the lower side can be easily finished when the metal wiring Al1 is reached.

  Next, a contact CT made of tungsten, for example, is filled in the via hole VA. The filling method of the contact CT is the same procedure as the filling of the contact CT into the via hole VA in the step of FIG.

  Thereafter, similarly to the above, metal wiring Al2 made of, for example, a thin film of titanium nitride and a thin film of aluminum copper is formed so as to cover the upper surface of contact CT. Here, two layers of metal wirings Al1 and Al2 are formed, but the number of metal wirings stacked is arbitrary.

  Referring to FIGS. 20A and 20B, a passivation film PA made of, for example, a silicon nitride film is formed by, for example, a CVD method so as to cover interlayer insulating film II and metal wiring Al2.

  Next, an organic planarizing film ORG is formed by, for example, a CVD method. The organic planarizing film ORG is formed by applying an organic material coating solution and drying it. The organic flattening film ORG is not only a general resist material used for pattern formation, but also various synthetic resins such as acrylic resin, vinyl chloride resin, polyester resin, natural rubber, synthetic rubber, etc. Is formed by a coating solution in which is dissolved in an appropriate organic solvent. However, here, an inorganic flattening film may be used instead of the organic flattening film ORG.

  Referring to FIGS. 21A and 21B, color filter COL is formed on organic planarizing film ORG in the region where the light receiving element of FIG. 21A is formed.

  “R” and “G” in the figure mean that the color filter COL is made of a material that transmits only red (R) or green (B) light. The color filter COL is formed of a material that transmits only light having a wavelength of any one of red (R), green (G), and blue (B). The color of light transmitted through each of a pair of adjacent light receiving elements TMI among a plurality of light receiving elements TMI arranged in a matrix is preferably different. Further, it is preferable that the light receiving elements TMI that transmit green light are distributed so as to be larger than the light receiving elements TMI that transmit red or blue light.

  As an example, a color filter COL that transmits green is formed immediately above the photodiode PD in FIG. A color filter COL that transmits red is formed thereon, and the red color filter COL formed so as to overlap the green color filter COL is then removed.

  Referring to FIGS. 22A and 22B, a planarization film FLT may be formed again on the color filter COL. As the planarizing film FLT, a film similar to the organic planarizing film ORG may be formed. As a result, a step due to the color filter COL can be eliminated.

  Thereafter, a microlens LNS is formed immediately above the photodiode PD. A material for forming the microlens LNS is applied and then patterned, and a heat treatment called reflow is performed, so that a part of the surface becomes a curved shape.

  9 to 22, other transistors such as the light receiving element TMI and the reset transistor RMI shown in FIG. 3 are formed in the chip region IMC of the semiconductor wafer SW.

  9 to 22 show only one light receiving element TMI among the light receiving elements TMI arranged in the matrix shown in FIG. However, referring again to FIGS. 4 to 7, each step (such as exposure) in FIGS. 9 to 22 is actually performed on the region A (first region) in the chip region IMC in FIG. Next, the process is performed on the area B (second area) in the chip area IMC shown in FIG. 3, and then on the area C shown in FIG.

  That is, for example, the process shown in FIG. 9 is first performed on region A in FIG. 3, whereby a plurality of configurations shown in FIGS. 9A and 9B are arranged in a matrix in region A in FIG. Next, the same processing is performed on the region B in FIG. 3, so that a plurality of configurations shown in FIGS. 9A and 9B are arranged in a matrix in the region B in FIG. Formed as follows. Such processing (multiple exposure steps) is repeated in each step after FIG. 10 to form a semiconductor device (solid-state imaging device) having a cross-sectional shape as shown in FIG.

  Referring to FIGS. 23A and 23B, these are formed in a range straddling region A and region B in FIG. 3, and a total of three light receiving elements TMI (A) and other transistors (B), etc. Is shown in a sectional view. As described above, the region A and the region B are in contact with each other so that the exposure dividing line SPL extending along the vertical direction in the figure is located at the boundary between the region A and the region B. doing. The left and right pitch P2 in the figure and the left and right interval d2 in the figure of the adjacent light receiving elements TMI across the dividing line SPL, for example, of the adjacent light receiving elements TMI in the region A that do not straddle the dividing line SPL, It is formed so as to be larger than the repetition pitch P1 in the horizontal direction in the figure and the interval d1 in the horizontal direction in the figure. Here, in particular, it is preferable that d2 ≧ 2d1.

  Next, the effects of the embodiment will be described with reference to the comparative examples of FIGS.

  Referring to FIGS. 24 and 25, the repetition pitch and interval of the light receiving elements TMI are the same value (P1, d1 respectively) in the entire region of the chip region IMC including the dividing line SPL as in the first comparative example. In some cases, the distance between the edge of the pattern of the light receiving element TMI (for example, the point B in the region A) and the closest dividing line SPL (the dividing line SPL at the boundary between the region A and the region B) is very short. Become. This is because the above-described P1 and d1 have become very short with the miniaturization and high integration of the semiconductor device.

  26 and 27, as in the second comparative example, similar to FIG. 24 and FIG. 25, the repetition pitch and interval of the light receiving elements TMI are the same in all areas of the chip area IMC (P1 respectively). , D1) Consider a case where the chip region IMC in which the light receiving elements TMI and the like are arranged is formed by using the dividing line SPL near the center of the photodiode PD of the light receiving element TMI. Even in this case, if the photodiode PD is further miniaturized, the distance between the edge of the photodiode PD and the dividing line SPL cannot be secured. Similarly, the distance between the edge of the pattern such as the peripheral circuit PMI and the active region ACR and the dividing line SPL is shortened.

  In the pattern formed by the exposure process, in the vicinity of the end (boundary part) of the exposed region, accuracy of the pattern size and shape due to light interference during exposure may be deteriorated. For this reason, if the distance between the extreme end of the exposed region and the edge of the pattern formed by exposure is shortened, the pattern may deteriorate in accuracy such as dimensions and shape in the vicinity of the edge.

  Therefore, as in one embodiment (FIG. 3), if the pitch P2 and the interval d2 in the region straddling the dividing line are made longer than the repetition pitch P1 and the interval d1 in the region not straddling the dividing line, the dividing line SPL and the light reception are received. The distance from the edge of the pattern of the element TMI can be increased. The distance to the edge here refers to the distance x between the dividing line SPL in FIG. 7 and the edge EDG of the pattern with reference to FIG. 7 again. By increasing the distance x, the pattern formed can reduce the possibility of causing problems such as variations in size and shape even in the vicinity of the edge.

  Further, as the distance between the edge of the pattern of the light receiving element TMI and the dividing line SPL becomes longer, the interval between the edge of the pattern of other transistors such as the reset transistor RMI and the dividing line SPL is similarly increased in the active region ACR. be able to. For this reason, the dimension and shape of the pattern of other transistors can be stabilized.

  Even if the repetition pitch and the interval are increased, the miniaturization of the semiconductor device is progressing, and the absolute value of the repetition pitch and the interval is very small, so that the integration of the semiconductor device is hardly affected.

  Further, by setting the distance d2 to be not less than twice the distance d1, the distance x between the dividing line SPL and the pattern edge EDG shown in FIG. 7 can be made longer, and the accuracy of the dimension, shape, etc. of the pattern is deteriorated. It can suppress more reliably.

  In addition, the above is the effect which assumed that the distance of the dividing line SPL and the edge of the pattern of the light receiving element TMI generally becomes long with said pitch and space | interval becoming long. For example, the case where the interval does not become long because the dividing line SPL is located near the edge even though the pitch and the interval are long is not considered here.

(Embodiment 2)
The present embodiment differs from the first embodiment in the repetition pitch of the region straddling the dividing line SPL. The configuration and manufacturing method of the present embodiment will be described below with reference to FIGS.

  Referring to FIG. 28, also in the present embodiment, as in the first embodiment, the pitch P2 of the region straddling the dividing line SPL is larger than the repetitive pitch P1 of the region not striding the dividing line SPL. However, in the present embodiment, the pitch P2 of the region straddling the dividing line is more than twice the repetitive pitch P1 of the region not straddling the dividing line SPL. In this respect, the present embodiment is different from the first embodiment. ing.

  Referring to FIGS. 29A and 29B, these are formed in a range straddling region A and region B in FIG. 3, and a total of three light receiving elements TMI (A) and other transistors (B), etc. Is shown in a sectional view. Even in the present embodiment, it is formed by a manufacturing method that undergoes a plurality of exposure steps, which is basically the same as the manufacturing method of the first embodiment shown in FIGS. 9 to 23, but the dividing line SPL is formed as described above. It is formed so that the pitch P2 of the straddling region is at least twice the repetitive pitch P1 of the region not straddling the dividing line SPL. 29 (A) and 29 (B) show an aspect of the formed product as a result of the manufacturing method basically similar to that shown in FIGS. 9 to 22, and FIGS. 29 (A) and 29 (B) show FIG. ) And (B) are different in that P2 ≧ 2P1 is indicated.

  In the present embodiment, as a result of forming P2 ≧ 2P1, as in the first embodiment, the interval d2 between the adjacent light receiving elements TMI in the region straddling the dividing line SPL straddles the dividing line SPL. It is larger than the interval d1 between the adjacent light receiving elements TMI in the region that is not.

  Also in the present embodiment, the distance between the dividing line SPL and the edge of the pattern of the light receiving element TMI can be increased in a region straddling the dividing line SPL. If the pitch P2 of the region straddling the dividing line SPL is set to be not less than twice the repetitive pitch P1 of the region not striding the dividing line SPL as in the present embodiment, the adjacent light receiving elements TMI in the region straddling the dividing line SPL The interval d2 is larger than the interval d2 in the first embodiment. For this reason, the effect of lengthening the distance between the dividing line SPL and the edge of the pattern of the light receiving element TMI in the region straddling the dividing line SPL can be further enhanced.

  If the pitch P2 of the region straddling the dividing line SPL is set to be not less than twice the repetitive pitch P1 of the region not straddling the dividing line SPL, the value of the interval d2 is the pattern of the light receiving element TMI shown in FIG. It becomes larger than the dimension TR1 in the left-right direction. That is, there is a space for forming the light receiving element TMI in the element isolation region SPT defined by the interval d2. For this reason, the pattern of the light receiving element TMI can be supplemented to the region of the interval d2 by performing the data processing of the pixel data after forming the patterns shown in FIGS. 28 and 29 by a plurality of exposure steps.

  Even when data processing as described above is not performed, data for correcting errors in the size and shape of the pattern formed in the vicinity of the dividing line after the dividing line is normally positioned by a plurality of exposure processes. It is necessary to perform processing. For this reason, even if the data processing for supplementing the pattern of the light receiving element TMI in the region of the interval d2 as described above is performed, the work efficiency is not lowered.

(Embodiment 3)
The present embodiment is different from the first embodiment in the configuration of the photodiode PD and the arrangement of the dividing lines SPL. Hereinafter, the configuration and manufacturing method of the present embodiment will be described with reference to FIGS. 30 and 31. FIG.

  Referring to FIG. 30, also in the present embodiment, as in the first embodiment, the pitch P2 of the region straddling the dividing line SPL is larger than the repeating pitch P1 of the region not striding the dividing line SPL. However, the distance between adjacent light receiving elements TMI is substantially equal to d1 in both the region straddling the dividing line SPL and the region not striding the dividing line SPL. That is, there is no region where the interval between the light receiving elements TMI is d2.

  In the present embodiment, the light receiving element TMI is arranged so as to straddle the dividing line SPL. In other words, the boundary between the region A and the region B and the boundary between the region B and the region C are located so as to be divided through the light receiving element TMI, and the light receiving element TMI is arranged at the boundary. ing. Here, in particular, the dividing line SPL is preferably located so as to divide the photodiode PD of the light receiving element TMI.

  The dividing line SPL may be positioned so as to divide the photodiode PD of the light receiving element TMI. Even in this case, the function and characteristics of the light receiving element TMI across the dividing line SPL are not greatly affected. In order to suppress a large influence on the function and characteristics, it is preferable to perform data processing for correcting the pattern of the light receiving element TMI straddling the dividing line SPL as described above.

  The length PH2 in the horizontal direction of the figure in the region straddling the dividing line SPL, that is, the photodiode PD of the light receiving element TMI including the dividing line SPL, in the region not straddling the dividing line SPL, that is, including the dividing line SPL. The light receiving element TMI, in particular, the photodiode PD, is longer than the length PH1 in the horizontal direction of the figure.

  Other transistors to which a signal such as a voltage from the light receiving element TMI is transferred are arranged in a region immediately below the light receiving element TMI in FIG. However, as shown in FIG. 30, even if the light receiving element TMI (photodiode PD) in the region straddling the dividing line SPL becomes longer, the active region ACR of the other transistors immediately below the light receiving element TMI may not become longer. In this case, the dividing line SPL is positioned so as not to pass through the active region ACR.

  The present embodiment is different from the first embodiment in the above points, and the other points are the same as those of the first embodiment. That is, for example, in the present embodiment, the configuration of the first embodiment is combined, for example, the interval between the edges of the patterns of the adjacent light receiving elements TMI closest to the dividing line SPL (interval in the region straddling the dividing line SPL) is It is good also as a structure which becomes larger than the space | interval (space | interval in the area | region which straddles dividing line SPL) of the pattern of the light receiving element TMI mutually adjacent other than the above.

  Referring to FIGS. 31A and 31B, these cross-sectional views are the structures of regions similar to FIGS. 23A and 23B and FIGS. 29A and 29B in this embodiment. Is shown in a cross-sectional view. Also in the present embodiment, it is formed by a manufacturing method that undergoes a plurality of exposure steps similar to the manufacturing method of the first embodiment shown in FIGS. However, in the present embodiment, the light receiving element TMI is arranged in a region straddling the dividing line SPL so as to straddle the dividing line SPL. That is, a part of the light receiving element TMI is formed in the step of forming the region A, and a part other than the part of the light receiving element TMI is formed in the step of forming the region B, and both are connected by the dividing line SPL which is a boundary. Arranged so that.

  The length PH2 of the light receiving element TMI, particularly the photodiode PD, in the horizontal direction in the figure, which is divided by the dividing line SPL (in the region straddling the dividing line SPL) is not divided by the dividing line SPL (does not cross the dividing line SPL). The light receiving element TMI (in the region), in particular, the photodiode PD is formed to be longer than the length PH1 in the left-right direction in the figure.

  In the present embodiment, the dividing line SPL is positioned so as to straddle the light receiving element TMI (photodiode PD). However, the length PH2 of the light receiving element TMI straddling the dividing line SPL is not longer than the dividing line SPL. Longer than length PH1. Therefore, also in the present embodiment, the distance between the dividing line SPL and the edge of the pattern of the light receiving element TMI across the dividing line SPL can be increased.

(Embodiment 4)
This embodiment is different from the first embodiment in the arrangement of the light receiving elements. Hereinafter, the configuration and manufacturing method of the present embodiment will be described with reference to FIGS.

  Referring to FIG. 32, in a region straddling dividing line SPL, that is, a region in which at least a part of a plurality of light receiving elements TMI including dividing line SPL does not straddle dividing line SPL (as in the third embodiment). In other words, the light receiving element has a planar aspect inverted with respect to the light receiving element TMI not including the dividing line SPL (similar to the third embodiment).

  Note that the plurality of light receiving elements TMI arranged so as to straddle the dividing line SPL may be the light receiving elements TMI1 having the above-described inverted plane aspect with respect to the first direction in which the dividing line SPL extends. Here, “continuous with respect to the first direction” means, for example, two or more adjacent to each other with respect to the first direction in which the dividing line SPL extends among the plurality of light receiving elements TMI arranged so as to straddle the dividing line SPL. This means that each of the light receiving elements TMI is a light receiving element TMI1 having an inverted plane mode.

  However, in the present embodiment, the light receiving element TMI1 has a planar form in which all of the plurality of light receiving elements TMI in the region straddling the dividing line SPL are inverted, and the plurality of light receiving elements TMI in the region not straddling the dividing line SPL. All of the light receiving elements TMI2 are not the light receiving element TMI1 having the above-described inverted plane mode. The arrangement and configuration of the light receiving element TMI2 are exactly the same as those of the light receiving element TMI described in the first to third embodiments, and the arrangement and configuration of the light receiving element TMI1 having an inverted planar aspect have an inverted planar aspect. Is the same as the light receiving element TMI described in the first to third embodiments.

  Here, the reversal means that the rotation is about 180 ° around the axis perpendicular to the paper surface (around the axis). That is, the light receiving element TMI in the region that does not straddle the dividing line SPL is the light receiving element TMI2 in which the photodiode PD is disposed on the left side of FIG. 32 and the capacitor region FD is disposed on the right side, whereas in the region straddling the dividing line SPL. All of the light receiving elements TMI are light receiving elements TMI1 having a planar form inverted so that the capacitor region FD is disposed on the left side of FIG. 32 and the photodiode PD is disposed on the right side.

  As described above, the chip region IMC according to the present embodiment is such that the light receiving element TMI is inverted. The chip region IMC in this embodiment is different for one column (at least a part of them) of the plurality of light receiving elements TMI arranged in a matrix. This is different from the light receiving elements TMI arranged in the row.

  The light receiving element TMI1 having the inverted plane mode shares the capacitance region FD with the light receiving element TMI2 adjacent to the light receiving element TMI2 particularly on the left side of the drawing. In other words, the capacitance region FD of the light receiving element TMI1 having the inverted planar form and the capacitance region FD of the left light receiving element TMI2 are the same. However, the components of the light receiving element TMI other than the capacitance region FD, that is, the photodiode PD and the transfer transistor gate electrode TGE are shared by the light receiving element TMI1 and the light receiving element TMI2 having a pair of inverted planes adjacent to each other. The light receiving element TMI1 and the light receiving element TMI2 are separately provided.

  Further, the active region ACR such as the reset transistor RMI arranged in the region immediately below in FIG. 32 between the light receiving element TMI1 having an inverted plane mode in FIG. 32 and the light receiving element TMI2 adjacent to the left side thereof is also the chip region. It may be formed continuously on the main surface of the IMC, and may be formed integrally as if sharing the active region ACR. However, although not shown, the active regions ACR immediately below the light receiving element TMI1 having an inverted plane mode and the light receiving element TMI2 adjacent to the left side thereof may be discontinuous and formed separately.

  In FIG. 32, for example, the entire length (in the horizontal direction in the figure) of the light receiving element TMI is all TR1 as described above, and the length of the photodiode PD (in the horizontal direction in the figure) of the light receiving element TMI is Similarly, it is assumed that all are PH1, and the length of the capacitor region FD is f regardless of inversion or non-inversion. In addition, it is assumed that the interval between the edges of the photodiode PD in a region that does not cross the dividing line SPL is a constant value d1.

  The present embodiment is different from the first embodiment in the above points, and the other points are the same as those of the first embodiment.

  Referring to FIGS. 33A and 33B, in the semiconductor device shown in FIG. 32, a part (all in this case) of light receiving element TMI1 in the region straddling dividing line SPL is inverted with respect to other light receiving elements TMI2. To be formed. Specifically, the light receiving element TMI on the left side of FIG. 33 (light receiving element TMI2) and the light receiving element TMI adjacent to it (light receiving element TMI1 having an inverted plane mode) are formed of a low-concentration n-type region NR1 and an n-type region NR2. The capacity region FD consisting of is shared. For this reason, the contact CT or the like formed immediately above is also shared between the pair of light receiving elements TMI.

  The configuration of the present embodiment may be appropriately combined with the configuration of each of the above-described embodiments, for example, by changing the repetition pitch or various intervals.

  According to the first example of the present embodiment shown in FIGS. 32 and 33, by forming the light receiving element TMI1 having an inverted plane mode, the capacitance region FD is shared with the light receiving element TMI2 adjacent thereto. Is possible. For this reason, the occupied space in the left-right direction in the drawing is reduced by d1 + f as compared with the case where the light receiving element TMI1 having the inverted planar mode is arranged as the normal light receiving element TMI2 without sharing the capacitance region FD. That is, for example, the interval d2 of the pattern immediately to the right of the straight line SPL in the figure is d2 = 2d1 + f.

  Since some of the light receiving elements TMI share the capacitance region FD in this way, space is saved, and thus the saved space can be applied to the distance from the dividing line SPL to the edge of the pattern. Therefore, as in the above embodiments, the distance from the dividing line SPL to the edge of the pattern can be made longer, and the pattern size and shape can be made more stable.

  Also, for the active region ACR, the active region ACR for the two light receiving elements TMI is continuously shared so that the distance between the pair of adjacent active regions ACR is longer than that when the active regions ACR are discontinuous. can do. Alternatively, for example, the interval between the reset transistor RMI and the selection transistor SMI adjacent to the reset transistor RMI can be increased, and the dividing line SPL can be located at the increased interval. For this reason, the distance between the edge of the pattern in the active region ACR and the dividing line SPL can be increased, and the dimensions and shapes of the patterns of other transistors can be stabilized.

  In the first example of the present embodiment shown in FIGS. 32 and 33, the photodiode PD of the light receiving element TMI1 having the inverted plane mode is arranged so as to straddle the dividing line SPL. The length of the photodiode PD of the light receiving element TMI1 having the same length as the photodiode PD of the chip region IMC not having the characteristics of the first example of the present embodiment is PH1, for example. However, referring to FIG. 34 and FIG. 35, in the second example of the present embodiment, the space is saved so that the length PH2 of the photodiode PD of the light receiving element TMI1 having the inverted planar aspect is longer than PH1. The portion may be allocated. In this case, PH2 = PH1 + d1 + f.

  In the second example as well, the light receiving element TMI1 having an inverted plane mode and the light receiving element TMI2 adjacent to the light receiving element TMI2 are arranged so as to share the capacitance region FD. Similarly to the first example of FIG. 32, for example, the entire length (in the horizontal direction in the figure) of the light receiving element TMI2 is all TR1 as described above, and the photodiode PD of the light receiving element TMI2 (in the horizontal direction in the figure) The length of the capacitor region FD is assumed to be f1. In FIG. 34, it is assumed that the interval between the edges of the photodiode PD is a constant value d1 in both the region straddling the dividing line SPL and the region not striding the dividing line SPL. Further, the length PH2 of the photodiode PD of the light receiving element TMI1 having an inverted planar aspect is longer than the length PH1, but the pitch between the point A and the point B is the pitch between the point B and the point C. Are both equal to P1.

  In this way, the distance from the dividing line SPL to the edge of the photodiode PD can be increased particularly when the photodiode PD is arranged so as to straddle the dividing line SPL. Furthermore, it has an excellent effect.

  In the first example and the second example of FIGS. 32 to 35, for example, similarly to the third embodiment, the light receiving element TMI is arranged so as to straddle the dividing line SPL. However, referring to FIGS. 36 and 37, in the third example of the present embodiment, for example, similarly to the first embodiment, light receiving elements TMI are arranged so as not to straddle dividing line SPL.

  In the third example, a light receiving element TMI1 having a planar aspect inverted in a region including the dividing line SPL, that is, a region straddling the dividing line SPL is arranged, and here is arranged in the vertical direction of the drawing in which the dividing line SPL extends. A light receiving element TMI1 having a planar aspect reversed to is arranged. In the third example, for example, the entire length of the light receiving element TMI (in the horizontal direction in the figure) is TR1, and the length of the photodiode PD (in the horizontal direction in the figure) of the light receiving element TMI is PH1. The length of the capacitor region FD is assumed to be f regardless of inversion or non-inversion. In addition, it is assumed that the interval between the edges of the photodiode PD in a region that does not cross the dividing line SPL is a constant value d1.

  In the third example, the light-receiving element TMI1 having an inverted planar aspect and the light-receiving element TMI2 adjacent to the light-receiving element TMI2 are arranged so as to share the capacitance region FD, and the space saved is the amount of the dividing line SPL. This is achieved by making the interval d2 between the adjacent light receiving elements TMI wider than the interval d1 in the region across the existing dividing line SPL. Specifically, d2 = 2d1 + f.

  In this way, when the dividing line SPL is located outside the photodiode PD, the distance from the dividing line SPL to the edge of the photodiode PD can be increased, and the same action as in the first example and the like described above. There is an effect.

  In addition, the light receiving element TMI1 having an inverted planar aspect that is originally disposed at the position where the light receiving element TMI2 is disposed basically functions in the same manner as the light receiving element TMI2. For this reason, in this embodiment, the total number of light receiving elements TMI formed over the entire chip area IMC is not substantially reduced. Therefore, it is possible to eliminate the deterioration of image quality due to the inversion of the light receiving element TMI.

(Embodiment 5)
The present embodiment basically has the same configuration as that of the fourth embodiment, and one column (at least a part of the columns) in which the plurality of light receiving elements TMI are arranged in a matrix form other columns. This is different from the light receiving element TMI arranged in the above. However, the present embodiment is slightly different from the fourth embodiment in the arrangement of the light receiving elements. Hereinafter, the configuration and manufacturing method of the present embodiment will be described with reference to FIGS. 38 and 39.

  Referring to FIG. 38, in the present embodiment, only a part of a plurality of light receiving elements TMI in a region straddling dividing line SPL, that is, including dividing line SPL (as in the third embodiment) is divided. This is the light receiving element TMI1 having a planar aspect that is inverted with respect to the light receiving element TMI that does not include the dividing line SPL in a region that does not cross the line SPL, that is, (as in the third embodiment). In this respect, the present embodiment is different from the fourth embodiment in which the light receiving element TMI1 has a planar form in which all of the light receiving elements TMI in the region straddling the dividing line SPL are inverted. In FIG. 38, the region C is not shown and only the region A and the region B are illustrated, but the region C may exist as in the other embodiments.

  Specifically, in the present embodiment, the plurality of light receiving elements TMI arranged in the vertical direction in the figure in the region straddling the dividing line SPL are alternately arranged with the light receiving elements TMI1 and TMI2 having an inverted plane mode. It is out. A semiconductor device is formed to have such an arrangement.

  The light receiving element TMI2 in the region straddling the dividing line SPL is arranged so as to share the capacitance region FD with the light receiving element TMI1 having an inverted planar aspect adjacent to the right side of the drawing. In addition, the light receiving element TMI1 having an inverted planar aspect adjacent to the light receiving element TMI2 in the vertical direction of the drawing along the dividing line SPL in the region straddling the dividing line SPL is adjacent to the light receiving element TMI2 adjacent to the left side of the drawing and the capacitance region FD. Arranged to share. Therefore, if attention is paid to the plurality of light receiving elements TMI arranged in the region straddling the dividing line SPL and the plurality of light receiving elements TMI adjacent to the right side of the light receiving element TMI in the drawing, the light receiving element TMI1 having an inverted planar aspect. Are arranged in a so-called staggered pattern in plan view.

  Also in the present embodiment, basically, as in the fourth embodiment, image quality deterioration due to the presence of the light receiving element TMI1 having the inverted planar aspect does not occur. Furthermore, variations (changes) other than image quality deterioration can be suppressed. This will be described below.

  If attention is paid to the light receiving element TMI1 having an arbitrary inverted plane aspect of the chip region IMC, in FIG. 38, all the light receiving elements TMI adjacent to this in the vertical direction and the horizontal direction in the figure are the light receiving elements TMI2. For this reason, image information can be supplied to the light receiving element TMI1 having an inverted plane mode with reference to the interpolation information of the image obtained from the surrounding light receiving element TMI2, and the change in the image quality of the entire solid-state imaging element can be suppressed.

  In the first example of the present embodiment shown in FIG. 38, for example, it is assumed that the entire length of the light receiving element TMI2 is TR1, and the length of the photodiode PD of the light receiving element TMI2 is PH1. Further, it is assumed that the interval between the edges of the adjacent light receiving elements TMI2 is d1. Since the light receiving element TMI1 having the inverted plane mode shares the capacitance region FD with the adjacent light receiving element TMI2, a space is saved by d1 + f in the horizontal direction of the drawing. In FIG. 38, this amount is applied to the length of the photodiode PD of the light receiving element TMI1 having the inverted planar aspect. For example, the length of the photodiode PD of the light receiving element TMI1 having the inverted planar aspect is PH2 = PH1 + d1 + f It has become. In this way, since the length of the light receiving element TMI1 having an inverted plane configuration arranged so as to pass through the dividing line SPL is larger than that of the light receiving element TMI2, the dividing line SPL and the dividing line The distance from the edge of the light receiving element TMI (photodiode PD) where the SPL is located can be increased, and the same effect as described above can be obtained.

  However, referring to FIG. 39, in the second example of the present embodiment, the length of the photodiode PD of the light receiving element TMI where the dividing line SPL is positioned is applied regardless of inversion or non-inversion. That is, the lengths of all the light receiving elements TMI1, TMI2 arranged so as to straddle the dividing line SPL are large. In this way, from the viewpoint that the distance between the dividing line SPL and the edges of all the light receiving elements TMI (photodiode PD) where the dividing line SPL is located can be increased, the operation is more effective than the first example of FIG. The effect is increased.

  In addition to the above, the configuration of the present embodiment may be appropriately combined with the configuration of each of the above embodiments by, for example, changing the repetition pitch and various intervals.

  Further, in the present embodiment, the light receiving elements TMI1 having the inverted planar form are arranged in a staggered manner, but the lengths of all the photodiodes PD of the light receiving elements TMI across the dividing line SPL are increased as shown in FIG. Thus, in order to achieve the operational effect of the present embodiment, for example, even if TMI1 having an inverted planar aspect is formed in a staggered pattern, dividing line SPL only needs to be positioned in a straight line. Therefore, since the end portion of the processing mask for forming the region A and the region B may be formed linearly, the processing mask can be easily formed.

(Embodiment 6)
Also in the present embodiment, as in the fourth and fifth embodiments, one column (at least a part of them) among the plurality of light receiving elements TMI arranged in a matrix is arranged in another column. It has a mode different from that of the light receiving element TMI. However, the light receiving element TMI of the present embodiment is not inverted. In the present embodiment, electrical connection between another transistor (such as a reset transistor RMI) and its upper layer in one column (at least a part of the plurality) of light receiving elements TMI arranged in a matrix. Is different from the other embodiments described above.

  Specifically, referring to FIG. 40 and FIG. 41, metal wirings Al1 and Al2 which are wirings for transmitting an electric signal from there to the periphery are arranged immediately above the other transistors. The other transistors arranged in the region that does not cross the dividing line SPL, that is, directly below the light receiving element TMI that does not include the dividing line SPL, are connected to the metal wirings Al1, Al via the contact CT formed by the via hole VA. It is electrically connected to Al2. However, other transistors arranged in a region straddling the dividing line SPL, that is, immediately below the light receiving element TMI including the dividing line SPL, are electrically connected to the metal wirings Al1 and Al2 without the contact CT immediately above them. It has not been. A semiconductor device is formed so as to have such an aspect.

  In the schematic plan view of the chip region IMC in each of the above embodiments, the contact CT electrically connected to other transistors is not shown, but in the present embodiment of FIG. 40, the contact CT This is shown in order to clarify the presence or absence.

  In FIG. 40 and FIG. 41, the size, interval, and repetition pitch of the light receiving elements TMI arranged in the chip region IMC are basically the same, but these are the same as in the other embodiments described above. You may change suitably. The configuration of this embodiment may be combined with the configurations of the other embodiments described above as appropriate.

  Since the light receiving element TMI in the region straddling the dividing line SPL is not electrically connected to the upper wirings Al1 and Al2, the light receiving element TMI does not function as a light receiving element. For this reason, the distance between the pattern of the light receiving element TMI adjacent to the light receiving element TMI in the region straddling the dividing line SPL and the dividing line SPL in the horizontal direction in the figure is substantially the shortest distance between the dividing line SPL and the light receiving element TMI. Become.

  For this reason, even if the light receiving element TMI in the region straddling the dividing line SPL has a defect such as a dimensional shape of the pattern caused by being close to the dividing line SPL, a distance from the adjacent light receiving element TMI is secured. Therefore, the above problems can be more reliably suppressed.

  In the present embodiment, although the light receiving element TMI does not exist in the region substantially straddling the dividing line SPL, the semiconductor device has been miniaturized and the absolute value of the repetitive pitch and interval is extremely high. Therefore, the integration of the semiconductor device is hardly affected.

  Finally, the main points (superordinate concept) of the embodiment will be described with reference to FIGS. 42 and 43. FIG.

  Referring to FIG. 42, a chip region IMC as a semiconductor device (solid-state imaging device) of one embodiment has a plurality of light receiving elements TMI arranged in a matrix on the main surface of the semiconductor substrate SUB. The light receiving element TMI includes a photodiode PD as a photoelectric conversion region. In the partial region, the pitch P2 of the light receiving elements TMI is larger than the repetition pitch P1 of the light receiving elements TMI in other regions other than the partial region. As a result, in some areas, the distance d2 between the light receiving elements TMI is larger than the distance d1 between the light receiving elements TMI in other areas other than the some areas.

  Referring to FIG. 43, a chip region IMC as a semiconductor device (solid-state imaging device) of one embodiment has a plurality of light receiving elements TMI arranged in a matrix on the main surface of the semiconductor substrate SUB. The light receiving element TMI includes a photodiode PD as a photoelectric conversion region. The light receiving elements TMI (photodiodes PD) arranged in a matrix have a mode different from the other areas in a part of the area, for example, one row indicated by hatching in the drawing. For example, the light receiving element TMI in a part of the region has a planar form inverted with respect to the light receiving element TMI in a region other than the part of the region. Alternatively, the light receiving element TMI in a part of the region is not connected to an upper layer wiring in which another transistor to which an electric signal from the light receiving element TMI is transferred, and the light receiving element in another region other than the part of the region In the TMI, another transistor to which an electric signal from the light receiving element TMI is transferred is connected to an upper layer wiring.

In addition, a part of the contents described in the embodiment will be described below.
(1) In the method for manufacturing a semiconductor device, first, a semiconductor substrate having a main surface is prepared. A plurality of light receiving elements arranged in a matrix in the first region of the main surface is formed by exposure. A plurality of light receiving elements arranged in a matrix in the second region adjacent to the first region on the main surface is formed by exposure. In the step of exposing and forming the light receiving element in the second region, the light receiving element is divided into boundaries between the first region and the second region extending along the first direction in which the plurality of light receiving elements are arranged. The line is located. At least a part of the plurality of light receiving elements arranged so as to straddle the dividing line is a light receiving element having a planar aspect inverted with respect to the light receiving elements not straddling the dividing line in the first region.

  (2) In the method of manufacturing a semiconductor device according to (1), the plurality of light receiving elements arranged so as to straddle the dividing line are light receiving elements having a planar aspect continuously inverted with respect to the first direction.

  (3) In the method of manufacturing a semiconductor device according to (1), the plurality of light receiving elements arranged so as to straddle the dividing line have a light receiving element having an inverted plane mode and an inverted plane mode with respect to the first direction. Non-inverted light receiving elements that are not light receiving elements are alternately arranged.

  (4) In the method for manufacturing a semiconductor device according to (2) or (3), the light receiving element includes a photoelectric conversion region and a capacitor region for converting the charge output from the photoelectric conversion region into a voltage signal. The light receiving element having the inverted planar aspect shares the capacitance region with the non-inverted light receiving element adjacent to the light receiving element having the planar aspect inverted with respect to the second direction intersecting the first direction.

  (5) The semiconductor device includes a semiconductor substrate, a plurality of light receiving elements, another transistor, and a wiring. The semiconductor substrate has a main surface. The plurality of light receiving elements are arranged on the main surface. The other transistor receives an electrical signal from the light receiving element. The wiring transmits an electrical signal from the other transistor to the periphery. The light receiving element includes a photoelectric conversion region. In the region where the plurality of light receiving elements are arranged in a matrix, other transistors in the region straddling the dividing line SPL extending along the first direction in which the plurality of light receiving elements are arranged are electrically connected to the wiring. Not. Other transistors in the region not straddling the dividing line SPL other than the region straddling the dividing line SPL are electrically connected to the wiring.

  (6) In the semiconductor device manufacturing method, first, a semiconductor substrate having a main surface is prepared. A plurality of light receiving elements arranged in a matrix in the first region of the main surface is formed by exposure. A plurality of light receiving elements arranged in a matrix in the second region adjacent to the first region on the main surface is formed by exposure. The light receiving element includes a photoelectric conversion region. Another transistor that receives an electric signal from the light receiving element and a wiring that transmits the electric signal from the other transistor to the periphery are further formed. In the step of exposing and forming the light receiving element in the second region, a dividing line that extends along the first direction in which the plurality of light receiving elements are arranged and serves as a boundary between the first region and the second region Is located. In the region where the plurality of light receiving elements are arranged in a matrix, other transistors in the region straddling the dividing line SPL extending along the first direction in which the plurality of light receiving elements are arranged are electrically connected to the wiring. Not. Other transistors in the region not straddling the dividing line SPL other than the region straddling the dividing line SPL are electrically connected to the wiring.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  ACR active region, Al1, Al2 metal wiring, AMI amplification transistor, CT contact, VA via hole, COL color filter, DLR dicing line region, EDG edge, FD capacitance region, FLM thin film, II interlayer insulating film, IMC chip region, MK Mark, NF silicon nitride film, NR1 low concentration n-type region, NR2 n-type region, NWL n-type impurity region, ORG organic planarization film, OX silicon oxide film, PD photodiode, PHR photoresist, PMI peripheral circuit, PWL p-type well region, RMI reset transistor, SMI selection transistor, SPL dividing line, SPT element isolation region, SW semiconductor wafer, SWI sidewall insulating film, TGE transfer transistor gate electrode, TMI, TMI2 light receiving element, T Receiving element having I1 inverted planar manner.

Claims (12)

A semiconductor substrate having a main surface;
A plurality of light receiving elements arranged on the main surface,
In a region where the plurality of light receiving elements are arranged, a first region where the plurality of light receiving elements are arranged in a matrix, and adjacent to the first region, and the plurality of light receiving elements are arranged in a matrix A second region to be
A dividing line extending along the first direction is located at the boundary between the first region and the second region,
A pitch between the light receiving element in the first region and the light receiving element in the second region adjacent to each other across the dividing line is a second crossing the first direction in the first region. A semiconductor device having a pitch larger than a repetitive pitch between the plurality of light receiving elements arranged adjacent to each other in the direction.   2. The interval in the second direction between the light receiving elements adjacent to each other across the dividing line is greater than the interval in the second direction between the light receiving elements adjacent in the first region. Semiconductor device.   The semiconductor device according to claim 1, wherein the pitch is twice or more the repetition pitch. The light receiving element includes a photoelectric conversion region,
The light receiving element is disposed so as to straddle the dividing line,
The length in the second direction of the photoelectric conversion region of the light receiving element arranged so as to straddle the dividing line is the photoelectric conversion of the light receiving element that does not straddle the dividing line in the first region. The semiconductor device according to claim 1, wherein the region is longer than a length in the second direction. Preparing a semiconductor substrate having a main surface;
Exposing and forming a plurality of light receiving elements arranged in a matrix in the first region of the main surface;
A step of exposing and forming a plurality of light receiving elements arranged in a matrix in a second region adjacent to the first region of the main surface,
In the step of exposing and forming the light receiving element in the second region, a boundary between the first region and the second region extending along a first direction in which the plurality of light receiving elements are arranged The dividing line becomes
A pitch between the light receiving element in the first region and the light receiving element in the second region adjacent to each other across the dividing line is a second crossing the first direction in the first region. A method for manufacturing a semiconductor device, wherein the pitch is larger than a repetitive pitch between the plurality of light receiving elements arranged adjacent to each other in the direction.   6. The interval in the second direction between the light receiving elements adjacent to each other across the dividing line is larger than the interval in the second direction between the light receiving elements adjacent in the first region. A method for manufacturing a semiconductor device.   The method for manufacturing a semiconductor device according to claim 5, wherein the pitch is twice or more the repetition pitch. The light receiving element includes a photoelectric conversion region,
The light receiving element is disposed so as to straddle the dividing line,
The length in the second direction of the photoelectric conversion region of the light receiving element arranged so as to straddle the dividing line is the photoelectric conversion of the light receiving element that does not straddle the dividing line in the first region. The method for manufacturing a semiconductor device according to claim 5, wherein the region is longer than a length in the second direction. A semiconductor substrate having a main surface;
A plurality of light receiving elements arranged on the main surface,
In a region where the plurality of light receiving elements are arranged, a first region where the plurality of light receiving elements are arranged in a matrix, and adjacent to the first region, and the plurality of light receiving elements are arranged in a matrix A second region to be
A dividing line extending along the first direction is located at the boundary between the first region and the second region,
At least a part of the plurality of light receiving elements arranged so as to straddle the dividing line is a light receiving element having a planar aspect that is inverted with respect to the light receiving element that does not straddle the dividing line in the first region. A semiconductor device.   The semiconductor device according to claim 9, wherein the plurality of light receiving elements arranged so as to straddle the dividing line are light receiving elements having the inverted planar aspect continuously with respect to the first direction.   The plurality of light receiving elements arranged so as to straddle the dividing line are light receiving elements that are not inverted light receiving elements that have the inverted planar aspect and light receiving elements that have the inverted planar aspect with respect to the first direction. The semiconductor device according to claim 9, wherein the elements are alternately arranged. The light receiving element includes a photoelectric conversion region, and a capacitance region for converting a charge output from the photoelectric conversion region into a voltage signal,
The light receiving element having the inverted planar aspect shares the capacitance region with the non-inverted light receiving element adjacent to the light receiving element having the inverted planar aspect with respect to the second direction intersecting the first direction. The semiconductor device according to claim 10 or 11.

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