JP2007142298A - Solid state imaging device, its manufacturing method and camera - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid state imaging apparatus, its manufacturing method, and a camera which reduces the dark current and allows the read voltage to be lowered and the electric field around a light receiver to be relaxed. <P>SOLUTION: The solid stage imaging apparatus has a plurality of light receivers 5 formed like a matrix on a substrate, first-conductivity transfer channels 14 formed between the columns of the light receivers 5 in the substrate, and transfer electrodes 21, 22 disposed around the receivers 5 so as to cover the transfer channels 14. The light receivers 5 have first-conductivity regions and second-conductivity regions 13 formed on the substrate surface. The second-conductivity region 13 has a first region 13a formed on the entire surface of the light receivers 5, and a second region 13b formed away in the row direction from transfer electrodes 20 at both sides, having a second-conductivity higher impurity concentration than the first region 13a. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, a manufacturing method thereof, and a camera, and more particularly, to a solid-state imaging device having a light receiving portion formed of an embedded photodiode, a manufacturing method thereof, and a camera.

An embedded photodiode is employed as a light receiving part of a CCD (Charge Coupled Device). In the embedded photodiode, since all pn junctions exist in the substrate, dark current is suppressed. A light-receiving portion made of an embedded photodiode has an n-type region and a p ⁺ region formed on the surface layer of the n-type region (see Patent Document 1).

In order to suppress the dark current, the p ⁺ region is designed to have a high concentration. At that time, the p ⁺ concentration locally increases at the site where the channel stop region and the p ⁺ region overlap. In the case of this structure, a strong electric field is generated at a site where the p ⁺ concentration is locally high when a read voltage is applied. In recent CCD image sensors, as the cell size shrinks, the potential gradient is applied to a very narrow region. Therefore, the electric field generated in the local p ⁺ concentration region is high, which is a factor. A phenomenon that white scratches occur.

In order to avoid this phenomenon, it is necessary to design the P ⁺ concentration on the surface of the light receiving portion to be low, but this is difficult because it causes an increase in dark current. On the other hand, although it is possible to reduce the p ⁺ concentration in the channel stop region, the concentration is lower than that of the p ⁺ region in the light receiving portion, and no effect can be obtained.

Further, since the formation of the p ⁺ region on the surface of the light receiving portion is designed by self-alignment with respect to the electrode opening, the p ⁺ region having a high concentration is implanted near the readout gate. At this time, the barrier in the vicinity of the read gate is increased, which causes a rise in the read voltage.

Further, the increase in p ⁺ concentration in the vicinity of the channel stop region affects the potential of the n ⁺ transfer channel constituting the vertical transfer unit, and thus induces an effective W / L deterioration of the vertical transfer path. For this reason, in order to ensure good vertical transfer characteristics, it is necessary to reduce the p ⁺ concentration in the vicinity of the channel stop region.
Japanese Patent No. 3320589

  The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce a dark current, reduce a readout voltage, and reduce an electric field around a light receiving unit, and a method for manufacturing the same. And providing a camera.

  In order to achieve the above object, a solid-state imaging device according to the present invention includes a plurality of light receiving units formed in a matrix on a substrate, and a first conductivity type transfer formed on the substrate between columns of the light receiving units. A transfer electrode disposed around the light receiving portion and covering the transfer channel, the light receiving portion on a surface of the substrate; and a first conductivity type region formed on the substrate. A second conductivity type region formed, and the second conductivity type region is formed in the row direction away from the first region formed on the entire surface of the light receiving portion and the transfer electrodes on both sides. And a second region having a second conductivity type impurity concentration higher than that of the first region.

  In order to achieve the above object, a method of manufacturing a solid-state imaging device according to the present invention includes a step of forming a first conductivity type transfer channel on a substrate, and a formation of a first conductivity type region in a region serving as a light receiving portion of the substrate. A step of forming a transfer electrode in a region on the transfer channel excluding the light receiving portion, and a step of forming a second conductivity type region in a region to be a light receiving portion of the substrate, The step of forming the second conductivity type region includes the step of ion-implanting a second conductivity type impurity using the transfer electrode as a mask to form the first region over the entire surface of the light receiving portion, and the ion implantation mask. Ion-implanting the second conductivity type impurity to form a second region having a second conductivity type impurity concentration higher than that of the first region and separated from the transfer electrode adjacent in the row direction; Have

  In order to achieve the above object, a camera of the present invention includes a solid-state imaging device, an optical system that focuses light on the imaging surface of the solid-state imaging device, and a predetermined signal with respect to an output signal from the solid-state imaging device. A signal processing circuit that performs processing, and the solid-state imaging device includes a plurality of light receiving portions formed in a matrix on the substrate, and a first conductivity type formed on the substrate between the rows of the light receiving portions. A transfer channel; and a transfer electrode disposed around the light receiving portion and covering the transfer channel, the light receiving portion including a first conductivity type region formed in the substrate, and a surface of the substrate The second conductivity type region is formed in the row direction away from the first region formed on the entire surface of the light receiving portion and the transfer electrodes on both sides. The second conductivity type impurity concentration is higher than that of the first region. And a frequency.

  In the above-described present invention, the second conductivity type region of the light receiving unit is formed in the row direction away from the first region formed on the entire surface of the light receiving unit and the transfer electrodes on both sides, and is second than the first region. And a second region having a high impurity concentration of two conductivity types. As a result, the concentration on the reading side and the non-reading side of the second conductivity type region is lowered. Accordingly, an increase in the second conductivity type impurity concentration in the read side region is suppressed, and an increase in the read voltage is suppressed. In addition, an increase in the second conductivity type impurity concentration in the non-read side region is suppressed, and electric field concentration is mitigated.

  According to the present invention, it is possible to realize a solid-state imaging device and a camera that reduce dark current, reduce read voltage, and reduce electric field around a light receiving unit.

  Embodiments of the present invention will be described below with reference to the drawings. In each figure, the same components are denoted by the same reference numerals. In the present embodiment, an example in which the present invention is applied to an interline transfer type CCD (Charge Coupled Device) type solid-state imaging device will be described. However, there is no particular limitation on the transfer method.

(First embodiment)
FIG. 1 is a schematic configuration diagram of a solid-state imaging apparatus according to the present embodiment. The solid-state imaging device 1 according to the present embodiment includes an imaging unit 2, a horizontal transfer unit 3, and an output unit 4.

  The imaging unit 2 includes a plurality of light receiving units 5 arranged in a matrix for each pixel, a vertical transfer unit 7 arranged for each column of the light receiving units 5, and between the light receiving unit 5 and the vertical transfer unit 7. And a read gate portion 6 arranged.

  The light receiving unit 5 is formed of, for example, an embedded photodiode, and photoelectrically converts image light (incident light) incident from a subject into signal charges having a charge amount corresponding to the amount of light, and accumulates the signal light. The read gate unit 6 reads the signal charges accumulated in the light receiving unit 5 to the vertical transfer unit 7.

  The vertical transfer unit 7 is driven by, for example, four-phase transfer pulses φV1, φV2, φV3, and φV4, and transfers the signal charges read from the light receiving unit 5 in the vertical direction (downward in the figure). The transfer pulse is not limited to four phases. The transfer pulses φV1 to φV4 are, for example, 0V or −7V.

  The horizontal transfer unit 3 is driven by the two-phase transfer pulses φH1 and φH2, and transfers the signal charges vertically transferred from the vertical transfer unit 7 in the horizontal direction (left direction in the figure).

  The vertical transfer unit 7 and the horizontal transfer unit 3 include a transfer channel formed in the transfer direction formed on the substrate, and a plurality of transfer electrodes formed side by side in the transfer direction with an insulating film interposed on the transfer channel. Have.

  The output unit 4 converts the signal charge horizontally transferred by the horizontal transfer unit 3 into an electric signal and outputs it. The output unit 4 is configured by, for example, a floating diffusion amplifier. The output unit 4 includes a transistor 4a including a floating diffusion FD, a reset gate RG, and a reset drain RD, an amplifier 4b, and an output terminal 4c.

  The voltage of the floating diffusion FD changes according to the amount of signal charges transferred horizontally by the horizontal transfer unit. The voltage of the floating diffusion FD is amplified by the amplifier 4b and taken out as an analog image signal by the output terminal 4c. Thereafter, a reset pulse is input to the reset gate RG, the transistor 4a is turned on, and the signal charge of the floating diffusion FD is swept away to the reset drain RD. A power supply voltage Vdd is applied to the reset drain RD.

  FIG. 2 is a plan view of the main part of the imaging unit 2. FIG. 2 illustrates only one pixel. In this example, an example in which the first conductivity type is n-type and the second conductivity type is p-type will be described.

Although not shown, the light receiving portion 5 has an n-type signal charge accumulation region (first conductivity type region) formed up to the deep portion of the substrate. A p ⁺ hole accumulation region (second conductivity type region) 13 is formed in the surface region of the light receiving unit 5.

  In the present embodiment, the hole accumulation region 13 has a two-layer structure, and includes a first region 13a and a second region 13b having a higher p-type impurity concentration than the first region 13a. The first region 13 a is formed on the entire surface of the light receiving unit 5. The first region 13 a is formed in a stripe shape only at the center of the light receiving unit 5.

  Two n-type transfer channels 14 are arranged on both sides of the light receiving unit 5 in the row direction. In this example, the light receiving unit 5 is read to the left transfer channel 14. A p-type read gate region 16 is disposed in the substrate region between the light receiving unit 5 and the transfer channel 14 on the read side.

  A p-type channel stop region 17 is arranged in a region other than the readout gate region 16 around the light receiving unit 5. That is, a channel stop region 17 is disposed between the light receiving unit 5 and the non-reading side (right side) transfer channel 14 and between the light receiving unit 5 and another light receiving unit adjacent in the column direction (vertical direction). ing. The channel stop region 17 is fixed to a predetermined potential, for example, a ground potential. An end of the second region 13b in the column direction overlaps with the channel stop region 17. Thereby, the second region 13b and the channel stop region 17 are electrically connected, and the second region 13b is fixed at a predetermined potential.

  A transfer electrode 20 is formed on the substrate around the light receiving unit 5 with an insulating film interposed therebetween. In the present embodiment, the transfer electrode 20 includes a first transfer electrode 21 and a second transfer electrode 22. When there is no need to distinguish between the first transfer electrode 21 and the second transfer electrode 22, they are simply referred to as the transfer electrode 20.

  The transfer electrode 20 has a two-layer structure, and is formed of, for example, two polysilicon layers. In this embodiment, two transfer electrodes 21 and 22 are arranged corresponding to each light receiving unit 5. However, the transfer electrode 20 may have a single layer structure or a structure of three or more layers. Further, three or more transfer electrodes may be formed for one light receiving unit 5.

  The first transfer electrode 21 is made of a first polysilicon layer. The first transfer electrode 21 covers the transfer channel 14, the read gate region 16, and the channel stop region 17. The plurality of first transfer electrodes 21 in the row direction are connected to each other.

  The second transfer electrode 22 is made of a second polysilicon layer. The second transfer electrode 22 covers the transfer channel 14, the read gate region 16, and the channel stop region 17. On the transfer channel 14, the end of the second transfer electrode 22 overlaps the end of the first transfer electrode 21. Between the light receiving portions 5 adjacent to each other in the column direction, the second transfer electrode 22 is disposed on the first transfer electrode 21 via an insulating film.

  At the time of reading, a positive read voltage is applied to the second transfer electrode 22. The read voltage is, for example, +10 to + 15V. By applying the read voltage, the signal charge (electrons) accumulated in the light receiving unit 5 is read to the transfer channel 14 below the second transfer electrode 22.

  In the vertical transfer after reading, 0V or negative voltage transfer pulses φV1 to φV4 are applied to the first transfer electrode 21 and the second transfer electrode 22 alternately arranged in the vertical direction. The transfer pulses φV1 to φV4 are, for example, 0V or −7V.

  In the present embodiment, the hole accumulation region 13 has a two-layer structure of a first region 13 a and a second region 13 b, and the first region 13 a is formed in a self-aligned manner with respect to the transfer electrode 20. The first region 13 a has a higher p-type impurity concentration than the read gate region 16 and the channel stop region 17. The second region 13b is arranged at a distance (for example, 0.1 to 0.3 μm) from the transfer electrodes 20 on both sides thereof. Further, the end of the second region 13b in the column direction overlaps the channel stop region 17. Further, a portion of the channel stop region 17 on the light receiving unit 5 side protrudes from the transfer electrode 20.

  FIG. 3 is a cross-sectional view taken along the line A-A ′ of FIG. 2. 4 is a cross-sectional view taken along line B-B ′ of FIG. 2. For simplification of illustration, the upper layer of the light shielding film is illustrated only in FIG.

  For example, a p-type well 11 is formed on an n-type silicon substrate 10 (hereinafter referred to as a substrate 10). The p-type well 11 forms an overflow barrier.

The light receiving unit 5 includes an n-type signal charge storage region 12 formed in the p-type well 11 and a p ⁺ hole storage region 13 formed in the surface layer of the signal charge storage region 12. The hole accumulation region 13 is provided in order to suppress dark current that is generated near the surface of the signal charge accumulation region 12 and becomes a noise source. In the present embodiment, the hole accumulation region 13 includes a p ⁺ first region 13a and a second region 13b having a higher p-type impurity than the first region 13a.

  In the light receiving portion 5, an npn structure is formed by the signal charge accumulation region 12, the p-type well 11 and the substrate 10. This npn structure is a vertical overflow drain that discharges signal charges to the substrate 10 side when signal light generated excessively due to strong light incident on the light receiving section 5 exceeds an overflow barrier formed by the p-type well 11. Configure the structure.

  Further, the light receiving unit 5 has a function of an electronic shutter. That is, by setting the substrate potential supplied to the substrate 10 to a high level (for example, +12 V), the potential barrier of the p-type well 11 is lowered, and the charge accumulated in the signal charge accumulation region 12 overcomes the potential barrier, It is swept away in the vertical direction, that is, the substrate 10. Thereby, the exposure period can be adjusted.

  The vertical transfer unit 7 includes an n-type transfer channel 14 formed in the p-type well 11 at a predetermined interval from the signal charge storage region 12, and a gate insulating film 30 made of a silicon oxide film on the transfer channel 14. The transfer electrodes 21 and 22 are made of, for example, polysilicon. A p-type well 15 having a relatively high concentration is formed under the transfer channel 14. The p-type well 15 forms a potential barrier under the transfer channel 14. For this reason, the signal charge photoelectrically converted in the deep portion of the substrate 10 is prevented from entering the transfer channel 14, and the occurrence of smear is suppressed.

  The read gate unit 6 includes a p-type read gate region 16 between the signal charge storage region 12 and the transfer channel 14 and a transfer electrode 20 formed on the read gate region 16 via a gate insulating film 30. ing. The read gate region 16 forms a potential barrier between the n-type signal charge storage region 12 and the transfer channel 14. At the time of reading, a positive read voltage (for example, +12 V) is applied to the first transfer electrode 21, the potential barrier of the read gate region 16 is lowered, and the signal charge is read from the signal charge storage region 12 to the transfer channel 14. .

  A p-type channel stop region 17 is formed on the side opposite to the reading side with respect to the signal charge storage region 12. A channel stop region 17 is formed between the light receiving portions 5 adjacent in the column direction and below the first transfer electrode 21 (see FIG. 4). The channel stop region 17 forms a potential barrier against the signal charge and prevents the signal charge from flowing in and out. The second region 13b of the hole accumulation region 13 is arranged so as to overlap with the channel stop region 17 adjacent in the column direction. For this reason, the channel stop region 17 and the second region 13 b are connected under the first transfer electrode 21.

  A light shielding film 50 is formed on the first transfer electrode 21 and the second transfer electrode 22 via an insulating film 31 made of silicon oxide. The light shielding film 50 is made of a refractory metal such as tungsten, for example. In the light shielding film 50, an opening 50a for allowing light to enter the light receiving portion 5 is formed.

  On the light shielding film 50, an interlayer insulating film 61 made of, for example, BPSG (Boron Phosphorous Silicate glass) is formed. A passivation film 62 made of, for example, silicon nitride is formed on the interlayer insulating film 61. The surface of the passivation film 62 is planarized.

  A color filter 70 is formed on the passivation film 62. The color filter 70 is, for example, a primary color type, and includes a green color filter, a blue color filter, and a red color filter. In the case of the complementary color type, the color filter 70 is formed of cyan, magenta, yellow, and green color filters.

  On the color filter 70, for example, a planarizing film 80 made of an acrylic thermosetting resin is formed. A microlens 90 is formed on the planarizing film 80.

  In the solid-state imaging device described above, incident light is collected by the microlens 90 and reaches each color filter 70. Only light in a predetermined wavelength region passes through each color filter and enters the light receiving unit 5. The light incident on the light receiving unit 5 is photoelectrically converted into a signal charge corresponding to the amount of incident light and accumulated in the signal charge accumulation region 12. Thereafter, the data is read out to the transfer channel 14 and transferred in the vertical direction by the vertical transfer unit 7.

  Next, a method for manufacturing the solid-state imaging device according to the present embodiment will be described with reference to FIGS. 5 to 10 are process cross-sectional views in manufacturing the solid-state imaging device.

  As shown in FIG. 5A, a p-type well 11 is formed on an n-type silicon substrate 10 by ion implantation. As the substrate 10, for example, a substrate in which an n-type epitaxial layer having a resistivity of about 20 to 40 Ωcm is formed on an n-type CZ substrate by about several μm to several tens of μm is used.

  Next, as shown in FIG. 5B, an n-type transfer channel 14, a p-type well 15, a p-type read gate region 16, and a p-type channel stop region 17 are formed on the substrate 10 by ion implantation. To do. There is no limitation on the order of these ion implantations.

  Next, as shown in FIG. 6A, an n-type signal charge storage region 12 is formed in a region to be a light receiving portion of the substrate 10 by ion implantation. The signal charge accumulation region 12 and the channel stop region 17 are formed so as to overlap each other.

  Next, as shown in FIG. 6B, a gate insulating film 30 made of a silicon oxide film is formed on the substrate 10 by thermal oxidation. Note that a stacked film of a silicon oxide film, a silicon nitride film, and a silicon oxide film may be formed as the gate insulating film 30.

  Subsequently, the transfer electrode 20 is formed on the substrate 10 via the gate insulating film 30. For example, a first transfer electrode 21 is formed by depositing a polysilicon layer on the substrate 10 and processing the polysilicon layer by a lithography technique and an etching technique. Subsequently, after forming an insulating film made of silicon oxide, a polysilicon layer is deposited, and the second transfer electrode 22 is formed by processing the polysilicon layer by a lithography technique and an etching technique. Thereby, the transfer electrode 20 having a two-layer structure is formed. The thickness of the polysilicon layer is 200 nm to 500 nm.

Next, as shown in FIG. 7A, p-type impurities are ion-implanted using the transfer electrode 20 as a mask to form a p ⁺ first region 13 a in the surface layer portion of the signal charge storage region 12. The first region 13 a is formed by self-alignment with the transfer electrode 20. Further, the first region 13 a is formed on the entire surface of the light receiving unit 5. The dose amount of ion implantation is, for example, 5 × 10 ¹² atoms / cm ² .

Next, as shown in FIG. 7B, a resist mask R is formed by resist application and lithography. Then, the second region 13b is formed only in the central portion of the light receiving portion 5 by ion implantation using the resist mask R. The dose of ion implantation is, for example, 1 × 10 ¹³ atoms / cm ² . Thereafter, the resist mask R is removed. Thereby, the hole accumulation region 13 including the first region 13a and the second region 13b is formed. Note that the second region 13b may be formed earlier than the first region 13a.

  Next, as shown in FIG. 8A, an insulating film 31 is formed on the entire surface. For example, a silicon oxide film is deposited by the CVD method. The film thickness of the insulating film 32 is set to around 100 nm so that it can withstand a drive voltage of several tens of volts.

  Next, as shown in FIG. 8B, a light shielding film 50 having an opening 50 a at the position of the light receiving portion 5 is formed on the insulating film 31. In the formation of the light shielding film 50, for example, a refractory metal film such as tungsten is deposited on the entire surface, and the refractory metal film is dry-etched using a resist mask.

  Next, as illustrated in FIG. 9A, for example, BPSG is deposited on the substrate 10, and an interlayer insulating film 61 is formed by performing a reflow process.

  Next, as shown in FIG. 9B, a silicon nitride film is deposited on the interlayer insulating film 61 by plasma CVD, and a passivation film 62 is formed by planarizing the surface of the silicon nitride film.

  Next, as shown in FIG. 10A, a color filter 70 is formed on the passivation film 62. The color filter 70 is formed using, for example, a color resist method. For example, after a green color resist is formed on the passivation film 62, the green color resist is exposed and developed to form a green color filter pattern. Similarly, a blue color filter and a red color filter are formed by performing color resist formation, exposure, and development. Note that the order of forming the color filter 70 is not limited.

  Next, as shown in FIG. 10B, a transparent flattening film 80 is formed on the color filter 70 for the purpose of flattening the surface unevenness of the color filter 70. As the planarization film 80, for example, an acrylic thermosetting resin is used.

  Next, a microlens 90 is formed on the planarizing film 80 (see FIG. 3). For example, after a lens material is applied, a microlens 90 is formed by forming a lens-shaped resist mask and performing etching under conditions such that the etching selectivity between the resist mask and the lens material is 1.

  The solid-state imaging device is used for a camera such as a video camera, a digital still camera, or an electronic endoscope camera, for example.

  FIG. 11 is a schematic configuration diagram of a camera in which the above-described solid-state imaging device is used.

  The camera 100 includes the solid-state imaging device 1 described above, an optical system 102, a drive circuit 103, and a signal processing circuit 104.

  The optical system 102 forms image light (incident light) from the subject on the imaging surface of the solid-state imaging device 1. As a result, in each light receiving unit 5 of the solid-state imaging device 1, incident light is converted into a signal charge corresponding to the amount of incident light.

  The drive circuit 103 gives various timing signals such as the above-described four-phase transfer pulses φV1, φV2, φV3, φV4 and two-phase transfer pulses φH1, φH2 to the solid-state imaging device 1. As a result, various types of driving such as signal charge readout, vertical transfer, and horizontal transfer of the solid-state imaging device 1 are performed. Further, by this driving, an analog image signal is output from the output unit 4 of the solid-state imaging device 1.

  The signal processing circuit 104 performs various signal processing such as noise removal and conversion into a digital signal on the analog image signal output from the solid-state imaging device 1. After the signal processing by the signal processing circuit 104 is performed, it is stored in a storage medium such as a memory.

  Next, effects of the solid-state imaging device and the manufacturing method thereof and the camera according to the above-described embodiment will be described.

  In the present embodiment, the hole accumulation region 13 is formed in a stripe shape only in the first region 13a formed on substantially the entire surface of the light receiving unit 5 and in the central portion of the light receiving unit 5, and is more p-type than the first region 13a. A second region 13b having a high impurity concentration.

  In the present embodiment, since the first region 13a has a lower concentration than the second region 13b, it is possible to suppress an increase in the p-type impurity concentration of the read gate region 16. As a result, an increase in the potential barrier of the read gate region 16 is suppressed, and an increase in the read voltage can be suppressed.

  For the same reason, an increase in the p-type impurity concentration of the channel stop region 17 between the light receiving unit 5 and the transfer channel 14 can be suppressed. As a result, generation of a strong electric field in the channel stop region 17 is suppressed. The generation of white scratches can be suppressed. Further, since the increase of the p-type impurity concentration in the channel stop region 17 can be suppressed, the potential fluctuation of the transfer channel 14 can be suppressed, and the vertical transfer characteristics can be maintained.

In addition, a second region 13 b having a higher concentration than the first region 13 a is formed at the center of the light receiving unit 5. The second region 13b is connected to the channel stop region 17 adjacent in the column direction, and is fixed at a predetermined potential. The dark current induced by the concentration difference between the hole accumulation region 13 and the signal charge accumulation region 12 of the light receiving unit 5 is mainly due to the positional relationship between the deepest potential position (maximum potential position) of the light receiving unit 5 and the sensor surface p ^+. It is considered to be decided. Therefore, by arranging the high-concentration second region 13b in the center of the light-receiving unit 5, the dark current can be sufficiently suppressed even if the high-concentration p ⁺ region is not arranged on the entire surface of the light-receiving unit 5.

  As described above, it is possible to realize a solid-state imaging device with improved imaging characteristics and stabilization. According to the camera including the solid-state imaging device according to the present embodiment, it is possible to realize a camera that improves and stabilizes imaging characteristics.

(Second Embodiment)
FIG. 12 is a cross-sectional view of the solid-state imaging device according to the second embodiment. 12 corresponds to a cross-sectional view taken along line AA ′ in FIG.

  In the present embodiment, the second region 13b of the hole accumulation region 13 is formed deeper than the first region 13a. In the solid-state imaging device according to the present embodiment, the second region 13b may be formed deeper than the first embodiment in the ion implantation process of the second region 13b.

  The effect of the solid-state imaging device according to the present embodiment will be described. FIG. 13 is a potential diagram of a pixel.

  As shown in FIG. 13, in order to increase the accumulated charge amount of the light receiving unit 5 (signal charge accumulation region 12) in the solid-state imaging device indicated by the potential distribution A, the n-type impurity concentration of the signal charge accumulation region 12 is designed to be high. It is possible. The potential distribution in this case is indicated by B. In the case of the potential distribution B, the amount of accumulated charge increases, but the potential well of the signal charge accumulation region 12 becomes deep in the center. As a result, the read voltage required to read all signal charges in the signal charge storage region 12 increases.

  In order to prevent this, by forming the second region 13b deeper than the first region 13a, the potential at the central portion of the signal charge storage region 12 is lowered due to the influence of the second region 13b (the potential well is made shallow). )be able to. As a result, a potential distribution C is obtained, the pn junction between the signal charge storage region 12 and the read gate region 16 becomes steep, and an increase in read voltage can be suppressed.

The present invention is not limited to the description of the above embodiment.
The present invention can be applied to a solid-state imaging device of a frame transfer system or a frame interline transfer system in addition to the interline transfer system. The structure of the transfer electrode 20 is not particularly limited. Therefore, it may be a transfer electrode having a single layer structure or a transfer electrode having a two-layer structure or a three-layer structure.
In addition, various modifications can be made without departing from the scope of the present invention.

It is a schematic block diagram which shows an example of the solid-state imaging device which concerns on 1st Embodiment. It is a principal part top view of an imaging part. It is sectional drawing in the A-A 'line of FIG. FIG. 3 is a cross-sectional view taken along line B-B ′ of FIG. 2. It is process sectional drawing in manufacture of the solid-state imaging device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the solid-state imaging device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the solid-state imaging device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the solid-state imaging device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the solid-state imaging device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the solid-state imaging device which concerns on 1st Embodiment. It is a schematic block diagram which shows an example of the camera which concerns on 1st Embodiment. It is sectional drawing of the solid-state imaging device which concerns on 2nd Embodiment. It is a potential diagram of the pixel of the solid-state imaging device concerning a 2nd embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device, 2 ... Imaging part, 3 ... Horizontal transfer part, 4 ... Output part, 4a ... Transistor, 4b ... Amplifier, 4c ... Output terminal, 5 ... Light-receiving part, 6 ... Read-out gate part, 7 ... Vertical transfer , 10 ... substrate, 11 ... p-type well, 12 ... signal charge storage region, 13 ... hole storage region, 13a ... first region, 13b ... second region, 14 ... transfer channel, 15 ... p-type well, 16 ... Reading gate region, 17 ... channel stop region, 20 ... transfer electrode, 21 ... first transfer electrode, 22 ... second transfer electrode, 30 ... gate insulating film, 31 ... insulating film, 50 ... light shielding film, 50a ... opening , 61 ... interlayer insulating film, 62 ... passivation film, 70 ... color filter, 80 ... flattening film, 90 ... microlens, 100 ... camera, 102 ... optical system, 103 ... drive circuit, 104 ... signal processing circuit, FD ... Flow Computing diffusion, RG ... reset gate, RD ... reset drain

Claims (9)

A plurality of light receiving portions formed in a matrix on the substrate;
A transfer channel of a first conductivity type formed in the substrate between the rows of the light receiving portions;
A transfer electrode disposed around the light receiving portion and covering the transfer channel;
The light receiving unit is
A first conductivity type region formed on the substrate;
A second conductivity type region formed on the surface of the substrate;
The second conductivity type region is
A first region formed on the entire surface of the light receiving unit;
A solid-state imaging device comprising: a second region formed away from the transfer electrodes on both sides in a row direction and having a second conductivity type impurity concentration higher than that of the first region. A second conductivity type channel stop region is provided in a region around the light receiving portion, except between the light receiving portion and the transfer channel on the reading side,
The solid-state imaging device according to claim 1, wherein the second region is connected to the channel stop region adjacent in the column direction. The solid-state imaging device according to claim 2, wherein the channel stop region protrudes from the transfer electrode. The solid-state imaging device according to claim 1, wherein the second region is deeper than the first region. Forming a first conductivity type transfer channel on a substrate;
Forming a first conductivity type region in a region to be a light receiving portion of the substrate;
Forming a transfer electrode on the transfer channel in a region excluding the light receiving portion;
Forming a second conductivity type region in a region to be a light receiving portion of the substrate,
The step of forming the second conductivity type region includes:
Ion-implanting a second conductivity type impurity using the transfer electrode as a mask to form a first region over the entire surface of the light receiving unit;
The second conductivity type impurity is ion-implanted using the ion implantation mask, and the second conductivity type impurity concentration is higher than that of the first region, and the second conductivity type impurity is separated from the transfer electrode adjacent in the row direction. A method of manufacturing a solid-state imaging device. Before the step of forming the transfer electrode, a step of forming a second conductivity type channel stop region around the light receiving portion and excluding the space between the light receiving portion and the transfer channel on the readout side Further comprising
The method for manufacturing a solid-state imaging device according to claim 5, wherein in the step of forming the second region, the second region is formed so as to overlap the channel stop region adjacent in the column direction. The method for manufacturing a solid-state imaging device according to claim 5, wherein in the step of forming the transfer electrode, the transfer electrode is formed so that the channel stop region protrudes from the transfer electrode. The method for manufacturing a solid-state imaging device according to claim 5, wherein in the step of forming the second region, a second region deeper than the first region is formed. A solid-state imaging device;
An optical system for imaging light on the imaging surface of the solid-state imaging device;
A signal processing circuit that performs predetermined signal processing on an output signal from the solid-state imaging device;
The solid-state imaging device
A plurality of light receiving portions formed in a matrix on the substrate;
A transfer channel of a first conductivity type formed in the substrate between the rows of the light receiving portions;
A transfer electrode disposed around the light receiving portion and covering the transfer channel;
The light receiving unit is
A first conductivity type region formed on the substrate;
A second conductivity type region formed on the surface of the substrate;
The second conductivity type region is
A first region formed on the entire surface of the light receiving unit;
And a second region that is formed in a row direction away from the transfer electrodes on both sides and has a second conductivity type impurity concentration higher than that of the first region.

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