JP2007058012A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress variation in a common electrode voltage and to reduce cost and consumed current in a liquid crystal display device performing dot inversion driving. <P>SOLUTION: A judging circuit 31 judges whether or not preliminarily determined detection object patterns are included by a preliminarily determined proportion or more in the display data DATAX of the next frame. A switch 32 switches, based on a judgment signal 33, to electrically connect an auxiliary capacitance line 23 of a liquid crystal panel 20 to a common electrode 24 or to connect to the ground. When such display data that greatly changes the common electrode voltage Vcom are inputted, the auxiliary capacitance line 23 is connected to the ground. Therefore, the load on a common electrode control circuit 13 is decreased and changes in the common electrode voltage Vcom can be suppressed. By using an inexpensive operational amplifier having low performance compared to a conventional component in the output stage of the common electrode control circuit 14, the cost and the consumed current in the liquid crystal display device 10 can be reduced. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device, and more particularly to an active matrix liquid crystal display device that performs dot inversion driving.

  Conventionally, an active matrix liquid crystal display device that performs dot inversion driving as shown in FIG. 10 is known. In FIG. 10, the liquid crystal panel 20 has a structure in which a liquid crystal material is sandwiched between two glass substrates. On one glass substrate, a plurality of pixel electrodes 21, a plurality of TFT (Thin Film Transistor) elements 22, scanning signal lines G1 to Gm, data signal lines S1 to Sk, and auxiliary capacitance lines 23 are formed, and the other A common electrode 24 is formed on the glass substrate.

  The liquid crystal display device shown in FIG. 10 is supplied with control signals (horizontal / vertical synchronization signal, enable signal and dot clock) and display data from the outside. Based on these input signals, the display control circuit 91 supplies control signals GCK and GSP to the scanning signal line drive circuit 92 and controls the control signals CK, SP, LP and REV to the data signal line drive circuit 93. And display data DATA are supplied. The scanning signal line driving circuit 92 drives the scanning signal lines G1 to Gm based on the signal supplied from the display control circuit 91. The data signal line drive circuit 93 drives the data signal lines S1 to Sk based on the signal supplied from the display control circuit 91.

  The common electrode control circuit 94 applies a common electrode voltage Vcom to the common electrode 24. The auxiliary capacitance line 23 is connected to the output signal line of the common electrode control circuit 94 outside the liquid crystal panel 20. As a result, the voltage Vcs having the same level as the common electrode voltage Vcom is applied to the auxiliary capacitance line 23.

  The following prior arts are known for the present invention. Patent Document 1 discloses a method for improving display quality by controlling a non-selected scanning electrode to a high impedance state in a liquid crystal display device that performs duty driving. Patent Document 2 discloses a method of improving display quality by preventing a periodic ripple from appearing on the common electrode voltage by shifting the timing at which the data signal line changes in a liquid crystal display device that performs duty driving. ing.

Patent Document 3 discloses a method of reducing the lateral crosstalk level and the charge error level by controlling the auxiliary capacitance line to be in a floating state during a part of the period in which the signal voltage is held in the pixel electrode. ing. Patent Document 4 discloses a method of reducing point defects caused by the drive capability of the memory unit by maintaining the storage capacitor line in a floating state in the still image display mode. Patent Documents 5 and 6 disclose a method of preventing horizontal stripes from being displayed when the power is turned on or off by controlling the voltage of the storage capacitor line when the power is turned on or off.
Japanese Patent Laid-Open No. 4-75020 JP-A-4-9817 JP 2003-228345 A JP 2003-263137 A JP 2005-17934 A JP 2005-49849 A

  The current consumption of a liquid crystal display device that performs dot inversion drive varies depending on display data supplied from the outside, and is maximum when display data is supplied that maximizes the voltage difference between adjacent data signal lines in the liquid crystal panel. It becomes. At this time, the voltage of the data signal line greatly fluctuates, and the common electrode voltage Vcom is most likely to fluctuate due to the influence. When the common electrode voltage Vcom fluctuates greatly, the consumption current of the operational amplifier that controls this voltage increases rapidly, and accordingly, the consumption current of the power supply circuit for the operational amplifier also increases abruptly. As a result, the current consumption of the entire liquid crystal display device is greatly increased.

  Therefore, in order to keep the common electrode voltage Vcom constant and suppress the current consumption of the entire liquid crystal display device, a high current is applied to the output stage of the common electrode control circuit 94 on the assumption that the worst display data is supplied. It is necessary to provide a capacity operational amplifier. With the recent increase in size and definition of liquid crystal panels, this tendency is becoming stronger.

  In recent years, normally black liquid crystal panels have also been used in order to realize a wide viewing angle. In general, in a liquid crystal panel, when a defective pixel is corrected by laser irradiation or the like, the corrected pixel is preferably a black dot. Therefore, in a liquid crystal display device including a normally black liquid crystal panel, the auxiliary capacitance line 23 is connected to the output signal line of the common electrode control circuit 94 outside the liquid crystal panel 20 (see FIG. 10).

  As shown in FIG. 11, in the liquid crystal panel 20, a cross capacitance is formed at a location X (a hatched portion) where the data signal lines S <b> 1 to Sk and the auxiliary capacitance line 23 intersect. For this reason, when the voltages of the data signal lines S <b> 1 to Sk vary, the influence extends to the common electrode voltage Vcom output from the common electrode control circuit 94 via the cross capacitance and the auxiliary capacitance line 23. Also from this point, the necessity to provide an operational amplifier with a high slew rate and a high current capacity at the output stage of the common electrode control circuit 94 is increasing.

  However, when an operational amplifier having a high slew rate and a high current capacity is provided at the output stage of the common electrode control circuit 94, there is a problem that the cost of the liquid crystal display device increases and the current consumption increases.

  Therefore, an object of the present invention is to suppress the fluctuation of the common electrode voltage and reduce the cost and current consumption of the liquid crystal display device in an active matrix liquid crystal display device that performs dot inversion driving.

The first invention is an active matrix type liquid crystal display device,
A liquid crystal panel including a plurality of pixel electrodes arranged two-dimensionally, a plurality of switching elements corresponding to the pixel electrodes, an auxiliary capacitance line intersecting with the pixel electrodes, and a common electrode facing the pixel electrodes; ,
A common electrode control circuit for applying a common electrode voltage to the common electrode;
A driving circuit for performing dot inversion driving of the liquid crystal panel based on given display data;
A determination circuit for determining the display data;
And a switching circuit that switches whether the auxiliary capacitance line is electrically connected to the common electrode or grounded based on a determination result by the determination circuit.

According to a second invention, in the first invention,
The determination circuit determines whether or not a predetermined detection target pattern is included in a predetermined ratio or more in the display data for one frame,
The switching circuit electrically connects the auxiliary capacitance line to the common electrode when the determination result is negative, and connects the auxiliary capacitance line to ground when the determination result is positive. .

According to a third invention, in the second invention,
The detection target pattern is a one-dimensional pattern,
The determination circuit determines whether or not the detection target pattern is included in a row direction of the display data by a predetermined ratio or more.

According to a fourth invention, in the third invention,
The detection target pattern is a one-dimensional pattern composed of two values.

A fifth invention is the fourth invention,
The detection target pattern includes a one-dimensional pattern composed of a minimum value and a maximum value that can be taken by the display data.

According to a sixth invention, in the fourth invention,
The detection target pattern includes a one-dimensional pattern including a value within a predetermined range from a minimum value that can be taken by the display data and a value within a predetermined range from a maximum value that can be taken by the display data. To do.

According to a seventh invention, in the fourth invention,
The detection target pattern includes a one-dimensional pattern in which a difference between two values is within a predetermined range from a difference between a maximum value and a minimum value that can be taken by the display data.

In an eighth aspect based on the first aspect,
The determination circuit and the switching circuit are built in the same semiconductor chip as all or part of the drive circuit.

In a ninth aspect based on the eighth aspect,
The determination circuit and the switching circuit are built in the same semiconductor chip as the timing generation circuit included in the drive circuit.

According to a tenth aspect of the present invention, a plurality of pixel electrodes arranged two-dimensionally, a plurality of switching elements corresponding to the pixel electrodes, an auxiliary capacitance line intersecting with the pixel electrodes, and a common electrode facing the pixel electrodes A method of driving a liquid crystal panel including:
Applying a common electrode voltage to the common electrode;
Based on the given display data, the liquid crystal panel is driven to invert the dots,
Determining the display data; and
Switching between the auxiliary capacitance line being electrically connected to the common electrode or grounded based on the determination result.

  According to the first or tenth aspect, the auxiliary capacitance line is electrically connected to the common electrode voltage or connected to the ground based on the result of the determination on the display data. Therefore, when display data that greatly changes the common electrode voltage is input, if the auxiliary capacitance line is connected to the ground, the load on the common electrode control circuit can be reduced and fluctuations in the common electrode voltage can be suppressed. At this time, since the output signal line of the common electrode control circuit is electrically disconnected from the auxiliary capacitance line, it is possible to prevent noise generated in the auxiliary capacitance line from affecting the common electrode voltage. Considering these points, the cost and current consumption of the liquid crystal display device can be reduced by using an operational amplifier having a lower performance than the conventional one at the output stage of the common electrode control circuit.

  According to the second aspect of the invention, if the data pattern that greatly changes the common electrode voltage is the detection target pattern, the auxiliary capacitance line is connected to the ground when the display data that greatly changes the common electrode voltage is input. be able to. Thereby, the fluctuation | variation of a common electrode voltage can be suppressed and the cost and current consumption of a liquid crystal display device can be reduced.

  According to the third or fourth aspect, the configuration of the determination circuit can be simplified by using a one-dimensional pattern as the detection target pattern and detecting the detection target pattern included in the row direction of the display data. .

  According to the fifth, sixth, or seventh invention, it is possible to determine whether or not display data that greatly fluctuates the common electrode voltage is input by using such a detection target pattern.

  According to the eighth or ninth invention, the liquid crystal display device of the present invention can be configured while minimizing the change of the peripheral circuit by incorporating the determination circuit and the switching circuit in the existing semiconductor chip. it can.

  FIG. 1 is a block diagram showing a configuration of a liquid crystal display device according to an embodiment of the present invention. A liquid crystal display device 10 shown in FIG. 1 is an active matrix liquid crystal display device that performs dot inversion driving. The liquid crystal display device 10 includes a display control circuit 11, a scanning signal line drive circuit 12, a data signal line drive circuit 13, a common electrode control circuit 14, a liquid crystal panel 20, a determination circuit 31, and a switch 32. Hereinafter, m and n represent an integer of 1 or more, and k represents 3n (3 times n).

  The liquid crystal panel 20 is a color liquid crystal panel having a (m × RGB × n) dot configuration. The liquid crystal panel 20 has a structure in which a liquid crystal material is sandwiched between two glass substrates. One glass substrate has (m × k) pixel electrodes 21, the same number of TFT elements 22, m scanning signal lines G1 to Gm, k data signal lines S1 to Sk, and auxiliary capacitors. A line 23 is formed. On the other glass substrate, a common electrode 24 is formed at a position facing all the pixel electrodes 21.

  The scanning signal lines G1 to Gm are arranged in parallel to each other. The data signal lines S1 to Sk are arranged in parallel to each other so as to be orthogonal to the scanning signal lines G1 to Gm. A TFT element 22 is disposed in the vicinity of the intersection of the scanning signal lines G1 to Gm and the data signal lines S1 to Sk. The pixel electrode 21 is disposed in the vicinity of each TFT element 22 in a one-to-one correspondence with the TFT elements 22. Thus, the k pixel electrodes 21 and the TFT elements 22 are arranged side by side in the row direction and m in the column direction.

  Three pixel electrodes 21 adjacent in the row direction (the direction in which the scanning signal lines G1 to Gm extend) are associated with red, blue, and green subpixels (also referred to as picture elements), respectively. Each of the scanning signal lines G1 to Gm is connected to a control terminal of the TFT element 22 arranged in the same row, and each of the data signal lines S1 to Sk is one of conduction terminals of the TFT elements 22 arranged in the same column. Connected to.

  The auxiliary capacitance line 23 is arranged in parallel with the scanning signal lines G1 to Gm and intersects with the pixel electrode 21 and the data signal lines S1 to Sk. A storage capacitor is formed at a location where the pixel electrode 21 and the storage capacitor line 23 intersect.

  The common electrode control circuit 14 applies a common electrode voltage Vcom to the common electrode 24. The scanning signal lines G1 to Gm are also called gate lines, the data signal lines S1 to Sk are also called source lines, the scanning signal line driving circuit 12 is also called a gate driver, and the data signal line driving circuit 13 is also called a source driver.

  The display control circuit 11, the scanning signal line driving circuit 12 and the data signal line driving circuit 13 form a driving circuit for the liquid crystal panel 20. This driving circuit drives the liquid crystal panel 20 in a dot inversion manner as described below.

  The liquid crystal display device 10 is supplied with a vertical synchronization signal, a horizontal synchronization signal, an enable signal (indicating a valid period of display data), a dot clock, and display data for three RGB colors from the outside. Based on these input signals, the display control circuit 11 supplies a gate clock GCK and a gate start pulse GSP to the scanning signal line drive circuit 12, and also supplies a clock CK and a start pulse SP to the data signal line drive circuit 13. , Latch pulse LP, polarity switching signal REV, and display data DATA (display data for three colors of RGB) are supplied. In this way, the display control circuit 11 functions as a timing generation circuit that determines the timing necessary for driving the liquid crystal panel 20.

  The scanning signal line driving circuit 12 drives the scanning signal lines G1 to Gm based on the gate start pulse GSP and the gate clock GCK. More specifically, the scanning signal line drive circuit 12 has m stages of shift registers. A gate start pulse GSP is input to the serial data input terminal of the shift register, and a gate clock GCK is input to the clock terminal. One of a voltage corresponding to the selected state and a voltage corresponding to the non-selected state is applied to the scanning signal lines G1 to Gm according to m signals output from the shift register.

  The data signal line drive circuit 13 drives the data signal lines S1 to Sk based on the clock CK, the start pulse SP, the latch pulse LP, the polarity switching signal REV, and the display data DATA. More specifically, the display control circuit 11 sequentially outputs a start pulse SP, one row of display data DATA (3n pieces of display data), and a latch pulse LP for each line time. When the latch pulse LP is output, the data signal line drive circuit 13 applies a voltage corresponding to the display data for one row output before that to the data signal lines S1 to Sk.

  The polarity switching signal REV is switched between a high level and a low level every one line time or several line times. In response to the polarity switching signal REV, the data signal line driving circuit 13 applies (1) a voltage higher than the common electrode voltage Vcom to the odd-numbered data signal line, and applies the voltage from the common electrode voltage Vcom to the even-numbered data signal line. (2) A voltage lower than the common electrode voltage Vcom is applied to the odd-numbered data signal line, and a voltage higher than the common electrode voltage Vcom is applied to the even-numbered data signal line. . In this way, the liquid crystal panel 20 is driven by dot inversion.

  Hereinafter, features of the liquid crystal display device 10 will be described. The liquid crystal display device 10 includes a determination circuit 31 and a switch 32 in addition to the components of the conventional liquid crystal display device (FIG. 10). The determination circuit 31 determines display data supplied from the outside of the liquid crystal display device 10. The switch 32 switches whether the auxiliary capacitance line 23 is electrically connected to the common electrode 24 or connected to the ground based on the determination result by the determination circuit 31. The details are as follows.

  The display control circuit 11 has a built-in frame memory that can store display data for one frame. The display control circuit 11 delays display data supplied from the outside of the liquid crystal display device 10 by one frame time, and supplies the delayed display data to the data signal line drive circuit 13 as display data DATA. Further, the display control circuit 11 supplies the display data of the (N + 1) th frame to the determination circuit 31 while supplying the display data of the Nth frame to the data signal line driving circuit 13. Hereinafter, the display data supplied from the display control circuit 11 to the determination circuit 31 is referred to as DATAX.

  The determination circuit 31 determines the display data DATAX for one frame supplied from the display control circuit 11, and outputs a determination signal 33 indicating the result. More specifically, the determination circuit 31 determines whether or not a predetermined detection target pattern is included in a predetermined ratio or more (for example, 70% or more) in the display data DATAX for one frame. Here, the determination circuit 31 outputs a high level determination signal 33 when the determination result is affirmative, and outputs a low level determination signal 33 when the determination result is negative.

  The switch 32 has two input terminals, one control terminal, and one output terminal. One input terminal (hereinafter referred to as a first input terminal) of the switch 32 is connected to the output signal line of the common electrode control circuit 14, and the other input terminal (hereinafter referred to as a second input terminal) is connected to the ground. The control terminal of the switch 32 is connected to the output signal line of the determination circuit 31, and the output terminal is connected to the auxiliary capacitance line 23 outside the liquid crystal panel 20.

  When the determination signal 33 is at a low level (that is, when the determination result is negative), the switch 32 connects the output terminal to the first input terminal. Therefore, at this time, the auxiliary capacitance line 23 is connected to the output signal line of the common electrode control circuit 14 outside the liquid crystal panel 20, and the auxiliary capacitance line 23 has the same level as the common electrode voltage Vcom applied to the common electrode 24. The voltage Vcs is applied. On the other hand, when the determination signal 33 is at a high level (that is, when the determination result is affirmative), the switch 32 connects the output terminal to the second input terminal. Accordingly, at this time, the auxiliary capacitance line 23 is connected to the ground, and a ground voltage (0 V) is applied to the auxiliary capacitance line 23.

  Hereinafter, what data pattern is used as the detection target pattern in the determination circuit 31 will be described. In the liquid crystal display device 10, when display data that increases the voltage difference between adjacent data signal lines S <b> 1 to Sk is supplied, the common electrode voltage Vcom fluctuates greatly and current consumption increases. Therefore, in the determination circuit 31, a data pattern in which the voltage difference between the adjacent data signal lines S1 to Sk is large is used as a detection target pattern.

  Here, when the minimum value that can be taken by the display data is V0 and the maximum value is VM, the determination circuit 31 has a one-dimensional pattern (VA, VB) composed of two values VA, VB (where V0 ≦ VA ≦ VM). , V0 ≦ VB ≦ VM) is used as the detection target pattern. In this case, the determination circuit 31 determines whether or not a one-dimensional pattern as a detection target pattern is included in a row direction of the display data at a predetermined ratio or more. Thereby, the structure of the determination circuit 31 can be simplified. As shown below, the detection target pattern may include only one one-dimensional pattern or a plurality of one-dimensional patterns.

  For example, the detection target pattern may include only a one-dimensional pattern (V0, VM) composed of the minimum value V0 and the maximum value VM that can be taken by the display data (first example). In this case, the determination circuit 31 determines whether or not the one-dimensional pattern (V0, VM) is included in the row direction of the display data at a predetermined ratio or more.

  Alternatively, the detection target pattern includes a one-dimensional pattern (VA, VB) including a value VA within a predetermined range from the minimum value V0 that the display data can take and a value VB within the predetermined range from the maximum value VM that the display data can take. It may be included (second example). In this case, the determination circuit 31 determines whether or not a one-dimensional pattern (VA, VB) satisfying VA−V0 ≦ t and VM−VB ≦ t is included in the row direction of the display data at a predetermined ratio or more. .

  Alternatively, the detection target pattern includes a difference between the maximum value VM and the minimum value V0 that the display data can take (VB−VA) (VM−V0) in the difference (VB−VA) between VA and VB in the one-dimensional pattern (VA, VB). A one-dimensional pattern that is within a predetermined range may be included (third example). In this case, the determination circuit 31 determines whether or not a one-dimensional pattern (VA, VB) satisfying (VM−V0) − (VB−VA) ≦ t is included in the row direction of the display data at a predetermined ratio or more. judge. Note that the value of t in the second and third examples is determined based on the characteristics and specifications of the liquid crystal display device 10.

  As a specific example, when the data width of the display data is 8 bits, the minimum value that the display data can take is 0 and the maximum value is 255. In this case, the detection target pattern according to the first example includes only the one-dimensional pattern (0, 255). When the value of t is 1, the detection target pattern according to the second example includes four one-dimensional patterns (0, 255), (1, 255), (0, 254), (1, 254). The detection target pattern according to the third example includes three one-dimensional patterns (0, 255), (1, 255), and (0, 254).

  Note that the determination circuit 31 uses the display data DATAX (display data for three RGB colors) supplied from the display control circuit 11 in accordance with the arrangement order of the pixel electrodes in the liquid crystal panel 20, R, G, B, R, G, B, It is arranged in the order of ..., and it is determined whether or not the detection target pattern is included in the arranged data. For example, the first three display data are (R, G, B) = (V0, VM, V0), and the next three display data are (R, G, B) = (VM, V0, VM). When the one-dimensional pattern (V0, VM) is included in the detection target pattern, the determination circuit 31 detects this detection target pattern five times.

  FIG. 2 is a timing chart of the liquid crystal display device 10. FIG. 2 shows a state in which the display data of the last row of the Nth frame is supplied from the display control circuit 11 to the data signal line driving circuit 13. In FIG. 2, the start pulse SP and the latch pulse LP become high level for one cycle per one line time. After the start pulse SP becomes high level, the display data DATA is output over n cycles in synchronization with the clock CK. Since three display data are output per cycle, a total of 3n (= k) display data (corresponding to one row of display data) is output in one line time.

  When the latch pulse LP becomes a high level, the data signal line drive circuit 13 applies a voltage corresponding to the display data DATA for one row output before that to the data signal lines S1 to Sk. In addition, before the latch pulse LP becomes high level, the polarity switching signal REV is fixed at high level or low level. The data signal line drive circuit 13 applies a voltage higher than the common electrode voltage Vcom and a voltage lower than the common electrode voltage Vcom to the polarity switching signal REV for the odd-numbered data signal lines and the even-numbered data signal lines. Switching is applied according to.

  While the display data of the Nth frame is being supplied to the data signal line driving circuit 13, the display data of the (N + 1) th frame is supplied to the determination circuit 31. When the determination circuit 31 receives all the display data of the (N + 1) th frame, the determination circuit 31 outputs a determination signal 33 indicating the determination result of the display data of the (N + 1) th frame at the switching timing shown in FIG. At this time, the switch 32 switches whether to connect the auxiliary capacitance line 23 to the common electrode 24 or to ground according to the determination signal 33. Therefore, when it is determined in the determination circuit 31 that the display data of the (N + 1) th frame includes a detection target pattern at a predetermined ratio or more, the display data of the (N + 1) th frame is the data signal line drive circuit 13. The ground voltage (0 V) is applied to the storage capacitor line 23 before being supplied to the storage capacitor line 23.

  Hereinafter, the effect of the liquid crystal display device 10 according to the present embodiment will be described with reference to FIG. FIG. 3A is a circuit diagram showing an equivalent circuit of the liquid crystal panel 20 included in the conventional liquid crystal display device. FIG. 3B is a circuit diagram illustrating an equivalent circuit of the liquid crystal panel 20 when the determination result is affirmative in the liquid crystal display device 10 according to the present embodiment. 3A and 3B, the pixel capacitance Clc is a capacitance formed by the pixel electrode 21 and the common electrode 24. The auxiliary capacitance Ccs is a capacitance formed at a location where the pixel electrode 21 and the auxiliary capacitance line 23 intersect. The cross capacitance Cx is a capacitance formed at a location where the data signal lines S1 to Sk and the auxiliary capacitance line 23 intersect (the hatched portion in FIG. 11).

  In the conventional liquid crystal display device (FIG. 10), the auxiliary capacitance line 23 is connected to the output signal line of the common electrode control circuit 94 outside the liquid crystal panel 20. For this reason, in the equivalent circuit shown in FIG. 3A, the electrode of the pixel capacitor Clc that is not connected to the TFT element 22 and the electrode of the auxiliary capacitor Ccs that is not connected to the TFT element 22 are not used. All the electrodes on the side are connected to the output signal line of the common electrode control circuit 94.

  Therefore, when the voltage applied to the data signal lines S1 to Sk fluctuates, the influence is caused by the common electrode control circuit via the cross capacitance Cx and the auxiliary capacitance line 23 as shown by arrows in FIG. 94 to the common electrode voltage Vcom output. Therefore, it is necessary to provide an operational amplifier with a high slew rate and a high current capacity at the output stage of the common electrode control circuit 94.

  On the other hand, in the liquid crystal display device 10 (FIG. 1), when the determination result is affirmative, the auxiliary capacitance line 23 is connected to the ground instead of the output signal line of the common electrode control circuit 14. For this reason, in the equivalent circuit shown in FIG. 3B, the electrode on the side not connected to the TFT element 22 among the electrodes of the pixel capacitor Clc is connected to the output signal line of the common electrode control circuit 14, Of the electrodes of the auxiliary capacitor Ccs, the electrode not connected to the TFT element 22 is connected to the ground.

  Therefore, even if the voltage applied to the data signal lines S1 to Sk fluctuates, the influence is exerted on the signal line connected to the ground via the cross capacitor Cx as shown by the arrow in FIG. However, it does not reach the common electrode voltage Vcom output from the common electrode control circuit 14.

  Therefore, when the determination result is affirmative, the load on the common electrode control circuit 14 can be reduced by the amount of the auxiliary capacitance line 23, and fluctuations in the common electrode voltage Vcom output from the common electrode control circuit 14 can be suppressed. Further, since an operational amplifier having a lower slew rate and a lower current capacity than that of a conventional liquid crystal display device can be used at the output stage of the common electrode control circuit 14, the cost and current consumption of the liquid crystal display device can be reduced.

  Hereinafter, the above effect will be described in detail with reference to FIGS. Here, a case is considered where display data (hereinafter referred to as a vertical stripe pattern) shown in FIG. 4B is supplied to a liquid crystal display device having the dot configuration shown in FIG. In the vertical stripe pattern shown in FIG. 4, the minimum value V0 that can be taken by the display data and the maximum value VM that can be taken by the display data appear alternately for each column. In the liquid crystal display device 10, the polarity switching signal REV changes every two line times, and the determination circuit 31 uses a detection target pattern including only a one-dimensional pattern (V0, VM).

  When the vertical stripe pattern is supplied, the voltage applied to the data signal lines S1 to Sk of the liquid crystal display device 10 changes as shown in FIG. In FIG. 5, the data signal lines Sj and Sj + 2 are driven based on the maximum value VM that the display data can take, and the data signal line Sj + 1 is driven based on the minimum value V0 that the display data can take.

  In the first two line times, a voltage VMH higher than the common electrode voltage Vcom is applied to the data signal lines Sj and Sj + 2, and a voltage V0L lower than the common electrode voltage Vcom is applied to the data signal line Sj + 1. In the next two line times, a voltage VML lower than the common electrode voltage Vcom is applied to the data signal lines Sj and Sj + 2, and a voltage V0H higher than the common electrode voltage Vcom is applied to the data signal line Sj + 1. As an example of the voltage applied to the data signal line Sj, the voltage VML is 0V, the voltage V0L is 5.6V, the voltage V0H is 6.4V, and the voltage VMH is 12.0V.

  When the vertical stripe pattern is supplied to a conventional liquid crystal display device, the common electrode voltage Vcom varies as shown in FIG. The common electrode voltage Vcom shown in FIG. 6A includes a noise component that repeats pushing up and pushing down every two line times (referred to as a first noise) and a noise component that pushes down greatly every four line times (the second noise). Noise).

  The reason why the first noise occurs is that the influence of inversion driving of the data signal lines S1 to Sk every two line times extends to the common electrode voltage Vcom. The reason for the generation of the second noise is that the influence of fluctuations in the voltage applied to the data signal lines S1 to Sk is caused by the cross capacitance Cx (the cross capacitance formed at the location where the data signal line and the auxiliary capacitance line 23 intersect). ) And the auxiliary capacitance line 23, and reaches the common electrode voltage Vcom.

  On the other hand, when the vertical stripe pattern is supplied to the liquid crystal display device 10 according to this embodiment, the common electrode voltage Vcom varies as shown in FIG. In the common electrode voltage Vcom shown in FIG. 6B, the first noise is reduced as compared with the conventional case, and the second noise is completely suppressed. The reason why the first noise is reduced is that the load of the common electrode control circuit 14 is reduced by the amount of the auxiliary capacitance line 23. The reason why the second noise is suppressed is that the output signal line of the common electrode control circuit 14 is electrically disconnected from the auxiliary capacitance line 23.

  As described above, according to the liquid crystal display device 10 according to the present embodiment, when display data that greatly changes the common electrode voltage Vcom is input, this is detected and the auxiliary capacitance line 23 is connected to the ground. As a result, the load on the common electrode control circuit 14 can be reduced, and fluctuations in the common electrode voltage Vcom can be suppressed. At this time, since the output signal line of the common electrode control circuit 14 is electrically disconnected from the auxiliary capacitance line 23, it is possible to prevent noise generated in the auxiliary capacitance line 23 from affecting the common electrode voltage Vcom. it can.

  It should be noted that the conventional liquid crystal display device having the dot configuration shown in FIG. 4A is added to the display data (1 × 1 checkered pattern) shown in FIG. 7A and the display data (2) shown in FIG. Even when a (× 1 checkered pattern) is supplied, the common electrode voltage Vcom varies greatly as in FIG. On the other hand, in the liquid crystal display device 10 according to the present embodiment, if a one-dimensional pattern (V0, VM) is included in the detection target pattern used in the determination circuit 31, FIGS. 7 (a) and 7 (b). Even when the display data shown is supplied, the fluctuation of the common electrode voltage Vcom can be suppressed in the same manner as in FIG.

  Hereinafter, a mounting form of the liquid crystal display device 10 will be described. The liquid crystal display device 10 can be mounted in any form as long as it has the functional configuration shown in FIG. For example, the liquid crystal display device 10 can be configured by adding a semiconductor chip incorporating the determination circuit 31 and the switch 32 to the conventional liquid crystal display device (FIG. 10). Alternatively, a semiconductor chip incorporating the determination circuit 31 and the switch 32 may be added separately to the conventional liquid crystal display device.

  Alternatively, as shown in FIG. 8, a determination circuit 31 and a switch 32 may be incorporated in a semiconductor chip 41 in which the display control circuit 11 is incorporated. Alternatively, as shown in FIG. 9, a determination circuit 31 and a switch 32 may be incorporated in a semiconductor chip 42 that incorporates the display control circuit 11 and the common electrode control circuit 14. Alternatively, the determination circuit 31 and the switch 32 may be incorporated in a semiconductor chip that incorporates the display control circuit 11, the scanning signal line drive circuit 12, the data signal line drive circuit 13, and the common electrode control circuit 14. As described above, the peripheral circuit is changed by incorporating the determination circuit 31 and the switch 32 in the same semiconductor chip as all or part of the drive circuit of the liquid crystal panel 20 (particularly, the display control circuit 11 functioning as a timing generation circuit). The liquid crystal display device 10 can be configured while minimizing the above.

  In addition, the liquid crystal panel 20 may be formed monolithically or entirely with the display control circuit 11, the scanning signal line drive circuit 12, the data signal line drive circuit 13, and the common electrode control circuit 14. And / or both of the switches 32 may be formed monolithically.

  As described above, according to the liquid crystal display device according to the present embodiment, the auxiliary capacitance line is electrically connected to the common electrode voltage or connected to the ground based on the result of the determination on the display data. Is done. Therefore, when display data that greatly fluctuates the common electrode voltage is input, the load of the common electrode control circuit can be reduced and the fluctuation of the common electrode voltage can be suppressed by connecting the auxiliary capacitance line to the ground. . At this time, since the output signal line of the common electrode control circuit is electrically disconnected from the auxiliary capacitance line, it is possible to prevent noise generated in the auxiliary capacitance line from affecting the common electrode voltage. Further, in consideration of these points, the cost and current consumption of the liquid crystal display device can be reduced by using an operational amplifier having lower performance and lower cost than the conventional one at the output stage of the common electrode control circuit.

  Further, by using a one-dimensional pattern as a detection target pattern and detecting a detection target pattern included in the row direction of the display data, the configuration of the determination circuit can be simplified. Further, by using the detection target patterns of the first to third examples described above, it is possible to determine whether or not display data that greatly fluctuates the common electrode voltage is input. Further, by incorporating the determination circuit and the switch in the existing semiconductor chip, the liquid crystal display device according to the present embodiment can be configured while minimizing the change of the peripheral circuit.

It is a block diagram which shows the structure of the liquid crystal display device which concerns on one Embodiment of this invention. 2 is a timing chart of the liquid crystal display device shown in FIG. 1. It is a circuit diagram which shows the equivalent circuit of a liquid crystal panel about the liquid crystal display device conventionally and shown in FIG. It is a figure which shows the example of the display data supplied to a liquid crystal display device. It is a figure which shows the voltage change of the data signal line when the display data shown in FIG. 4 is supplied. FIG. 5 is a diagram showing how the common electrode voltage fluctuates when the display data shown in FIG. 4 is supplied to the conventional liquid crystal display device shown in FIG. It is a figure which shows the other example of the display data supplied to a liquid crystal display device. It is a figure which shows the example of the mounting form of the liquid crystal display device shown in FIG. It is a figure which shows the other example of the mounting form of the liquid crystal display device shown in FIG. It is a block diagram which shows the structure of the conventional liquid crystal display device. It is a figure which shows the cross capacity in a liquid crystal panel.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Liquid crystal display device 11 ... Display control circuit 12 ... Scanning signal line drive circuit 13 ... Data signal line drive circuit 14 ... Common electrode control circuit 20 ... Liquid crystal panel 21 ... Pixel electrode 22 ... TFT element 23 ... Auxiliary capacitance line 24 ... Common Electrode 31 ... Determination circuit 32 ... Switch 33 ... Determination signal 41, 42 ... Semiconductor chip

Claims (10)

An active matrix type liquid crystal display device,
A liquid crystal panel including a plurality of pixel electrodes arranged two-dimensionally, a plurality of switching elements corresponding to the pixel electrodes, an auxiliary capacitance line intersecting with the pixel electrodes, and a common electrode facing the pixel electrodes; ,
A common electrode control circuit for applying a common electrode voltage to the common electrode;
A driving circuit for performing dot inversion driving of the liquid crystal panel based on given display data;
A determination circuit for determining the display data;
A liquid crystal display device comprising: a switching circuit that switches whether the auxiliary capacitance line is electrically connected to the common electrode or grounded based on a determination result by the determination circuit. The determination circuit determines whether or not a predetermined detection target pattern is included in a predetermined ratio or more in the display data for one frame,
The switching circuit electrically connects the auxiliary capacitance line to the common electrode when the determination result is negative, and connects the auxiliary capacitance line to ground when the determination result is positive. The liquid crystal display device according to claim 1. The detection target pattern is a one-dimensional pattern,
The liquid crystal display device according to claim 2, wherein the determination circuit determines whether or not the detection target pattern is included in a row direction of the display data by a predetermined ratio or more.   The liquid crystal display device according to claim 3, wherein the detection target pattern is a one-dimensional pattern including two values.   The liquid crystal display device according to claim 4, wherein the detection target pattern includes a one-dimensional pattern including a minimum value and a maximum value that can be taken by the display data.   The detection target pattern includes a one-dimensional pattern including a value within a predetermined range from a minimum value that can be taken by the display data and a value within a predetermined range from a maximum value that can be taken by the display data. The liquid crystal display device according to claim 4.   5. The detection target pattern includes a one-dimensional pattern in which a difference between two values is within a predetermined range from a difference between a maximum value and a minimum value that can be taken by the display data. Liquid crystal display device.   2. The liquid crystal display device according to claim 1, wherein the determination circuit and the switching circuit are built in the same semiconductor chip as all or part of the drive circuit.   9. The liquid crystal display device according to claim 8, wherein the determination circuit and the switching circuit are built in the same semiconductor chip as a timing generation circuit included in the drive circuit. A liquid crystal panel including a plurality of pixel electrodes arranged two-dimensionally, a plurality of switching elements corresponding to the pixel electrodes, an auxiliary capacitance line intersecting with the pixel electrodes, and a common electrode facing the pixel electrodes A method of driving,
Applying a common electrode voltage to the common electrode;
Based on the given display data, the liquid crystal panel is driven to invert the dots,
Determining the display data; and
A method of driving a liquid crystal panel, comprising: switching the auxiliary capacitance line to be electrically connected to the common electrode or to ground based on a determination result.

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