KR101443373B1 - Liquid crystal panel, discharging method thereof and liquid crystal display device having the same - Google Patents

Abstract

A liquid crystal panel, a discharging method thereof, and a liquid crystal display device having the same are disclosed.

In the liquid crystal panel of the present invention, a storage capacitor is formed between the pixel electrode and the storage line. At power-on, a first data voltage is applied to the pixel electrode and a second data voltage is applied to the storage line. When power is off, the ground voltage is applied to the storage line. Accordingly, the first data voltage of the pixel electrode is lowered by the storage capacitor by the voltage change amount of the storage line. The voltage change amount of the storage line is a difference value between the second data voltage and the ground voltage.

Therefore, as soon as the power is turned off, the data voltage of the pixel electrode is discharged to the ground voltage immediately, so that the flicker due to the power on / off can be prevented and the image quality can be improved.

Liquid crystal display, BDF, discharge, scotch, flicker

Description

[0001] The present invention relates to a liquid crystal panel, a method of discharging the same, and a liquid crystal display device having the same.

The present invention relates to a liquid crystal panel capable of improving image quality, a discharging method thereof, and a liquid crystal display device having the same.

Due to the development of the information society, display devices capable of displaying information are actively being developed. The display device includes a liquid crystal display device, an organic electro-luminescence display device, a plasma display panel, and a field emission display device.

Of these, liquid crystal display devices have advantages such as light weight, low power consumption, and full color video implementation, and are widely applied to mobile phones, navigation, monitors, and televisions.

The liquid crystal display device periodically applies a positive polarity data voltage and a negative polarity data voltage to prevent deterioration of the liquid crystal. The positive polarity data voltage is at least higher than the common voltage, and the negative polarity data voltage is at least lower than the common voltage. When the range of the data voltage used in the liquid crystal display is 0V to 12V, the common voltage is 6V. Therefore, the range of the positive polarity data voltage is 6V to 12V, and the range of the negative polarity data voltage is 0V to 6V. A data voltage of a desired gradation can be applied to the liquid crystal display in each of the range of the positive polarity data voltage and the range of the negative polarity data voltage.

These data voltages are charged in the pixel electrodes arranged in the respective pixel regions of the liquid crystal display device.

At power-off, the voltage charged in the pixel electrode is discharged to the ground voltage. However, in the case of the positive polarity data voltage, since the pixel electrode is charged up to 12V at the maximum, it is not discharged quickly at the time of power-off.

A voltage not discharged during power-off remains in the pixel electrode with the residual DC.

In this case, there is a problem that the desired image is not displayed due to the residual DC remaining on the pixel electrode at power-on, resulting in deterioration of the image quality.

An object of the present invention is to provide a liquid crystal panel, a discharge method therefor, and a liquid crystal display device having the same, which can improve image quality by accelerating discharge.

According to an embodiment of the present invention, a liquid crystal panel includes: a plurality of gate lines; A plurality of data lines arranged to intersect with the respective gate lines and having a plurality of pixel regions defined by intersections with the gate lines; A plurality of thin film transistors arranged in each of the pixel regions; A plurality of pixel electrodes connected to each of the thin film transistors; A plurality of storage lines arranged in parallel to each of the gate lines; And a plurality of storage capacitors formed by the pixel electrodes and the storage lines, respectively, wherein a data voltage supplied to the data lines is applied to the storage lines at power-on, Voltage is applied.

According to another embodiment of the present invention, there is provided a liquid crystal display comprising a plurality of gate lines, a plurality of data lines arranged crossing the respective gate lines, A plurality of thin film transistors arranged in each of the pixel regions, a plurality of pixel electrodes connected to each of the thin film transistors, a plurality of storage lines arranged in parallel to each of the gate lines, A liquid crystal panel including a plurality of storage capacitors formed by the pixel electrodes and the storage lines, respectively; A gate driver for supplying a scan signal to the gate lines of the liquid crystal panel; A data driver for supplying a first data voltage to the data lines of the liquid crystal panel; And a voltage generator for applying a second data voltage to the storage lines of the liquid crystal panel at power-on and applying a ground voltage during power-off.

According to another embodiment of the present invention, there is provided a liquid crystal display device including: a plurality of gate lines; a plurality of data lines arranged in a crossing relation to the gate lines and having a plurality of pixel regions defined by intersection of the gate lines; A plurality of thin film transistors arranged in each of the pixel regions, a plurality of pixel electrodes connected to the thin film transistors, a plurality of storage lines arranged in parallel to the gate lines, And a plurality of storage capacitors formed by the storage lines, the method comprising: during the first period, the thin film transistors are turned on by a scan signal, and the pixel electrodes connected to the thin film transistors Applying a first data voltage to each storage line and applying a second data voltage to each of the storage lines; And applying a ground voltage to each of the storage lines during a first period and during a second period, wherein each of the thin film transistors is turned off and applies a ground voltage to each of the storage lines during the first period, A difference value of the data voltage is charged and a first data voltage applied to the pixel electrodes is dropped by a voltage variation amount of the storage line during the second interval.

As described above, in the present invention, a storage capacitor formed between the pixel electrode and the storage line is used to apply a maximum value of a data voltage, for example, a positive polarity data voltage, to the storage line at power- Apply the voltage. As a result, the data voltage of the pixel electrode is lowered by the amount of voltage change of the storage line by the storage capacitor, so that the data voltage of the pixel electrode is discharged immediately to the ground voltage as soon as the data voltage is turned off, thereby preventing flicker due to power on / off The image quality can be improved.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram showing a liquid crystal display device of the present invention.

1, a liquid crystal display includes a timing controller 12, a gate driver 14, a data driver 16, a gamma generator 24, a voltage generator 22, and a liquid crystal panel 30 .

The timing controller 12 generates a first control signal for driving the gate driver 14 and a second control signal for driving the data driver 16 to control the gate driver 14 and the data driver 16, (16). The timing controller 12 supplies red, green, and blue digital data signals to the data driver 16 for display on the liquid crystal panel 30. The timing controller 12 controls the voltage generator 22 to generate a voltage in the voltage generator 22. The voltage generator 22 may be operated independently of the timing controller 12. That is, the voltage generator 22 operates at power-on and generates a voltage. When the voltage generator 22 is not powered-off, the voltage generator 22 can be maintained at the ground voltage. The voltage generated in the voltage generator 22 is supplied to the liquid crystal panel 30. [ In this embodiment, the voltage generated by the voltage generator 22 may be the same as the data voltage output from the data driver 16. More specifically, the voltage generated by the voltage generating unit 22 may be the same as the maximum value of the positive polarity data voltage output from the data driver 16. [

The gate driver 14 generates a scan signal in response to the first control signal supplied from the timing controller and supplies the scan signal to the liquid crystal panel 30. The scan signal may be generated in units of one horizontal period (1H). A predetermined region may be overlapped between the respective scan signals supplied from the gate driver 14. [

The data driver 16 converts the red, green, and blue digital data signals supplied from the timing controller 12 into red, green, and blue analog data voltages, respectively, according to a second control signal supplied from the timing controller, And supplies it to the liquid crystal panel 30.

The gamma voltage generated by the gamma generator 24 may be used to convert the digital data signal into the analog data voltage. The gamma generating unit 24 generates a plurality of negative gamma voltages in a range from a ground voltage to a reference voltage and generates a plurality of positive gamma voltages in a range from a reference voltage to a supply voltage. The reference voltage may be the same as the common voltage supplied to the liquid crystal panel 30 and the supply voltage may be the same voltage as the maximum value of the positive polarity data voltage output from the data driver 16. [ The positive gamma voltage and the negative gamma voltage are supplied to the data driver 16.

The data driver 16 converts red, green, and blue digital data signals supplied from the timing controller 12 into red, green, and blue digital data signals using the positive gamma voltages and negative gamma voltages supplied from the gamma generator 24, Green and blue analog data voltages. For example, based on the red digital data signal supplied from the timing controller 12, the data driver 16 determines which polarity data voltage of the positive data voltage or the negative data voltage is to be output, Selects the gamma voltage of the corresponding polarity supplied from the gamma generator 24 based on the digital data signal and the determined polarity, and generates the analog data voltage using the selected gamma voltage.

The liquid crystal panel 30 includes a first substrate, a second substrate, and a liquid crystal layer interposed between the first and second substrates.

The first substrate is arranged so that a plurality of gate lines 31 and a plurality of data lines 32 cross each other. A pixel region is defined by the intersection of each gate line 31 and each data line 32. Accordingly, in the first substrate, a plurality of pixel regions may be arranged in a matrix form. A thin film transistor 34 is disposed at the intersection of each gate line 31 and each data line 32 and a pixel electrode 35 is connected to each thin film transistor 34. The storage line 33 is arranged in parallel with each gate line 31. Thus, the thin film transistor 34 may have a gate connected to the gate line 31, a source connected to the data line 32, and a drain connected to the pixel electrode 35. A storage capacitor 36 may be formed between the storage line 33 and the pixel electrode 35 by an insulating layer such as a gate insulating layer and a protective layer. The storage capacitor 36 maintains the voltage charged in the pixel electrode 35 for a predetermined period, for example, one frame.

The second substrate is provided with a color filter layer including red, green and blue color filters. Each color filter may be arranged to correspond to a pixel region. Between each color filter, a black matrix for blocking light by preventing light leakage may be disposed. On the color filter layer, a common electrode to which a common voltage generated by the common voltage generating portion 22 (not shown) is applied is disposed.

A liquid crystal layer including a plurality of liquid crystal molecules may be interposed between the first and second substrates.

The liquid crystal panel 30 may be a TN (twisted nematic) mode in which a thin film transistor is disposed on a first substrate and a color filter layer is disposed on a second substrate.

The operation of the liquid crystal display device at power-on will be described with reference to Figs. 1 and 2. Fig.

The scan signals supplied from the gate driver 14 are applied to the gate lines 31 of the first substrate. The thin film transistor 34 connected to each gate line 31 is turned on by the scan signal. The scan signal means a gate high voltage. The scan signal may be supplied to each gate line 31 during one horizontal period (1 H). Therefore, the gate line voltage can be supplied to each gate line 31 during the remaining period of one frame except for one horizontal period (1 H).

An analog data voltage supplied from the data driver 16, that is, a positive polarity data voltage or a negative polarity data voltage (hereinafter referred to as "data voltage") is applied to each data line 32 of the first substrate. The positive data voltage may be a voltage between the common voltage and the maximum value of the positive data voltage, and the negative data voltage may be a voltage between the ground voltage and the common voltage. The data voltage is applied to the pixel electrode 35 via the turn-on thin film transistor 34 connected to each data line 32. [

The maximum value of the voltage supplied from the voltage generator 22, that is, the positive polarity data voltage, is applied to the storage line 33 of the first substrate.

Therefore, the storage capacitor 36 may be maintained at a difference value between the data voltage and the maximum value of the positive polarity data voltage.

The common voltage supplied from the common voltage generator 22 is applied to the common electrode of the second substrate.

Therefore, when the positive polarity data voltage is applied to the pixel electrode 35, the positive polarity data voltage is at least higher than the common voltage, and therefore, the potential difference between the positive polarity data voltage and the common voltage causes the first and / An electric field is generated between the second substrate and the liquid crystal molecules are displaced by such an electric field, and the amount of light transmitted is controlled to display an image. When the negative data voltage is applied to the pixel electrode 35, since the negative data voltage is at least lower than the common voltage, the potential difference between the negative data voltage and the common voltage causes the first and second An electric field is generated between the substrates, and liquid crystal molecules are displaced by such an electric field, so that the amount of light transmitted is controlled to display an image. The pixel electrode 35 is formed in the storage capacitor 36 formed by the pixel electrode 35 and the storage line 33 since the same voltage as the maximum value of the positive polarity data voltage is continuously applied to the storage line 33. [ And the maximum value of the positive polarity data voltage applied to the storage line 33 can be maintained for one frame.

The liquid crystal molecules may be displaced in opposite directions according to the positive polarity data voltage and the negative polarity data voltage. As a result, a data voltage of the same polarity is applied to the liquid crystal molecules, so that the liquid crystal molecules are displaced only in one direction, and the liquid crystal can be prevented from deteriorating.

On the other hand, as shown in FIGS. 1 and 2, since the liquid crystal display device is not operated during power-off, the data voltage can no longer be applied to the pixel electrode 35, The image is not displayed.

The timing controller 12 is not operated when the power is turned off so that the first and second control signals for driving the gate driver 14 and the data driver 16 are not generated. As a result, the gate driver 14 and the data driver 16 are not operated, so that a scan signal is not generated in the gate driver 14 and a data voltage is not generated in the data driver 16. In addition, since the voltage generating unit 22 is not operated and a voltage equal to the maximum value of the positive polarity data voltage is not generated, the ground voltage is maintained, so that the storage line 33 is also maintained at the ground voltage.

The data stored in the pixel electrode 35 by the storage capacitor 36 formed between the pixel electrode 35 and the storage line 33 as the storage line 33 is maintained at the ground voltage during power- The voltage is increased by the amount of change of the voltage of the storage line 33. [ Since the amount of change in the voltage of the storage line 33 is changed by the difference between the maximum value of the positive data voltage and the ground voltage, the pixel electrode 35 is also enhanced by the difference between the maximum value of the positive data voltage and the ground voltage It is possible. The data voltage charged in the pixel electrode 35 is enhanced to a ground voltage so that rapid discharge can be performed. When the data voltage is not the maximum value of the positive polarity data voltage, the data voltage is lower than the maximum value of the positive polarity data voltage. Can be quickly strengthened to the ground voltage faster than the maximum value of the positive polarity data voltage.

FIG. 3A is a view for explaining the operation of the unit pixel region at power-on, and FIG. 3B is a view for explaining the operation of the unit pixel region at power-off.

3A, when the thin film transistor 34 is turned on by the scan signal supplied to the gate line 31 at power-on, the data voltage supplied to the data line 32 is applied to the turn- 34 to the pixel electrode 35. A maximum value of the positive polarity data voltage supplied from the voltage generator 22 may be applied to the storage line 33. [

In this case, the charge amount Q of the storage capacitor 36 is as follows.

은 파워 온시의 스토리지 캐패시터(36)의 전압 변화량이고, Vd는 파워 온시의 화소전극(35)에 충전된 데이터전압이고, Vdmax는 파워 온시의 스토리지라인(33)에 인가된 정극성 데이터전압의 최대값이다. Here, Cst is the storage capacitance formed between the pixel electrode 35 and the storage line 33, and?

Vd is the data voltage charged in the pixel electrode 35 at the time of power ON and Vdmax is the maximum voltage of the positive polarity data voltage applied to the storage line 33 at the time of power ON Value.

As shown in FIG. 3B, when the power is turned off, the scan signal is not supplied to the gate line 31, so that the thin film transistor 34 is turned off. As a result, the application of the data voltage to the pixel electrode 35 is cut off by the thin film transistor 34. When the maximum value of the positive polarity data voltage is applied to the storage line 33 in the pixel electrode 35, the previous data voltage can be maintained by the storage capacitor 36.

However, when the power is turned off, the storage line 33 is maintained at the ground voltage. Therefore, at the time of power-off, the voltage change amount of the storage line 33 becomes the difference value between the maximum value (Vdmax) of the positive polarity data voltage and the ground voltage (Vg).

In this case, the charge amount Q 'of the storage capacitor 36 is as follows.

은 파워 오프시의 스토리지 캐패시터(36)의 전압 변화량이고, V'd는 파워 오프시의 화소전극(35)에 충전된 데이터전압이고, Vg는 파워 오프시의 스토리지라인(33)에 인가된 그라운드 전압의 최대값이다. Here,?

Vd is a data voltage charged in the pixel electrode 35 at power-off, and Vg is a ground voltage applied to the storage line 33 at the time of power- It is the maximum value of the voltage.

The amount of charge Q at the time of power ON and the amount of charge Q 'at the time of power OFF are the same because the amount of charge at power-on and power-off must be maintained by the charge conservation law. Since the storage capacitance is uniquely determined by the material properties, it is the same at power-on and power-off.

)과 파워 오프시의 스토리지 캐패시터(36)의 전압 변하량(Δ

) 또한 동일하고, 다음과 같이 나타낼 수 있다.Therefore, the voltage change amount (?) Of the storage capacitor 36 at power-

) Of the storage capacitor 36 at the time of power-off

) Are also the same and can be expressed as follows.

In summary,

은 스토리지라인(33)의 전압 변화량이고,

은 화소전극(35)의 전압 변화량이다.here,

Is a voltage variation amount of the storage line 33,

Is a change amount of the voltage of the pixel electrode 35.

Therefore, the pixel electrode 35 is changed to the same amount of change by the amount of change of the storage line 33. [

Equation (6) is summarized as follows.

Vd '= Vd- (Vdmax-Vg)

Therefore, the voltage Vd 'charged in the pixel electrode 35 at the time of power-off is lowered by the voltage variation amount of the storage line 33 at the voltage Vd charged in the pixel electrode 35 at the time of power-on.

For example, it is assumed that the maximum value of the positive polarity data voltage supplied to the storage line 33 is 12V, and the ground voltage supplied to the storage line 33 is 0V.

The data voltage charged in the pixel electrode 35 can also be lowered to 12V because the difference between the maximum value of the positive polarity data voltage and the ground voltage, that is, 12V, is lowered on the storage line 33 during power-off. When the maximum value of the positive polarity data voltage is charged in the pixel electrode 35 because the maximum value of the positive polarity data voltage is 12 V, the data voltage charged in the pixel electrode 35 falls immediately by 12 V at the time of power- So that a rapid discharge can be achieved. In addition, since the data voltage other than the maximum value of the positive polarity data voltage charged in the pixel electrode 35 is at least lower than the maximum value of the positive polarity data voltage, the maximum value of the positive polarity data voltage charged in the pixel electrode 35 Other data voltages are immediately dropped to the ground voltage, so that a rapid discharge can be achieved. Therefore, any data voltage charged in the pixel electrode 35 at the time of power-off is immediately discharged to the ground voltage, so that no residual DC remains in the pixel electrode 35 and an image with improved image quality at the time of power- have.

The present embodiment can be applied to a TN mode of a brightness dot free (BDF) structure in which a dark point is improved. The TN mode of the BDF structure has the same structure as the liquid crystal panel 30 of FIG. However, the TN mode of the BDF structure is a structure that is manufactured so as to be driven by the luminescent spot by improving the dark spot caused by a conductive foreign substance in a specific pixel region or a TFT defect due to the application of a data voltage to the pixel electrode 35. If a dark spot is generated in a specific pixel area, the pixel electrode 35 and the storage line 33 in a specific pixel area are artificially short-circuited by using a laser or the like. In this case, the maximum value of the voltage supplied to the storage line 33, for example, the positive polarity data voltage, may be applied to the pixel electrode 35. [ Since the maximum value of the positive polarity data voltage is a voltage capable of generating the maximum potential difference with the common voltage, the maximum electric potential difference between the maximum value of the positive polarity data voltage applied to the pixel electrode 35 and the common voltage And is displayed in black so that the dark point is maintained. In the TN mode, when a maximum potential difference is generated between the common electrode and the pixel electrode 35, a black image can be displayed.

1 is a block diagram showing a liquid crystal display device of the present invention.

Fig. 2 is a waveform chart of power on / off in the liquid crystal display of Fig. 1; Fig.

3A is a view for explaining the operation of the power-on unit pixel region;

FIG. 3B is a view for explaining the operation of a unit pixel region at power-off; FIG.

Description of the Related Art

12: timing controller 14: gate driver

16: Data driver 22: Voltage generator

24: gamma generator 30: liquid crystal panel

31: gate line 32: data line

33: storage line 34: thin film transistor

35: pixel electrode 36: storage capacitor

Claims (13)

A plurality of gate lines; A plurality of data lines arranged to intersect with the respective gate lines and having a plurality of pixel regions defined by intersections with the gate lines; A plurality of thin film transistors arranged in each of the pixel regions; A plurality of pixel electrodes connected to each of the thin film transistors; A plurality of storage lines arranged in parallel to each of the gate lines; And A plurality of storage capacitors formed by each of the pixel electrodes and each of the storage lines, A positive data voltage or a negative data voltage supplied to each of the data lines is applied to each of the pixel electrodes, And applies a maximum value of a positive polarity data voltage to each of the storage lines while the positive polarity data voltage or the negative polarity data voltage is applied, And a ground voltage is applied to each of the plurality of liquid crystal panels. delete The liquid crystal panel according to claim 1, wherein, in power-off, a voltage applied to each of the pixel electrodes is lowered by the storage capacitor by a difference between a maximum value of the positive polarity data voltage and the ground voltage. delete The liquid crystal panel according to claim 1, wherein a defective pixel region of the pixel region shorts between the pixel electrode of the pixel region and the storage line. A plurality of gate lines, a plurality of data lines arranged in an intersection with the gate lines, wherein a plurality of pixel regions are defined by intersections of the gate lines and a plurality of data lines arranged in each of the pixel regions, A plurality of pixel electrodes connected to each of the thin film transistors, a plurality of storage lines arranged in parallel to each of the gate lines, and a plurality of gate lines formed by each of the pixel electrodes and the storage lines, A liquid crystal panel including a plurality of storage capacitors; A gate driver for supplying a scan signal to the gate lines of the liquid crystal panel; A data driver for applying a first data voltage, which is either a positive data voltage or a negative data voltage, to the data lines of the liquid crystal panel; And And a voltage generator for applying a second data voltage, which is a maximum value of a positive polarity data voltage at the time of power-on, to the storage lines of the liquid crystal panel, and applying a ground voltage at power- Wherein the voltage generating unit operates at power-on and is not operated at power-off. delete delete A plurality of gate lines, a plurality of data lines arranged in an intersection with the gate lines, wherein a plurality of pixel regions are defined by intersections of the gate lines and a plurality of data lines arranged in each of the pixel regions, A plurality of pixel electrodes connected to each of the thin film transistors, a plurality of storage lines arranged in parallel to each of the gate lines, and a plurality of gate lines formed by each of the pixel electrodes and the storage lines, A method of discharging a liquid crystal panel including a plurality of storage capacitors, During the first period, each thin film transistor is turned on by a scan signal, and a first data voltage, which is either a positive data voltage or a negative data voltage, is applied to the pixel electrodes connected to the thin film transistors, Applying a second data voltage which is a maximum value of the positive polarity data voltage to the storage line; And And applying a ground voltage to each of the storage lines during the second period, wherein each thin film transistor is turned off, The storage capacitors are charged with the difference between the first data voltage and the second data voltage during the first interval and the difference between the first data voltage and the second data voltage is applied to the pixel electrodes during the second interval, Lt; RTI ID = 0.0 > 1, < / RTI > Wherein a maximum value of the positive polarity data voltage is applied to each of the storage lines while the positive polarity data voltage or the negative polarity data voltage is applied, and while the positive polarity data voltage or the negative polarity data voltage is not applied, And a ground voltage is applied to each of the first and second electrodes. The method of claim 9, wherein the first period is a power-on period and the second period is a power-off period. 10. The method of claim 9, wherein the first data voltage is directly dropped to the ground voltage by the storage capacitors. delete delete

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