JP2007053195A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2007053195A5 JP2007053195A5 JP2005236591A JP2005236591A JP2007053195A5 JP 2007053195 A5 JP2007053195 A5 JP 2007053195A5 JP 2005236591 A JP2005236591 A JP 2005236591A JP 2005236591 A JP2005236591 A JP 2005236591A JP 2007053195 A5 JP2007053195 A5 JP 2007053195A5
- Authority
- JP
- Japan
- Prior art keywords
- tab
- semiconductor device
- manufacturing
- groove
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims 25
- 238000004519 manufacturing process Methods 0.000 claims 8
- 239000011347 resin Substances 0.000 claims 3
- 229920005989 resin Polymers 0.000 claims 3
- 238000007789 sealing Methods 0.000 claims 3
- 238000005530 etching Methods 0.000 claims 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims 1
- 229910052802 copper Inorganic materials 0.000 claims 1
- 239000010949 copper Substances 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
Claims (15)
（ｂ）前記半導体チップを、前記ダイアタッチフィルムを介して搭載するタブと、
（ｃ）前記タブの周囲に配置された複数のリードと、
（ｄ）前記複数のリードと前記半導体チップを接続する複数のワイヤと、
（ｅ）前記半導体チップを封止する樹脂とを備え、
前記タブは枠形状をしていることを特徴とする半導体装置。 (A) a semiconductor chip having a die attach film attached to one surface;
(B) a tab for mounting the semiconductor chip via the die attach film;
(C) a plurality of leads disposed around the tab;
(D) a plurality of wires connecting the plurality of leads and the semiconductor chip;
(E) a resin for sealing the semiconductor chip;
2. The semiconductor device according to claim 1, wherein the tab has a frame shape.
（ｂ）ダイアタッチフィルムを貼り付けた半導体チップを前記タブ上に搭載する工程と、
（ｃ）前記タブの周囲に配置された複数のリードと前記半導体チップとを複数のワイヤで接続する工程と、
（ｄ）前記半導体チップを封止する工程とを備えることを特徴とする半導体装置の製造方法。 (A) preparing a lead frame having a frame-shaped tab;
(B) mounting a semiconductor chip with a die attach film on the tab;
(C) connecting a plurality of leads arranged around the tab and the semiconductor chip with a plurality of wires;
(D) A method for manufacturing a semiconductor device, comprising: sealing the semiconductor chip.
（ｅ）前記半導体チップを封止することにより形成された半導体装置を、鉛を含有しない半田を介して実装基板に実装することを特徴とする請求項８記載の半導体装置の製造方法。 further,
9. The method of manufacturing a semiconductor device according to claim 8, wherein the semiconductor device formed by sealing the semiconductor chip is mounted on a mounting substrate via solder not containing lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005236591A JP4668729B2 (en) | 2005-08-17 | 2005-08-17 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005236591A JP4668729B2 (en) | 2005-08-17 | 2005-08-17 | Manufacturing method of semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2007053195A JP2007053195A (en) | 2007-03-01 |
| JP2007053195A5 true JP2007053195A5 (en) | 2008-10-02 |
| JP4668729B2 JP4668729B2 (en) | 2011-04-13 |
Family
ID=37917443
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005236591A Expired - Fee Related JP4668729B2 (en) | 2005-08-17 | 2005-08-17 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4668729B2 (en) |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6215844A (en) * | 1985-07-15 | 1987-01-24 | Hitachi Ltd | Semiconductor lead frame |
| JPS63248155A (en) * | 1987-04-03 | 1988-10-14 | Mitsubishi Electric Corp | Semiconductor device |
| US5233222A (en) * | 1992-07-27 | 1993-08-03 | Motorola, Inc. | Semiconductor device having window-frame flag with tapered edge in opening |
| JPH06236899A (en) * | 1992-09-29 | 1994-08-23 | Toshiba Corp | Resin sealed type semiconductor device |
| JPH06268146A (en) * | 1993-03-15 | 1994-09-22 | Toshiba Corp | Semiconductor device |
| JPH10303352A (en) * | 1997-04-22 | 1998-11-13 | Toshiba Corp | Semiconductor device and manufacture of semiconductor device |
| JP3605651B2 (en) * | 1998-09-30 | 2004-12-22 | 日立化成工業株式会社 | Method for manufacturing semiconductor device |
| JP3062691B1 (en) * | 1999-02-26 | 2000-07-12 | 株式会社三井ハイテック | Semiconductor device |
| JP3895570B2 (en) * | 2000-12-28 | 2007-03-22 | 株式会社ルネサステクノロジ | Semiconductor device |
| JP2003332522A (en) * | 2002-05-17 | 2003-11-21 | Mitsubishi Electric Corp | Semiconductor device |
| JP2005203401A (en) * | 2004-01-13 | 2005-07-28 | Sumitomo Bakelite Co Ltd | Semiconductor device and manufacturing method thereof |
-
2005
- 2005-08-17 JP JP2005236591A patent/JP4668729B2/en not_active Expired - Fee Related
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI337387B (en) | Leadframe for leadless package, package structure and manufacturing method using the same | |
| JP3420057B2 (en) | Resin-sealed semiconductor device | |
| US8159055B2 (en) | Semiconductor device, lead-frame product used for the same and method for manufacturing the same | |
| US7176557B2 (en) | Semiconductor device | |
| JP5227501B2 (en) | Stack die package and method of manufacturing the same | |
| JP2009076658A5 (en) | ||
| KR20090033141A (en) | Integrated circuit package system with leadframe array | |
| KR101440933B1 (en) | Integrated circuit package system employing bump technology | |
| JP2006128455A5 (en) | ||
| JP2005223331A (en) | Lead frame, semiconductor chip package using the same, and manufacturing method of the semiconductor chip package | |
| JP2006261519A (en) | Semiconductor device and its manufacturing method | |
| JP2005142554A (en) | Lead frame and method for manufacturing semiconductor package using it | |
| US20220157700A1 (en) | Two sided bondable lead frame | |
| JP4987041B2 (en) | Manufacturing method of semiconductor device | |
| US7432127B2 (en) | Chip package and package process thereof | |
| TW201216384A (en) | Chip package structure and chip packaging method | |
| JP2007053195A5 (en) | ||
| JP2010010634A5 (en) | ||
| JP2007134585A5 (en) | ||
| JP2682200B2 (en) | Semiconductor device | |
| JP2000012741A (en) | Semiconductor device and its manufacture | |
| KR100911461B1 (en) | Semiconductor package | |
| KR20090059192A (en) | Substrate for manufacturing semiconductor package and, method for manufacturing semiconductor package using the same | |
| TWI662659B (en) | Carrier | |
| JP5149694B2 (en) | Semiconductor device and manufacturing method thereof |