JP2007052290A - Display device and its drive method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device and its drive method that can optimize both the black brightness and white brightness. <P>SOLUTION: This device has gate lines 105-1 to 105-m arranged corresponding to the row arrangement in the pixel circuit, capacitor wiring 106-1 to 106-m arranged corresponding to the row arrangement in the pixel circuit, a vertical drive circuit 102 to selectively drive the gate lines and capacitor wiring, and a generator circuit 104 to generate a common voltage signals of a small amplitude changing its level at a predetermined cycle. Each pixel circuit includes a liquid crystal cell LC201 having a first and second pixel electrodes and a sustaining capacitor CS201 having a first and second pixel electrodes. The first electrode of the liquid crystal cell and the first electrode of the sustaining capacitor are connected to an end of the TFT, and the second electrode of the sustaining capacitor is connected to the capacitor wiring of the row it matches, then the common voltage signal is applied to the second pixel electrode of the liquid crystal cell. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an active matrix display device in which, for example, liquid crystal cells are arranged in a matrix form with display elements (electro-optical elements) of pixels in a display region, and a driving method thereof.

  A display device, for example, a liquid crystal display device using a liquid crystal cell as a pixel display element (electro-optical element), is characterized by being thin and low power consumption, for example, a personal digital assistant (PDA), portable It is applied to a wide range of electronic devices such as telephones, digital cameras, video cameras, and display devices for personal computers.

FIG. 1 is a block diagram illustrating a configuration example of a liquid crystal display device (see, for example, Patent Documents 1 and 2).
As shown in FIG. 1, the liquid crystal display device 1 includes an effective pixel unit 2, a vertical drive circuit (VDRV) 3, and a horizontal drive circuit (HDRV) 4.

In the effective pixel portion 2, a plurality of pixel circuits 21 are arranged in a matrix.
Each pixel circuit 21 includes a thin film transistor (TFT) 21 as a switching element, a liquid crystal cell LC 21 having a pixel electrode connected to the drain electrode (or source electrode) of the TFT 21, and one electrode connected to the drain electrode of the TFT 21. The storage capacitor Cs21 is connected.
For each of these pixel circuits 21, scanning lines (gate lines) 5-1 to 5-m are wired along the pixel arrangement direction for each row, and signal lines 6-1 to 6-n are provided for each column. Wiring is performed along the pixel array direction.
The gate electrodes of the TFTs 21 of the pixel circuits 21 are connected to the same scanning lines 5-1 to 5-m in units of rows. The source electrode (or drain electrode) of each pixel circuit 21 is connected to the same signal line 6-1 to 6-n in each column unit.

Further, in a general liquid crystal display device, the storage capacitor line Cs is independently wired, and the storage capacitor line Cs21 is formed between the storage capacitor line Cs and the first electrode of the liquid crystal cell LC21. Cs receives a common voltage VCOM and an in-phase pulse, and is used as a storage capacitor. In a general liquid crystal display device, the storage capacitors Cs21 of all the pixel circuits 21 in the effective pixel unit 2 are commonly connected to one storage capacitor line Cs.
The second electrode of the liquid crystal cell LC21 of each pixel circuit 21 is commonly connected to the supply line 7 of the common voltage Vcom whose polarity is inverted every horizontal scanning period (1H), for example.

  The scanning lines 5-1 to 5-m are driven by the vertical driving circuit 3, and the signal lines 6-1 to 6-n are driven by the horizontal driving circuit 4.

The vertical driving circuit 3 performs a process of sequentially selecting each pixel circuit 21 connected to the scanning lines 5-1 to 5-m in units of rows by scanning in the vertical direction (row direction) every field period.
That is, when the scanning pulse SP1 is applied from the vertical driving circuit 3 to the scanning line 5-1, the pixel in each column of the first row is selected and the scanning pulse SP2 is applied to the scanning line 5-2. In this case, the pixels in each column of the second row are selected. Similarly, scanning pulses SP3,..., SPm are sequentially applied to the scanning lines 5-3,.

  2A to 2E are timing charts in the so-called 1HVcom inversion driving method of the general liquid crystal display device shown in FIG.

As another driving method, a capacitive coupling driving method is known in which the voltage applied to the liquid crystal is modulated using coupling from the storage capacitor wiring Cs (see, for example, Patent Document 3).
Japanese Patent Laid-Open No. 11-119746 JP 2000-298459 A Japanese Patent Laid-Open No. 2-157815

  Compared to the 1HVcom inversion driving method, the capacitive coupling driving method described above can improve the response speed of the liquid crystal due to so-called overdrive, and can reduce audio noise generated in the Vcom frequency band. There is a feature that can be made.

However, this capacitive coupling driving method described in Patent Document 3 is adopted in a liquid crystal display device using a liquid crystal material (corresponding to normally white) having a liquid crystal dielectric constant ε characteristic with respect to an applied voltage as shown in FIG. In this case, as shown in the following formula (1) and FIGS. 4 and 5, there is a disadvantage that white luminance becomes black (sinks) when black luminance is optimized.
As a result, in the liquid crystal display device adopting the current capacitive coupling driving method, there is a disadvantage that both the black luminance and the white luminance cannot be optimized simultaneously.

(Equation 1)
ΔVpix1 = Vsig + {Ccs / (Ccs + Clc)} * ΔVcs−Vcom (1)

In Expression (1), ΔVpix represents the effective pixel potential, Vsig represents the video signal voltage, Ccs represents the storage capacitor, Clc represents the liquid crystal capacitance, ΔVcs represents the potential of the signal CS, and Vcom represents the common voltage.
As described above, when the black luminance is optimized, the white luminance is sunk in the term {Ccs / (Ccs + Clc)} * ΔVcs in the above formula (1), and the nonlinearity of the liquid crystal dielectric constant. This affects the effective pixel potential.

  An object of the present invention is to provide a display device capable of optimizing both black luminance and white luminance and a driving method thereof.

  A display device according to a first aspect of the present invention is disposed so as to correspond to a pixel portion in which a plurality of pixel circuits for writing image pixel data through switching elements are arranged in a matrix and a row arrangement of the pixel circuits, A plurality of scanning lines for controlling the conduction of the switching elements, a plurality of capacitance wirings arranged to correspond to the row arrangement of the pixel circuits, and arranged to correspond to the column arrangement of the pixel circuits, A plurality of signal lines that propagate pixel data, a driving circuit that selectively drives the plurality of scanning lines, and the plurality of capacitance lines, and a generation that generates a common voltage signal having a small amplitude whose level is switched at a predetermined cycle. Each pixel circuit arranged in the pixel portion includes a display element having a first pixel electrode and a second pixel electrode, and a first electrode and a second electrode. The first pixel electrode of the display element, the first electrode of the storage capacitor, and one terminal of the switching element are connected, and the second electrode of the storage capacitor is arranged in a corresponding row. The common voltage signal is applied to the second pixel electrode of the display element connected to the capacitor wiring.

  Preferably, the driving circuit drives a scanning line of a selected row to write pixel data in a desired pixel circuit, and then drives the capacitor wiring of the same row.

  Preferably, the drive circuit selects one of a first level and a second level lower than the first level as a signal for driving the capacitor line, and applies the selected signal to the corresponding capacitor line.

  Preferably, the amplitude value of the common voltage signal and the value of the potential difference between the first level and the second level of the signal for driving the capacitive wiring are selected so that the effective pixel potential is not more than a predetermined threshold value. ing.

  Preferably, the display element of the pixel circuit is a liquid crystal cell.

  A display device according to a second aspect of the present invention corresponds to a pixel portion in which a plurality of pixel circuits for writing video pixel data propagated through a signal line through a switching element are arranged in a matrix, and a row arrangement of the pixel circuits. And a plurality of scanning lines for controlling the conduction of the switching elements, a plurality of capacitance lines arranged to correspond to the row arrangement of the pixel circuits, and the pixels arranged in the pixel portion The circuit includes a display element having a first pixel electrode and a second pixel electrode, and a storage capacitor having a first electrode and a second electrode, wherein the first pixel electrode of the display element and the first electrode of the storage capacitor And a terminal of the switching element is connected, and the second electrode of the storage capacitor is connected to the capacitor wiring arranged in a corresponding row, the method of driving the display device, The wiring is driven individually, a common voltage signal having a small amplitude whose level is switched at a predetermined cycle is applied to the second pixel electrode of the display element, and the scanning line of the selected row is driven to form a desired pixel circuit. After writing the pixel data, the capacitor wiring in the same row is driven.

  According to the present invention, there is an advantage that both black luminance and white luminance can be optimized.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 6 is a diagram illustrating a configuration example of an active matrix display device according to an embodiment of the present invention in which, for example, a liquid crystal cell is used as a pixel display element (electro-optical element).

  As shown in FIG. 6, the display device 100 includes an effective pixel unit 101, a vertical drive circuit (VDRV) 102, a horizontal drive circuit (HDRV) 103, and a common voltage generation circuit (VcomGen) 104 as main components. is doing.

As shown in FIG. 7, the effective pixel unit 101 includes a plurality of pixel circuits PXLC arranged in an m × n matrix. Specifically, for example, 320 × RGB × 320 pixel circuits are arranged so that normal display is possible as a whole.
In FIG. 7, a 4 × 4 matrix arrangement is shown for simplification of the drawing.

As shown in FIG. 7, each pixel circuit PXLC includes a TFT (thin film transistor) 201 as a switching element, a liquid crystal cell LC201 having a first pixel electrode connected to the drain electrode (or source electrode) of the TFT 201, The storage capacitor Cs201 includes a first electrode connected to the drain electrode of the TFT201.
Note that a node ND201 is formed by a connection point between the drain of the TFT 201, the first pixel electrode of the liquid crystal cell LC201, and the first electrode of the storage capacitor CS201.

  For each of these pixel circuits PXLC, gate lines (scanning lines) 105-1 to 105-m and storage capacitor lines (hereinafter referred to as storage lines) 106-1 to 106-m are arranged in the pixel arrangement direction for each row. The signal lines 107-1 to 107-n are wired along the pixel arrangement direction for each column.

The gate electrode of the TFT 201 of each pixel circuit PXLC is connected to the same gate line 105-1 to 105-m for each row.
The second electrode of the storage capacitor Cs of each pixel circuit PXLC is connected to the same storage line 106-1 to 106-m for each row.
Further, the source electrode (or drain electrode) of each pixel circuit PXLC is connected to the same signal line 107-1 to 107-n for each column.
The second pixel electrode of the liquid crystal cell LC201 of each pixel circuit PXLC is connected in common to a supply line (not shown) of a small amplitude common voltage VCOM whose polarity is inverted during one horizontal scanning period (1H).

  Each of the gate lines 105-1 to 105-m is driven by a gate driver of the vertical drive circuit 102, and each of the storage lines 106-1 to 106-m is driven by a capacity driver (CS driver) of the vertical drive circuit 102. The signal lines 107-1 to 107-n are driven by the horizontal drive circuit 103.

The vertical drive circuit 102 basically scans in the vertical direction (row direction) for each field period and sequentially selects each pixel circuit PXLC connected to the gate lines 105-1 to 105-m in units of one row. Perform the process.
That is, the vertical driving circuit 102 applies the gate pulse GP1 to the gate line 105-1 to select the pixels in each column of the first row, and applies the gate pulse GP2 to the gate line 105-2. A pixel in each column in the second row is selected. Similarly, gate pulses GP3,..., GPm are sequentially applied to the gate lines 105-3,.

  Further, the vertical drive circuit 102 has a first level (CSH, for example, 3V-4V) or a second level (CSL) for each storage line 106-1 to 106-m independently wired corresponding to each gate line. , For example, 0V), the capacitance signals (hereinafter referred to as storage signals) CS1 to CSm selected in order are given.

  8A to 8L are timing charts showing examples of driving the gate lines and the storage lines of the vertical drive circuit of this embodiment.

The vertical drive circuit 102 drives the gate lines 105-1 to 105-m and the storage lines 106-1 to 106-m in order from the first row, for example, but drives one gate line with a gate pulse. After (after signal writing), the levels of the storage signals CS1 to CSm applied to the storage lines 106-1 to 106-m at the timing of the rise of the gate pulse of the next gate line are changed to the first level CSH as follows. And the second level CSL are alternately selected and applied.
For example, when the vertical drive circuit 102 selects the first level CSH and applies the storage signal CS1 to the storage line 106-1 in the first row, the second level in the storage line 106-2 in the second row. The CSL is selected and the storage signal CS2 is applied, the first level CSH is selected and the storage signal CS3 is applied to the third row storage line 106-3, and the fourth row storage line 106-4 is applied. Selects the second level CSL, applies the storage signal CS4, and similarly selects the first level CSH and the second level CSL alternately to transfer the storage signals CS5 to CSm to the storage lines 106-5 to 106-m. Apply to.
Further, when the storage signal CS1 is applied by selecting the second level CS1 to the first-line storage line 106-1, the first-level CSH is selected and stored in the second-line storage line 106-2. The signal CS2 is applied, the second level CSL is selected for the third row storage line 106-3 and the storage signal CS3 is applied, and the first level CSH is applied to the fourth row storage line 106-4. The storage signal CS4 is selected and applied, the second level CSL and the first level CSH are alternately selected in the same manner, and the storage signals CS5 to CSm are applied to the storage lines 106-5 to 106-m.

  In the present embodiment, after the fall of the gate pulse GP (after writing from the signal line), the storage lines 106-1 to 106-m are driven and coupled via the storage capacitor CS201, thereby causing the pixel potential (node). The voltage applied to the liquid crystal is modulated by changing the potential of the ND 201.

FIG. 7 schematically shows an example of the level selection output unit of the CS driver 1020 of the vertical drive circuit 102.
The CS driver 1020 includes a variable power supply unit 1021, a first level supply line 1022 connected to the positive electrode side of the power supply unit 1021, a second level supply line 1023 connected to the negative electrode side of the power supply unit 1021, and a first level. It includes switches SW1 to SWm that selectively connect the storage lines 106-1 to 106-m in which the supply line 1022 or the second level supply line 1023 is wired for each row of the pixel array.

In FIG. 7, ΔVcs indicates a level difference (potential difference) between the first level CSH and the second level CSL.
As will be described in detail later, the amplitude ΔVcom of the alternating common voltage Vcom having a small amplitude with respect to ΔVcs is selected to be a value that can optimize both the black luminance and the white luminance.
For example, as will be described later, the effective pixel potential ΔVpix applied to the liquid crystal during white display. The values of ΔVcs and ΔVcom are determined so that W becomes a value of 0.5V or less.

The vertical drive circuit 102 includes a vertical shift register group, and includes a plurality of shift registers VSR provided corresponding to gate buffers to which gate lines arranged for each row are connected corresponding to the pixel arrangement. Each shift register VSR is supplied with a vertical start pulse VST for instructing the start of vertical scanning generated by a clock generator (not shown) and a vertical clock VCK (or vertical clocks VCK and VCKX having opposite phases to each other) as a reference for vertical scanning. The
For example, the shift register shifts the vertical start pulse VST in synchronization with the vertical clock VCK and supplies it to the corresponding gate buffer.
Further, the vertical start pulse VST is propagated from the upper side or the lower side of the effective pixel portion 101 and is sequentially shifted into each shift register.
Therefore, basically, the gate lines are sequentially driven through the gate buffers by the vertical clock supplied from the shift register VSR.

  The horizontal drive circuit 103 receives an input video signal Vsig based on a horizontal start pulse HST for instructing the start of horizontal scanning and a horizontal clock HCK (or vertical clocks HCK and HCKX having opposite phases to each other) as a reference for horizontal scanning. Sampling is sequentially performed every 1H (H is a horizontal scanning period), and writing processing is performed on each pixel circuit PXLC selected in units of rows by the vertical driving circuit 102 via the signal lines 107-1 to 107-n.

The common voltage generation circuit 104 generates a small-amplitude common voltage VCOM whose polarity is inverted every horizontal scanning period (1H), and supplies the liquid crystal cells LC201 of all the pixel circuits PXLC of the effective pixel unit 101 through a supply line (not shown). Commonly supplied to two pixel electrodes.
The value of the amplitude ΔVcom of the amplitude of the common voltage Vcom is selected such that the black luminance and the white luminance can be optimized together with the difference ΔVcs between the first level of the storage signal CS and the CSH and the second level CSL.
For example, as will be described later, the effective pixel potential ΔVpix applied to the liquid crystal during white display. The values of ΔVcs and ΔVcom are determined so that W becomes a value of 0.5V or less.

  In FIG. 6, a configuration in which the common voltage generation circuit 104 is provided in the liquid crystal panel is shown as an example. However, it is also possible to arrange the common voltage generation circuit 104 outside the panel and supply the common voltage Vcom from the outside of the panel. .

FIG. 9 is a circuit diagram illustrating a configuration example of the common voltage generation circuit according to the present embodiment.
The example of FIG. 9 shows a case where a common voltage Vcom having a small amplitude is generated by an external part of the panel.

  The common voltage generation circuit of FIG. 9 includes flicker adjusting resistance elements R1 and R2, a smoothing capacitor C1, a capacitor C4 for amplifying by a small amplitude ΔVcom, a wiring resistance Rcom of the Vcom supply line 108, and a parasitic capacitance of the Vcom supply line 108. Ccom is included.

Resistance elements R1 and R2 are connected in series between the supply line of the power supply voltage VCC and the ground line GND, and a voltage divided by the resistance elements R1 and R2 is generated at the connection node ND1 of the resistance elements. The resistance element R2 is a variable resistance, and the generated voltage can be adjusted.
A connection node ND1 is connected to the panel terminal T. The first electrode of the capacitor C1 is connected to the connection line between the connection node ND1 and the terminal T, and the second electrode is grounded.
The first electrode of the capacitor C2 is connected to the connection line between the connection node ND1 and the terminal T, and the second electrode is connected to the supply line of the signal FRP.

  In the common voltage generation circuit of FIG. 9, the small amplitude ΔVcom is determined according to the following equation.

(Equation 2)
ΔVcom = {C2 / (C1 + C2 + Ccom)} × FRP (2)

Small amplitudes can be used using capacitive coupling (digital coupling) or digitally generated.
The value of the small amplitude ΔVcom is preferably as small as possible, for example, about 10 mV to 1.0 V. The reason is that otherwise, effects such as improvement of response speed by overdrive and reduction of acoustic noise are reduced.

As described above, in the present embodiment, when the liquid crystal display device 100 performs capacitive coupling drive using capacitive coupling, the value of the amplitude ΔVcom of the amplitude of the common voltage Vcom and the first level of the storage signal CS. And the value of the difference ΔVcs between the CSH and the second level CSL are selected so as to optimize both the black luminance and the white luminance.
For example, the effective pixel potential ΔVpix applied to the liquid crystal during white display The values of ΔVcs and ΔVcom are determined so that W becomes a value lower than 0.5V.
Hereinafter, the capacitive coupling drive of this embodiment will be described in more detail.

10A to 10E are timing charts showing driving waveforms of main liquid crystal cells of the present embodiment.
FIG. 10A shows the gate pulse GP. FIG. 10B shows the common voltage Vcom, and FIG. 10C shows the storage signal CS. 10D shows the video signal Vsig, and FIG. 10E shows the signal Pix applied to the liquid crystal cell. N is shown respectively.

In the capacitive coupling drive according to the present embodiment, the common voltage Vcom is not a constant DC voltage, but is generated as an alternating signal having a small amplitude whose polarity is inverted every horizontal scanning period (1H), and the liquid crystal cell of each pixel circuit PXLC. Applied to the second pixel electrode of the LC 201.
The storage signal CS N is the first level (CSH, for example, 3V to 4V) or the second level (CSL, for example, 0V) for each storage line 106-1 to 106-m independently wired corresponding to each gate line. Choose to give one.
The effective pixel potential ΔVpix applied to the liquid crystal when driven in this way is given by the following equation.

As shown in FIG. 11, in Expression (3), Vsig is a video signal voltage, Ccs is a holding capacitor, Clc is a liquid crystal capacitor, Cg is a capacitor between the node ND201 and the gate line, and Csp is between the node ND201 and the signal line. ΔVcs represents the potential of the signal CS, and Vcom represents a common voltage.
In Expression (3), the second term {(Ccs / Ccs + Clc) * ΔVcs} of the approximate expression is a term that causes the low gradation (white luminance side) to become black (sink) due to the nonlinearity of the liquid crystal dielectric constant. The third term {(Ccl / Ccs + Clc) * ΔVcom / 2} in the approximate expression is a term that whitens (floats) the low gradation side due to the nonlinearity of the liquid crystal dielectric constant.
In other words, the second term of the approximate expression operates so as to compensate the portion where the low gradation (white luminance side) tends to become black (sinks) by the function of making the low gradation side white (floating) by the third term.
The optimum contrast can be obtained by selecting values that can optimize both the black luminance and the white luminance.

12A and 12B show the effective pixel potential ΔVpix applied to the liquid crystal during white display when the liquid crystal material (normally white liquid crystal) used in the liquid crystal display device is used. It is a figure for demonstrating the selection criteria of W. FIG. 12A is a diagram illustrating the characteristic of the relative dielectric constant ε with respect to the applied voltage, and FIG. 12B is a diagram illustrating an enlarged region where the characteristic of FIG.

As shown in the figure, in the liquid crystal characteristics used in the liquid crystal display device, when a voltage of about 0.5 V or more is applied, white luminance is reduced.
Therefore, in order to optimize the white luminance, the effective pixel potential ΔVpix applied to the liquid crystal at the time of white display. W needs to be 0.5V or less. Therefore, the effective pixel potential ΔVpix The values of ΔVcs and ΔVcom are determined so that W is 0.5V or less.

  As a result of actual evaluation, an optimum contrast was obtained when ΔVcs = 3.8V and ΔVcom = 0.5V.

FIG. 13 is a diagram illustrating a relationship between the video signal voltage and the effective pixel potential in the driving method, the related capacitive coupling driving method, and the normal 1HVcom driving method according to the embodiment of the present invention.
In FIG. 13, the horizontal axis indicates the video signal voltage Vsig, and the vertical axis indicates the effective pixel potential ΔVpix. In FIG. 13, the line indicated by A indicates the characteristics of the driving method according to the embodiment of the present invention, the characteristic indicated by B indicates the characteristic of the capacitive coupling driving method, and the line indicated by C indicates the normal 1 HVcom driving method. The characteristics are shown.

  As can be seen from FIG. 13, according to the driving method according to the present embodiment, a sufficient characteristic improvement is obtained as compared with the related capacitive coupling driving method.

FIG. 14 is a diagram showing the relationship between the video signal voltage and the luminance in the driving method according to the embodiment of the present invention and the related capacitively coupled driving method.
In FIG. 14, the horizontal axis indicates the video signal voltage Vsig, and the vertical axis indicates the luminance. In FIG. 14, the line indicated by A indicates the characteristic of the driving method according to the embodiment of the present invention, and the characteristic indicated by the line B indicates the characteristic of the capacitive coupling driving method.

  As can be seen from FIG. 14, in the related capacitive coupling driving method, when the black luminance (2) was optimized, the white luminance (1) was sunk. On the other hand, according to the driving method according to the present embodiment, both black luminance (1) and white luminance (1) can be optimized by setting Vcom to a small amplitude.

In the following formula (4), the effective pixel potential ΔVpix at the time of black display and the case of black display when specific numerical values are set in the above formula (3) of the driving method according to the present embodiment. Effective pixel potential ΔVpix when displaying B and white The value of W is shown.
Further, the effective pixel potential ΔVpix at the time of black display and black display when specific numerical values are set in the above formula (1) of the capacitive coupling driving method related to the formula (5). B and effective pixel potential ΔVpix The value of W is shown.

As shown in the equations (4) and (5), when displaying black, the effective pixel potential ΔVpix is used for both the driving method according to the present embodiment and the driving method related to this embodiment. B is 3.3 V, and the black luminance is optimized.
In the case of white display, the effective pixel potential ΔVpix of the related driving method as shown in Expression (5). W becomes 0.8V of 0.5V or more, and the white luminance is reduced as described in relation to FIG.
On the other hand, the effective pixel potential ΔVpix of the driving method according to the present embodiment. W becomes 0.4V, which is 0.5V or less, and the white luminance is optimized as described with reference to FIG.

  Next, the operation according to the above configuration will be described.

The shift register of the vertical drive circuit 102 is supplied with a vertical start pulse VST for instructing the start of vertical scanning generated by a clock generator (not shown) and vertical clocks VCK and VCKX having opposite phases as a reference for vertical scanning.
In the shift register, the level shift operation of the vertical clock is performed, and each is delayed by a different delay time. For example, in the shift register, the vertical start pulse VST is shifted in synchronization with the vertical clock VCK and supplied to the corresponding gate buffer.
Further, the vertical start pulse VST is propagated from the upper side or the lower side of the effective pixel portion 101 and is sequentially shifted into each shift register.
Therefore, basically, the gate lines 105-1 to 105-m are sequentially driven through the gate buffers by the vertical clock supplied from the shift register VSR.

As described above, the gate lines 105-1 to 105-m are sequentially driven from the first row by the vertical drive circuit 102, for example, and the storage lines 106-1 to 106-m are driven accordingly. To go. At this time, after driving one gate line with the gate pulse, the levels of the storage signals CS1 to CSm applied to the storage lines 106-1 to 106-m at the rising timing of the gate pulse of the next gate line are The first level CSH and the second level CSL are alternately selected and applied.
For example, when the first level CSH is selected for the storage line 106-1 in the first row and the storage signal CS1 is applied, the second level CSL is selected for the storage line 106-2 in the second row. The storage signal CS2 is applied, the first level CSH is selected and applied to the storage line 106-3 in the third row, the storage signal CS3 is applied, and the second level CSL is applied to the storage line 106-4 in the fourth row. The storage signal CS4 is selected and the first level CSH and the second level CSL are alternately selected in the same manner, and the storage signals CS5 to CSm are applied to the storage lines 106-5 to 106-m.

  Further, an alternating common voltage Vcom having a small amplitude ΔVcom is commonly applied to the second pixel electrodes of the liquid crystal cells LC201 of all the pixel circuits PXLC of the effective pixel unit 101.

The horizontal drive circuit 103 generates a sampling pulse in response to a horizontal start pulse HST for instructing the start of horizontal scanning generated by a clock generator (not shown) and horizontal clocks HCK and HCKX which are opposite in phase to be a reference for horizontal scanning. Then, the input video signal is sequentially sampled in response to the generated sampling pulse, and is supplied to each signal line 107-1 to 107-n as a data signal SDT to be written to each pixel circuit PXLC.
For example, first, the R corresponding selector switch is driven and controlled to be conductive, R data is output to each signal line, and R data is written. When the writing of R data is completed, only the selector switch corresponding to G is driven and controlled so that the G data is output and written to each signal line. When the writing of the G data is completed, only the selector switch corresponding to B is driven and controlled so that the B data is output to each signal line and written.

In the present embodiment, after writing from this signal line (after the fall of the gate pulse GP), coupling is performed from the storage lines 106-1 to 106-m via the storage capacitor CS201, thereby causing the pixel potential (of the node ND201). The voltage applied to the liquid crystal is modulated by changing the potential.
At this time, the common voltage Vcom is supplied as an alternating signal with a small amplitude ΔVcom (10 mV to 1.0 V) instead of a constant value.
Thereby, not only the black luminance but also the white luminance is optimized.

  As described above, according to the present embodiment, the plurality of pixel circuits PXLC for writing the pixel data for video through the TFT 201 are arranged so as to correspond to the effective pixel portion 101 arranged in a matrix and the row arrangement of the pixel circuits. Gate lines 105-1 to 105-m, a plurality of capacitor wirings 106-1 to 106-m arranged to correspond to the row arrangement of the pixel circuits, and arranged to correspond to the column arrangement of the pixel circuits. Vertical drive circuit 102 that selectively drives the signal lines 107-1 to 107-m, gate lines, and capacitor lines, and a generation circuit 104 that generates a common voltage signal with a small amplitude whose level is switched at a predetermined cycle. Each pixel circuit includes a liquid crystal cell LC201 having a first pixel electrode and a second pixel electrode, and a storage capacitor CS having a first electrode and a second electrode. 01, the first pixel electrode of the liquid crystal cell, the first electrode of the storage capacitor, and one terminal of the TFT are connected, and the second electrode of the storage capacitor is connected to the capacitor wiring arranged in the corresponding row, and the liquid crystal Since a common voltage signal is applied to the second pixel electrode of the cell, both black luminance and white luminance can be optimized. As a result, there is an advantage that the contrast can be optimized.

  In the above embodiment, an analog video signal is input to the liquid crystal display device, and after latching the analog video signal, it is applied to a liquid crystal display device equipped with an analog interface driving circuit that writes the analog video signal to each pixel in a dot sequence. As described above, the present invention can be similarly applied to a liquid crystal display device equipped with a drive circuit that inputs a digital video signal and writes the video signal to pixels in a line-sequential manner using a selector method.

In the above embodiment, the case where the present invention is applied to an active matrix liquid crystal display device using a liquid crystal cell as a display element (electro-optical element) of each pixel has been described as an example. The present invention is not limited, and the present invention can be applied to all active matrix display devices such as an active matrix EL display device using an electroluminescence (EL) element as a display element of each pixel.
The display device according to the embodiment described above is used as a display panel of a direct-view type video display device (liquid crystal monitor, liquid crystal viewfinder) and a projection type liquid crystal display device (liquid crystal projector), that is, an LCD (liquid crystal display) panel. Is possible.

It is a block diagram which shows the structural example of a general liquid crystal display device. 2 is a timing chart in the so-called 1HVcom inversion driving method of the general liquid crystal display device shown in FIG. It is a figure which shows the relationship between the applied voltage of a normally white liquid crystal, and a dielectric constant. It is a figure which shows the relationship between the video signal voltage and effective pixel electric potential of the liquid crystal display device which employ | adopted the capacitive coupling drive system relevant to 1HVcom inversion drive system. It is a figure which shows that white brightness will become black (it will sink) if the black luminance of the liquid crystal display device which employ | adopted the related capacitive coupling drive system is optimized. It is a figure which shows the structural example of the active matrix type display apparatus which concerns on one Embodiment of this invention. FIG. 2 is a circuit diagram illustrating a specific configuration example of a pixel portion of the circuit of FIG. 1. 4 is a timing chart showing an example of driving a gate line and a storage line of the vertical drive circuit according to the embodiment. It is a circuit diagram which shows the structural example of the common voltage generation circuit which concerns on this embodiment. It is a timing chart which shows the drive waveform of the main liquid crystal cells of this embodiment. FIG. 4 is a diagram illustrating each capacity of a liquid crystal cell in Formula 3. Effective pixel potential ΔVpix applied to the liquid crystal during white display when the liquid crystal material (normally white liquid crystal) used in the liquid crystal display device is used. It is a figure for demonstrating the selection criteria of W. It is a figure which shows the relationship between the video signal voltage and effective pixel electric potential of the drive system which concerns on embodiment of this invention, the related capacitive coupling drive system, and the normal 1HVcom drive system. It is a figure which shows the relationship between the video signal voltage and the brightness | luminance of the drive system which concerns on embodiment of this invention, and a related capacitive coupling drive system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Liquid crystal display device, 101 ... Effective pixel part, 102 ... Vertical drive circuit (VDRV), 103 ... Horizontal drive circuit (HDRV), 104 ... Common voltage generation circuit, 105-1 ˜105-m... Gate line, 106-1 to 106-m... Capacitance wiring (storage line), 107-1 to 107-n... Signal line, PXLC. (Switching element), LC201... Liquid crystal cell, CS201.

Claims (6)

A pixel unit in which a plurality of pixel circuits for writing image pixel data through a switching element are arranged in a matrix; and
A plurality of scan lines arranged to correspond to the row arrangement of the pixel circuits, and for controlling conduction of the switching elements;
A plurality of capacitor wirings arranged to correspond to the row arrangement of the pixel circuits;
A plurality of signal lines arranged to correspond to the column arrangement of the pixel circuits and propagating the pixel data;
A drive circuit for selectively driving the plurality of scan lines and the plurality of capacitance lines;
A generation circuit that generates a small-amplitude common voltage signal whose level is switched at a predetermined period;
Each pixel circuit arranged in the pixel portion is
A display element having a first pixel electrode and a second pixel electrode;
A storage capacitor having a first electrode and a second electrode,
The first pixel electrode of the display element, the first electrode of the storage capacitor, and one terminal of the switching element are connected,
A second electrode of the storage capacitor is connected to the capacitor wiring arranged in a corresponding row;
The display device, wherein the common voltage signal is applied to a second pixel electrode of the display element. 2. The display device according to claim 1, wherein the drive circuit drives a scanning line in a selected row to write pixel data in a desired pixel circuit, and then drives the capacitor line in the same row. 3. The display device according to claim 2, wherein the drive circuit selects one of a first level and a second level lower than the first level as a signal for driving the capacitor line, and applies the selected signal to the corresponding capacitor line. The amplitude value of the common voltage signal and the value of the potential difference between the first level and the second level of the signal for driving the capacitive wiring are selected so that the effective pixel potential is not more than a predetermined threshold value. 3. The display device according to 3. The display device according to claim 4, wherein the display element of the pixel circuit is a liquid crystal cell. A pixel unit in which a plurality of pixel circuits for writing image pixel data propagated through a signal line through a switching element are arranged in a matrix;
A plurality of scan lines arranged to correspond to the row arrangement of the pixel circuits, and for controlling conduction of the switching elements;
A plurality of capacitor wirings arranged to correspond to the row arrangement of the pixel circuits;
Each pixel circuit arranged in the pixel portion is
A display element having a first pixel electrode and a second pixel electrode;
A storage capacitor having a first electrode and a second electrode,
The first pixel electrode of the display element, the first electrode of the storage capacitor, and one terminal of the switching element are connected,
A driving method of a display device in which the second electrode of the storage capacitor is connected to the capacitor wiring arranged in a corresponding row,
The above capacity wiring is driven individually,
A small amplitude common voltage signal whose level is switched at a predetermined cycle is applied to the second pixel electrode of the display element,
A driving method of a display device, in which a scanning line of a selected row is driven to write pixel data in a desired pixel circuit, and then the capacitor wiring of the same row is driven.

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