JP2007049719A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize high speed external output operation synchronized with an external clock signal with respect to suppression of clock delay. <P>SOLUTION: The semiconductor integrated circuit has an external output buffer (53), a latch circuit (90) which latches data to be output from the external output buffer synchronously with an external clock signal (100), and a processing circuit (20) of data to be latched into the latch circuit. The latch circuit and the processing circuit input in common the output of a clock buffer (101) which receives the external clock signal. By performing the output latch operation of the latch circuit receiving a clock signal from the outside, it becomes possible to reduce the influence of internal clock delay in the output operation synchronized with the external clock signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit technology for coping with speeding up of an external output operation synchronized with a clock signal. For example, a semiconductor integrated circuit using a MOS transistor having a higher breakdown voltage than an internal circuit in an external interface part, Furthermore, the present invention relates to a technique effective when applied to a burn-in method in such a semiconductor integrated circuit.

  In Japanese Patent Laid-Open No. 9-8632, from the viewpoint of circuit element miniaturization and low power consumption, the external power supply voltage is stepped down inside the LSI, the stepped down voltage is used as the operating power supply for the internal circuit, and an external interface circuit is provided. A technique for operating with an external power supply voltage is described. Japanese Patent Laid-Open No. 2000-353947 discloses a semiconductor output circuit having a function of converting an internal signal level to a signal level equal to or higher than a semiconductor device breakdown voltage, and a function of outputting at an internal signal level before conversion. For the output buffer provided with a protection MOS transistor on the power supply side to increase the gate-source breakdown voltage of the output buffer transistor, the signal rising change rate due to the on-resistance of the protection MOS transistor does not perform level conversion In order to prevent a delay in the case where the power supply voltage of the output buffer is the same as that of the internal circuit, a technique is described in which the on-resistance of the protection MOS transistor can be varied by gate voltage control.

Japanese Patent Laid-Open No. 9-8632 JP 2000-353947 A

  However, in the above prior art, attention is not paid to the output operation delay due to the level conversion function and further the external output operation delay due to the propagation delay of the clock signal in order to cope with the high speed of the external output operation synchronized with the clock signal. . The present inventor has studied the following points in terms of dealing with speeding up of the external output operation synchronized with the clock signal.

  First, the output operation delay due to the level conversion function was examined. For example, a semiconductor integrated circuit after the 0.35 μm process uses a low breakdown voltage MOS transistor inside, and uses a high breakdown voltage MOS transistor for an interface portion with the outside. In order to operate the internal circuit at a low voltage such as 3.3V and enable the interface unit to operate at a high voltage such as 5.0V, a low voltage amplitude is set between the internal circuit and the input / output buffer. A level conversion circuit for converting to voltage amplitude is inserted. If a low voltage power supply is supplied to both the internal circuit and the interface unit, the entire semiconductor integrated circuit can be operated at a low voltage. Here, it was examined to mount a host interface module for LPC (Low Pin Count) bus interface (hereinafter also simply referred to as an LPC module), which is a parallel interface in a PC (personal computer), in such a semiconductor integrated circuit. In high-speed host interface specifications such as LPC, bus wiring is suppressed, and data communication is performed in synchronization with a 33 MHz PCI (Peripheral Component Interconnect) clock (external clock signal). Demands a stricter design. As for the external power supply, a low signal amplitude is realized by using a low voltage power supply such as 3.3V. However, the present inventors have found that the delay of the data output timing with respect to the external clock signal increases due to the output operation delay by the level conversion circuit and the propagation delay of the internal clock.

  Therefore, the present inventor, as for the output operation delay due to the level conversion circuit, when the operation of the LPC module is guaranteed, both the internal circuit and the interface unit are only operated at a low voltage. We considered measures to bypass the slice. However, when the interface section is operated at a high voltage such as 7.0 V in order to apply a high voltage to the high voltage MOS transistor during burn-in, and the internal circuit is operated at a low voltage such as 4.6 V, the bypassed portion However, since the level conversion function is not realized, an intermediate potential is applied to a circuit such as an inverter or a clocked inverter that receives a low-amplitude signal in such an interface unit, and a through current flows. This through current causes a threshold voltage shift of the MOS transistor due to hot carriers and destruction of the MOS transistor.

  If a low voltage of about 4.6 V is applied to both the internal circuit and the interface section during burn-in, the above problem will not occur, but conversely, sufficient voltage stress cannot be applied to the high voltage MOS transistor. An initial failure is not found, and there is a high possibility that the failure will become apparent in the market after shipment, and the reliability is inevitably lowered. The external terminal for the LPC module conforms to the PCI bus and is used in an environment with no termination using reflected waves. In the worst case, twice the power supply voltage is applied to the terminal. This is because the MOS transistor in the interface section is still required to have a high breakdown voltage.

  Second, the external output operation delay due to the propagation delay of the clock signal was examined. For example, in the LPC module, the output data must be determined within a predetermined allowable delay time from the rise change of the 33 MHz PCI clock (external clock signal). It has been found by the present inventor that if the allowable delay time is shortened, using a clock signal generated by an internal CPG (clock pulse generator) as a latch clock signal for data output may not be in time.

  An object of the present invention is to provide a semiconductor integrated circuit capable of realizing a high-speed external output operation synchronized with a clock signal from the viewpoint of eliminating an output operation delay by a level conversion circuit and maintaining a high breakdown voltage of an output buffer. It is in.

  An object of the present invention is to provide a semiconductor integrated circuit capable of realizing a high-speed external output operation synchronized with an external clock signal from the viewpoint of suppressing clock delay.

  Another object of the present invention is to improve the reliability due to burn-in in a semiconductor integrated circuit in which the clock-synchronized external output operation is speeded up from the viewpoint of eliminating output operation delay by the level conversion circuit and maintaining a high breakdown voltage of the output buffer. It is to provide a burn-in method that can be used.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] The semiconductor integrated circuit of the present invention from the viewpoint of eliminating the delay in output operation by the level conversion circuit and maintaining the high breakdown voltage of the output buffer includes the first circuit (4, 7) and a higher breakdown voltage than the first circuit. It is possible to have the second circuit (3) and to make the operating voltage of both circuits equal or different. The second circuit has a plurality of level conversion circuits (34, 35, 54, 55) capable of level-converting the output of the first circuit according to the operating voltage, and a plurality of external outputs for receiving the output of the level conversion circuit. A buffer (33, 53), a bypass path (70, 71) for bypassing an input of a predetermined level conversion circuit (54, 55) to an input of a predetermined external output buffer (53), and the predetermined external output buffer And a selection circuit (74) for selecting connection of the predetermined level conversion circuit or bypass path to the input.

  In a usage mode in which the first circuit and the second circuit are operated at a low voltage, a bypass path in the predetermined level conversion circuit is connected to an input of a predetermined external output buffer. An external interface using an external output buffer connected to the bypass path is not affected by an operation delay due to level conversion, and a high-speed interface with the outside can be realized.

  In a usage mode in which a high voltage is used for an external interface according to a requirement on a system to which a semiconductor integrated circuit is applied, the first circuit is operated at a low voltage, the second circuit is operated at a high voltage, and even in the predetermined external output buffer, a bypass path is used. The low voltage signal amplitude in the first circuit is converted to the high voltage signal amplitude in the second circuit and can be supplied to the external output buffer by interposing the level conversion circuit without selecting.

  In any of the above usage forms, in burn-in, the first circuit is operated with a low voltage for burn-in, the second circuit is operated with a high voltage for burn-in, and the bypass path is not selected even in the predetermined external output buffer. By interposing a level conversion circuit, the signal amplitude of the low voltage for burn-in in the first circuit is converted into the signal amplitude of the high voltage for burn-in in the second circuit and can be supplied to the external output buffer. Since a through current does not flow through the second circuit due to an intermediate level signal having a relatively small amplitude of the first circuit, characteristic deterioration or destruction of the second circuit due to the through current does not occur. Therefore, the first circuit and the second circuit can be burned in using an operating power supply corresponding to the withstand voltage, and thus reliability by burn-in can be guaranteed.

  [2] The level conversion circuit may be composed of a plurality of level conversion circuits having different level conversion ranges. In order to be able to cope with the case where the operating voltage difference is large when the first circuit and the second circuit have different operating voltages, a plurality of optimum level conversion circuits are prepared according to the level conversion range. In addition, the level conversion circuit to be used may be selected according to the operating voltage difference when the semiconductor integrated circuit is actually operated.

  [3] As a specific form of the present invention, when the semiconductor integrated circuit has an internal power supply step-down circuit for stepping down the input voltage from the first external terminal (VCC), the second circuit is supplied to the first external terminal. The input voltage is the operating voltage. The first circuit uses the step-down output voltage of the internal power supply step-down circuit or the input voltage from the second external terminal (VCL) as an operation power supply.

  When different operating voltages are used for the first circuit and the second circuit, an external power supply voltage may be connected to the first terminal, and a stabilization capacitor element may be connected to the second terminal. In order to make the operating voltages of the first circuit and the second circuit equal, the same external power supply voltage may be connected to the first terminal and the second terminal. At this time, the operation of the internal power supply step-down circuit may be stopped, but since the power supply capability is smaller than that of the external power supply circuit, there is no problem even if it is operated.

  The first circuit may include register means (94) for holding selection control information (87) of the selection circuit.

  The first circuit includes, for example, an output latch circuit (90) for holding output data of the predetermined external output buffer in synchronization with a clock signal (104, 105), and data for processing data latched in the output latch circuit And a processing circuit (20).

  At this time, the output latch circuit may be a part of a predetermined IO port. Alternatively, the output latch circuit may be a dedicated circuit adjacent to the predetermined external output buffer. Adjacent to the external output buffer can reduce the propagation delay of the latch data to the external output buffer.

  The clock signal may be supplied from the outside to the output latch circuit and the data processing circuit in parallel. When the output latch circuit receives an external clock signal and performs an output latch operation, the influence of the clock delay can be reduced in the output operation synchronized with the external clock signal.

  As a more specific form, the data processing circuit is a host interface control circuit. For example, the host interface control circuit and the output latch circuit operate in synchronization with the external clock signal of 33 MHz.

  [4] The burn-in method according to the present invention includes the first circuit and the second circuit having a higher breakdown voltage than the first circuit, and the operating voltages of both circuits can be made equal or different. The second circuit selects a level conversion circuit capable of level-converting the output of the first circuit according to its operating voltage, an external output buffer for receiving the output of the level conversion circuit, and an input of a predetermined level conversion circuit When burn-in is performed on a semiconductor integrated circuit having a bypass circuit that is bypassed to the input of the external output buffer, the operating voltages of the first circuit and the second circuit are made different, and bypass deselection is set for the bypass circuit.

  [5] The semiconductor integrated circuit according to the present invention from the viewpoint of suppressing clock delay latches the external output buffer (53) and data to be output from the external output buffer in synchronization with the external clock signal (100). A latch circuit (90) and a data processing circuit (20) to be latched in the latch circuit are included. The latch circuit and the processing circuit commonly receive the output of a clock buffer (101) that receives the external clock signal.

  When the latch circuit receives an external clock signal and performs an output latch operation, it is possible to reduce the influence of the internal clock delay in the output operation synchronized with the external clock signal.

  If the latch circuit is arranged in the vicinity of the external output buffer, the delay of propagation of latch data to the external output buffer can be reduced.

  In addition to the latch circuit, an IO port (93) that can latch data to be output from the external output buffer in synchronization with an internal clock signal is provided, and the operation of the IO port and the operation of the latch circuit are selectively performed. You may comprise so that switching is possible.

  [6] A semiconductor integrated circuit according to still another aspect of the present invention includes a central processing unit, a clock generation circuit that receives a reference clock signal and generates an operation clock to be supplied to the central processing unit, and the central processing unit. A plurality of output buffers coupled to the internal bus, a plurality of latch circuits for latching data to be output from the plurality of output buffers in synchronization with an external clock signal, and the plurality of latch circuits; A host interface module having a processing circuit for processing data to be latched; and an external terminal to which the external clock signal is supplied from the outside, wherein the plurality of latch circuits are respectively close to the plurality of output buffers. The external clock signal arranged and supplied to the external terminal is input in common to the plurality of latch circuits. .

  As a specific aspect, in the above, the host interface module may be an LPC (Low Pin Count) bus interface host interface module.

  As a more specific aspect, there is an IO port that can latch data to be output from the plurality of output buffers in synchronization with an internal clock signal output from the clock generation circuit, and selectively operate the IO port. The operation of the latch circuit may be switchable.

  And an AD conversion circuit coupled to the internal bus for converting an analog signal supplied from the outside into a digital signal, wherein the host interface module converts the digital signal converted by the AD conversion circuit into the semiconductor It may be configured to supply a host processor to be coupled to the integrated circuit.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  In other words, in the usage mode in which the first circuit and the second circuit having a higher withstand voltage than the first circuit are operated at a low voltage, the bypass path in the predetermined level conversion circuit is connected to the input of the predetermined external output buffer. In the external interface using the external output buffer, it is possible to realize a high-speed interface with the outside without being affected by the operation delay due to the level conversion.

  In a usage mode in which a high voltage is used for the external interface, the first circuit is operated at a low voltage, the second circuit is operated at a high voltage, and a level conversion circuit is interposed in the predetermined external output buffer without selecting a bypass path, The low-voltage signal amplitude in the first circuit is converted into the high-voltage signal amplitude in the second circuit and can be supplied to the external output buffer.

  In any of the above-described usage forms in the semiconductor integrated circuit, in the burn-in, the first circuit is operated with a low voltage for burn-in, the second circuit is operated with a high voltage for burn-in, and a bypass path is also formed in the predetermined external output buffer. The signal amplitude of the low voltage for burn-in in the first circuit is converted to the signal amplitude of the high voltage for burn-in in the second circuit by interposing a level conversion circuit without selection, and can be supplied to the external output buffer. Since a through current does not flow through the second circuit due to an intermediate level signal having a relatively small amplitude of the first circuit, characteristic deterioration or destruction of the second circuit due to the through current does not occur. Therefore, the first circuit and the second circuit can be burned in using an operating power supply corresponding to the withstand voltage, and thus reliability by burn-in can be guaranteed.

  From the viewpoint of eliminating output operation delay due to the level conversion circuit and maintaining a high breakdown voltage of the output buffer, it is possible to realize high speed external output operation synchronized with the clock signal.

  From the viewpoint of suppressing the clock delay, it is possible to realize a high-speed external output operation synchronized with the external clock signal.

  From the viewpoint of eliminating output operation delay by the level conversion circuit and maintaining high breakdown voltage of the output buffer, it is possible to improve the reliability due to burn-in in the semiconductor integrated circuit in which the clock-synchronized external output operation is speeded up.

  FIG. 1 shows a microcomputer as an example of a semiconductor integrated circuit according to the present invention. The microcomputer 1 shown in the figure is formed on a single semiconductor substrate (chip) such as single crystal silicon by, for example, a known CMOS integrated circuit manufacturing technique. Although not particularly limited, a large number of external terminals 2 such as bonding pads are arranged around the chip, and a buffer unit 3, an input / output port 4, an analog port 5, and an internal power supply voltage down circuit 6 are arranged inside the chip. In addition, an internal digital unit 7 and an analog unit 8 are arranged.

  The input / output port 4 and the internal digital unit 7 form a first circuit composed of a MOS transistor having a relatively low withstand voltage. On the other hand, the buffer unit 3 constitutes a second circuit with a high breakdown voltage, which is composed of a MOS transistor having a relatively high breakdown voltage. The analog port 5, the internal power supply step-down circuit 6 and the analog unit 8 are also configured by MOS transistors having a relatively high breakdown voltage.

  The internal digital unit 7 includes a clock oscillator 10 that generates an internal operation clock signal based on a vibrator or a reference system clock signal, a central processing unit (CPU) 11, a ROM 12 that stores an operation program of the CPU 11, a work area of the CPU 11, and the like. RAM 13, used in response to an exception processing request and an interrupt processing request, an interrupt controller 14 that controls an interrupt to the CPU 11, a data transfer controller (DTC) 15 that controls data transfer according to an initial setting by the CPU 11, the CPU 11 or data A bus controller 16 that controls the internal bus and the external bus in response to an access operation by the transfer controller 15 is provided. Further, the internal digital unit 6 includes, as an IO controller (input / output control circuit), a serial communication interface (SCI) controller 18, an ISA (Industry Standard Architecture) bus HIF (Host Interface) circuit 19, and an LPC bus HIF circuit (LPC bus). 20) (also referred to as an interface module). In addition, the internal digital unit 6 includes a watchdog timer (WDT) 21, a 16-bit free running timer 22, an 8-bit timer 23, an 8-bit PWM (Pulse Width Modulator) 24, a 14-bit PWM 25, and an I2C (Inter IC) 26. Prepare.

  The analog unit 8 includes an analog / digital conversion circuit (A / D) 27 and a digital / analog conversion circuit (D / A) 28.

  The microcomputer 1 has, as power supply terminals, a power supply terminal VCC, a circuit ground terminal GND, a low voltage operation terminal VCL, an analog power supply terminal AVCC, and an analog ground terminal AVSS. The analog power supply terminal AVCC and the analog ground terminal AVSS are dedicated to the analog port 5 and the analog circuit unit 8.

  The operating power supplied from the power supply terminal VCC is supplied to the buffer unit 3 and the internal power supply step-down circuit 6. The internal power supply step-down circuit 6 steps down the voltage of the operating power supplied from the power supply terminal VCC, and supplies the stepped down voltage as a step-down power supply for the input / output port 4 and the internal digital unit 7. The low-voltage operation terminal VCL is connected to a supply path for a step-down power supply. The microcomputer 1 corresponds to both a high voltage operation that operates by receiving a relatively high voltage at the power supply terminal VCC and a low voltage operation that operates by receiving a relatively low voltage at the power supply terminal VCC.

  FIG. 2 illustrates a power supply terminal connection form when the microcomputer operates at a high voltage. An external power supply of 4.5 to 5.5 V is supplied from the external power supply circuit 30 to the power supply terminal VCC. The internal power supply step-down circuit outputs a step-down voltage that is stepped down to about 3.2V, for example. A stabilization capacitor 31 (for example, 0.1 μF) is connected to the low-voltage operation terminal VCL. Thus, the buffer unit 3 operates with an external power supply of 4.5 to 5.5V, and the input / output port 4 and the internal digital unit 7 operate with a step-down voltage of about 3.2V.

  FIG. 3 illustrates a power supply terminal connection form when the microcomputer operates at a low voltage. An external power supply of 3.0 to 3.6 V is supplied from the external power supply circuit 32 to the power supply terminal VCC and the low-voltage operation terminal VCL. The internal power supply step-down circuit 6 only needs to stop the step-down operation, but its power supply capability is smaller than that of the external power supply circuit 32, so that it can be operated without any problem. As a result, the buffer unit 3, the input / output port 4 and the internal digital unit 7 operate with a relatively low external power source of 3.0 to 3.6V.

  FIG. 4 illustrates an output buffer and a level conversion circuit in the buffer unit 3. The output buffer 33 is composed of a p-channel MOS transistor Q1 and an n-channel MOS transistor Q2 as a CMOS inverter. The gate electrodes of MOS transistors Q1 and Q2 receive the outputs of level conversion circuits 34 and 35 through inverters 36 and 37, respectively. Latch data of the output latch circuit 40 of the input / output port 4 is supplied to the level conversion circuits 34 and 35 via the output control circuit 41. During the high voltage operation, the level conversion circuits 34 and 35 receive a signal having a relatively small amplitude with the step-down voltage as an amplitude, convert the signal into an amplitude of the external power supply voltage, and output it. For example, in the level conversion circuit 34, when the MOS transistors Q3 and Q4 receive a high level of the step-down voltage and the MOS transistors Q5 and Q6 receive a low level, the MOS transistor Q4 is turned on, the MOS transistors Q3 and Q7 are turned off, and the MOS transistor Q6 is turned on. Off, MOS transistors Q5 and Q8 are turned on, and a high level of the external power supply voltage is obtained at the common drain of MOS transistors Q5 and Q6. With this level conversion function, it is possible to suppress malfunction and undesired generation of through current caused by a circuit having an external power supply as an operation power supply in the buffer unit 3 receiving the high level of the step-down voltage as an intermediate level.

  During low-voltage operation, no substantial level conversion is performed between the input and output of the level conversion circuit, but it is necessary to go through a static latch operation in the level conversion circuit in order to determine the output logic value that responds to the input. Yes, this constitutes an output operation delay.

  In FIG. 4, reference numerals 42 and 43 denote inverters. The output control circuit 41 includes inverters 44 to 47, a 2-input NOR gate 48, and a 2-input NAND gate 49. The output control circuit 41 sets the output buffer 33 to a high output impedance when the control signal 50 is at a low level, and enables the output data of the latch data by the output buffer 33 when the control signal 50 is at a high level.

  FIG. 5 illustrates an output buffer and level conversion circuit allocated to the output of the LPC bus HIF circuit 20 in the buffer unit 3. The configuration shown in the figure is based on the output buffer 53, the level conversion circuits 54 and 55, and the output control circuit 61, which have the same configuration as that in FIG. 4, and further includes bypass paths 70 and 71 and a selection circuit 74. It is prepared for.

  The bypass paths 70 and 71 bypass the inputs of the level conversion circuits 54 and 55 to the inputs of the output buffer 53 via the inverters 72 and 73 and the like. The selection circuit 74 is a circuit that selects connection of the level conversion circuits 54 and 55 or the bypass paths 70 and 71 to the output buffer 53. The selection circuit 74 has clocked inverters 75 and 76 that are exclusively output-enabled to select connection of the level conversion circuit 54 or the bypass path 70, and outputs of the clocked inverters 75 and 76 are inverters 80, 76. 56 is connected to the gate electrode of the MOS transistor Q1. The selection circuit 74 has clocked inverters 77 and 78 that are exclusively output-operable in order to select connection of the level conversion circuit 55 or the bypass path 71. The outputs of the clocked inverters 77 and 78 are inverters. It is connected to the gate electrode of the MOS transistor Q2 through 81 and 57.

  The operation of the clocked inverters 75 to 78 is selected by a control signal 87. The control signal 87 is converted into a complementary signal via the inverters 82 to 84 and supplied to the clocked inverters 75 to 78. The bypass paths 70 and 71 are selected by the high level of the control signal 87, and the outputs of the level conversion circuits 54 and 55 are selected by the low level of the control signal 87.

  In FIG. 5, the output control circuit 61 includes inverters 64-67, a 2-input NOR gate 68, and a 2-input NAND gate 69. The output control circuit 61 sets the output buffer 53 to a high output impedance when the control signal 85 is at a low level, and enables the output buffer 53 to output data 88 when the control signal 85 is at a high level. The data 88 is output from an output latch circuit 86 shown as a representative. The output latch circuit 86 latches data in synchronization with the clock signal supplied to the clock terminal CK.

  FIG. 6 illustrates signal waveforms in the buffer unit 3 of FIG. When the output waveforms of the bypass paths 70 and 71 are compared with the outputs of the inverters 62 and 63 in the level conversion circuits 54 and 55, the outputs of the level conversion circuits 54 and 55 are delayed due to the operation delay, but in the bypass paths 70 and 71, There is no delay due to such operation delay.

  When host interface control using the LPC bus HIF circuit 20 is performed (when LPC communication is valid), the output path of the latch circuit 86 (latch circuit) is selected by selecting the bypass paths 70 and 71 with the high-level control signal 87. The latch data is output from the output terminal 2 at a relatively early timing with respect to the clock change that defines the latch operation of the data 88 by 86. This is because the latch data output path at this time is not affected by the operation delay caused by the level conversion circuits 54 and 55.

  When host interface control using the LPC bus HIF circuit 20 is not performed (when LPC communication is disabled), the output operation timing of the latch circuit 86 is selected by selecting the level conversion circuits 54 and 55 with the low level control signal 87. The latch data is output from the output terminal 2 at a delayed timing with respect to (clock change defining the latch operation). This is because at this time, the operation is affected by the operation delay caused by the level conversion circuits 54 and 55.

  FIG. 7 illustrates the correspondence between LPC communication valid / invalid and operating power supply. The operation state is broadly divided into burn-in and normal operation (operation states other than burn-in), and the normal operation is broadly divided into LPC communication valid and invalid states. When LPC communication in normal operation is valid, the low voltage operation state is set, a low voltage such as 3.3V is supplied to the terminals VCC and VCL, and the buffer unit 3, the input / output port 4 and the internal digital unit 7 are set to 3.3V. Operate with a low voltage power supply. In this operation mode, when host interface control using the LPC bus HIF circuit 20 is performed, the control signal 87 is set to a high level (in this case, 3.3 V), whereby the buffer unit 3 for the interface is used. Then, the clocked inverters 76 and 77 of the selection circuit 74 are turned on, the clocked inverters 75 and 78 are turned off, the bypass paths 70 and 71 are selected, and the high-speed LPC bus interface can be realized. Regarding the external interface buffer unit other than the LPC bus interface, the output signal passes through the level conversion circuit even in the low voltage operation state. This is because the external interface other than the LPC bus interface does not require a strict output timing so that the operation delay of the level conversion circuit becomes a problem.

  When LPC communication in normal operation is disabled, a high voltage operation state is set, an external power supply of 5.0 V is supplied to the terminal VCC, a stabilization capacitor is coupled to the terminal VCL, and the buffer unit 3 is operated by an external power supply. 4 and the internal digital section 7 are operated at an internal step-down voltage such as 3.2V. In this operation mode, the control signal 87 is set to a low level (in this case, 0 V). In the buffer unit 3, the clocked inverters 76 and 77 of the selection circuit 74 are turned off and the clocked inverters 75 and 78 are turned on. The output of the level conversion circuits 54 and 55 is selected, and the low amplitude signal of the step-down voltage can be expanded to the amplitude of the external power supply by the level conversion circuits 54 and 55 and output from the output buffer 53 to the external terminal 2. Therefore, it is possible to operate by applying to a data processing system using a relatively high operating voltage such as 5V.

  Regardless of whether LPC communication is enabled or disabled during normal operation, a burn-in high voltage such as 7.0 V is applied to the power supply terminal VCC during burn-in, and control is performed in the same manner as in the normal operation LPC communication disabled state. The signal 87 is set to a low level, and the conversion function by the voltage conversion circuits 54 and 55 is enabled. Therefore, burn-in can be performed at a relatively low voltage of about 4.6 V for the input / output port 4 and the internal digital unit 7 having a relatively low breakdown voltage, and the buffer unit 3 having a high breakdown voltage can be used. Can be burned in with an external power supply voltage of about 7.0 V, which is a relatively high voltage, and the burn-in reliability can be guaranteed even for the high voltage circuit 3. In addition, since the input / output port 2 operated at a low voltage is connected to the buffer unit 3 operated at a high voltage via the level conversion circuits 54 and 55, the intermediate level signal is directly supplied from the input / output port 2 to the inverter of the buffer unit 3. Does not occur at all.

  FIG. 8 shows, as a comparative example with FIG. 5, a case where a microcomputer that does not employ a bypass path for the LPC bus interface is used as LPC communication valid during normal operation. In FIG. 8, the inputs of inverters 64 and 65 are pulled up, the outputs of inverters 62 and 63 are floated, the output of NOR gate 68 is bypassed to the input of inverter 56 by wiring, and the output of NAND gate 69 is connected to inverter 57 by wiring. Bypass to input. Processing such as bypass is selected by a fixed method on the process such as wiring master slice. As a result, in the usage mode in which the low-voltage operated LPC communication is enabled, the operation delay of the level conversion circuits 54 and 55 does not affect the data output operation for the LPC interface. However, at the time of burn-in, if a burn-in voltage of about 7.0 V is applied to the external terminal VCC in the high voltage operation state as in the case of the burn-in in FIG. Although an intermediate level signal having a voltage amplitude of about 4.6 V is input to the gates of the inverters 56 and 57 via the bypass wiring, a through current flows through the inverters 56 and 57, and the threshold voltage changes. There is a risk of destruction. As illustrated in FIG. 5, there is no such concern in the microcomputer employing the bypass paths 70 and 71 and the selection circuit 74 for the LPC bus interface.

  FIG. 9 illustrates a connection relationship between the circuit configuration of FIG. 5 and the LPC bus HIF circuit 20. Corresponding to the circuit configuration of FIG. 5, the input / output port 4 includes, for example, an output control circuit 91 having an LPC output latch circuit 90 and an output control circuit 93 having a general-purpose output latch circuit 92. The output control circuit 91 is connected to the LPC bus HIF circuit 20 and dedicated. The output control circuit 93 can be connected to other peripheral circuits such as the 8-bit timer 23 via the internal data bus and is used for general purposes.

  The LPC bus HIF circuit 20 has a control register 94 including control bits such as an LPC enable bit Elpc. When Elpc = “1 (high level)”, LPC communication is enabled, and when Elpc = “0 (low level)”, LPC communication is disabled. The LPC enable bit Elpc is supplied to the output control circuits 91 and 93 and is supplied to the selection circuit 74 as a control signal 87.

  When the LPC communication indicated by Elpc = “1” (87 = “1”) is valid, the LPC output control circuit 91 is enabled and the general-purpose output control circuit 93 is disabled. At this time, the bypass paths 70 and 71 are selected by the high-level control signal 87, the level conversion function is disabled, and the high-speed output operation by the low voltage operation is enabled. On the other hand, when the LPC communication instructed by Elpc = “0” (87 = “0”) is disabled, the LPC output control circuit 91 is disabled and the general-purpose output control circuit 93 is enabled. At this time, the level conversion function by the level conversion circuits 54 and 55 is enabled by the low level control signal 87, and the level conversion output operation by the high voltage operation is enabled.

  The microcomputer for enabling the LPC communication is supplied with operating power in a low voltage operation mode. When the LPC communication indicated by Elpc = “1” (87 = “1”) is valid, the LPC output control circuit 91 is enabled and the general-purpose output control circuit 93 is disabled. When enabled, the output control circuit 91 causes the output latch circuit 90 to latch the interface data from the LPC bus HIF circuit 20 in synchronization with the clock signal, and enables the output gate circuit 61 to perform the output operation by the control signal 85. By controlling, the data 88 can be output from the output buffer 53. At this time, since the selection circuit 74 selects the bypass paths 70 and 71 by the control signal 87, the output operation by the output buffer 53 is not affected by the operation delay by the level conversion circuits 54 and 55, and is speeded up. When the general-purpose output control circuit 93 is disabled, it controls the output terminals of the control signal 85 and the data 88 to the high output impedance state.

  On the other hand, the microcomputer for disabling LPC communication is supplied with operating power in a high voltage operation mode. When LPC communication instructed by Elpc = “0” (87 = “0”) is disabled, the general-purpose output control circuit 93 is enabled, and the LPC output control circuit 91 is disabled. When enabled, the output control circuit 93 causes the output latch circuit 92 to latch interface data supplied from a predetermined peripheral circuit via the internal data bus in synchronization with the clock signal. The circuit 61 is controlled so as to be able to perform the output operation, so that the data 88 can be output from the output buffer 53. At this time, since the selection circuit 74 selects the level conversion circuits 54 and 55 by the control signal 87, the output operation by the output buffer 53 is affected by the operation delay by the level conversion circuits 54 and 55. Output operation is performed through level conversion to voltage amplitude. When the output control circuit 91 for LPC is disabled, it controls the output terminals of the control signal 85 and the data 88 to the high output impedance state.

  FIG. 10 illustrates a transmission system of a latch clock signal for the output latch circuit 90 for the LPC bus interface. In FIG. 10, a PCI clock signal 100 for an LPC bus interface is input from the clock input terminal 2 (CK), and the clock input buffer 101 of the buffer unit 3, the clock input port 102 of the input / output port 4, and the clock driver 103 are input. Thus, the internal clock signal 104 is supplied to the LPC bus HIF circuit 20. The LPC bus HIF circuit 20 performs bus interface control in synchronization with the internal clock signal 104 and outputs output data to the output latch circuit 90. The output latch circuit 90 receives the internal clock signal 104 at the clock terminal CK and performs a latch operation. Data 88 latched in the output latch circuit 90 in synchronization with the clock signal 104 is output to the data output terminal 2 (D) via the buffer unit 3. In this clock signal transmission system, the delay element when data is output from the data output terminal 2 (D) in synchronization with the change of the PCI clock signal 100 is the clock input of the output latch circuit 90 from the clock input terminal 2 (CK). The clock delay to the terminal CK and the propagation delay of data from the output latch circuit 90 to the data output terminal 2 (D). The data propagation delay is improved by the bypass paths 70 and 71 selectable by the selection circuit 74. For the clock delay, the number of gate stages in the clock transmission path may be reduced.

  FIG. 11 shows an example in which the clock delay and the data propagation delay are further improved. In order to further reduce the clock delay for the data output operation for the LPC bus interface, an output latch circuit 90 is arranged in the vicinity of the clock input buffer 101 of the PCI clock signal 100, and the clock signal output from the clock input buffer 101 is displayed. 105 is supplied to the output latch circuit 90. In order to further reduce the data propagation delay, the output latch circuit 90 is disposed in the immediate vicinity of the output buffer 53, that is, in the immediate vicinity of the data output terminal 2 (D). An internal clock signal 107 generated by the built-in clock oscillator 10 is supplied to the output data latch circuit 92 used for general-purpose input / output. In FIG. 11, the output data latch circuit 90 is enabled to perform a latch output operation according to the high level of the control signal 87, and is set to a high output impedance state according to the low level of the control signal 87. The output data latch circuit 92 is enabled to perform a latch output operation according to the low level of the control signal 87, and is set to a high output impedance state according to the high level of the control signal 87.

  FIG. 12 illustrates a layout near the buffer unit. The clock input buffer 101 and the output data latch circuit 90 for the LPC bus interface are arranged in the immediate vicinity of the output buffer 53 and the data output terminal 2 (D). On the other hand, the output data latch circuit 92 for the general-purpose interface is disposed at the input / output port 2 and is relatively distant from the output buffer 53 and the data output terminal 2 (D).

  FIG. 13 shows an example of a semiconductor integrated circuit in which the voltage of the external power supply operated at a high voltage can be selected in two ways. The low voltage operation mode in normal operation is VCC = VCL = 1.8V, the first high voltage operation mode in normal operation is VCC = 3.3V, VCL = 1.8V, and the second high voltage operation mode in normal operation is VCC = 5.0V, VCL = 1.8V. The high voltage operation mode at the time of burn-in is assumed to be VCC = 7.0V and VCL = 2.8V. The level conversion circuit for dealing with this must have different level conversion ranges according to the external power supply. In the case where the high-speed conversion is performed first with respect to a plurality of level conversion ranges with the same circuit configuration, it is advantageous to employ level conversion circuits having different circuit configurations according to the level conversion ranges. Therefore, in FIG. 13, level conversion circuits 110, 111, and 113 are employed for conversion with a wide conversion level range. They add MOS transistors Q10 and Q11 to the level conversion circuits 54 and 55 in order to accelerate the charge extraction with respect to the common drain of the MOS transistors Q3 and Q4, and similarly, common drains of the MOS transistors Q5 and Q6. MOS transistors Q12 and Q113 are added in order to accelerate the charge extraction with respect to. Clock selectors 114 and 115 for selecting the level conversion circuits 110 and 111 are added to the selection circuit 116. Further, it is assumed that there are three selection signals 120, 121, 122 for performing the selection operation of the selection circuit 116. The selection signals 121 and 122 are subjected to level conversion by the level conversion circuits 112 and 113 and supplied to the clocked inverters 75 and 76 and the clocked inverters 114 and 115. In the example of FIG. 5, the level that the signal 87 can take in the high voltage operation mode is limited to the low level, and therefore, no level conversion is required in the propagation path of the selection control signal 87. On the other hand, in the example of FIG. 13, the level that the signals 121 and 122 can take in the high voltage operation mode is not limited to the low level, and thus the level conversion circuits 112 and 113 are required. In the circuit configuration of FIG. 13, circuit elements having the same functions as those in FIG.

  FIG. 14 illustrates the correspondence relationship between the validity / invalidity of LPC communication and the operation power supply in the semiconductor integrated circuit of FIG. The operation state is roughly divided into burn-in and normal operation (operation states other than burn-in), and the normal operation is roughly divided into LPC communication valid and invalid states, as in FIG. In the low voltage operation mode (VCC = VCL = 1.8 V) in normal operation, LPC communication is valid. In this operation mode, when host interface control using the LPC bus HIF circuit 20 is performed, the control signal 120 is set to a high level (in this case, the VCL level), and the control signals 121 and 122 are set to a low level (in this case). In the buffer unit 3 for the interface, the clocked inverters 76 and 77 of the selection circuit 116 are turned on, the clocked inverters 75, 78, 114, and 115 are turned off. Bypass paths 70 and 71 are selected, and the high-speed LPC bus interface can be realized.

  In the first high voltage operation mode (VCC = 3.3V, VCL = 1.8V) in normal operation, LPC communication is disabled. In this operation mode, in this operation mode, the control signal 121 is set to the high level and the control signals 120 and 122 are set to the low level. In the buffer unit 3, the clocked inverters 76, 77, 114, and 115 of the selection circuit 116 are turned off. Then, the clocked inverters 75 and 78 are turned on, the outputs of the level conversion circuits 54 and 55 are selected, the low amplitude signal of the step-down voltage is expanded to the amplitude of the external power supply by the level conversion circuits 54 and 55, and the output buffer 53 Can be output from the external terminal 2. It is possible to operate by applying to a system using an operating voltage such as 3.3V.

  In the second high voltage operation mode (VCC = 5.0V, VCL = 1.8V) in normal operation, LPC communication is disabled. In this operation mode, in this operation mode, the control signal 122 is set to the high level and the control signals 120 and 121 are set to the low level. In the buffer unit 3, the clocked inverters 75 to 78 of the selection circuit 116 are turned off. 114 and 115 are turned on, the outputs of the level conversion circuits 110 and 111 are selected, the low-amplitude signal of the step-down voltage is expanded to the amplitude of the external power supply by the level conversion circuits 110 and 111, and the external buffer 2 is output from the output buffer 53. Can be output. It is possible to operate by applying it to a system using an operating voltage such as 5.0V.

  The high voltage operation mode at the time of burn-in is VCC = 7.0V, VCL = 2.8V, and the control signals 120 and 121 are set to low level and 122 is set to high level as in the second high voltage operation mode in normal operation. Then, the conversion function by the voltage conversion circuits 110 and 111 is enabled. Therefore, burn-in can be performed at a relatively low voltage of about 2.8 V for the input / output port 4 and the internal digital unit 7 having a relatively low withstand voltage. Can be burned in with an external power supply voltage of about 7.0 V, which is a relatively high voltage, and the burn-in reliability can be guaranteed even for the high voltage circuit 3. In addition, since the input / output port 2 operated at a low voltage is connected to the buffer unit 3 operated at a high voltage via the level conversion circuits 110 and 111, the intermediate level signal is directly transmitted from the input / output port 2 to the inverter of the buffer unit 3. Does not occur at all.

  FIG. 15 illustrates a data processing system using the microcomputer 1 as various interface controller LSIs connected to the LPC bus. A plurality of interface controllers 1 (A), 1 (B), 1 (C), etc. each constituted by the microcomputer 1 are connected to the LPC bus 131 coupled to the host processor 130. The interface controller 1 (A) implements a keyboard interface, the interface controller 1 (B) implements a mouse interface, and the interface controller 1 (C) implements a power management information exchange interface. The configuration of the LPC bus HIF circuit (LPC) of each interface controller 1 (A), 1 (B), 1 (C) is equivalent to the configuration described in FIG. 11 and FIG. 12, and each LPC bus HIF The circuit (LPC) is operated in synchronism with the PCI clock signal 100 output from the host processor 130, and the output operation achieves high-speed output that is determined within a predetermined time from the rise of the PCI clock signal 100. Reference numeral 132 denotes a circuit block generically including the data output buffer 53, the selection circuit 74, the level conversion circuits 54 and 55, the bypass paths 70 and 71, the data input buffer, the data output latch circuit, and the like. As shown in the figure, the interface controller 1 (A) includes an AD conversion circuit (A / D) that converts an analog signal 151 supplied from the outside into a digital signal, a central processing circuit (CPU), and the AD conversion described above. The internal bus 150 includes a circuit (A / D), a central processing circuit (CPU), and the LPC bus HIF circuit (LPC). The central processing circuit (CPU) is not particularly limited, but the processing is such that the digital signal converted by the AD conversion circuit (A / D) is transferred to the LPC bus HIF circuit (LPC) via the internal bus 150. I do.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the circuit that performs the external interface in synchronization with the clock is not limited to the LPC bus HIF circuit, and may be another interface circuit module. Further, the configuration of the level conversion circuit is not limited to the static latch configuration. In the above description, the level conversion circuit and bypass path for the output buffer have been described. Although it is possible to provide a level conversion circuit for the input buffer as well, the level conversion in that case is a drop in level. In that sense, there is no problem in the input operation even if the level conversion circuit is not provided, and the burn-in operation is the same. There is no hindrance. The semiconductor integrated circuit is not limited to a circuit named microcomputer, and can be widely applied to an LSI called an interface controller or a system LSI. Further, the operating voltage of the semiconductor integrated circuit is not limited to the above. The types of external power supply voltages that can be applied in the high-voltage operation mode are not limited to the two types described with reference to FIGS. 13 and 14, and the present invention can be applied to the case of three or more types. The use of the LPC bus HIF circuit is not limited to the use described with reference to FIG.

1 is a block diagram showing a microcomputer as an example of a semiconductor integrated circuit according to the present invention. It is explanatory drawing which illustrates the power supply terminal connection form at the time of the high voltage operation | movement of a microcomputer. It is explanatory drawing which illustrates the power supply terminal connection form at the time of the low voltage operation | movement of a microcomputer. It is a circuit diagram which illustrates the output buffer and level conversion circuit in a buffer part. FIG. 6 is a circuit diagram illustrating an output buffer and a level conversion circuit assigned to an output of an LPC bus HIF circuit in a buffer unit. FIG. 6 is a signal waveform diagram illustrating a signal waveform in the buffer unit of FIG. 5. It is explanatory drawing which illustrates the correspondence of the validity / invalidity of LPC communication, and an operation power supply. FIG. 6 is a circuit diagram showing, as a comparative example with FIG. 5, a case where a microcomputer that does not employ a bypass path for the LPC bus interface is used as LPC communication valid during normal operation. FIG. 6 is an explanatory diagram illustrating a connection relationship between the circuit configuration of FIG. 5 and an LPC bus HIF circuit. FIG. 5 is a block diagram illustrating a transmission system of a latch clock signal for an output latch circuit for an LPC bus interface. It is a block diagram which shows the example which further improves a clock delay and a data propagation delay. It is a schematic plan view which illustrates the layout of the buffer part vicinity. It is a circuit diagram showing an example of a semiconductor integrated circuit which enables selection of two types of voltages of an external power supply operated at a high voltage. FIG. 14 is an explanatory diagram exemplifying a correspondence relationship between validity / invalidity of LPC communication and an operating power supply in the semiconductor integrated circuit of FIG. 13. It is a block diagram which illustrates the data processing system which uses a microcomputer as various interface controller LSIs connected to a LPC bus.

Explanation of symbols

1, 1 (A), 1 (B), 1 (C) Microcomputer 2 External terminal 2 (CK) Clock input terminal 2 (D) Data output terminal 3 Buffer section 4 I / O port 6 Internal power supply voltage down converter 7 Internal digital Part VCC Power supply terminal VCL Low voltage operation terminal 11 CPU
20 LPC bus HIF circuit 53 Output buffer 54, 55 Level conversion circuit 61 Output control circuit 70, 71 Bypass path 74 Selection circuit 75-78 Clocked inverter 85 Control signal 86 Output latch circuit 87 Selection control signal 88 Latch output data 90, 92 Output latch circuit 91, 93 Output control circuit 94 Control register Elpc LPC enable bit 100 PCI clock signal 101 Clock input buffer 102 Clock input port 105 Clock signal 110, 111, 112, 113 Level conversion circuit 116 Selection circuit 120-122 Selection control signal 130 Host processor 131 LPC bus

Claims (7)

An external output buffer, a latch circuit that latches data to be output from the external output buffer in synchronization with an external clock signal, and a data processing circuit to be latched in the latch circuit,
The semiconductor integrated circuit according to claim 1, wherein the latch circuit and the processing circuit are formed by commonly inputting an output of a clock buffer that receives the external clock signal.   2. The semiconductor integrated circuit according to claim 1, wherein the latch circuit is arranged in the vicinity of the external output buffer.   It has an IO port that can latch data to be output from the external output buffer in synchronization with an internal clock signal, and the operation of the IO port and the operation of the latch circuit can be selectively switched. 3. The semiconductor integrated circuit according to claim 1, wherein A central processing unit;
A clock generation circuit that receives a reference clock signal and generates an operation clock to be supplied to the central processing unit;
An internal bus coupled to the central processing unit;
A plurality of output buffers coupled to the internal bus, a plurality of latch circuits for latching data to be output from the plurality of output buffers in synchronization with an external clock signal, and data to be latched by the plurality of latch circuits A host interface module having a processing circuit for processing;
An external terminal supplied with the external clock signal from the outside,
The plurality of latch circuits are arranged in the vicinity of the plurality of output buffers,
The semiconductor integrated circuit, wherein the external clock signal supplied to the external terminal is input in common to the plurality of latch circuits.   5. The semiconductor integrated circuit according to claim 4, wherein the host interface module is a host interface module for an LPC (Low Pin Count) bus interface.   There is an IO port that can latch data to be output from the plurality of output buffers in synchronization with an internal clock signal output from the clock generation circuit, and the operation of the IO port and the operation of the latch circuit are selectively performed. 6. The semiconductor integrated circuit according to claim 5, wherein the semiconductor integrated circuit is switchable. And an AD conversion circuit coupled to the internal bus for converting an analog signal supplied from the outside into a digital signal,
6. The semiconductor integrated circuit according to claim 5, wherein the host interface module supplies the digital signal converted by the AD converter circuit to a host processor to be coupled to the semiconductor integrated circuit.

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