JP2007034841A - Subtractor circuit, adder circuit, video signal processor by use thereof, and rectifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processing circuit suitable for high-frequency signal processing. <P>SOLUTION: An adder circuit comprising switched capacitors 110a to 110c or a subtractor circuit comprising the switched capacitors allows for appropriate high-frequency video signal processing. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a subtracting circuit (bandpass filter circuit), an adding circuit (trap filter circuit) having excellent high frequency characteristics, and a video signal processing apparatus using them. The present invention also relates to a rectifier circuit having excellent high frequency characteristics.

  As disclosed in Patent Document 1, a video signal processing apparatus that converts a video signal on which a luminance signal (Y), a color difference signal (C), and a synchronization signal (Sync) called a composite signal are superimposed into an RGB signal or the like is disclosed. Widely used.

  FIG. 21 shows the configuration of a conventional video signal processing apparatus. A video signal of a desired channel is selected by the tuner 12 from the radio wave received by the antenna 10, processed by the SAW filter 14 and the intermediate frequency conversion circuit 16, and then the luminance signal (Y) + synchronization in the Y / C separation circuit 18. The signal (Sync) and the color difference signal (C) are separated, and after being subjected to post-processing such as contour correction in the signal processing circuit 20, they are displayed as an image on the cathode ray tube 22.

  The luminance signal (Y) is represented by the signal intensity of the DC component of the composite signal. Further, as shown in FIG. 22, the color difference signal (C) is superimposed on the luminance signal (Y) as a high-frequency signal whose phase is shifted by 180 degrees for each horizontal line.

  Accordingly, when the correlation between the luminance signals (Y) of two horizontal lines received consecutively is strong, as shown in FIG. 23, one horizontal line is delayed by one horizontal scanning period and added with the other horizontal line. Thus, a trap filter that extracts only the luminance signal (Y) can be configured. Further, it is possible to configure a band pass filter that extracts only the color difference signal (C) by delaying one horizontal line by one horizontal scanning period and subtracting it from the other horizontal line. That is, the Y / C separation circuit 18 can be configured by a memory circuit for delaying a video signal and an addition circuit / subtraction circuit.

  On the other hand, when the correlation between the luminance signals (Y) of two consecutive horizontal lines is weak, the luminance signal (Y) and the color difference signal (C) are separated only by adding or subtracting the video signals of those horizontal lines. I can't. Therefore, in general, Y / C separation is performed using a trap filter and a bandpass filter including a CR filter including a resistor, a capacitor, an operational amplifier, and the like. The trap filter is configured as a filter that attenuates only the frequency band with 3.58 MHz and 4.43 MHz as center frequencies. The luminance signal (Y) and the synchronization signal (Sync) are separated from the video signal and output by the trap filter. The bandpass filter is configured as a filter that transmits only frequency bands centered on 3.58 MHz and 4.43 MHz. Only the color difference signal (C) is separated from the video signal by the bandpass filter and output.

  Thus, in order to switch the Y / C separation processing based on the correlation of the luminance signal (Y), the video signal (H1) of the reference horizontal line and the video signal (H0) of the previous horizontal line are used. ) Or the correlation with the video signal (H2) of the next horizontal line. For example, by providing a comparison circuit including a memory circuit, the video signals H0 to H2 are held in the memory circuit, the correlation between the video signal H1 and the video signal H0, and the correlation between the video signal H1 and the video signal H2, And the Y / C separation circuit is switched according to the result.

JP 2003-32701 A

  In an apparatus that processes a signal including a high-frequency signal such as a video signal, it is necessary to use a circuit that suppresses adverse effects on high-frequency characteristics due to parasitic capacitance of the circuit. In addition, it is desired to have a simple circuit configuration in order to increase the processing speed in the video signal processing apparatus and reduce the manufacturing cost.

  Accordingly, an object of the present invention is to provide a subtracting circuit, a bandpass filter circuit, an adding circuit, a trap filter circuit, a video signal processing apparatus and a rectifier circuit using them, which satisfy these requirements.

  The present invention provides a capacitor for holding a charge corresponding to a voltage value of an input signal, and a first charge for supplying the input signal to the capacitor during sampling and storing the charge according to the intensity of the input signal at the time of sampling. A switched capacitor circuit comprising at least one memory unit including a switching element that switches between a mode in which the signal is output and a second mode that outputs a signal corresponding to the charge accumulated in the capacitor at the time of output, A signal selection circuit comprising a plurality of switched capacitor circuits to which a first signal serving as a reference and a second signal different from the first signal are respectively input.

  The signal selection circuit according to the present invention is a video signal that controls switching of the switching elements of the plurality of switched capacitor circuits at the time of output based on the correlation between the first horizontal line and the second horizontal line. It can function as a selection circuit. Thus, when selecting a signal to be processed based on the correlation between video signals, only the signal to be processed can be selected and supplied.

  In the signal selection circuit of the present invention, the output terminals of the plurality of switched capacitor circuits are connected to each other, and control is performed so that the number of capacitors electrically connected to the output terminal is always constant during output. It is preferred that

  As described above, in the signal selection circuit of the present invention, the variation of the capacitance (capacitance) of the selection circuit viewed from the output side circuit is small regardless of the signal to be selected, and the output impedance can be stabilized. Accordingly, it is possible to provide a signal processing circuit with good switching characteristics and high signal processing speed.

  The present invention also provides a first capacitor for holding a charge corresponding to the voltage value of the first input signal, and the first input signal is supplied to the first capacitor during sampling to supply the first capacitor. A first mode in which charge corresponding to the intensity of the input signal is stored in one capacitor, and a sampling value of the first input signal corresponding to the charge stored in the first capacitor at the time of output. A first switched capacitor circuit including at least one memory unit including a switching element capable of selecting one of the two modes, and a first capacitor for holding a charge corresponding to the voltage value of the second input signal. Two capacitors and the second input signal is supplied to the second capacitor at the time of sampling, and the electric charge corresponding to the intensity of the input signal is accumulated in the second capacitor. A switching element capable of selecting a third mode and a fourth mode in which the sampling value of the second input signal corresponding to the charge accumulated in the second capacitor at the time of output is inverted and output; And a second switched capacitor circuit including at least one memory unit including: a subtracting circuit that outputs a difference between the first input signal and the second input signal. .

  By applying the signal selection circuit of the present invention, it can function as a subtraction circuit. For example, a video signal of a first horizontal line serving as a reference is input to the first switched capacitor circuit, and a second different from the first horizontal line is input to the second switched capacitor circuit. A horizontal line video signal is input, and a difference between the first video signal and the second video signal is calculated to function as a bandpass filter circuit that extracts a color difference signal (C) from the video signal. be able to.

  In the subtraction circuit of the present invention, the output terminals of the first and second switched capacitor circuits are connected to each other, and the number of capacitors electrically connected to the output terminal at the time of output is always constant. Is preferred.

  Thus, in the subtraction circuit of the present invention, the variation in capacitance (capacitance) seen from the circuit on the output side is small, and the output impedance can be stabilized. As a result, it is possible to provide a subtracting circuit (bandpass filter) having good switching characteristics and high signal processing speed.

  In addition, the present invention provides a capacitor for holding a charge corresponding to the voltage value of the input signal, and supplies the input signal to the capacitor at the time of sampling and accumulates a charge corresponding to the intensity of the input signal in the capacitor. At least one memory unit including: a first mode for switching; and a switching element capable of selecting a second mode for outputting a sampling value of the input signal corresponding to the charge accumulated in the capacitor at the time of output. The adder circuit includes a plurality of switched capacitor circuits.

  By applying the signal selection circuit of the present invention, it can function as an adder circuit. For example, a video signal of a first horizontal line serving as a reference and a video signal of a second horizontal line different from the first horizontal line are input to each of the plurality of switched capacitor circuits, and the first By adding the video signal and the second video signal, it can function as a trap filter circuit that extracts a luminance signal (Y) from the video signal.

  In the adder circuit of the present invention, it is preferable that the output terminals of the plurality of switched capacitor circuits are connected to each other, and the number of capacitors electrically connected to the output terminal during output is always constant. is there.

  As described above, in the adder circuit of the present invention, the variation in capacitance (capacitance) seen from the circuit on the output side is small, and the output impedance can be stabilized. Accordingly, it is possible to provide an adder circuit (trap filter) having good switching characteristics and high signal processing speed.

  Note that by applying the signal selection circuit of the present invention, it is possible to function as a rectifier circuit. Specifically, a first capacitor for holding a charge corresponding to the voltage value of the input signal, and the input signal is supplied to the first capacitor by supplying the input signal to the first capacitor during sampling. The first mode for accumulating charges according to the intensity of the signal and the second mode for outputting the sampling value of the input signal according to the charges accumulated in the first capacitor at the time of output can be selected. A first switched capacitor circuit including at least one memory unit including a switching element, a second capacitor for holding a charge corresponding to a voltage value of the input signal, and the second capacitor during sampling. A third mode in which the input signal is supplied to the capacitor and a charge corresponding to the intensity of the input signal is accumulated in the second capacitor; And at least one memory unit including a switching element capable of selecting a fourth mode for inverting and outputting the sampling value of the input signal corresponding to the charge accumulated in the second capacitor. A second switched capacitor circuit, and exclusively selects the second mode and the fourth mode at the time of output based on a relationship between the input signal and a reference signal serving as a reference. A rectifier circuit can be configured.

  In addition, the present invention provides a capacitor for holding a charge corresponding to a sampling value of an input signal, and supplies the input signal to the capacitor at the time of sampling and accumulates a charge corresponding to the intensity of the input signal in the capacitor. And a switching element that enables selection between a first mode for switching and a second mode for connecting both ends of the capacitor to the inverting output terminal and the output terminal of the operational amplifier at the time of output. An analog memory circuit is characterized.

  In this way, by connecting the capacitor holding the sampling value obtained by sampling the input signal as an electric charge to the inverting output terminal and the output terminal of the operational amplifier at the time of output, the capacitor is connected between the inverting output terminal and the output terminal of the operational amplifier. A terminal voltage is applied, and a voltage substantially equal to the terminal voltage of the capacitor is output from the operational amplifier. By using such an analog memory circuit, the voltage value of the input signal can be stored in the capacitor as an analog value. Therefore, an advantage that an error due to quantization does not occur at the time of sampling can be obtained as compared with a digital memory circuit that quantizes and stores a signal.

  Further, it is possible to provide an analog memory circuit with less influence of parasitic capacitance on a signal to be processed as compared with a case where a voltage buffer type analog memory circuit is used. In addition, an analog memory circuit having a wide dynamic range and a high signal processing speed can be provided as compared with a case where a charge transfer type analog memory circuit is used.

  Specifically, a plurality of the memory units are provided, and one of the plurality of memory units is sequentially selected to switch the switching element of the selected memory unit to the first mode, and the plurality of memories The analog memory circuit can be configured by further including a shift register that outputs a signal for switching the switching element of the memory unit other than the selected memory unit among the units to the second mode.

  Such an analog memory circuit can be applied to a video signal processing apparatus including a Y / C separation circuit that separates at least one of a luminance signal and a color difference signal from a video signal using a delayed video signal. That is, the analog memory circuit of the present invention is useful when processing a high-frequency signal such as a video signal.

  A video signal processing apparatus can be configured by appropriately selecting and combining the signal selection circuit, subtraction circuit, addition circuit, and analog memory circuit in the present invention.

  For example, a first capacitor for holding a charge corresponding to an input signal, and an input signal is supplied to the first capacitor at the time of sampling, and a charge corresponding to the intensity of the input signal is stored in the first capacitor. A memory unit comprising: a first mode for switching; and a switching element capable of selecting a second mode for connecting both ends of the first capacitor to the inverting output terminal and the output terminal of the operational amplifier at the time of output. An analog memory circuit including a plurality of analog memory circuits that receive a video signal as an input signal and delay and output the video signal; and a second capacitor for holding a charge corresponding to a voltage value of the input signal; And supplying an input signal to the second capacitor at the time of sampling according to the strength of the input signal to the second capacitor. A memory unit comprising: a switching element capable of selecting a third mode for accumulating electric charge and a fourth mode for outputting a signal corresponding to the electric charge accumulated in the second capacitor at the time of output. A switched capacitor circuit including at least one, a video signal of a first horizontal line delayed by the analog memory circuit, and a video signal of a second horizontal line different from the first horizontal line; And a video signal selection circuit including a plurality of switched capacitor circuits to which each is input.

  In addition, the first capacitor for holding the charge corresponding to the input signal, and the input signal is supplied to the first capacitor at the time of sampling, and the charge corresponding to the intensity of the input signal is stored in the first capacitor. A memory unit comprising: a first mode for switching; and a switching element capable of selecting a second mode for connecting both ends of the first capacitor to the inverting output terminal and the output terminal of the operational amplifier at the time of output. An analog memory circuit including a plurality of analog memory circuits that receive a video signal as an input signal and output the video signal with a delay, and a voltage value of the video signal of the first horizontal line delayed by the analog memory circuit A second capacitor for holding a charge corresponding to the first capacitor, and the second capacitor at the time of sampling to the first capacitor A third mode in which a horizontal line video signal is supplied and electric charge corresponding to the intensity of the first horizontal line video signal is stored in the second capacitor; A first switched capacitor comprising at least one memory unit including a switching element capable of selecting a fourth mode for outputting a sampling value of the video signal of the first horizontal line corresponding to the charged charge A circuit, a third capacitor for holding a charge corresponding to a voltage value of a video signal in a second horizontal line different from the first horizontal line, and the second capacitor in the third capacitor during sampling. The horizontal line video signal is supplied to the third capacitor to store charges corresponding to the video signal intensity of the second horizontal line. And a switching element that enables selection of a sixth mode for outputting a sampling value of the video signal of the second horizontal line according to the electric charge accumulated in the third capacitor at the time of output. And a second switched capacitor circuit including at least one memory unit including the first horizontal line video signal and the second horizontal line video signal. And a video signal processing apparatus characterized by comprising an adder circuit.

  In addition, the first capacitor for holding the charge corresponding to the input signal, and the input signal is supplied to the first capacitor at the time of sampling, and the charge corresponding to the intensity of the input signal is stored in the first capacitor. A memory unit comprising: a first mode for switching; and a switching element capable of selecting a second mode for connecting both ends of the first capacitor to the inverting output terminal and the output terminal of the operational amplifier at the time of output. An analog memory circuit including a plurality of analog memory circuits that receive a video signal as an input signal and output the video signal with a delay, and a voltage value of the video signal of the first horizontal line delayed by the analog memory circuit A second capacitor for holding a charge corresponding to the first capacitor, and the second capacitor at the time of sampling to the first capacitor A third mode in which a horizontal line video signal is supplied and electric charge corresponding to the intensity of the first horizontal line video signal is stored in the second capacitor; A first switch comprising at least one memory unit including a switching element capable of selecting a fourth mode in which a sampling value of the video signal of the first horizontal line corresponding to the charged charge is inverted and output. A capacitor circuit, a third capacitor for holding a charge corresponding to a voltage value of a video signal on a second horizontal line different from the first horizontal line, and a third capacitor for sampling at the time of sampling. The video signal of the second horizontal line is supplied and electric charge corresponding to the intensity of the video signal of the second horizontal line is accumulated in the third capacitor. A switching element capable of selecting a fifth mode and a sixth mode for outputting a sampling value of the video signal of the second horizontal line corresponding to the electric charge accumulated in the third capacitor at the time of output And a second switched capacitor circuit including at least one memory unit including: a difference between the video signal of the first horizontal line and the video signal of the second horizontal line; A video signal processing apparatus comprising: a subtracting circuit characterized by:

  When the signal selection circuit of the present invention is used, when a signal to be processed is switched based on a correlation between signals, only a signal to be processed can be selected and supplied from a plurality of signals. At this time, in the signal selection circuit of the present invention, the variation of the capacitance (capacitance) of the selection circuit seen from the output side circuit is small regardless of the signal to be selected, and the output impedance can be stabilized. Accordingly, it is possible to provide a signal processing circuit with good switching characteristics and high signal processing speed.

  Further, if the addition circuit or subtraction circuit of the present invention is used, signal addition processing or subtraction processing can be performed with a simple circuit configuration. A signal rectifier circuit can also be configured with a similar circuit configuration.

  Further, by using the bandpass filter of the present invention, it is possible to perform filter processing such as removing a DC component from a signal with a simple circuit configuration. For example, a color difference signal (C) having a frequency band centered on 3.58 MHz and 4.43 MHz can be extracted from the video signal.

  Further, if the analog memory circuit of the present invention is used, an analog memory circuit with good switching characteristics and high signal processing speed can be provided. Further, it is possible to provide an analog memory circuit in which the influence of parasitic capacitance is small on a signal to be processed.

  Each circuit in the present invention is particularly suitable for processing a signal including a high frequency component such as a video signal. For example, the effect is remarkable when applied to a video signal processing apparatus including a Y / C separation circuit and a comparison circuit.

  As shown in FIG. 1, a video signal processing apparatus 100 according to an embodiment of the present invention includes an antenna 10, a tuner 12, a SAW filter 14, an intermediate frequency conversion circuit 16, a memory circuit 30, a comparison circuit 32, and a Y / C separation circuit. 34, including a signal processing circuit 20 and a cathode ray tube 22. In the video signal processing apparatus 100, the same components as those in the conventional video signal processing apparatus are denoted by the same reference numerals as those in FIG.

  The memory circuit 30 receives the video signal output from the intermediate frequency conversion circuit 16 and holds video signals corresponding to a plurality of horizontal lines for a predetermined delay time, and then to the comparison circuit 32 and the Y / C separation circuit 34. Output. In this embodiment, the comparison circuit 32 examines the correlation between the video signal H1 of the reference horizontal line, the video signal H0 of the previous horizontal line, and the video signal H2 of the next horizontal line. . In the Y / C separation circuit 34, the filter using the addition circuit / subtraction circuit or the CR filter is switched based on the correlation between the video signal H1 and the video signal H0 and the correlation between the video signal H1 and the video signal H2. / C treatment is performed.

  The memory circuit 30 includes an analog memory circuit including a plurality of memory units each including a switching element and a capacitor. In the memory circuit 30, analog memory circuits are connected in series, and in each analog memory circuit, video signals of a plurality of horizontal lines are output by delaying a video signal by a predetermined delay time (an integral multiple of the horizontal synchronization period). . That is, the memory circuit 30 is used as a video signal delay circuit.

  For example, as shown in FIG. 2, the memory circuit 30 holds an analog memory circuit 42-1 for holding and outputting the video signal H1 of the reference horizontal line, and holds the video signal H2 of the horizontal line immediately before the reference. And an analog memory circuit 42-2 for output. The analog memory circuits 42-1 and 42-2 are connected in series. The video signal output from the intermediate frequency conversion circuit 16 is input to the first-stage analog memory circuit 42-1. Note that when the correlation between the video signals of a larger number of horizontal lines is investigated in the comparison circuit 32, the number of analog memory circuits 42 may be increased.

  Specifically, each of the analog memory circuits 42-1 and 42-2 includes operational amplifiers 50a and 50b, a plurality of memory units 52-1 to 52-m, and a shift register 54 as shown in FIG. can do. The memory unit 52 is provided by the sampling number m for the video signal of one horizontal line. For example, when a composite video signal on which a color difference signal (C) having a center frequency of 3.58 MHz is superimposed is sampled at a sampling frequency four times that of the color difference signal (C), the NTSC video signal has a horizontal scanning frequency. Since the frequency is 15.734 kHz, m = 911 memory units 52 are provided in each of the analog memory circuits 42-1 to 42-n. As a result, the video signal for one horizontal line can be sampled and held in each of the analog memory circuits 42-1 and 42-2.

  The inverting input terminal and output terminal of the operational amplifier 50a are short-circuited. The operational amplifier 50a functions as a buffer that receives the video signal output from the intermediate frequency conversion circuit 16 at its non-inverting input terminal and outputs the video signal to the memory units 52-1 to 52-m.

  Each of the memory units 52-1 to 52-m has a capacitor, a switching element for holding the voltage according to the voltage value of the video signal from the operational amplifier 50a, and both ends of the capacitor as a feedback circuit of the operational amplifier 50b. And a switching element for connection.

  The memory unit 52-1 will be described as an example. The memory unit 52-1 can include transistors Tia, Toa, Tib, Tob and a capacitor C. Each of the transistors Tia, Toa, Tib, and Tob functions as a switching element that becomes conductive between the drain and the source when the gate becomes a high level. The transistors Tia and Toa constitute a switching element for connecting one end (first terminal) of the capacitor C to the output terminal of the operational amplifier 50a or the output terminal of the operational amplifier 50b, or maintaining the floating state. When the gate of the transistor Tia becomes high level, the output terminal of the operational amplifier 50a and the first terminal of the capacitor C are connected via the drain-source of the transistor Tia. Further, when the gate of the transistor Toa becomes high level, the output terminal of the operational amplifier 50b and the first terminal of the capacitor C are connected via the drain-source of the transistor Toa. When the gates of the transistors Tia and Toa are both low, the first terminal of the capacitor C is in a floating state. The transistors Tib and Tob constitute a switching element for grounding the other end (second terminal) of the capacitor C, connecting to the inverting input terminal of the operational amplifier 50b, or maintaining the floating state. When the gate of the transistor Tib becomes high level, the second terminal of the capacitor C is grounded via the drain-source of the transistor Tib. When the gate of the transistor Tob becomes high level, the inverting input terminal of the operational amplifier 50b and the second terminal of the capacitor C are connected via the drain-source of the transistor Tob. When the gates of the transistors Tib and Tob are both low, the second terminal of the capacitor C is in a floating state.

  The memory units 52-2 to 52-m have the same configuration as the memory unit 52-1. The gates of the transistors Tia and Tib of the memory unit 52-1 are short-circuited and connected in common to the gates of the transistors Toa and Tob of the next memory unit 52-2. Similarly, the memory unit 52-i (i is a natural number of 1 to m) is also connected to the next-stage memory unit 52- (i + 1).

  The shift register 54 is provided for sequentially selecting a memory unit for storing a video signal and a memory unit for outputting a video signal from the plurality of memory units 52-1 to 52-m. The shift register 54 includes a series circuit of m flip-flops FF1 to FFm that are equal to the memory units 52-1 to 52-m. In other words, the output terminal (Q terminal) of the flip-flop FF1 is connected to the data terminal (D terminal) of the next flip-flop FF2. Similarly, the Q terminal of the flip-flop FFi (i is a natural number of 1 to m) is connected to the D terminal of the next flip-flop FFi + 1. A horizontal synchronizing pulse is input from the intermediate frequency conversion circuit 16 to the data terminal (D terminal) of the first flip-flop FF1 in synchronization with the horizontal synchronizing signal of the video signal. A clock pulse synchronized with the sampling period is input to the clock terminals (C terminals) of the flip-flops FF1 to FFm in common.

  Further, the Q terminal of the flip-flop FF1 is commonly connected to the gates of the transistors Tia and Tib of the first-stage memory unit 52-1 and the gates of the transistors Toa and Tob of the second-stage memory unit 52-2. . Similarly, the Q terminal of the flip-flop FFi (i is a natural number of 1 to m) is connected to the gates of the transistors Tia and Tib of the i-th memory unit 52-i and the memory unit 52- (i + 1) of the i + 1-th memory unit 52-i. Commonly connected to the gates of the transistors Toa and Tob. However, the Q terminal of the flip-flop FFm is connected to the gates of the transistors Toa and Tob of the memory unit 52-1 in the first stage.

  Hereinafter, a process of outputting a video signal with a delay of one horizontal line in each of the analog memory circuits 42-1 and 42-2 will be described. In the initial state, the flip-flops FF1 to FFm of the shift register 54 are reset, and the capacitor C of each memory unit 52-1 to 52-m is in a floating state.

  In synchronization with the horizontal synchronization signal of the video signal input to the non-inverting input terminal of the operational amplifier 50a, a horizontal synchronization pulse is input from the intermediate frequency conversion circuit 16 to the D terminal of the first flip-flop FF1 of the shift register 54. The Further, when a clock pulse synchronized with the sampling period is input to the C terminal of the flip-flop FF1, the flip-flop FF1 is set, and the Q terminal of the flip-flop FF1 is held at a high level. As a result, the transistors Tia and Tib of the memory unit 52-1 become conductive, and the terminal voltage of the capacitor C of the memory unit 52-1 becomes equal to the voltage of the video signal output from the operational amplifier 50a. Accordingly, a charge corresponding to the voltage of the video signal output from the operational amplifier 50a is accumulated in the capacitor C of the memory unit 52-1. That is, the voltage value of the video signal is sampled and held in the memory unit 52-1. Further, the transistors Toa and Tob of the memory unit 52-2 become conductive, and the output terminal and the inverting input terminal of the operational amplifier 50b are connected via the capacitor C of the memory unit 52-2. As a result, the terminal voltage of the capacitor C of the memory unit 52 is applied between the output terminal and the inverting input terminal of the operational amplifier 50b, and a voltage equal to the terminal voltage is output from the output terminal of the operational amplifier 50b.

  When the next clock pulse is input, the flip-flop FF1 is reset, the Q terminal of the flip-flop FF1 becomes low level, the flip-flop FF2 is set, and the Q terminal of the flip-flop FF2 is held at high level. Is done. As a result, the transistors Tia and Tib of the memory unit 52-2 become conductive, and charges corresponding to the voltage value of the video signal output from the operational amplifier 50a are accumulated in the capacitor C of the memory unit 52-2. That is, the voltage value of the video signal is sampled and held in the memory unit 52-2. Further, the transistors Toa and Tob of the memory unit 52-3 become conductive, and the output terminal and the inverting input terminal of the operational amplifier 50b are connected via the capacitor C of the memory unit 52-3. As a result, the terminal voltage of the capacitor C of the memory unit 52 is applied between the output terminal and the inverting input terminal of the operational amplifier 50b, and the non-inverting input terminal of the operational amplifier 50b is grounded. A voltage equal to the terminal voltage is output.

  Similarly, every time a clock pulse is input, the shift register 54 shifts the pulse to the next stage. When the clock pulse is input n times (n is a natural number of 1 to m), the Q terminal of the flip-flop FFn is maintained at the high level, and the video signal is newly sampled and held in the capacitor C of the memory unit 52-n. Then, a voltage corresponding to the sampling value of the video signal held in the capacitor C of the memory unit 52- (n + 1) is output from the operational amplifier 50b. However, for the m-th clock pulse, the Q terminal of the flip-flop FFm is maintained at a high level, the video signal is newly sampled and held in the capacitor C of the memory unit 52-m, and the memory unit 52-1. A voltage corresponding to the sampling value of the video signal held in the capacitor C is output from the operational amplifier 50b.

  Since the number of stages of the shift register 54 and the number of the memory units 52 are set to the sampling number m of one horizontal line, the analog memory circuits 42-1 and 42-2 are respectively set by matching the frequency of the clock pulse with the sampling frequency. The video signal can be delayed and output only during the horizontal synchronization period.

  In the memory circuit 30, as shown in FIG. 2, by inputting the output of the analog memory circuit 42-1 to the analog memory circuit 42-2, a horizontal line serving as a reference from each of the analog memory circuits 42-1 and 42-2. Video signal (H1) and the video signal (H0) of the previous horizontal line are output. Together with these video signals (H0, H1), the video signal (H2) of the horizontal line immediately after the reference is input to the comparison circuit 32 and the Y / C separation circuit 34.

  In this way, the analog memory circuits 42-1 and 42-2 are applied to the memory circuit 30 to store the voltage value of the video signal in the capacitor C as an analog value. Therefore, compared to a digital memory circuit that quantizes and stores a signal, there is an advantage that an error due to quantization does not occur during sampling.

  Each of the analog memory circuits 42-1 and 42-2 may be configured as a circuit including operational amplifiers 60a and 60b, a plurality of memory units 62-1 to 62-m, and a shift register 64, as shown in FIG. . The analog memory circuit 42 shown in FIG. 4 is a circuit called a voltage buffer type. Similarly to the above, the memory unit 62 is provided by the sampling number m for the video signal of one horizontal line.

  Each of the memory units 62-1 to 62-m transmits a capacitor, a switching element for holding the capacitor according to the voltage value of the video signal from the operational amplifier 60a, and a terminal voltage of the capacitor to the operational amplifier 60b. And a switching element.

  The memory unit 62-1 will be described as an example. The memory unit 62-1 includes transistors Tia and Toa and a capacitor C. Each of the transistors Tia and Toa functions as a switching element in which the drain-source is brought into conduction when the gate is at a high level. The transistors Tia and Toa constitute a switching element for connecting one end (first terminal) of the capacitor C to the output terminal of the operational amplifier 60a or the non-inverting input terminal of the operational amplifier 60b, or to maintain the floating state. When the gate of the transistor Tia becomes high level, the output terminal of the operational amplifier 60a and the first terminal of the capacitor C are connected via the drain-source of the transistor Tia. When the gate of the transistor Toa becomes high level, the non-inverting input terminal of the operational amplifier 60b and the first terminal of the capacitor C are connected via the drain-source of the transistor Toa. When the gates of the transistors Tia and Toa are both low, the first terminal of the capacitor C is in a floating state. The other end (second terminal) of the capacitor C is grounded.

  The memory units 62-2 to 62-m have the same configuration as the memory unit 62-1. The gate of the transistor Tia of the memory unit 62-1 is connected to the gate of the transistor Toa of the next memory unit 62-2. Similarly, the memory unit 62-i (i is a natural number of 1 to m) is also connected to the next memory unit 62- (i + 1).

  The shift register 64 includes a series circuit of a number m of flip-flops FF1 to FFm, which is equal to the memory units 62-1 to 62-m, like the shift register 54 of FIG. The Q terminals of the flip-flops FFi (i is a natural number of 1 to m) are connected to the D terminals of the flip-flops FFi + 1 of the next stage. A horizontal synchronizing pulse is input from the intermediate frequency conversion circuit 16 to the data terminal (D terminal) of the first flip-flop FF1 in synchronization with the horizontal synchronizing signal of the video signal. A clock pulse synchronized with the sampling period is input to the clock terminals (C terminals) of the flip-flops FF1 to FFm in common.

  The Q terminal of the flip-flop FF1 is commonly connected to the gate of the transistor Tia of the first-stage memory unit 62-1 and the gate of the transistor Toa of the second-stage memory unit 62-2. Similarly, the Q terminal of the flip-flop FFi (i is a natural number of 1 to m) is the gate of the transistor Tia of the i-th memory unit 62-i and the transistor Toa of the i + 1-th memory unit 62- (i + 1). Commonly connected to the gates. However, the Q terminal of the flip-flop FFm is connected to the gate of the transistor Toa of the memory unit 62-1 in the first stage.

  Hereinafter, a process of outputting a video signal with a delay of one horizontal line in each of the analog memory circuits 42-1 and 42-2 will be described. In the initial state, the flip-flops FF1 to FFm of the shift register 64 are reset, and the first terminals of the capacitors C of the memory units 62-1 to 62-m are in a floating state.

  In synchronization with the horizontal synchronization signal of the video signal input to the non-inverting input terminal of the operational amplifier 60a, a horizontal synchronization pulse is input from the intermediate frequency conversion circuit 16 to the D terminal of the first-stage flip-flop FF1 of the shift register 64. The Further, when a clock pulse synchronized with the sampling period is input to the C terminal of the flip-flop FF1, the flip-flop FF1 is set, and the Q terminal of the flip-flop FF1 is held at a high level. As a result, the transistor Tia of the memory unit 62-1 becomes conductive, and charges corresponding to the voltage value of the video signal output from the operational amplifier 60a are accumulated in the capacitor C of the memory unit 62-1. That is, the voltage value of the video signal is sampled and held in the memory unit 62-1. Further, the transistor Toa of the memory unit 62-2 becomes conductive, and the first terminal of the capacitor C of the memory unit 62-2 is connected to the non-inverting input terminal of the operational amplifier 60b. Since the output terminal and the inverting input terminal of the operational amplifier 60b are short-circuited, a voltage equal to the terminal voltage is output from the output terminal of the operational amplifier 60b.

  Next, when a clock pulse is input, the flip-flop FF1 is reset, the Q terminal of the flip-flop FF1 becomes low level, the flip-flop FF2 is set, and the Q terminal of the flip-flop FF2 becomes high level. Retained. As a result, the transistor Tia of the memory unit 62-2 becomes conductive, and charges corresponding to the voltage value of the video signal output from the operational amplifier 60a are accumulated in the capacitor C of the memory unit 62-2. That is, the voltage value of the video signal is sampled and held in the memory unit 62-2. Further, the transistor Toa of the memory unit 62-3 is turned on, and the first terminal of the capacitor C of the memory unit 62-3 is connected to the non-inverting input terminal of the operational amplifier 60b. As a result, a voltage equal to the terminal voltage is output from the output terminal of the operational amplifier 60b.

  Similarly, every time a clock pulse is input, the shift register 64 shifts the pulse to the next stage. When the clock pulse is input n times (n is a natural number from 1 to m), the Q terminal of the flip-flop FFn is maintained at a high level, and the video signal is newly sampled and held in the capacitor C of the memory unit 62-n. Then, a voltage corresponding to the sampling value of the video signal held in the capacitor C of the memory unit 62- (n + 1) is output from the operational amplifier 60b. However, for the m-th clock pulse, the Q terminal of the flip-flop FFm is maintained at a high level, the video signal is newly sampled and held in the capacitor C of the memory unit 62-m, and the memory unit 62-1. A voltage corresponding to the sampling value of the video signal held in the capacitor C is output from the operational amplifier 60b.

  Since the number of stages of the shift register 64 and the number of the memory units 62 are set to the sampling number m of one horizontal line, each of the analog memory circuits 42-1 and 42-2 is set by matching the frequency of the clock pulse with the sampling frequency. The video signal can be delayed and output only during the horizontal synchronization period.

  However, in the voltage buffer type analog memory circuit 42, as shown in FIG. 5, as the number of stages of the memory unit 62 increases, the non-inverting input terminal of the operational amplifier 60b on the output side is affected by the relatively large parasitic capacitance Cp. Will receive. The parasitic capacitance Cp degrades the frequency characteristics in the analog memory circuit 42. Therefore, when handling a signal that is easily affected by the high frequency characteristics of the circuit, such as a video signal, it is more preferable to use the analog memory circuit 42 having the circuit configuration shown in FIG. By using the analog memory circuit 42 having the circuit configuration shown in FIG. 3, it is possible to provide the video signal processing apparatus 100 that is hardly affected by the parasitic capacitance Cp, has good switching characteristics, and has a high signal processing speed.

  As shown in FIG. 6, each of the analog memory circuits 42-1 and 42-2 includes operational amplifiers 70a and 70b, a plurality of memory units 72-1 to 72-m, a shift register 74, a transfer capacitor 76, a changeover switch 78, A circuit including the output capacitor 80 and the operational amplifier 82 can also be configured. The analog memory circuit 42 shown in FIG. 6 is a circuit called a charge transfer type. Similarly to the above, the memory unit 72 is provided by the sampling number m for the video signal of one horizontal line.

  Each of the memory units 72-1 to 72-m includes a capacitor, a switching element for causing the capacitor to hold a voltage corresponding to the voltage value of the video signal from the operational amplifier 70a, and a transfer capacitor 76 for transferring the charge accumulated in the capacitor. And a switching element for transferring to the network.

  The memory unit 72-1 will be described as an example. The memory unit 72-1 includes transistors Tia and Toa and a capacitor C. Each of the transistors Tia and Toa functions as a switching element in which the drain-source is brought into conduction when the gate is at a high level. The transistors Tia and Toa constitute a switching element for connecting one end (first terminal) of the capacitor C to the output terminal of the operational amplifier 70a or the inverting input terminal of the operational amplifier 70b, or to keep it floating. When the gate of the transistor Tia becomes high level, the output terminal of the operational amplifier 70a and the first terminal of the capacitor C are connected via the drain-source of the transistor Tia. When the gate of the transistor Toa becomes high level, the inverting input terminal of the operational amplifier 70b and the first terminal of the capacitor C are connected via the drain-source of the transistor Toa. When the gates of the transistors Tia and Toa are both low, the first terminal of the capacitor C is in a floating state. The other end (second terminal) of the capacitor C is grounded.

  The memory units 72-2 to 72-m have the same configuration as the memory unit 72-1. The gate of the transistor Tia of the memory unit 72-1 is connected to the gate of the transistor Toa of the next memory unit 72-2. Similarly, the memory unit 72-i (i is a natural number of 1 to m) is also connected to the next-stage memory unit 72- (i + 1), respectively.

  The non-inverting input terminal of the operational amplifier 70b is grounded, and the transfer capacitor 76 and the changeover switch 78 are connected in parallel between the inverting input terminal and the output terminal of the operational amplifier 70b. Further, the output terminal of the operational amplifier 70 b is connected to the non-inverting input terminal of the operational amplifier 82 via the changeover switch 78. The changeover switch 78 exclusively switches a state in which both ends of the transfer capacitor 76 are short-circuited or a state in which the output terminal of the operational amplifier 70 b and the non-inverting input terminal of the operational amplifier 82 are connected. The non-inverting input terminal of the operational amplifier 82 is grounded via the output capacitor 80, and the output terminal of the operational amplifier 82 is connected to the inverting input terminal of the operational amplifier 82.

  The shift register 74 includes a series circuit of a number m of flip-flops FF1 to FFm, which is equal to the memory units 72-1 to 72-m, similarly to the shift register 54 of FIG. The Q terminals of the flip-flops FFi (i is a natural number of 1 to m) are connected to the D terminals of the flip-flops FFi + 1 of the next stage. A horizontal synchronizing pulse is input from the intermediate frequency conversion circuit 16 to the data terminal (D terminal) of the first flip-flop FF1 in synchronization with the horizontal synchronizing signal of the video signal. A clock pulse synchronized with the sampling period is input to the clock terminals (C terminals) of the flip-flops FF1 to FFm in common.

  The Q terminal of the flip-flop FF1 is commonly connected to the gate of the transistor Tia of the first-stage memory unit 72-1 and the gate of the transistor Toa of the second-stage memory unit 72-2. Similarly, the Q terminal of the flip-flop FFi (i is a natural number of 1 to m) is the gate of the transistor Tia of the i-th memory unit 72-i and the transistor Toa of the i + 1-th memory unit 72- (i + 1). Commonly connected to the gates. However, the Q terminal of the flip-flop FFm is connected to the gate of the transistor Toa of the first-stage memory unit 72-1.

  Hereinafter, a process of outputting a video signal with a delay of one horizontal line in each of the analog memory circuits 42-1 and 42-2 will be described. In the initial state, the flip-flops FF1 to FFm of the shift register 74 are reset, and the first terminals of the capacitors C of the memory units 72-1 to 72-m are in a floating state.

  In synchronization with the horizontal synchronization signal of the video signal input to the non-inverting input terminal of the operational amplifier 70a, a horizontal synchronization pulse is input from the intermediate frequency conversion circuit 16 to the D terminal of the first-stage flip-flop FF1 of the shift register 74. The Further, when a clock pulse synchronized with the sampling period is input to the C terminal of the flip-flop FF1, the flip-flop FF1 is set, and the Q terminal of the flip-flop FF1 is held at a high level. As a result, the transistor Tia of the memory unit 72-1 is turned on, and charges corresponding to the voltage value of the video signal output from the operational amplifier 70a are accumulated in the capacitor C of the memory unit 72-1. That is, the voltage value of the video signal is sampled and held in the memory unit 72-1. Further, the transistor Toa of the memory unit 72-2 becomes conductive, and the first terminal of the capacitor C of the memory unit 72-2 is connected to the inverting input terminal of the operational amplifier 70b. The charge stored in the capacitor C of the memory unit 72-2 is transferred to the transfer capacitor 76, and a voltage across the transfer capacitor 76 is applied between the inverting input terminal and the output terminal of the operational amplifier 70b. Since the non-inverting input terminal of the operational amplifier 70b is grounded and the inverting output terminal and the output terminal of the operational amplifier 82 are short-circuited, a voltage substantially equal to the terminal voltage of the capacitor C of the memory unit 72-2 is output from the output terminal of the operational amplifier 82. Is output. The charge transferred to the transfer capacitor 76 can be reset by switching the changeover switch 78 to short-circuit both ends of the transfer capacitor 76.

  Next, when a clock pulse is input, the flip-flop FF1 is reset, the Q terminal of the flip-flop FF1 becomes low level, the flip-flop FF2 is set, and the Q terminal of the flip-flop FF2 becomes high level. Retained. As a result, the transistor Tia of the memory unit 72-2 becomes conductive, and charges corresponding to the voltage value of the video signal output from the operational amplifier 70a are accumulated in the capacitor C of the memory unit 72-2. That is, the voltage value of the video signal is sampled and held in the memory unit 72-2. Further, the transistor Toa of the memory unit 72-3 becomes conductive, and the first terminal of the capacitor C of the memory unit 72-3 is connected to the inverting input terminal of the operational amplifier 70b. By transferring the charge stored in the capacitor C of the memory unit 72-3 to the transfer capacitor 76, a voltage equal to the terminal voltage is output from the output terminal of the operational amplifier 82.

  Similarly, every time a clock pulse is input, the shift register 74 shifts the pulse to the next stage. When the clock pulse is input n times (n is a natural number of 1 to m), the Q terminal of the flip-flop FFn is maintained at a high level, and the video signal is newly sampled and held in the capacitor C of the memory unit 72-n. Then, a voltage corresponding to the sampling value of the video signal held in the capacitor C of the memory unit 72- (n + 1) is output from the operational amplifier 82. However, for the m-th clock pulse, the Q terminal of the flip-flop FFm is maintained at a high level, and the video signal is newly sampled and held in the capacitor C of the memory unit 72-m. The electric charge held in the capacitor C is transferred to the transfer capacitor 76, and a voltage corresponding to the sampling value of the video signal is output from the operational amplifier 82.

  Since the number of stages of the shift register 74 and the number of the memory units 72 are set to the sampling number m of one horizontal line, the analog memory circuits 42-1 and 42-2 are respectively set by matching the clock pulse frequency to the sampling frequency. The video signal can be delayed and output only during the horizontal synchronization period.

  In the charge transfer type analog memory circuit 42, the output voltage is determined by the capacitance ratio between the capacitor C and the transfer capacitor 76 of each memory unit 72. Therefore, the variation in the capacitor C for each memory unit 72 causes a deviation between the output voltage from the analog memory circuit 42 and the terminal voltage of the capacitor C. On the other hand, in the analog memory circuit 42 having the circuit configuration shown in FIG. 3, the capacitor C included in the memory unit 52 is directly connected to the operational amplifier 50b on the output side, so that it is not affected by variations in the capacitor C. Therefore, it is more preferable to use the analog memory circuit 42 having the circuit configuration shown in FIG. By using the analog memory circuit 42 having the circuit configuration shown in FIG. 3, it is possible to provide the video signal processing apparatus 100 with good switching characteristics.

  Further, in the charge transfer type analog memory circuit 42, accumulation of charge in the capacitor C of the memory unit 72, transfer of charge from the capacitor C of the memory unit 72 to the transfer capacitor 76, and discharge of charge of the transfer capacitor 76, It is necessary to perform the steps. On the other hand, in the analog memory circuit 42 having the circuit configuration shown in FIG. 3, it is only necessary to perform the steps of accumulating charges in the capacitor C of the memory unit 52 and connecting the capacitor C to the operational amplifier 50b. Therefore, the time required for writing to and reading from the memory in the analog memory circuit 42 having the circuit configuration shown in FIG. 3 can be shorter than that of the charge transfer type analog memory circuit 42. Therefore, it is more preferable to use the analog memory circuit 42 having the circuit configuration shown in FIG. By using the analog memory circuit 42 having the circuit configuration shown in FIG. 3, it is possible to provide the video signal processing apparatus 100 having a high signal processing speed.

The comparison circuit 32 receives video signals for a plurality of horizontal lines from the memory circuit 30 and checks the correlation between the horizontal lines of the video signal. In the present embodiment, the video signal H1 and video are received by receiving the video signal H1 of the reference horizontal line, the video signal H0 of the previous horizontal line, and the video signal H2 of the next horizontal line. The correlation with the signal H0 and the correlation between the video signal H1 and the video signal H2 are investigated. Correlation between the video signal H1 and the video signal H0 is estimated by covariance S ₀₁ shown in Equation (1). Similarly, the correlation between the video signal H1 and the video signal H2 can be evaluated by covariance S ₂₁ shown in Equation (2). Here, H0 (i) is the i-th sampling value of the video signal H0, H1 (i) is the i-th sampling value of the video signal H1, H2 (i) is the i-th sampling value of the video signal H2, and H0ave is The average value of the video signal H0, H1ave is the average value of the video signal H1, H2ave is the average value of the video signal H2, and m per horizontal line is the number of samplings.

Comparison circuit 32, the covariance _{S 01} is a predetermined threshold _{T 01} or more, the covariance _{S 21} is in the case where the predetermined threshold _{T 21} is less than the video signal H1 and the video signal H0 in the Y / C separation circuit 34 A control signal instructing to perform Y / C separation processing by addition / subtraction is output to the Y / C separation circuit 34. Covariance _{S 01} is smaller than the predetermined threshold value _{T 01,} the covariance _{S 21} is subtracting the Y / C of the video signal H1 and the video signal H2 in the Y / C separation circuit 34 when a predetermined threshold _{T 21} or more A control signal instructing to perform the separation process is output to the Y / C separation circuit 34. Covariance _{S 01} is a predetermined threshold _{T 01} or more, if the covariance _{S 21} is also predetermined threshold _{T 21} or more, Y / C separation process by addition and subtraction processing using all of the video signal H0~H2 A control signal instructing to perform is output to the Y / C separation circuit 34. Further, when the covariance S ₀₁ is smaller than the predetermined threshold T ₀₁ and the covariance S ₂₁ is also smaller than the predetermined threshold T ₂₁ , a CR filter including a resistor, a capacitor, an operational amplifier, and the like with respect to the video signal H1. A control signal is output to the Y / C separation circuit 34 so as to perform the Y / C separation using the trap filter and the band pass filter.

  As shown in FIG. 7, the Y / C separation circuit 34 includes an addition / subtraction filter circuit 90, a CR filter circuit 92, and a changeover switch 94. The Y / C separation circuit 34 receives the video signals for a plurality of horizontal lines from the memory circuit 30 and the control signal from the comparison circuit 32, and performs Y / C separation of the video signal according to the instruction content of the control signal. In order to synchronize the processing of the comparison circuit 32 and the Y / C separation circuit 34, a delay circuit may be provided in front of the Y / C separation circuit 34 as necessary.

  As shown in FIG. 7, the addition / subtraction filter circuit 90 includes an addition circuit 90a and a subtraction circuit 90b. The addition / subtraction filter circuit 90 receives video signals of a plurality of horizontal lines from the memory circuit 30 and realizes Y / C separation processing of the video signal by addition / subtraction processing according to the control signal from the comparison circuit 32. In the present embodiment, as in the comparison circuit 32, the video signal H1 of the reference horizontal line, the video signal H0 of the previous horizontal line, and the video signal H2 of the next horizontal line are input. The

  When the addition / subtraction filter circuit 90 receives a control signal instructing to perform Y / C separation processing by addition / subtraction of the video signal H1 and the video signal H0 from the comparison circuit 32, the addition / subtraction filter circuit 90 adds the video signal H0 to the video signal H1. The luminance signal (Y) is extracted, and the color difference signal (C) is extracted by subtracting the video signal H0 from the video signal H1. When the addition / subtraction filter circuit 90 receives a control signal instructing to perform Y / C separation processing by addition / subtraction of the video signal H1 and the video signal H2 from the comparison circuit 32, the addition / subtraction filter circuit 90 adds the video signal H2 to the video signal H1. Thus, the luminance signal (Y) is extracted, and the color difference signal (C) is extracted by subtracting the video signal H2 from the video signal H1. Further, when the addition / subtraction filter circuit 90 receives a control signal instructing to perform the Y / C separation process by the addition / subtraction process using all of the video signals H0 to H2 from the comparison circuit 32, the addition / subtraction filter circuit 90 receives the video signals H0 to H2 from the control signal. The luminance signal (Y) is extracted by adding with a predetermined weight, and the color difference signal (C) is extracted by subtracting with a predetermined weight with respect to the video signals H0 to H2. In addition, when the addition / subtraction filter circuit 90 receives a control signal for instructing the video signal H1 to perform Y / C separation processing using the CR filter from the comparison circuit 32, the addition / subtraction filter circuit 90 outputs the reference video signal H1 as it is. .

  As shown in FIG. 8, the adder circuit 90a can be configured to include switched capacitor circuits 110a, 110b, and 110c corresponding to the video signals H0, H1, and H2, respectively. The switched capacitor circuits 110a to 110c are of a voltage buffer type and include at least one transistor Ti and To and a capacitor C, respectively.

  The switched capacitor circuit 110a for the video signal H0 includes two transistors Ti and To and two capacitors C, respectively. Each of the transistors Ti and To functions as a switching element in which the drain-source is brought into conduction when the gate is at a high level. The transistor Ti is a switching element for transmitting the video signal H0 input from the memory circuit 30 to the capacitor C and holding the charge corresponding to the voltage value of the video signal H0 in the capacitor C. One end (first terminal) of the capacitor C and the input terminal of the video signal H0 are connected via the drain-source of the transistor Ti. The transistor To is a switching element for outputting a terminal voltage corresponding to the charge held in the capacitor C. One end (first terminal) of the capacitor C is connected to the output terminal via the drain-source of the transistor To. The other end (second terminal) of the capacitor C is grounded.

  The switched capacitor circuits 110b and 110c for the video signals H1 and H2 are similarly configured. The switched capacitor circuit 110b for the video signal H1 includes four transistors Ti and To and four capacitors C, respectively. In the switched capacitor circuit 110b, one end (first terminal) of the capacitor C and the input terminal of the video signal H1 are connected via the drain-source of the transistor Ti. In the switched capacitor circuit 110b, one end (first terminal) of the capacitor C is connected to the output terminal via the drain-source of the transistor To. The other end (second terminal) of the capacitor C is grounded. The switched capacitor circuit 110c for the video signal H2 includes two transistors Ti and To and two capacitors C, respectively. In the switched capacitor circuit 110c, one end (first terminal) of the capacitor C and the input terminal of the video signal H2 are connected via the drain-source of the transistor Ti. In the switched capacitor circuit 110c, one end (first terminal) of the capacitor C is connected to the output terminal via the drain-source of the transistor To. The other end (second terminal) of the capacitor C is grounded.

  Hereinafter, processing in the adding circuit 90a will be described. In the initial state, the transistors of the switched capacitor circuits 110a to 110c are assumed to be in a non-conductive state.

  Timing at which sampling values H0 (i), H1 (i), H2 (i) (i is a natural number of 1 to m) of the video signals H0, H1, H2 are output from the memory circuit 30 (for example, input to the memory circuit 30) The gates of the transistors Ti of the switched capacitor circuits 110a to 110c are set to the high level in synchronization with the rising edge of the clock pulse). As a result, the transistors Ti of the switched capacitor circuits 110a to 110c are turned on, and the video signals H0, H1, and H2 are transmitted to the capacitors C of the switched capacitor circuits 110a to 110c, respectively, so that the switched capacitor circuit 110a. Charges corresponding to the sampling values H0 (i), H1 (i), and H2 (i) are accumulated in each of the capacitors C to 110c.

  Next, a timing after a predetermined time from when the sampling values H0 (i), H1 (i), H2 (i) (i is a natural number of 1 to m) of the video signals H0, H1, H2 are output from the memory circuit 30. In synchronization with (for example, the fall of the clock pulse input to the memory circuit 30), the gates of the transistors Ti of the switched capacitor circuits 110a to 110c are set to the low level, and the transistor To of the switched capacitor circuits 110a to 110c is set. At least one of the gates is set to the high level. The transistor To whose gate is set to the high level is selected based on the control signal from the comparison circuit 32.

  Specifically, when the comparison circuit 32 instructs to perform Y / C separation processing by adding and subtracting the video signal H1 and the video signal H0, the switch capacitor circuit 110a outputs a control signal output from the comparison circuit 32. A high level signal is output to the gates of all the transistors To and the gates of the two transistors To in the switched capacitor circuit 110b. As a result, as shown in FIG. 9, video signals H0 and H1 corresponding to the charges accumulated in the two capacitors C are added from the switched capacitor circuits 110a and 110b, respectively, and output. When the comparator circuit 32 instructs to perform Y / C separation processing by adding and subtracting the video signal H1 and the video signal H2, all the switching capacitor circuits 110c output control signals from the comparator circuit 32. A high level signal is output to the gate of the transistor To and the gates of the two transistors To in the switched capacitor circuit 110b. As a result, as shown in FIG. 10, video signals H1 and H2 corresponding to the charges accumulated in the two capacitors C are added and output from the switched capacitor circuits 110b and 110c, respectively. Further, when instructing the Y / C separation process to be performed by addition / subtraction using all of the video signals H0 to H2 from the comparison circuit 32, 1 in the switched capacitor circuit 110a is output as a control signal output from the comparison circuit 32. A high level signal is output to the gates of two transistors To, the gates of two transistors To in the switched capacitor circuit 110b, and the gate of one transistor To in the switched capacitor circuit 110c. As a result, as shown in FIG. 11, the video signals H0 and H2 corresponding to the charges stored in one capacitor C from the switched capacitor circuits 110a and 110c, and two signals from the switched capacitor circuit 110b, respectively. A video signal H1 corresponding to the charge accumulated in the capacitor C is added and output. When the comparison circuit 32 instructs to perform the Y / C separation processing using the CR filter circuit 92 instead of the addition / subtraction filter circuit 90, the control circuit outputs the control signal in the switched capacitor circuits 110a and 110c. The gate of the transistor To is maintained at a low level, and a high level signal is output to the gates of the four transistors To in the switched capacitor circuit 110b. As a result, as shown in FIG. 12, the video signal H1 corresponding to the charges accumulated in the four capacitors C is output from the switched capacitor circuit 110b as it is.

  The adder circuit in the present embodiment is configured by a signal selection circuit including a switched capacitor circuit, and can be configured more simply and at a lower cost than a conventional adder circuit. Further, the adder circuit in this embodiment can change the addition ratio of the video signal depending on from which capacitor the signal is read based on the control signal.

  Further, in the adder circuit in the present embodiment, the same number of capacitors are connected to the output terminal in any output state. Therefore, the electric capacity (capacitance) of the adding circuit as seen from the external circuit connected to the output terminal is constant, and the output impedance to the external circuit is stabilized. As a result, fluctuations in the high frequency characteristics of the external circuit can be suppressed.

  Further, as shown in FIG. 13, the subtracting circuit 90b can also be configured to include switched capacitor circuits 120a, 120b, and 120c respectively corresponding to the video signals H0, H1, and H2. Each of the switched capacitor circuits 120a to 120c includes at least one transistor Ti and To and a capacitor C.

  The switched capacitor circuit 120a for the video signal H0 includes two units each including a combination of transistors Tia, Tib, Toa, Tob and a capacitor C. Each of the transistors Tia, Toa, Tib, and Tob functions as a switching element that becomes conductive between the drain and the source when the gate becomes a high level. One end (first terminal) of the capacitor C and the input terminal of the video signal H0 are connected via the drain-source of the transistor Tia, and the other end (second terminal) of the capacitor C via the drain-source of the transistor Tib. ) Is grounded. The first terminal of the capacitor C is grounded through the drain and source of the transistor Toa, and the second terminal and the output terminal of the capacitor C are connected through the drain and source of the transistor Tob.

  The switched capacitor circuit 120c for the video signal H2 is configured in the same manner as the switched capacitor circuit 120a. The switched capacitor circuit 120c includes two units composed of combinations of transistors Tia, Tib, Toa, Tob and a capacitor C. Each of the transistors Tia, Toa, Tib, and Tob functions as a switching element that becomes conductive between the drain and the source when the gate becomes a high level. One end (first terminal) of the capacitor C is connected to the input terminal of the video signal H2 through the drain-source of the transistor Tia, and the other end (second terminal) of the capacitor C through the drain-source of the transistor Tib. ) Is grounded. The first terminal of the capacitor C is grounded through the drain and source of the transistor Toa, and the second terminal and the output terminal of the capacitor C are connected through the drain and source of the transistor Tob.

  The switched capacitor circuit 110b for the video signal H1 includes four units including transistors Ti and To and a capacitor C. In the switched capacitor circuit 110b, one end (first terminal) of the capacitor C and the input terminal of the video signal H1 are connected via the drain-source of the transistor Ti, and the capacitor via the drain-source of the transistor To. One end (first terminal) of C is connected to the output terminal. The other end (second terminal) of the capacitor C is grounded.

  Hereinafter, processing in the subtraction circuit 90b will be described. In the initial state, all the transistors of the switched capacitor circuits 120a to 120c are assumed to be non-conductive.

  Timing at which sampling values H0 (i), H1 (i), H2 (i) (i is a natural number of 1 to m) of the video signals H0, H1, H2 are output from the memory circuit 30 (for example, input to the memory circuit 30) The gates of the transistors Ti, Tia, and Tib of the switched capacitor circuits 120a to 120c are set to the high level in synchronization with the rising edge of the clock pulse. As a result, the transistors Ti, Tia, and Tib of the switched capacitor circuits 120a to 120c become conductive, and the sampling values H0 (i), H1 (i), and H2 are applied to the capacitors C of the switched capacitor circuits 120a to 120c, respectively. Charges corresponding to (i) are accumulated.

  Next, a timing after a predetermined time from when the sampling values H0 (i), H1 (i), H2 (i) (i is a natural number of 1 to m) of the video signals H0, H1, H2 are output from the memory circuit 30. In synchronization with (for example, the fall of the clock pulse input to the memory circuit 30), the gates of the transistors Ti, Tia, and Tib of the switched capacitor circuits 120a to 120c are set to the low level, and the switched capacitor circuits 120a to At least one gate of the transistors To, Toa, and Tob of 120c is set to the high level. Of the transistors To, Toa, and Tob, the element whose gate is set to the high level is selected based on the control signal from the comparison circuit 32.

  Specifically, when instructing the Y / C separation processing to be performed by adding / subtracting the video signal H1 and the video signal H0 from the comparison circuit 32, as a control signal output from the comparison circuit 32, in the switched capacitor circuit 120a. A high level signal is output to the gates of all the transistors Toa and Tob and the gates of the two transistors To in the switched capacitor circuit 120b. As a result, as shown in FIG. 14, the video signal H1 corresponding to the electric charge accumulated in the two capacitors C of the switched capacitor circuit 120b was accumulated in the two capacitors C of the switched capacitor circuit 120a. An inverted signal of the video signal H0 corresponding to the charge is added. That is, the video signal H0 is subtracted from the video signal H1 and output. Further, when the comparison circuit 32 instructs to perform the Y / C separation process by adding and subtracting the video signal H1 and the video signal H2, all the switching capacitor circuits 120c as control signals output from the comparison circuit 32 are used. A high level signal is output to the gates of the transistors Toa and Tob and the gates of the two transistors To in the switched capacitor circuit 120b. As a result, as shown in FIG. 15, the video signal H1 corresponding to the electric charge accumulated in the two capacitors C of the switched capacitor circuit 120b was accumulated in the two capacitors C of the switched capacitor circuit 120c. An inverted signal of the video signal H2 corresponding to the charge is added. That is, the video signal H2 is subtracted from the video signal H1 and output. When the comparison circuit 32 instructs to perform the Y / C separation process by addition / subtraction using all of the video signals H0 to H2, the control signal output from the comparison circuit 32 is 1 in the switched capacitor circuit 120a. A high level signal is output to the gates of the pair of transistors Toa and Tob, the gates of the two transistors To in the switched capacitor circuit 120b, and the gates of the pair of transistors Toa and Tob in the switched capacitor circuit 120c. To do. As a result, as shown in FIG. 16, a video signal H1 corresponding to the charges stored in the two capacitors C from the switched capacitor circuit 120b is stored in one capacitor C from each of the switched capacitor circuits 120a and 120c. The inverted signals of the video signals H0 and H2 corresponding to the charges that have been added are added. That is, the video signals H0 and H2 are subtracted from the video signal H1 and output.

  Similar to the addition circuit, the subtraction circuit in the present embodiment is configured by a signal selection circuit including a switched capacitor circuit, and can be configured more simply and at a lower cost than the conventional subtraction circuit. Further, the subtraction circuit in this embodiment can change the subtraction ratio of the video signal depending on which capacitor reads the signal based on the control signal.

  Further, in the subtraction circuit according to the present embodiment, the same number of capacitors are connected to the output terminal in any output state. Therefore, the electric capacity (capacitance) of the subtracting circuit viewed from the external circuit connected to the output terminal is constant, and the output impedance to the external circuit is stabilized. As a result, fluctuations in the high frequency characteristics of the external circuit can be suppressed.

  Further, as in this embodiment, a comb filter (trap filter, bandpass filter) is configured by combining a memory circuit and an adder circuit that are delay circuits, or a memory circuit and a subtractor circuit that are delay circuits. By doing so, the analog / digital converter and the digital / analog converter are not required as compared with the conventional digital system, and the circuit can be simplified. In addition, there is an advantage that quantization processing by an analog / digital converter is unnecessary, and an error due to quantization does not occur during sampling.

  In the present embodiment, the adder circuit and the subtractor circuit are constituted by voltage buffer type switched capacitor circuits, but are not limited thereto. For example, the addition circuit and the subtraction circuit can also be configured by a voltage transfer type switched capacitor circuit or the like.

  The CR filter circuit 92 includes a trap filter 92a and a bandpass filter 92b. For NTSC video signals, the trap filter 92a is configured as a filter that attenuates only the frequency band with 3.58 MHz and 4.43 MHz as the center frequencies. The bandpass filter 92b is configured as a filter that transmits only frequency bands centered on 3.58 MHz and 4.43 MHz. The trap filter 92a and the band pass filter 92b can be configured by appropriately combining resistors, capacitors, operational amplifiers, and the like.

  The CR filter circuit 92 receives the output signal of the adder circuit 90a. When the horizontal horizontal video signal H1 as a reference is input from the adder circuit 90a, the CR filter circuit 92 extracts and outputs the luminance signal (Y) by applying a trap filter to the video signal H1. . Further, the color difference signal (C) is extracted and output by applying a band pass filter to the video signal H1.

  The changeover switch 94 receives the output signals from the addition / subtraction filter circuit 90 and the CR filter circuit 92 and selects and outputs the output signal from one of the circuits based on the control signal from the comparison circuit 32. Thereby, Y / C separation processing for switching the addition / subtraction filter circuit 90 and the CR filter circuit 92 based on the correlation between a plurality of horizontal lines can be realized.

  Specifically, when the comparison circuit 32 instructs to perform Y / C separation processing by addition / subtraction of the video signal H1 and the video signal H0, the comparison circuit 32 adds / subtracts Y / C by the addition / subtraction of the video signal H1 and the video signal H2. When instructing to perform the C separation processing, and when instructing the Y / C separation processing by the addition / subtraction using all of the video signals H0 to H2 from the comparison circuit 32, the changeover switch 94 is an addition / subtraction filter circuit. The output signal from 90 is selected and output. On the other hand, when the comparison circuit 32 instructs to perform the Y / C separation processing using the CR filter circuit 92 instead of the addition / subtraction filter circuit 90, the changeover switch 94 selects and outputs the output signal from the CR filter circuit 92. Let

  The luminance signal (Y) and color difference signal (C) thus separated are subjected to post-processing such as contour correction in the signal processing circuit 20 and then displayed on the cathode ray tube 22 as an image.

  As described above, according to the selection circuit such as the addition circuit or the subtraction circuit in the present embodiment, when a signal to be processed is switched based on a correlation between signals, a signal to be processed from a plurality of signals. Only can be selected and supplied. At this time, in the selection circuit of the present invention, the fluctuation of the electric capacitance (capacitance) seen from the circuit on the output side is small regardless of the signal to be selected, and the output impedance can be stabilized. Accordingly, it is possible to provide a signal processing circuit with good switching characteristics and high signal processing speed.

  Further, according to the addition circuit or subtraction circuit in the present embodiment, signal addition processing or subtraction processing can be performed with a simple circuit configuration. A signal rectifier circuit can also be configured with a similar circuit configuration.

  In addition, according to the trap filter based on the combination of the memory circuit and the addition circuit or the band pass filter based on the combination of the memory circuit and the subtraction circuit in the present embodiment, a predetermined frequency band is extracted from the signal with a simple circuit configuration. Filter processing can be performed. For example, a luminance signal (Y) whose center frequencies are 3.58 MHz and 4.43 MHz and a color difference signal (C) whose center frequencies are 3.58 MHz and 4.43 MHz can be extracted from the video signal.

  In addition, according to the analog memory circuit in this embodiment, an analog memory circuit with good switching characteristics and high signal processing speed can be provided. Further, it is possible to provide an analog memory circuit in which the influence of parasitic capacitance is small on a signal to be processed.

  Each circuit in the present invention is particularly suitable for processing a signal including a high frequency component such as a video signal. For example, the effect is remarkable when applied to a video signal processing apparatus including a Y / C separation circuit and a comparison circuit.

<Rectifier circuit>
Note that a rectifier circuit can be formed by using a selection circuit such as an addition circuit and a subtraction circuit in this embodiment. As shown in FIG. 17, the rectifier circuit 90c can be configured to include switched capacitor circuits 130a and 130b and a control circuit 130c.

  The switched capacitor circuits 130a and 130b each include at least one transistor Ti and To and a capacitor C.

  The switched capacitor circuit 130a includes two units composed of a combination of transistors Tia, Tib, Toa, Tob and a capacitor C. Each of the transistors Tia, Toa, Tib, and Tob functions as a switching element that becomes conductive between the drain and the source when the gate becomes a high level. One end (first terminal) and the input terminal of the capacitor C are connected via the drain-source of the transistor Tia, and the other end (second terminal) of the capacitor C is grounded via the drain-source of the transistor Tib. The The first terminal of the capacitor C is grounded through the drain and source of the transistor Toa, and the second terminal and the output terminal of the capacitor C are connected through the drain and source of the transistor Tob.

  The switched capacitor circuit 130b includes two units composed of transistors Ti and To and a capacitor C. In the switched capacitor circuit 130b, one end (first terminal) of the capacitor C is connected to the input terminal via the drain-source of the transistor Ti, and one end (first terminal) of the capacitor C is connected via the drain-source of the transistor To. The first terminal is connected to the output terminal. The other end (second terminal) of the capacitor C is grounded.

  The control circuit 130c includes a comparison circuit that compares the potentials of a plurality of signals and outputs a control signal. The control circuit 130c receives a reference signal that defines a predetermined reference potential (for example, ground potential) and an input signal that is input to the input terminal, and switches the control signal according to the magnitude relationship between the input voltage and the reference potential. Output to capacitor circuits 130a and 130b.

  Hereinafter, processing for causing the selection circuit to function as a rectifier circuit will be described. In the initial state, all the transistors of the switched capacitor circuits 130a and 130b are assumed to be in a non-conductive state. Further, it is assumed that an input signal that swings up and down across the reference potential is input to the input terminal.

  The control circuit 130c synchronizes with a predetermined system clock (for example, in synchronization with the rising edge of the system clock), and sets one of the gates of the transistors Ti, Tia, and Tib included in the switched capacitor circuits 130a and 130b. High level. As a result, as shown in FIG. 18, the transistors Ti, Tia, and Tib of the switched capacitor circuits 130a and 130b are turned on, and the capacitors C connected to the transistors Ti, Tia, and Tib that are turned on. The charge corresponding to the voltage of the input signal is accumulated in the.

  Next, in synchronization with the timing after a predetermined time (for example, in synchronization with the falling edge of the clock pulse), the gates of the transistors Ti, Tia, and Tib of the switched capacitor circuits 130a and 130b are set to the low level, and the switching is performed. The gates of the transistors Toa and Tob of the capacitor circuit 130a or the transistor To of the switched capacitor circuit 130b are set to the high level. Of the transistors To, Toa, and Tob, the element whose gate is set to the high level is selected based on the control signal from the comparison circuit 32.

  Specifically, the control circuit 130c compares the potential of the input signal with the reference potential, and when the input signal is lower than the reference potential (when the input signal is a negative potential when the reference potential is the ground potential) ) Outputs a high level signal as a control signal to the gates of the transistors Toa and Tob of the capacitor C connected to the input terminal immediately before in the switched capacitor circuit 130a, and at the switched capacitor circuit 130b. A low level signal is output to the gates of the transistors Ti and To of the capacitor C connected to the input terminal immediately before. As a result, as shown in FIG. 19, the input signal held in one capacitor C of the switched capacitor circuit 130a is inverted and output. On the other hand, when the input signal is below the reference potential (when the reference potential is the ground potential, the input signal is 0 or a positive potential), the control circuit 130c uses the control circuit 130c as a control signal in the switched capacitor circuit 130b. A high level signal is output to the gate of the transistor To of the capacitor C connected to the input terminal immediately before, and the transistors Tia, Tib, and Cb of the capacitor C connected to the input terminal immediately before in the switched capacitor circuit 130a. A low level signal is output to the gates of Toa and Tob. As a result, as shown in FIG. 20, the input signal held in the capacitor C of the switched capacitor circuit 130b is output without being inverted.

  Thus, the output signal can be controlled by outputting the input signal by inverting or non-inverting the reference potential as a threshold value. If the reference potential is a ground potential, it can be used as a rectifier circuit.

  As shown in FIGS. 19 and 20, the input signal is held in the capacitor C that is not used for the output in the switched capacitor circuits 130a and 130b while outputting the inverted signal or the non-inverted signal of the input signal. It is also suitable to make it. In this manner, the input signal is alternately stored in the two capacitors C, so that the processing speed can be increased.

  Similar to the adder circuit and the subtractor circuit, this rectifier circuit is configured by a signal selection circuit including a switched capacitor circuit, and can be configured more simply and inexpensively than a conventional rectifier circuit.

It is a block diagram which shows the structure of the video signal processing apparatus in embodiment of this invention. 1 is a block diagram showing a configuration of a memory circuit in an embodiment of the present invention. 1 is a circuit diagram showing a configuration example of an analog memory circuit in an embodiment of the present invention. It is a circuit diagram which shows another example of a structure of the analog memory circuit in embodiment of this invention. It is a figure explaining the influence of the parasitic capacitance in the analog memory circuit in embodiment of this invention. It is a circuit diagram which shows another example of a structure of the analog memory circuit in embodiment of this invention. It is a block diagram which shows the structure of the Y / C separation circuit in embodiment of this invention. It is a block diagram which shows the structure of the addition circuit (trap filter) in embodiment of this invention. It is a figure explaining the effect | action of the addition circuit in embodiment of this invention. It is a figure explaining the effect | action of the addition circuit in embodiment of this invention. It is a figure explaining the effect | action of the addition circuit in embodiment of this invention. It is a figure explaining the effect | action of the addition circuit in embodiment of this invention. It is a block diagram which shows the structure of the subtraction circuit (band pass filter) in embodiment of this invention. It is a figure explaining the effect | action of the subtraction circuit in embodiment of this invention. It is a figure explaining the effect | action of the subtraction circuit in embodiment of this invention. It is a figure explaining the effect | action of the subtraction circuit in embodiment of this invention. It is a block diagram which shows the structure of the rectifier circuit in embodiment of this invention. It is a figure explaining the effect | action of the rectifier circuit in embodiment of this invention. It is a figure explaining the effect | action of the rectifier circuit in embodiment of this invention. It is a figure explaining the effect | action of the rectifier circuit in embodiment of this invention. It is a block diagram which shows the structure of the conventional video signal processing apparatus. It is a figure explaining the characteristic of the color difference signal (C) of a video signal. It is a figure which shows the structure of a comb filter.

Explanation of symbols

  10 antenna, 12 tuner, 14 SAW filter, 16 intermediate frequency conversion circuit, 18 Y / C separation circuit, 20 signal processing circuit, 22 cathode ray tube, 30 memory circuit, 32 comparison circuit, 34 Y / C separation circuit, 42 analog memory circuit 50a, 50b operational amplifier, 52 memory unit, 54 shift register, 60a, 60b operational amplifier, 62 memory unit, 64 shift register, 70a, 70b operational amplifier, 72 memory unit, 74 shift register, 76 transfer capacitor, 78 selector switch, 80 output Capacitor, 82 operational amplifier, 90 addition / subtraction filter circuit, 90a addition circuit (trap filter), 90b subtraction circuit (bandpass filter), 90c rectifier circuit, 92 CR filter circuit, 94 changeover switch, 100 110a, 110b, 110c, 120a, 120b, 120c, 130a, 130b Switched capacitor circuit, 130c control circuit, FF flip-flop, Ti, Tia, Tib, To, Toa, Tob transistor (switching element) ).

Claims (6)

A first capacitor for holding a charge corresponding to the voltage value of the first input signal;
A first mode in which the first input signal is supplied to the first capacitor at the time of sampling and electric charge corresponding to the intensity of the input signal is accumulated in the first capacitor; and the first capacitor at the time of output And a switching element capable of selecting a second mode for outputting a sampling value of the first input signal corresponding to the charge accumulated in the first switched capacitor. Circuit,
A second capacitor for holding a charge corresponding to the voltage value of the second input signal;
A third mode in which the second input signal is supplied to the second capacitor at the time of sampling and electric charge corresponding to the intensity of the input signal is accumulated in the second capacitor; and the second capacitor at the time of output A second switch comprising at least one memory unit including a switching element capable of selecting a fourth mode for inverting and outputting a sampling value of the second input signal corresponding to the charge stored in And capacitor circuit,
A subtracting circuit that outputs a difference between the first input signal and the second input signal. The subtraction circuit according to claim 1,
The output terminals of the first and second switched capacitor circuits are connected to each other, and the number of capacitors electrically connected to the output terminal during output is always constant. . A subtracting circuit according to claim 1 or 2,
A first horizontal line video signal serving as a reference is input to the first switched capacitor circuit, and a second horizontal line different from the first horizontal line is input to the second switched capacitor circuit. The band-pass filter circuit is characterized in that the difference between the first video signal and the second video signal is calculated. A capacitor for holding a charge corresponding to the voltage value of the input signal;
A first mode in which the input signal is supplied to the capacitor at the time of sampling and electric charge corresponding to the intensity of the input signal is accumulated in the capacitor; and the input signal in accordance with the electric charge accumulated in the capacitor at the time of output A plurality of switched capacitor circuits including at least one memory unit including a switching element capable of selecting a second mode for outputting a sampling value of
The output circuit of the plurality of switched capacitor circuits is connected to each other, and the number of capacitors electrically connected to the output terminal during output is always constant. An adder circuit according to claim 4,
A first horizontal line video signal serving as a reference and a second horizontal line video signal different from the first horizontal line are input to each of the plurality of switched capacitor circuits, and the first video signal is input. And a trap filter circuit, wherein the second video signal is added. A first capacitor for holding a charge corresponding to the voltage value of the input signal;
A first mode in which the input signal is supplied to the first capacitor at the time of sampling and electric charge corresponding to the intensity of the input signal is accumulated in the first capacitor; and an accumulation in the first capacitor at the time of output. A first switched capacitor circuit including at least one memory unit including: a switching element capable of selecting a second mode for outputting a sampling value of the input signal corresponding to the generated charge;
A second capacitor for holding a charge corresponding to the voltage value of the input signal;
A third mode in which the input signal is supplied to the second capacitor at the time of sampling and electric charge corresponding to the intensity of the input signal is accumulated in the second capacitor, and is accumulated in the second capacitor at the time of output. A second switched capacitor circuit including at least one memory unit including a switching element capable of selecting a fourth mode in which a sampling value of the input signal corresponding to the generated charge is inverted and output. With
A rectifier circuit that exclusively selects the second mode and the fourth mode at the time of output based on a relationship between the input signal and a reference signal as a reference.