JPH09275569A - Analog delay circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To set a delay time as a delay circuit main body accurately and also a total delay time accurately even in the case of presence of a delay attended with read/write a memory capacitor and of a group delay of input output filter circuits. SOLUTION: This circuit has n-sets of memory cells 11-1-11-n each consisting of a memory capacitor Ci and a selector switch Si and the memory cells 11-1-11-n are driven alternately by a scanning circuit 12. In this case, a clock generating circuit 14 generating a clock pulse given to the scanning circuit 12 is configured to be phase locked loop(PLL) circuit configuration and a voltage controlled oscillator 15 generates a clock pulse (n+α).FH (α is an optional natural number), the clock pulse is divided by a frequency divider 16 by a frequency division ratio of 1/(n+α) and phase-locked to a reference frequency (horizontal synchronizing frequency) FH and the delay time is set optionally based on the number α.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog delay circuit, and in particular, it has a large number of memory capacities, and charges of the analog signals are written into these memory capacities and the analog signal is delayed by a process of reading the charges. Regarding the delay circuit.

[0002]

2. Description of the Related Art A delay circuit for analog signals is, for example, P
It is required when the color signal is delayed by 1H (horizontal sweep period) in the color signal demodulation circuit of the AL (Phase Alternation by Line) type color TV receiver. That is, in the PAL system, in order to improve the color reproduction error caused by the non-linearity of DG (differential gain) and DP (differential phase),
One of the modulated wave signals of the two color signals is inverted in polarity for each scanning line (line) and transmitted.

Therefore, the receiver side needs a so-called 1H delay line for delaying 1H to obtain line correlation. As a method of obtaining this line correlation, a method performed in a state of being modulated by a subcarrier and a method performed in a baseband after demodulation are known. Considering the case of forming the delay line on the semiconductor chip, the latter method is usually easier to make. FIG. 8 shows an example of the configuration of the color signal demodulation circuit of the PAL system color TV receiver.

In FIG. 8, a PAL decoder 81 demodulates a chroma (C) signal separated from a luminance (Y) signal to obtain baseband BY and RY color difference signals.
These color difference signals are input to one of the adders 82 and 83, and are delayed by 1H by the 1H delay lines 84 and 85 to be input to the other of the adders 82 and 83. The adders 82 and 83 average the two color difference signals by taking the sum of the signal delayed by 1H and the original signal.

In the color signal demodulation circuit having such a configuration, one of the particularly important characteristics is that the accuracy of the delay time (phase) of the 1H delay lines 84 and 85 must be sufficiently accurate within the band of the color difference signal. There are points. Otherwise, averaging line by line will not be done correctly.

FIG. 9 is a conceptual diagram of an analog delay circuit using a capacitor as a memory cell. In the figure, n memory capacities Cn are arranged, the charge based on the previous information stored in the i-th memory capacity Ci at a certain clock is read out, and then the charge based on the current information is stored in the memory capacity Ci. Write. The operation is Ci → Ci + 1 →
.. .fwdarw.Cn, and then by circling to C1, a delay of about n clocks can be obtained.

As shown in FIG. 10, an actual memory cell is composed of a memory capacity Ci and a selection switch Si. The selection switch Si is, for example, MOSFET, J
It is realized by using (junction type) FET, bipolar transistor and the like.

FIG. 11 is a circuit diagram showing a conventional example of an analog delay circuit using a capacitor as a memory cell. In the figure, n memory cells each consisting of a selection switch Si and a memory capacitance Ci connected in series between a signal line L and a ground are arranged. In order to selectively drive these n memory cells. A scanning circuit 101 is provided. The scanning circuit 101 includes n stages of shift registers SR1 to SRn corresponding to the number of memory cells.

In this scanning circuit 101, only one of the n outputs makes the selection switch Si of the memory cell conductive, and sequentially shifts it by the clock pulse CLK output from the voltage controlled oscillator 102. Read / write to the selected memory cell. To set only one output of the scanning circuit 101 to the selected state, the NOR gate 103 detects a state in which the output of each stage other than the final stage is at a low level (hereinafter, referred to as “L” level), and a high level is detected. The detection output of the level (hereinafter referred to as "H" level) is input to the shift register SR1 of the first stage as a scanning pulse.

Further, there is provided a phase comparator 104 for phase-comparing the scanning pulse of the first stage input of the scanning circuit 101 and the reference signal (horizontal synchronizing frequency) FH. The phase comparator 104 uses the phase difference output between the scan pulse of the first stage input and the reference signal FH as the control input of the voltage controlled oscillator 102, and controls the oscillation frequency of the voltage controlled oscillator 102 according to the phase difference. Phase synchronization is applied. Therefore, the frequency of the clock pulse CLK, which is the oscillation output of the voltage controlled oscillator 102, is n · FH.

[0011]

By adopting the configuration as described above, the required delay of 1H can be accurately obtained. However, in reality, it is desirable that the delay in the delay circuit body is slightly smaller than 1H. The reason will be described below.

FIG. 12 is a block diagram showing a 1H delay circuit and its peripheral circuits in a PAL system color demodulation circuit. In the figure, the color difference signals BY / RY that are demodulated by the PAL decoder 105 are input to an LPF (low pass filter) 106. The LPF 106 removes subcarrier components, their harmonic components, and out-of-band noise. After that, the writing circuit 107 samples the data and writes it in the memory cell of the delay circuit 108.

Since the signal read from the memory cell of the delay circuit 108 has many harmonics because it has an intermittent pulse waveform, the waveform shaping circuit 109 including a sample hold circuit or the like shapes the signal into a staircase waveform. To be done. Furthermore, harmonic components are removed by the LPF 110 at the next stage,
It is taken out as a delayed color difference signal BY / RY.

As is apparent from the above configuration, in reality, there is a delay of 1H including the filter circuits (LPFs 106 and 110) and the peripheral circuits (writing circuit 107 and waveform shaping circuit 109) of the delay circuit 108. desired. Therefore, the delay time of the delay circuit 108 body is 1
From H to filter circuit (106, 110) and peripheral circuit (1
07,109) is ideally the time after subtracting the delay.

FIG. 13 shows an example of the configuration of a delay circuit including an input / output section. In the figure, a write switch S1 and a read switch S2 are connected in series between the circuit input terminal 111 and the inverting (-) input terminal of the operational amplifier A1. The non-inverting (+) input terminal of the operational amplifier A1 is grounded, and the read capacitor Co and the reset switch S3 are connected in parallel between the inverting input terminal and the output terminal. Further, N selection switches S (N) and N memory capacitors C (n) are connected between the connection point P of the switches S1 and S2 and the ground.

A switch S4 is provided at the output terminal of the operational amplifier A1.
Is connected to one end and the other end is connected to the non-inverting input end of the operational amplifier A2. The inverting input terminal and the output terminal of the operational amplifier A2 are short-circuited, and the capacitor C1 is connected between the non-inverting input terminal and the ground. This switch S4
And the capacitance C1 causes the sample hold circuit 112 to
Is configured. One end of the switch S5 is connected to the output end of the operational amplifier A2, and the other end is the circuit output terminal 11
Connected to 3. The capacitor C2 is connected between the other end of the switch S5 and the ground. The sample hold circuit 114 is configured by the switch S5 and the capacitor C2.

FIG. 14 shows the operation waveform of each part. First,
In the period T1 in which the clock pulse CLK is at "H" level, the write switch S1 is turned on (closed) and the input signal V
The voltage V1 of the memory capacity C (n) captures in. The charges finally remaining in the memory capacitance C (n) are obtained by sampling the point A at the moment when the write switch S1 is turned off (open). This charge is transferred to the read capacitor Co in the section T2 in which the clock pulse CLK is at the “L” level. That is, the switch S3 is turned off, the operational amplifier A1 enters the integration state, and the read switch S2 is turned on, whereby the data is transferred to the read capacitance Co.

The output voltage V2 of the operational amplifier A1 has a waveform obtained by inverting the input voltage V1. However, in FIG. 14, the output voltage V2 is inverted for clarity. In addition, actually, the charges written in the section T1 are read to the read capacitor Co in the section T2 after 1H, which is also shown in FIG.
4 is omitted. Since the output V2 of the operational amplifier A1 has a pulse waveform, it is sampled and held by the sample hold circuit 112 of the switch S4 and the capacitor C1 and becomes the voltage V3 through the operational amplifier A2.

Since the waveform of the voltage V3 still reflects the rising portion of the integration of the read capacitance Co, another step of the sample hold circuit 114 of the switch S5 and the capacitance C2 produces a clean staircase wave. The voltage becomes Vo. Eventually, the signal is sampled at the point A, which becomes the stairs of the area B in FIG. 12. In this method, in addition to the original 1H, the difference between the point A and the middle point of the area B, that is, one clock. An extra delay is generated by that amount. In addition, if the group delay of the input / output LPFs 106 and 110 in FIG. 12 is inserted, the delay due to the writing / reading of the memory cell portion is smaller than 1H by 2 to 3 clocks, so that an ideal operation can be obtained.

As another means for avoiding this problem, FIG.
At the adder 8 from the PAL decoder 81 without delay
A method is also conceivable in which a delay circuit corresponding to 2 to 3 clocks is inserted in the two signal paths extending to 2,83 and the relative delay time is correctly maintained at 1H. However, if the delay circuit is inserted in each of the two signal paths, the circuit configuration becomes complicated, and the number of new elements accompanied by signal deterioration increases.

The present invention has been made in view of the above problems, and an object of the present invention is to accurately include a delay associated with a read / write operation with respect to a memory capacity and a group delay of an input / output filter circuit. An object is to provide an analog delay circuit whose delay time can be set.

[0022]

In order to solve the above-mentioned problems, in the present invention, n (n is a natural number) memory cells consisting of a memory capacity and a selection switch element and these memory cells are sequentially scanned and selected. A scanning circuit that is uniformly driven and a clock generation circuit that supplies a clock signal having a frequency n times the reference frequency f to the scanning circuit, and the capacitance charge of the i-th (1 ≦ i ≦ n) memory cell In the analog delay circuit which reads out as an output signal, then writes the input analog signal into the i-th memory cell as a capacitive charge, and performs this read / write processing with n clocks as one cycle. When the voltage-controlled oscillator that generates the clock signal and α is an arbitrary natural number, the oscillation frequency of the voltage-controlled oscillator is 1 / (n + α)
A PLL including a frequency dividing circuit for performing frequency division with a frequency dividing ratio of ## EQU1 ## and a phase comparison circuit for phase-comparing the output frequency of the frequency dividing circuit and the reference frequency f and using the phase difference output as a control input of the voltage controlled oscillator. (Phase Locked Loop) Circuit configuration.

In the analog delay circuit having the above-mentioned configuration, the clock generation circuit has a PLL circuit configuration, a clock signal is generated by a voltage controlled oscillator, and the clock signal is divided by a division ratio of 1 / (n + α) to obtain a reference frequency f. By performing the phase synchronization, the period of the scanning start pulse of the scanning circuit corresponding to the delay time depends on α. That is, α
By selecting, it is possible to set an arbitrary delay time. As a result, an accurate delay time can be set including the delay associated with the read / write operation in the present analog delay circuit and the group delay of the input / output filter circuit.

[0024]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration diagram showing a first embodiment of the present invention. In FIG. 1, n (n is a natural number) memory cells 11-1 to 11-n are arranged between the signal line L and the ground. The memory cells 11-1 to 11-n have selection switches S1 to Sn whose one ends are connected to the signal line L and selection switches S1 to Sn.
Of the memory capacitors C1 to Cn each having one end connected to each other and the other end grounded. A scanning circuit 12 is provided to selectively drive these n memory cells 11-1 to 11-n.

The scanning circuit 12 includes memory cells 11-1 to 11-2.
N-stage shift registers SR1 corresponding to the number n of 11-n
To SRn, only one of the n outputs sequentially turns to the “H” level in synchronization with a scan pulse given from the outside, and one of the selection switches S1 to Sn is turned on ( Closed). The output of each stage other than the final stage of the scanning circuit 12 is (n-
1) Inputs. The NOR gate 13 is the scanning circuit 1
Shift registers SR1 to SRn of each stage except the final stage
When all the outputs of -1 become "L" level, the drive pulse of "H" level is output, and the shift register SR of the first stage is output.
Feed to 1.

Further, there is provided a clock generation circuit 14 which generates a clock pulse of a predetermined frequency and supplies it to the scanning circuit 12 as a scanning pulse. The clock generation circuit 14 includes a voltage controlled oscillator 15, a frequency divider 16 that divides the oscillation frequency of the voltage controlled oscillator 15 into 1 / (n + α), a frequency division output frequency of the frequency divider 16, and a reference frequency. (Horizontal synchronization frequency of video signal) The phase is compared with FH, and the phase difference output is used as the control input of the voltage controlled oscillator 15 and the phase comparator 17 is used as the PLL circuit configuration. Note that α is an arbitrary integer.

That is, this embodiment has n memory cells 11-1 to 11-n and each memory cell 11-1 to 11-n.
-n is sequentially selected by the scan clock, and charge / read processing is performed on the memory capacity Ci of the selected memory cell 11-i, thereby realizing a signal delay of a time corresponding to n clocks. In the analog delay circuit, the voltage controlled oscillator 15 generates a clock pulse and divides it by 1 / (n + α) to obtain the reference frequency FH.
The phase synchronization is adopted.

Next, regarding the circuit operation of the above configuration, FIG.
This will be described with reference to the timing chart of FIG. First, in the clock generation circuit 14, the voltage-controlled oscillator 15 generates a clock pulse having a frequency of (n + α) · FH by the phase locked loop. On the other hand, the drive pulse, which is the scan start pulse of the scanning circuit 12, receives the NOR gate when the outputs of the shift registers SR1 to SRn-1 of each stage other than the final stage of the scanning circuit 12 become "L" level. 1
Since it is a signal output from 3, it is generated every n clocks. As a result, the reference frequency F
The relationship between H and the drive pulse shifts by α clock for each cycle of the reference frequency FH. In this example, α = 2
Shows the case.

As a result, the period of the reference frequency FH is To,
If the period of the drive pulse (corresponding to the delay time) is Td, the relational expression Td = To · n / (n + α) is obtained, and it is possible to set an arbitrary delay time by α. In addition, the frequency divider 16 having a variable frequency division ratio is used, and the frequency division ratio can be arbitrarily adjusted. By changing the value of α as necessary, the delay time can be reduced. Fine adjustment is possible.

As described above, the position of the drive pulse on the time axis, that is, the access position of the memory cell is the reference frequency FH.
Since the clock generation circuit 14 having the PLL circuit configuration is configured so as to deviate with respect to the above, it is possible to set an arbitrary delay time by α, so that the delay caused by the read / write operation in the analog delay circuit and , The accurate delay time including the group delay of the input / output filter circuit (see FIG. 12), that is, the delay time To of the reciprocal (= cycle) of the reference frequency FH can be set.

In the present invention, the period T of the reference frequency FH is
It is not limited to the case where the total delay time becomes To with respect to o, and includes the case of an integer ratio. Here, the total delay time means the delay due to the write / read operation in the period Td of the drive pulse in FIG.
The group delay of the input / output filter circuit is added. That is, it includes the case where the reference frequency FH is an integral multiple or an integral fraction thereof. If it is expressed including the ratio, the frequency divider 1
The division ratio of 6 is K times the reference frequency FH (K is a positive integer)
In the case of, it becomes 1 / (n / K + α), and in the case of 1 / K times, it becomes 1 / (nK−α).

By using the analog delay circuit as the 1H delay lines 84 and 85 in the color signal demodulation circuit of the PAL system color TV receiver shown in FIG. 8, for example,
Since an accurate delay time can be set, it is possible to configure a color signal demodulation circuit that is more ideal. Further, since it is not necessary to insert a minute delay circuit for adjustment in the signal path which is not delayed by 1H, it is possible to avoid signal deterioration.

FIG. 3 is a block diagram showing a second embodiment of the present invention. In the figure, the same parts as those in FIG. 1 are designated by the same reference numerals. In FIG. 3, the selection switch Smn and the memory capacity Cmn connected in series between the row line RLn and the ground are used as memory cells, and the memory cells are arranged in a matrix of u columns and v rows (u and v are natural numbers). ing. That is, for the memory cells in the first row, one end of each of the selection switches S11 to Su1 is connected to the input / output node A via the row line RL1.
A memory capacity C11 is provided between the other end of Su1 and the ground.
~ Cu1 are connected.

As for the second row, similarly to the first row, one end of each of the selection switches S12 to Su2 is connected to the input / output node A through the row line RL2, and the selection switches S12 to S12.
Between the other end of u2 and the ground, the memory capacity C12-
Cu2 is connected. Also in the v-th row, similarly to the first and second rows, one end of each of the selection switches S1v to Suv is connected to the input / output node A via the row line RLv, and each of the other ends of the selection switches S1v to Suv is connected to the ground. Memory capacities C1v to Cuv are connected between and.

The u · v selection switches S11 to Suv can be constituted by MOSFETs, JFETs, and bipolar transistors as in the conventional case.
FIG. 4 shows the configuration of a memory cell at column i and row j when a MOSFET, for example, is used as the selection switch. In the figure, the gate electrode of the MOSFET Qij serving as a selection switch is connected to the anode of the diode Dij and the resistor Ri.
One end of j is connected. The column selection signal Xi is applied to the other end of the resistor Rij, and the row selection signal Yj is applied to the cathode of the diode Dij. Only when the column selection signal Xi and the row selection signal Yj are both at high potential, the memory is stored. It becomes possible to read / write the cell Cij.

Selection switches S11 to Suv based on column selection signals X1 to Xu in the X direction and row selection signals Y1 to Yv in the Y direction with respect to u.v memory capacities C11 to Cuv.
By the drive control of (1), charge writing / reading is performed. The column selection signals X1 to Xu are output from the X direction scanning circuit 12x, and the row selection signals Y1 to Yv are the Y direction scanning circuit 12
It is output from y. The X-direction scanning circuit 12x has u stages of shift registers XSR1 equal to the number u of columns of the cell matrix.
~ XSRu. Y-direction scanning circuit 1
2y is composed of v-stage shift registers YSR1 to XSRv equal to the number v of rows in the cell matrix.

The shift registers XSR1 to XSR1 of the respective stages other than the shift register XSRu of the final stage of the X-direction scanning circuit 12x.
The output of XSRu-1 is (u- of NOR gate 13x.
1) Inputs. The NOR gate 13x is a shift register XS of each stage except the final stage of the X-direction scanning circuit 12x.
When the outputs of R1 to XSRu-1 are all at the "L" level, an "H" level X drive pulse is output and supplied to the first-stage shift register XSR1 and also to the Y-direction scanning circuit 12y as a clock pulse. To do.

Similarly, the shift register Y of each stage other than the shift register YSRv of the final stage of the Y-direction scanning circuit 12Y.
The outputs of SR1 to YSRv-1 are (v-1) inputs of the NOR gate 13Y. NOR gate 13y is Y
When the outputs of the shift registers YSR1 to YSRv-1 of each stage except the final stage of the directional scanning circuit 12y are all at the "L" level, the Y drive pulse of the "H" level is output to the shift register YSR1 of the first stage. Supply. Further, a clock pulse having a frequency of (n + α) · FH generated by the clock generation circuit 14 is supplied to the X-direction scanning circuit 12x as a scanning pulse. The clock generation circuit 14 has a first
The same PLL circuit configuration as in the case of the above embodiment is adopted.

Next, the circuit operation of the above configuration will be briefly described. First, a clock pulse having a frequency of (n + α) · FH is supplied from the clock generation circuit 14 to the X-direction scanning circuit 12x. Then, the X-direction scanning circuit 12x
The NOR gate 13x outputs an X drive pulse when all the outputs of the respective stages other than the final stage have become "L" level. This drive pulse has a frequency of 1 / u of the clock pulse, becomes a scanning start pulse of the X-direction scanning circuit 12x, and simultaneously becomes a clock pulse of the shift registers YSR1 to YSRv of the Y-direction scanning circuit 12y.
Therefore, when one cycle of scanning in the X direction ends,
The Y-direction scanning circuit 12y is shifted by one row.
By repeating the above-described operation, as shown in FIG. 5, raster scan-like scanning in the television scanning direction is performed.

By the way, in general, as in the first embodiment shown in FIG. 1, in the method in which one shift register is associated with one memory cell, the circuit scale of the scanning circuit 12 is larger than that of the memory cell body. In view of the chip occupation area and power consumption, the number of memory cells is largely restricted.
On the other hand, by adopting the matrix method as in the present embodiment, even if the number of memory cells increases, the number of stages of the shift register does not increase so much, so the number of memory cells (that is, the product of the band and the delay time) is reduced. It becomes very effective when it is large.

FIG. 6 is a block diagram showing a third embodiment of the present invention. In the figure, the same parts as those in FIG. 3 are designated by the same reference numerals. In the present embodiment, the clock pulse having the frequency (n + α) · FH generated by the clock generation circuit 14 is commonly supplied to the X-direction scanning circuit 12x and the Y-direction scanning circuit 12y. The other configurations are the same as those in the second embodiment.

That is, in FIG. 6, the row line RLn
Selection switch Sm connected in series between the switch and ground
n and the memory capacity Cmn are used as memory cells, and the memory cells are arranged in a matrix of u columns and v rows. Specifically, in the memory cell in the first row, one end of each of the selection switches S11 to Su1 is connected to the input / output node A via the row line RL1, and each of the other ends of the selection switches S11 to Su1 is connected to the ground. Between the memory capacity C11 ~ Cu1
Is connected.

As for the second row, similarly to the first row, one end of each of the selection switches S12 to Su2 is connected to the input / output node A through the row line RL2, and the selection switches S12 to S2.
Between the other end of u2 and the ground, the memory capacity C12-
Cu2 is connected. Also in the v-th row, similarly to the first and second rows, one end of each of the selection switches S1v to Suv is connected to the input / output node A via the row line RLv, and each of the other ends of the selection switches S1v to Suv is connected to the ground. Memory capacities C1v to Cuv are connected between and.

Selection switches S11 to Suv by column selection signals X1 to Xu in the X direction and row selection signals Y1 to Yv in the Y direction for u · v memory capacities C11 to Cuv.
By the drive control of (1), charge writing / reading is performed. The column selection signals X1 to Xu are output from the X direction scanning circuit 12x, and the row selection signals Y1 to Yv are the Y direction scanning circuit 12
It is output from y. The X-direction scanning circuit 12x has u stages of shift registers XSR1 equal to the number u of columns of the cell matrix.
~ XSRu. Y-direction scanning circuit 1
2y is composed of v-stage shift registers YSR1 to XSRv equal to the number v of rows in the cell matrix.

The shift registers XSR1 to XSR1 of the respective stages other than the shift register XSRu of the final stage of the X-direction scanning circuit 12x.
The output of XSRu-1 is (u- of NOR gate 13x.
1) Inputs. The NOR gate 13x is a shift register XS of each stage except the final stage of the X-direction scanning circuit 12x.
When the outputs of R1 to XSRu-1 are all at the "L" level, the "H" level X drive pulse is output and supplied to the first-stage shift register XSR1.

Similarly, the shift register Y of each stage other than the shift register YSRv of the final stage of the Y-direction scanning circuit 12Y.
The outputs of SR1 to YSRv-1 are (v-1) inputs of the NOR gate 13Y. NOR gate 13y is Y
When the outputs of the shift registers YSR1 to YSRv-1 of each stage except the final stage of the directional scanning circuit 12y are all at the "L" level, the Y drive pulse of the "H" level is output to the shift register YSR1 of the first stage. Supply.

The X-direction scanning circuit 12x and the Y-direction scanning circuit 12y are supplied with a clock pulse having a frequency (n + α) · FH generated by the clock generation circuit 14 as a scanning pulse. The clock generation circuit 14 has the same PLL circuit configuration as that of the first embodiment. Further, in order to scan all the memory cells, it is necessary to set the arrangement numbers u and v in the X and Y directions so as not to have a common divisor other than 1. As a result, the shift register XSR1 of the X-direction scanning circuit 12x is naturally provided.
The number u of stages ~ XSRu and the number v of stages of the shift registers YSR1 to YSRv of the Y-direction scanning circuit 12y are also set so as not to have a common divisor except one.

As described above, the X-direction scanning circuit 12x and the Y-direction scanning circuit 12y are driven at the same clock frequency, and the register stages u and v are set to have no common divisor except 1. When the memory cell is selectively scanned, the address in both the X and Y directions changes every clock. As a result, the scanning direction is not the raster scan scanning as in the second embodiment (see FIG. 5) but the arrow shown in FIG.
All the memory cells are scanned diagonally according to a certain rule.

As a result, in FIG. 4, the column selection signal Xi
And the row selection signal Yj is 1 for every memory cell.
Since the clock width is used and the driving conditions of all the memory cells are the same, fixed pattern noise is less likely to occur. On the other hand, in the case of the raster scan scanning shown in FIG.
When the gate electrode waveforms of the MOSFET Qij are different between the 1st column, the uth column, and the other columns, the difference in the gate electrode waveforms is M.
Through the parasitic capacitance of the OSFET or due to a slight difference in conduction state, it appears as a difference in gain / offset characteristic of input / output characteristics of writing / reading, and may cause generation of fixed pattern noise.

[0050]

As described above, according to the present invention,
A clock generation circuit for supplying a clock signal to a scanning circuit that scans n memory cells has a PLL circuit configuration, a clock signal is generated by a voltage controlled oscillator, and the clock signal is generated at a frequency division ratio of 1 / (n + α). Since the frequency is divided and the phase is synchronized with the reference frequency f, the period of the scanning start pulse of the scanning circuit corresponding to the delay time is α.
Since any delay time can be set by selecting α, the delay associated with the read / write operation with respect to the memory capacity and the accurate delay including the group delay of the input / output filter circuit You will be able to set the time.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the first embodiment.

FIG. 3 is a configuration diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram of an example of a memory cell.

FIG. 5 is a conceptual diagram of raster scan according to a second embodiment.

FIG. 6 is a configuration diagram showing a third embodiment of the present invention.

FIG. 7 is a conceptual diagram of oblique scanning according to the third embodiment.

FIG. 8 is a block diagram showing a color signal demodulation circuit of a PAL type color TV receiver.

FIG. 9 is a conceptual diagram of analog delay.

FIG. 10 is a configuration diagram of a memory cell.

FIG. 11 is a configuration diagram showing a conventional example.

FIG. 12 is a block diagram showing a delay circuit and its peripheral circuits.

FIG. 13 is a circuit diagram showing an overall configuration of an analog delay circuit.

14 is an operation waveform diagram of each part of FIG.

[Explanation of symbols]

11-1 to 11-n memory cell 12 scanning circuit 1
2x X-direction scanning circuit 12y Y-direction scanning circuit 14 Clock generation circuit 15 Voltage controlled oscillator 16 Dividing circuit 17 Phase comparator

Claims (3)

[Claims] 1. An n-number (n is a natural number) memory cell including a memory capacity and a selection switch element, and a scanning circuit which scans the n-number of memory cells in sequence and selectively drives them.
A clock generation circuit for supplying a clock signal having a frequency n times as high as the reference frequency f to the scanning circuit, and reading the capacitance charge of the i-th (1 ≦ i ≦ n) memory cell as an output signal; An analog delay circuit for writing an input analog signal into an i-th memory cell as a capacitive charge and performing this read / write processing with n clocks as one cycle, wherein the clock generation circuit is a voltage control circuit for generating the clock signal. An oscillator, a frequency divider circuit for dividing the oscillation frequency of the voltage controlled oscillator by a frequency division ratio of 1 / (n + α) when α is an arbitrary natural number, an output frequency of the frequency divider circuit and the reference frequency f. And a phase comparison circuit using the phase difference output as a control input of the voltage controlled oscillator. 2. The reference frequency f is a frequency K times (K is a natural number) the horizontal synchronizing frequency FH of the video signal, and the frequency dividing ratio of the frequency dividing circuit is set to 1 / (n / K + α). The analog delay circuit according to claim 1, wherein the analog delay circuit is provided. 3. The reference frequency f is a frequency that is 1 / K times (K is a natural number) the horizontal synchronizing frequency FH of the video signal, and the dividing ratio of the dividing circuit is 1 / (nK-α). The analog delay circuit according to claim 1, wherein the analog delay circuit is set to.