CN116820185B - Programmable multiphase clock device - Google Patents
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Abstract
The invention provides a programmable multi-phase clock device, comprising: the device comprises a time sequence control module, a multiplexing module, a multi-phase delay line module and a phase interpolator; the time sequence control module is respectively connected with the multiplexing module and the phase interpolator, and the multiplexing module is also respectively connected with the phase interpolator and the multi-phase delay line module; the clock input end of the multi-phase delay line module is connected with a reference clock signal, and the input end of the time sequence control module is connected with a delay selection signal; the multi-phase delay line module comprises a delay line formed by a plurality of delay units, and is used for providing multi-phase clock signals output by each delay unit for the multiplexing module; the time sequence control module is used for controlling the multiplexing module to output the two selected multiphase clock signals with the preset phase difference to the phase interpolator according to the frequency division ratio and controlling the phase interpolator to output the multiphase delay clock after the reference clock is divided. The invention realizes the generation of the multiphase clock signal with high linearity, high resolution and variable frequency.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a programmable multiphase clock device.
Background
The current multiphase clock device usually supports integer frequency division, and is difficult to realize the fractional frequency division function, and the setting of the delay clock period is not fine enough.
Disclosure of Invention
The invention aims to overcome the defect that the setting of a delay clock period is not fine enough because the multi-phase clock device is difficult to realize the decimal frequency division function in the prior art.
The invention solves the technical problems by the following technical scheme:
the invention provides a programmable multi-phase clock device, comprising: the device comprises a time sequence control module, a multiplexing module, a multi-phase delay line module and a phase interpolator;
the time sequence control module is respectively connected with the multiplexing module and the phase interpolator, and the multiplexing module is also respectively connected with the phase interpolator and the multi-phase delay line module;
the clock input end of the multi-phase delay line module is connected with a reference clock signal, and the input end of the time sequence control module is connected with a delay selection signal; wherein the delay selection signal comprises a frequency division ratio of delay time to a reference clock period, the frequency division ratio comprising an integer portion and a fractional portion;
the multi-phase delay line module comprises a delay line formed by a plurality of delay units, and is used for providing multi-phase clock signals output by each delay unit for the multiplexing module;
the time sequence control module is used for controlling the multiplexing module to output two selected multiphase clock signals with preset phase difference to the phase interpolator according to the frequency division ratio, and controlling the phase interpolator to output multiphase delay clocks after the reference clock is divided.
Preferably, the phase difference between two adjacent delay units is the preset phase difference;
the time sequence control module is used for controlling the multiplexing module to output the multiphase clock signals output by the selected adjacent two delay units to the phase interpolator according to the frequency division ratio.
Preferably, the first output end of the timing control module transmits the integer part of the frequency division ratio to the multiplexing module, the second output end of the timing control module outputs the high order of the fractional part of the frequency division ratio to the multiplexing module, and the third output end of the timing control module outputs the low order of the fractional part of the frequency division ratio to the phase interpolator as the weight of the phase interpolator;
the control input end of the multi-phase delay line module is connected with a control code signal, the output end of the multi-phase delay line module outputs the multi-phase clock signal to the multiplexing module, and the first output end and the second output end of the multiplexing module are respectively and electrically connected with the clock input end of the phase interpolator.
Preferably, the timing control module is configured to obtain the frequency division ratio according to the delay selection signal, send high bits of an integer part and a fractional part of the frequency division ratio to the multiplexing module respectively, and send low bits of the fractional part of the frequency division ratio to the phase interpolator.
Preferably, the multiplexing module is configured to select two adjacent phase multiphase clock signals from the multiphase clock signals provided by the multiphase delay line module according to the high order of the integer part and the fractional part, and output the two adjacent phase multiphase clock signals to the phase interpolator.
Preferably, the phase interpolator is configured to output the divided multiphase delay clock according to the multiphase clock signals of the two adjacent phases and the low order of the fractional part.
Preferably, the multi-phase delay line module includes: the device comprises a delay line sub-module, a phase discriminator sub-module, an accumulator sub-module, a frequency divider sub-module and a conversion sub-module;
the reference clock signal is respectively input into a first input end of the delay line sub-module, a first input end of the phase discriminator sub-module and an input end of the frequency divider sub-module, the control code signal is input into a second input end of the delay line sub-module, a feedback output end of the delay line sub-module is electrically connected with the second input end of the phase discriminator sub-module, an output end of the phase discriminator sub-module is electrically connected with a first input end of the accumulator sub-module, an output end of the frequency divider sub-module is electrically connected with a second input end of the accumulator sub-module, an output end of the accumulator sub-module is electrically connected with an input end of the conversion sub-module, and an output end of the conversion sub-module is electrically connected with a third input end of the delay line sub-module;
the delay clock output end of the delay line submodule outputs the multiphase clock signal;
the delay line submodule is used for forming a delay line, generating time delay and outputting the multiphase clock signals;
the phase discriminator submodule is used for comparing the phase difference between the reference clock signal and the feedback signal output by the delay line and quantizing the phase difference into a digital output signal;
the accumulator submodule is used for accumulating output signals of the phase discriminator submodule;
the frequency divider submodule is used for dividing the reference clock signal and then taking the divided reference clock signal as a clock signal of the accumulator submodule;
the conversion submodule is used for converting an input signal into a thermometer code analog signal so as to adjust the delay time.
Preferably, the delay line submodule comprises a delay line formed by sequentially connecting the delay units in series through a delay line input end and a delay line output end;
the delay line input end of the last delay unit on the delay line is used as the first input end of the delay line submodule to receive the reference clock signal, and the delay line output end of the last delay unit on the delay line is used as the feedback output end of the delay line submodule to send the feedback signal;
each of the delay units also receives the control code signal and the thermometer code analog signal; wherein the control code signal is used for roughly adjusting the delay time, and the thermometer code analog signal is used for finely adjusting the delay time;
each delay unit also has a clock output interface to output the multi-phase clock signal.
Preferably, each of the delay units further includes: the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube, the first inverter, the second inverter, the third inverter, the fourth inverter and the first capacitor;
the first end of the first capacitor in each delay sheet is used as the first end of the delay sheet, the second end of the first capacitor is electrically connected with the drain electrode of the second NMOS tube, the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube is connected with a control code signal;
the delay units are connected in parallel to form a delay slice group, and each delay unit is provided with a first delay slice group, a second delay slice group, a third delay slice group and a fourth delay slice group;
taking the grid electrode of the first PMOS tube as the input end of the delay line and the drain electrode of the third PMOS tube as the output end of the delay line;
the grid electrode of the first PMOS tube is also electrically connected with the grid electrode of the first NMOS tube, the source electrode of the first NMOS tube is grounded, the source electrode of the first PMOS tube is connected with a power supply voltage, and the drain electrode of the first PMOS tube is electrically connected with the drain electrode of the first NMOS tube and the input end of the first inverter respectively;
the output end of the first inverter is respectively and electrically connected with the first end of the delay chip in the first delay chip set and the input end of the second inverter, the output end of the second inverter is respectively and electrically connected with the first end of the delay chip in the second delay chip set and the input end of the third inverter, the output end of the third inverter is respectively and electrically connected with the first end of the delay chip in the third delay chip set and the input end of the fourth inverter, the output end of the fourth inverter is respectively and electrically connected with the first end of the delay chip in the fourth delay chip set, the grid electrode of the third PMOS tube and the grid electrode of the third NMOS tube, the grounding ends of the first inverter, the second inverter, the third inverter and the fourth inverter are all grounded, the output ends of the first inverter, the second inverter and the fourth inverter are respectively and electrically connected with the second end of the delay chip in the third delay chip set and the fourth inverter, the grid electrode of the PMOS tube is electrically connected with the second drain electrode of the PMOS tube, and the drain electrode of the PMOS tube is electrically connected with the analog voltage meter;
the source electrode of the third NMOS tube is grounded, the source electrode of the third PMOS tube is connected with the power supply voltage, the drain electrode of the third PMOS tube is also electrically connected with the drain electrode of the third NMOS tube, the grid electrode of the fourth PMOS tube and the grid electrode of the fourth NMOS tube respectively, the source electrode of the fourth NMOS tube is grounded, the source electrode of the fourth PMOS tube is connected with the power supply voltage, the drain electrode of the fourth PMOS tube is electrically connected with the drain electrode of the fourth NMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the fifth NMOS tube respectively, the source electrode of the fifth NMOS tube is grounded, the source electrode of the fifth PMOS tube is connected with the power supply voltage, and the drain electrode of the fifth PMOS tube is electrically connected with the drain electrode of the fifth NMOS tube;
and taking the drain electrode of the fifth PMOS tube as the clock output interface.
Preferably, when the signal of the first input end of the phase discriminator sub-module leads the signal of the second input end, the output of the phase discriminator sub-module is 0;
the output of the phase detector sub-module is 1 when the second input signal of the phase detector sub-module leads the first input signal.
The invention has the positive progress effects that: the time sequence control module obtains a frequency division ratio according to the delay selection signal, and respectively sends the high bits of the integer part and the decimal part of the frequency division ratio to the multiplexing module, and sends the low bits of the decimal part of the frequency division ratio to the phase interpolator; the multiplexing module selects two adjacent phase multiphase clock signals from the multiphase clock signals provided by the multiphase delay line module according to the high bits of the integer part and the decimal part and outputs the two adjacent phase multiphase clock signals to the phase interpolator; the phase interpolator outputs the frequency-divided multiphase delay clock according to the multiphase clock signals of two adjacent phases and the low bit of the decimal part, namely, the phase interpolator converts the low bit of the decimal part into a required weight factor, then the phase interpolation is carried out between the multiphase clock signals of two adjacent phases to obtain the decimal frequency-divided multiphase delay clock, the clock precision is improved, and the generation of the multiphase clock signals with high linearity, high resolution and variable frequency is realized.
Drawings
FIG. 1 is a block diagram of a programmable multi-phase clock device according to a preferred embodiment of the present invention.
FIG. 2 is a block diagram of a multi-phase delay line module in a programmable multi-phase clock device according to a preferred embodiment of the present invention.
FIG. 3 is a block diagram of a delay line sub-block in a programmable multi-phase clock device according to a preferred embodiment of the present invention.
Fig. 4 is a circuit diagram of a delay unit in a programmable multi-phase clock device according to a preferred embodiment of the invention.
Detailed Description
The invention is further illustrated by means of the preferred embodiments, but the invention is not limited to the described embodiments.
The present embodiment provides a programmable multiphase clock device, referring to fig. 1, the programmable multiphase clock device includes: a timing control module 1, a multiplexing module 2, a multi-phase delay line module 3 and a phase interpolator 4.
The time sequence control module 1 is respectively connected with the multiplexing module 2 and the phase interpolator 4, and the multiplexing module 2 is also respectively connected with the phase interpolator 4 and the multi-phase delay line module 3.
The clock input of the multi-phase Delay line module 3 is connected to a reference clock signal (ref_clk), and the input of the timing control module 1 is connected to a delay_time_select signal (delay_time_select). The delay selection signal comprises a frequency division ratio of delay time and a reference clock period, wherein the frequency division ratio comprises an integer part N and a decimal part f, and both N and f are positive integers.
The multi-phase delay line module 3 includes a delay line composed of a plurality of delay units, and the multi-phase delay line module 3 is configured to provide the multi-phase clock signal (tap_out) output by each delay unit to the multiplexing module 2.
The timing control module 1 is configured to control the multiplexing module 2 to Output the two multiphase clock signals (dll_out) with the preset phase difference to the phase interpolator 4 according to the frequency division ratio, and control the phase interpolator 4 to Output the multiphase delay clock (Output) after dividing the reference clock.
Where the integer part N represents the whole period, 0.F is considered here with emphasis, i.e. a finer fraction is produced. The fractional part f is divided into upper bits (f_msb) and lower bits (f_lsb). The upper bits (f_msb) are the control codes of the delay line and the lower bits (f_lsb) are the control codes of the phase interpolator.
Assume that: f is 6, the upper bit (f_msb) is a 3-bit control code, and the lower bit (f_lsb) is a 5-bit control code. Then f_msb is 100 and f_lsb is 11001 in order to achieve a delay time of 0.6 period. This is because: f_MSB is a 3-bit control code, each step is 0.125,0.6 between 0.125 x 4 and 0.125 x 5, and the corresponding control code is 4, namely 100; f_LSB is a control code of 5 bits, each step is 0.125/32,0.6-0.5=0.1, and the corresponding control code is 25, namely 11001.
The phase interpolator performs phase interpolation between two clock signals having a phase difference. The phase interpolator changes the weight factor of the interpolation signal according to the digital control code and superimposes the outputs of each basic cell. The two rising edges of the input clock have different arrival moments, and different phase interpolation is generated by changing the speed of charge and discharge. The phase interpolator is a prior art and will not be described in detail here.
The multi-phase delay line of the architecture of the independent Muti tap dll (a delay line architecture) can gradually deteriorate the transmission of signals between the stages, and when the loads are not matched, the delay time of each stage is different, and the precision is poor; the phase interpolator needs two clock edges with phase difference, and the application scene is limited. Compared with a multi-phase delay line of a single Muti tap dll architecture, the programmable multi-phase clock device of the embodiment improves precision, and the delay line and the phase interpolator are respectively controlled through a frequency division ratio output form of N.f, so that the final output clock frequency is different from the input clock frequency, and frequency adjustability is realized.
In this embodiment, the timing control module obtains the frequency division ratio according to the delay selection signal, and sends the high bits of the integer part and the decimal part of the frequency division ratio to the multiplexing module respectively, and sends the low bits of the decimal part of the frequency division ratio to the phase interpolator; the multiplexing module selects two adjacent phase multiphase clock signals from the multiphase clock signals provided by the multiphase delay line module according to the high bits of the integer part and the decimal part and outputs the two adjacent phase multiphase clock signals to the phase interpolator; the phase interpolator outputs the frequency-divided multiphase delay clock according to the multiphase clock signals of two adjacent phases and the low bit of the decimal part, namely, the phase interpolator converts the low bit of the decimal part into a required weight factor, then the phase interpolation is carried out between the multiphase clock signals of two adjacent phases to obtain the decimal frequency-divided multiphase delay clock, the clock precision is improved, and the generation of the multiphase clock signals with high linearity, high resolution and variable frequency is realized.
In one embodiment, the phase difference between two adjacent delay units is a preset phase difference.
The timing control module 1 is used for controlling the multiplexing module 2 to output the multiphase clock signals output by the selected adjacent two delay units to the phase interpolator 4 according to the frequency division ratio.
In one embodiment, the first output of the timing control module 1 transmits the integer part of the frequency division ratio to the multiplexing module 2, the second output of the timing control module 1 outputs the high order of the fractional part of the frequency division ratio to the multiplexing module 2, and the third output of the timing control module 1 outputs the low order of the fractional part of the frequency division ratio to the phase interpolator 4 as the weight of the phase interpolator 4.
The control input end of the multi-phase Delay line module 3 is connected with a control code signal (delay_cap_control), the output end of the multi-phase Delay line module 3 outputs a multi-phase clock signal to the multiplexing module 2, and the first output end and the second output end of the multiplexing module 2 are respectively and electrically connected with the clock input end of the phase interpolator 4.
In one embodiment, the timing control module 1 is configured to obtain the frequency division ratio according to the delay selection signal, and send the high bits of the integer part and the fractional part of the frequency division ratio to the multiplexing module 2 respectively, and send the low bits of the fractional part of the frequency division ratio to the phase interpolator 4.
In one embodiment, the multiplexing module 2 is configured to select two adjacent phase multiphase clock signals from the multiphase clock signals provided by the multiphase delay line module 3 according to the high order bits of the integer part and the fractional part and output the two adjacent phase multiphase clock signals to the phase interpolator 4.
In one embodiment, the phase interpolator 4 is configured to output a divided multi-phase delay clock based on the multi-phase clock signals of two adjacent phases and the low order bits of the fractional part.
In one embodiment, referring to fig. 2, the multi-phase delay line module 3 includes: delay line submodule 31, phase discriminator submodule 32, accumulator submodule 33, frequency divider submodule 34 and conversion submodule 35.
The reference clock signal is input to the first input of the Delay line submodule 31, the first input of the phase discriminator submodule 32 and the input of the frequency divider submodule 34, respectively, the control code signal (delay_cap_control) is input to the second input of the Delay line submodule 31, the feedback output of the Delay line submodule 31 is electrically connected to the second input of the phase discriminator submodule 32, the output of the phase discriminator submodule 32 is electrically connected to the first input of the accumulator submodule 33, the output of the frequency divider submodule 34 is electrically connected to the second input of the accumulator submodule 33, the output of the accumulator submodule 33 is electrically connected to the input of the conversion submodule 35, and the output of the conversion submodule 35 is electrically connected to the third input of the Delay line submodule 31.
The delay clock output of the delay line submodule 31 outputs a multiphase clock signal.
The delay line sub-block 31 is used to compose a delay line, generate a time delay, and output a multi-phase clock signal.
The phase detector sub-module 32 is configured to compare the phase difference between the reference clock signal and the feedback signal output by the delay line and to quantize the digital output signal (PD out ）。
The accumulator sub-module 33 is configured to accumulate the output signals of the phase detector sub-module 32.
The divider submodule 34 is used to divide the reference clock signal to act as the clock signal for the accumulator submodule.
The conversion sub-module 35 is configured to convert the input signal into a thermometer code analog signal to adjust the delay time.
The phase discriminator sub-module, the accumulator sub-module, the conversion sub-module and the delay line sub-module form a negative feedback loop to finely adjust the delay time.
In the embodiment, the reference clock is locked in one period after delay through the delay line, and the delay time of the delay line is adjusted through rough adjustment and fine adjustment; the phase discriminator submodule, the accumulator submodule, the conversion submodule and the delay line submodule form a negative feedback loop to finely adjust the delay time; the multi-phase delay line module locks the input reference clock signal through the delay line and delays the reference clock signal by a preset delay time to obtain the multi-phase clock signal, so that errors caused by component mismatch are effectively reduced, and the requirements of high precision and high linearity of the delay line are met.
In one embodiment, referring to fig. 2 and 3, the Delay line submodule 31 includes a plurality of Delay cells 311 (Delay cells in fig. 3) connected in series sequentially through Delay line inputs (inputs in fig. 3) and Delay line outputs (outputs in fig. 3).
The delay line input of the first delay cell 311 on the delay line is used as the first input of the delay line sub-module to receive the reference clock signal, and the delay line output of the last delay cell 311 on the delay line is used as the feedback output of the delay line sub-module to transmit the feedback signal (DLL out ）。
Each delay unit 311 also receives a control code signal and a thermometer code analog signal. Wherein the control code signal is used for roughly adjusting the delay time, and the thermometer code analog signal is used for finely adjusting the delay time.
Each delay unit 311 also has a clock output interface to output a multi-phase clock signal (tap_out).
In the embodiment, the reference clock is locked in one period after delay through the delay line, and the delay time of the delay line is adjusted through rough adjustment and fine adjustment; the phase difference between the reference clock signal and the feedback signal output by the delay line is resolved by the phase discriminator submodule, the control signal is accumulated by the accumulator submodule, and then the thermometer code analog signal generated by conversion of the conversion submodule is finely regulated; the multi-phase delay line module locks the input reference clock signal through the delay line and delays the reference clock signal by a preset delay time to obtain the multi-phase clock signal, so that errors caused by component mismatch are effectively reduced, and the requirements of high precision and high linearity of the delay line are met.
In one embodiment, referring to fig. 4, each delay unit 311 further includes: the first PMOS pipe PM1, the second PMOS pipe PM2, the third PMOS pipe PM3, the fourth PMOS pipe PM4, the fifth PMOS pipe PM5, the first NMOS pipe NM1, the second NMOS pipe NM2, the third NMOS pipe NM3, the fourth NMOS pipe NM4, the fifth NMOS pipe NM5, the first inverter PI1, the second inverter PI2, the third inverter PI3, the fourth inverter PI4 and the first capacitor C1.
The first end of the first capacitor C1 in each delay sheet is used as the first end of the delay sheet, the second end of the first capacitor C1 is electrically connected with the drain electrode of the second NMOS tube NM2, the source electrode of the second NMOS tube NM2 is grounded, and the grid electrode of the second NMOS tube NM2 is connected with a control code signal.
The delay units 311 are provided with a first delay slice group, a second delay slice group, a third delay slice group and a fourth delay slice group.
The grid electrode of the first PMOS tube PM1 is used as the input end of the delay line, and the drain electrode of the third PMOS tube PM3 is used as the output end of the delay line.
The grid electrode of the first PMOS tube PM1 is also electrically connected with the grid electrode of the first NMOS tube NM1, the source electrode of the first NMOS tube NM1 is grounded, the source electrode of the first PMOS tube PM1 is connected with a power supply voltage, and the drain electrode of the first PMOS tube PM1 is electrically connected with the drain electrode of the first NMOS tube NM1 and the input end of the first inverter PI1 respectively.
The output end of the first inverter PI1 is respectively and electrically connected with the first end of the delay piece in the first delay piece group and the input end of the second inverter PI2, the output end of the second inverter PI2 is respectively and electrically connected with the first end of the delay piece in the second delay piece group and the input end of the third inverter PI3, the output end of the third inverter PI3 is respectively and electrically connected with the first end of the delay piece in the third delay piece group and the input end of the fourth inverter PI4, the output end of the fourth inverter PI4 is respectively and electrically connected with the first end of the delay piece in the fourth delay piece group, the grid electrode of the third PMOS tube PM3 and the grid electrode of the third NMOS tube NM3, the grounding ends of the first inverter PI1, the second inverter PI2, the third inverter PI3 and the fourth inverter PI4 are all grounded, the power supply ends of the first inverter PI1, the second inverter PI2, the third inverter PI3 and the fourth inverter PI4 are all electrically connected with the drain electrode PM2 of the second PMOS tube PM2, and the drain electrode PM2 of the second PMOS tube PM2 is connected with the analog voltage meter.
The source electrode of the third NMOS tube NM3 is grounded, the source electrode of the third PMOS tube PM3 is connected with a power supply voltage, the drain electrode of the third PMOS tube PM3 is also electrically connected with the drain electrode of the third NMOS tube NM3, the grid electrode of the fourth PMOS tube PM4 and the grid electrode of the fourth NMOS tube NM4 respectively, the source electrode of the fourth NMOS tube NM4 is grounded, the source electrode of the fourth PMOS tube PM4 is connected with the power supply voltage, the drain electrode of the fourth PMOS tube PM4 is electrically connected with the drain electrode of the fourth NMOS tube NM4, the grid electrode of the fifth PMOS tube PM5 and the grid electrode of the fifth NMOS tube NM5 respectively, the source electrode of the fifth NMOS tube NM5 is grounded, and the source electrode of the fifth PMOS tube PM5 is electrically connected with the power supply voltage, and the drain electrode of the fifth PMOS tube PM5 is electrically connected with the drain electrode of the fifth NMOS tube NM 5.
The drain electrode of the fifth PMOS tube PM5 is used as a clock output interface.
In one embodiment, the output of the phase detector sub-module 32 is 0 when the first input signal of the phase detector sub-module 32 leads the second input signal.
The output of the phase detector sub-block 32 is 1 when the second input signal of the phase detector sub-block 32 leads the first input signal.
In one embodiment, the number of delay cells 311 is 8.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the principles and spirit of the invention, but such changes and modifications fall within the scope of the invention.
Claims (8)
1. A programmable multi-phase clock device, comprising: the device comprises a time sequence control module, a multiplexing module, a multi-phase delay line module and a phase interpolator;
the time sequence control module is respectively connected with the multiplexing module and the phase interpolator, and the multiplexing module is also respectively connected with the phase interpolator and the multi-phase delay line module;
the clock input end of the multi-phase delay line module is connected with a reference clock signal, and the input end of the time sequence control module is connected with a delay selection signal; wherein the delay selection signal comprises a frequency division ratio of delay time to a reference clock period, the frequency division ratio comprising an integer portion and a fractional portion;
the multi-phase delay line module comprises a delay line formed by a plurality of delay units, and is used for providing multi-phase clock signals output by each delay unit for the multiplexing module;
the time sequence control module is used for controlling the multiplexing module to output two selected multiphase clock signals with preset phase difference to the phase interpolator according to the frequency division ratio, and controlling the phase interpolator to output multiphase delay clocks after the reference clock is divided;
a first output end of the time sequence control module transmits an integer part of the frequency division ratio to the multiplexing module, a second output end of the time sequence control module outputs a high order of a decimal part of the frequency division ratio to the multiplexing module, and a third output end of the time sequence control module outputs a low order of the decimal part of the frequency division ratio to the phase interpolator as a weight of the phase interpolator;
the control input end of the multi-phase delay line module is connected with a control code signal, the output end of the multi-phase delay line module outputs the multi-phase clock signal to the multiplexing module, and the first output end and the second output end of the multiplexing module are respectively and electrically connected with the clock input end of the phase interpolator;
the multi-phase delay line module includes: the device comprises a delay line sub-module, a phase discriminator sub-module, an accumulator sub-module, a frequency divider sub-module and a conversion sub-module;
the reference clock signal is respectively input into a first input end of the delay line sub-module, a first input end of the phase discriminator sub-module and an input end of the frequency divider sub-module, the control code signal is input into a second input end of the delay line sub-module, a feedback output end of the delay line sub-module is electrically connected with the second input end of the phase discriminator sub-module, an output end of the phase discriminator sub-module is electrically connected with a first input end of the accumulator sub-module, an output end of the frequency divider sub-module is electrically connected with a second input end of the accumulator sub-module, an output end of the accumulator sub-module is electrically connected with an input end of the conversion sub-module, and an output end of the conversion sub-module is electrically connected with a third input end of the delay line sub-module;
the delay clock output end of the delay line submodule outputs the multiphase clock signal;
the delay line submodule is used for forming a delay line, generating time delay and outputting the multiphase clock signals;
the phase discriminator submodule is used for comparing the phase difference between the reference clock signal and the feedback signal output by the delay line and quantizing the phase difference into a digital output signal;
the accumulator submodule is used for accumulating output signals of the phase discriminator submodule;
the frequency divider submodule is used for dividing the reference clock signal and then taking the divided reference clock signal as a clock signal of the accumulator submodule;
the conversion submodule is used for converting an input signal into a thermometer code analog signal so as to adjust the delay time.
2. The programmable multi-phase clock device of claim 1, wherein a phase difference between two adjacent delay units is the preset phase difference;
the time sequence control module is used for controlling the multiplexing module to output the multiphase clock signals output by the selected adjacent two delay units to the phase interpolator according to the frequency division ratio.
3. The programmable multi-phase clock device of claim 1, wherein the timing control module is configured to obtain the frequency division ratio according to the delay selection signal, and to send high bits of the integer portion and the fractional portion of the frequency division ratio to the multiplexing module, respectively, and low bits of the fractional portion of the frequency division ratio to the phase interpolator.
4. A programmable multi-phase clock apparatus as recited in claim 3 wherein the multiplexing module is configured to select two adjacent phases of the multi-phase clock signals from the multi-phase clock signals provided by the multi-phase delay line module based on the upper bits of the integer portion and the fractional portion and output the two adjacent phases of the multi-phase clock signals to the phase interpolator.
5. The programmable multi-phase clock apparatus of claim 4, wherein the phase interpolator is to divide the multi-phase delay clock based on the two adjacent phase multi-phase clock signals and the fractional portion of the low-order output.
6. The programmable multi-phase clock device of claim 1, wherein the delay line submodule comprises a delay line formed by sequentially connecting the delay units in series through a delay line input end and a delay line output end;
the delay line input end of the last delay unit on the delay line is used as the first input end of the delay line submodule to receive the reference clock signal, and the delay line output end of the last delay unit on the delay line is used as the feedback output end of the delay line submodule to send the feedback signal;
each of the delay units also receives the control code signal and the thermometer code analog signal; wherein the control code signal is used for roughly adjusting the delay time, and the thermometer code analog signal is used for finely adjusting the delay time;
each delay unit also has a clock output interface to output the multi-phase clock signal.
7. The programmable multi-phase clock device of claim 6, wherein each of the delay cells further comprises: the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube, the first inverter, the second inverter, the third inverter, the fourth inverter and the first capacitor;
the first end of the first capacitor in each delay sheet is used as the first end of the delay sheet, the second end of the first capacitor is electrically connected with the drain electrode of the second NMOS tube, the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube is connected with a control code signal;
the delay units are connected in parallel to form a delay slice group, and each delay unit is provided with a first delay slice group, a second delay slice group, a third delay slice group and a fourth delay slice group;
taking the grid electrode of the first PMOS tube as the input end of the delay line and the drain electrode of the third PMOS tube as the output end of the delay line;
the grid electrode of the first PMOS tube is also electrically connected with the grid electrode of the first NMOS tube, the source electrode of the first NMOS tube is grounded, the source electrode of the first PMOS tube is connected with a power supply voltage, and the drain electrode of the first PMOS tube is electrically connected with the drain electrode of the first NMOS tube and the input end of the first inverter respectively;
the output end of the first inverter is respectively and electrically connected with the first end of the delay chip in the first delay chip set and the input end of the second inverter, the output end of the second inverter is respectively and electrically connected with the first end of the delay chip in the second delay chip set and the input end of the third inverter, the output end of the third inverter is respectively and electrically connected with the first end of the delay chip in the third delay chip set and the input end of the fourth inverter, the output end of the fourth inverter is respectively and electrically connected with the first end of the delay chip in the fourth delay chip set, the grid electrode of the third PMOS tube and the grid electrode of the third NMOS tube, the grounding ends of the first inverter, the second inverter, the third inverter and the fourth inverter are all grounded, the output ends of the first inverter, the second inverter and the fourth inverter are respectively and electrically connected with the second end of the delay chip in the third delay chip set and the fourth inverter, the grid electrode of the PMOS tube is electrically connected with the second drain electrode of the PMOS tube, and the drain electrode of the PMOS tube is electrically connected with the analog voltage meter;
the source electrode of the third NMOS tube is grounded, the source electrode of the third PMOS tube is connected with the power supply voltage, the drain electrode of the third PMOS tube is also electrically connected with the drain electrode of the third NMOS tube, the grid electrode of the fourth PMOS tube and the grid electrode of the fourth NMOS tube respectively, the source electrode of the fourth NMOS tube is grounded, the source electrode of the fourth PMOS tube is connected with the power supply voltage, the drain electrode of the fourth PMOS tube is electrically connected with the drain electrode of the fourth NMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the fifth NMOS tube respectively, the source electrode of the fifth NMOS tube is grounded, the source electrode of the fifth PMOS tube is connected with the power supply voltage, and the drain electrode of the fifth PMOS tube is electrically connected with the drain electrode of the fifth NMOS tube;
and taking the drain electrode of the fifth PMOS tube as the clock output interface.
8. The programmable multi-phase clock apparatus of claim 1, wherein the output of the phase detector sub-module is 0 when the first input signal of the phase detector sub-module leads the second input signal;
the output of the phase detector sub-module is 1 when the second input signal of the phase detector sub-module leads the first input signal.
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| JPH09275569A (en) * | 1996-04-05 | 1997-10-21 | Sony Corp | Analog delay circuit |
| JP2003087113A (en) * | 2001-09-10 | 2003-03-20 | Nec Corp | Method for controlling clock, frequency divider circuit and pll circuit |
| CN106209093A (en) * | 2016-03-02 | 2016-12-07 | 北京大学 | A kind of digital fractional frequency-division phase-locked loop structure |
| CN114421967A (en) * | 2022-01-24 | 2022-04-29 | 高澈科技(上海)有限公司 | Phase interpolation circuit, phase-locked loop, chip and electronic device |
| CN116131845A (en) * | 2022-12-08 | 2023-05-16 | 晶晨半导体(上海)股份有限公司 | Clock signal noise reduction device, noise reduction method and multi-phase delay phase-locked loop |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09275569A (en) * | 1996-04-05 | 1997-10-21 | Sony Corp | Analog delay circuit |
| JP2003087113A (en) * | 2001-09-10 | 2003-03-20 | Nec Corp | Method for controlling clock, frequency divider circuit and pll circuit |
| CN106209093A (en) * | 2016-03-02 | 2016-12-07 | 北京大学 | A kind of digital fractional frequency-division phase-locked loop structure |
| CN114421967A (en) * | 2022-01-24 | 2022-04-29 | 高澈科技(上海)有限公司 | Phase interpolation circuit, phase-locked loop, chip and electronic device |
| CN116131845A (en) * | 2022-12-08 | 2023-05-16 | 晶晨半导体(上海)股份有限公司 | Clock signal noise reduction device, noise reduction method and multi-phase delay phase-locked loop |
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