JP2003218695A - D/a converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a D/A converter which has a small circuit scale and can reduce mixing of noise from a digital circuit to an analog circuit. <P>SOLUTION: The present invention comprises a digital filter, a noise shaper, and an analog filter 13. The analog filter 13 comprises capacitor sets 14a and 14b and an analog adder 15. Capacitors C1A and C1B of the capacitor set 14a and capacitors C2A and C2B of the capacitor set 14b are sequentially charged according to a 3rd digital signal outputted from the noise shaper, and electric charges which are accumulated and held are sequentially selected and supplied to the analog adder 15. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A converter for converting a digital signal into an analog signal, and more particularly to a D / A converter having an analog filter composed of a capacitor and an analog adder. is there.

[0002]

2. Description of the Related Art Generally, the output stage of a D / A converter is
An analog filter is used to remove high-frequency components of noise-shaped noise. For example, SI having a zero point at a frequency half the sampling frequency
An analog filter featuring an NC function-like input limiting effect can be mentioned. In order to form such a filter, the digital signal output from the noise shaper may be delayed at a constant cycle, and a signal obtained by adding the signal before delay and the signal after delay may be output.

For example, Japanese Laid-Open Patent Publication No. 11-355101 discloses an analog filter as shown in FIG. This analog filter includes a D / A converter 55 that converts a digital signal corresponding to the filter characteristics into an analog signal, a sample hold circuit 51 that holds the analog signal, and a shift register that holds and delays the input digital signal. 54, and a product-sum calculation means of the input digital signal and the analog signal held in the sample hold circuit 51, that is, a multiplier 52 and an adder 53.

The multiplier 52 multiplies the digital signal held by the shift register 54 by the analog signal held by the sample hold circuit 51. This multiplier 52
The result of multiplication is added by the adder 53, and the filtered analog signal is output from the adder 53.

[0005]

However, the sample-hold circuit 51 and the multiplier 52 of this analog filter are provided.
Are each configured to include an operational amplifier, and the same number of sample-hold circuits 5 as the number of bits of the digital signal.
Since 1 and the multiplier 52 are required respectively, the circuit scale tends to increase.

Further, since the shift register 54 for shifting the input digital signal, that is, the delay element by the digital circuit is required, a large pulse-shaped operation current is generated at the operation timing of the digital signal, which causes noise. Becomes mixed in with the analog signal. Since this noise has a signal-dependent component, in a D / A converter that handles two or more channels, crosstalk easily occurs between the channels.

In view of the above points, an object of the present invention is to provide a D / A converter capable of reducing the circuit scale and reducing the mixing of noise from a digital circuit into an analog circuit. A further object of the present invention is to provide a D / A converter that can reduce the occurrence of crosstalk between the channels when handling two or more channels.

[0008]

In order to solve the above problems and achieve the object of the present invention, the inventions described in claims 1 and 2 are configured as follows. That is, the invention according to claim 1 is a digital filter that inputs a first digital signal and outputs a second digital signal that is oversampled; and noise shaping that inputs the second digital signal. In a D / A converter including a noise shaper that outputs a third digital signal and an analog filter that filters the third digital signal, the analog filter includes a plurality of capacitor sets each including a plurality of capacitors. And an analog adder, wherein the plurality of capacitor sets are configured to sequentially charge each capacitor of the respective capacitor sets based on the third digital signal, and the analog adder includes: Configured to selectively add the charge held in each capacitor of multiple capacitor sets It is an octopus and features.

According to a second aspect of the present invention, in the D / A converter according to the first aspect, the plurality of capacitor sets include a first capacitor set including a first capacitor and a second capacitor, And a second capacitor set including a third capacitor and a fourth capacitor, wherein the charging of the first and second capacitors and the charging of the third and fourth capacitors are alternately repeated, and
Electric charges charged in the first and fourth capacitors,
It is characterized in that the charges charged in the second and third capacitors are alternately supplied to the analog adder.

As described above, according to the present invention, the analog signal based on the third digital signal is sequentially stored for each capacitor set, and the analog signals stored in each capacitor of the capacitor set are deviated in time. By selecting the signals and inputting them to the analog adder at the same time, it is possible to obtain an output obtained by delaying and adding the signals.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a D / A converter of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment of a D / A converter of the present invention. As shown in FIG. 1, the D / A converter according to this embodiment includes a digital filter 11 that inputs a first digital signal and outputs an oversampled second digital signal, and a second digital filter 11 thereof. A noise shaper 12 that inputs a signal and outputs a noise-shaped third digital signal, and an analog filter 13 that inputs the third digital signal and outputs a filtered analog signal are provided.

The analog filter 13 sequentially selects a plurality of capacitor sets 14 composed of a plurality of capacitors that are charged with electric charge based on a third digital signal, and the electric charges held in each capacitor of the capacitor set 14. It is composed of an analog adder 15 that performs addition.
Next, an example of a specific configuration of the analog filter 13 will be described with reference to FIG.

As shown in FIG. 2, the analog filter 13 comprises two capacitor sets 14a and 14b and an analog adder 15. Capacitor set 14a
Is a set of two capacitors C1A and C1B,
Changeover switch SD whose contact is switched according to the third digital signal output from the noise shaper 12.
1, SD2, and switches S1a to S1d, S3a, and S4a that are turned on / off by a non-overlap clock.

The change-over switches SD1 and SD2 select the first reference voltage (+ VREF) or the second reference voltage (-VREF) based on the third digital signal output from the noise shaper 12, and this selection is made. The reference voltage is supplied to the capacitors C1A and C1B. Further, by turning on the switches S1a to S1d, the capacitors C1A and C1B are charged at the same time, and by turning on the switches S3a and S4a at different timings, the respective charges of the capacitors C1A and C1B are turned on at different timings. It is adapted to be supplied to 15 operational amplifiers OP1.

The capacitor set 14b includes two capacitors C2A and C2B, which are a set, and a noise shaper 1.
Changeover switches SD3 and SD4 whose contacts are switched in accordance with a third digital signal output from S2 and a switch S2a which is turned on / off by a non-overlap clock.
~ S2d, S3b, S4b. The changeover switches SD3 and SD4 select the first reference voltage (+ VREF) or the second reference voltage (-VREF) based on the third digital signal output from the noise shaper 12, and select the selected reference voltage. Capacitor C2A,
It is designed to be supplied to C2B.

Further, by turning on the switches S2a to S2d, the capacitors C2A and C2B are charged at the same time, and by turning on the switches S3b and S4b at different timings, the charges charged in the capacitors C2A and C2B are changed at different timings. It is adapted to be supplied to the operational amplifier OP1 of the analog adder 15. The analog adder 15 has an operational amplifier OP1 as shown in FIG.
The capacitor C3 and the switches S3c and S4c that are turned on / off by the non-overlap clock integrate and hold the analog signals output from the two capacitor sets 14a and 14b. The analog adder 15 has a capacitor C4 and a switch S.
Since the resistance element composed of 5a, S5b, S6a, and S6b is connected in parallel to the capacitor C3, it has a function as a low-pass filter.

Next, an example of the operation of the analog filter 13 having such a configuration will be described with reference to FIGS. Here, FIG. 3 shows a reference clock as a reference of the operation of the analog filter 13 and a noise shaper 12.
3 shows the relationship between the third digital signal output from the device and the operating states of the capacitors C1A, C1B, C2A, and C2B shown in FIG.

Further, FIG. 4 shows the reference clock, the third digital signal, and the switches S1a to S shown in FIG.
The timings (waveform examples) of non-overlap clocks (hereinafter referred to as clocks) CK1 to CK6 for turning on and off 1d and the like are shown. While the clocks CK1 to CK6 are at “H” level, the switches S1a to S1d are turned on,
The "L" level period is turned off.

The switches S1a to S1d are CK1,
The switches S2a to S2d are the clock CK2 and the switch S.
3a to S3c are clocks CK3 and switches S4a to S4.
c is a clock CK4, switches S5a and S5b are a clock CK5, and switches S6a and S6b are a clock CK6. As shown in FIG. 3, the analog filter 13 outputs the third digital signal from the noise shaper 12 at the falling cycle of the reference clock.

First, in the cycle T1, the changeover switches SD1 to SD4 select the first reference potential (+ VREF) or the second reference potential (-VREF) according to the third digital signal D1. Further, in the period in which the reference clock is at the “L” level in the cycle T1, the clock CK1
Becomes "H" level, the switches S1a to S1d are turned on, and the capacitors C1A and C1 of the capacitor set 14a are turned on.
B is charged.

Next, in the cycle T1, when the reference clock is switched from the "L" level to the "H" level, the clock CK1 becomes the "L" level and the switches S1a to S1d.
Is turned off, the clock CK3 becomes "H" level, and the switches S3a to S3c are turned on. Therefore, the charges charged and held in the capacitor C1A are supplied to the operational amplifier OP1 of the analog adder 15.

Similarly, in the cycle T2, the change-over switches SD1 to SD4 have the first reference potential (+ VREF) or the second reference potential (-VREF) according to the third digital signal D2.
VREF). Further, during the period in which the reference clock is at the “L” level in the cycle T2, the clock CK2 becomes the “H” level and the switches S2a to S2d are turned on,
The capacitors C2A and C2B of the capacitor set 14b are charged with electric charges.

Next, in the cycle T2, when the reference clock is switched from the "L" level to the "H" level, the clock CK2 becomes the "L" level and the switches S2a to S2d.
Is turned off, the clock CK4 becomes "H" level, and the switches S4a to S4c are turned on. Therefore, the electric charge charged and held in the capacitor C2A is supplied to the operational amplifier OP1 of the analog adder 15. At this time, the electric charge charged in the capacitor C1B in the cycle T1 is also supplied to the operational amplifier OP1 of the analog adder 15.

Therefore, the reference clock of the cycle T2 is "H".
In the level period, the charge charged and held in the capacitor C1B based on the third digital signal D1 in the cycle T1 and the charge charged and held in the capacitor C2A based on the third digital signal D2 in the cycle T2. Are simultaneously input to the analog adder 15. further,
In the cycle T3, the changeover switches SD1 to SD4 change the first reference potential (+ VR) according to the third digital signal D3.
EF) or the second reference potential (-VREF). Further, during the period in which the reference clock is at the “L” level in the cycle T3, the clock CK1 becomes the “H” level, the switches S1a to S1d are turned on, and the capacitor set 14
The capacitors C1A and C1B of a are charged with electric charges.

Next, in the cycle T3, when the reference clock is switched from the "L" level to the "H" level, the clock CK1 becomes the "L" level and the switches S1a to S1d.
Is turned off, the clock CK3 becomes "H" level, and the switches S3a to S3c are turned on. Therefore, the charges charged and held in the capacitor C1A are supplied to the operational amplifier OP1 of the analog adder 15. At this time, the electric charge charged in the capacitor C2B in the cycle T2 is also supplied to the operational amplifier OP1 of the analog adder 15.

Therefore, the reference clock of the cycle T3 is "H".
In the level period, the charge charged and held in the capacitor C2B based on the third digital signal D2 in the cycle T2 and the charge charged and held in the capacitor C1A based on the third digital signal D3 in the cycle T3. ,
It is input to the analog adder 15 at the same time. Also, the period T
In 1 to T3, while the reference clock is at the "L" level, the clock CK6 is at the "H" level and the switches S6a and S6b of the analog adder 15 are turned on and the reference clock is at the "H" level. During the period, the clock CK5 becomes “H” level, and the switches S5a and S5b of the analog adder 15 are turned on.

The charges supplied to the analog adder 15 in this way are integrated by the capacitor C3, which is an integrating capacitor, and the reference clock is held during the "L" level period. Further, since the analog filter 13 is a low-pass filter, the analog adder 15 outputs a filtered analog signal. As can be seen from the above, the above capacitor sets 14a and 14b
In the analog filter 13 having, by repeating the above series of operations, the half of the sampling frequency is obtained.
It is possible to form an analog filter having a SINC function-like input limiting effect having a zero point at the frequency of. That is, since the D / A converter using this analog filter can add signals without using the delay element of the digital circuit, the high frequency component of the noise-shaped noise can be removed.

The analog adder 15 shown in FIG.
Is the integrating capacitor C3 of the integrating circuit in the above embodiment.
A resistance element was installed in parallel with to form a low-pass filter.
For example, a simple integrating circuit may be used, or all capacitors to be added may be connected in parallel. Further, the capacitor sets 14a and 14b shown in FIG. 2 can be made into two or more capacitor sets in which two or more capacitors are one set. In this case, it is preferable that the number of capacitor sets and the number of capacitors in the capacitor sets are the same because the above series of operations can be easily performed. Moreover, since the capacitance value of each capacitor can be arbitrarily selected, the transfer function of the analog filter can be set to a desired value.

Furthermore, the capacitor sets 14a, 14b
It is preferable to use all of the third digital signals D1, D2, D3, ... As shown in FIG. However, the charge of the capacitor may be performed by using a part of the third digital signals D1, D2, D3 ... Similarly, it is preferable that the charges charged in the capacitors of the capacitor sets 14a and 14b be supplied to the analog adder 15 in a continuous cycle as shown in FIG. However, it is not always necessary to supply the charges to the analog adder 15 in a continuous cycle.

[0030]

As described above, according to the configuration of the present invention, the circuit scale can be reduced. Further, according to the present invention, signals which are temporally shifted are added without using a delay element composed of a digital circuit, and a high frequency component of noise-shaped noise is removed. For this reason,
It is possible to reduce the mixing of noise from the digital circuit to the analog circuit, and further to reduce the occurrence of crosstalk between channels when handling two or more channels.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a D / A converter of the present invention.

FIG. 2 is a diagram showing the configuration of an embodiment of an analog filter used in the D / A converter of the present invention.

FIG. 3 is a diagram showing a relationship between operating states of respective capacitors in the analog filter shown in FIG.

4 is a timing diagram of a non-overlap clock for turning on / off each switch in the analog filter shown in FIG.

FIG. 5 is a diagram of a conventional analog filter.

[Explanation of symbols]

11 Digital Filter 12 Noise Shaper 13 Analog Filter 14, 14a, 14b Capacitor Set 15 Analog Adders S1a to S1d, S2a to S2d Switches S3a to S3c, S4a to S4c Switches S5a, S5b, S6a, S6b Switches SD1 to SD4 Change Switch C1A , C1B, C2A, C2B, C3, C4 Capacitor OP1 Operational amplifier

Claims (2)

[Claims] 1. A digital filter which inputs a first digital signal and outputs a second digital signal which is oversampled, and a third digital signal which is noise-shaped by inputting the second digital signal. In a D / A converter having an output noise shaper and an analog filter for filtering the third digital signal, the analog filter includes a plurality of capacitor sets each including a plurality of capacitors, and an analog adder. The plurality of capacitor sets are configured to sequentially charge each capacitor of the respective capacitor sets based on the third digital signal, and the analog adder is configured to charge each of the plurality of capacitor sets. D configured to selectively add charges held in a capacitor / A converter. 2. The plurality of capacitor sets includes a first capacitor set including a first capacitor and a second capacitor, and a second capacitor set including a third capacitor and a fourth capacitor. Charging the first and second capacitors and the charging of the third and fourth capacitors alternately, and charging the first and fourth capacitors,
The D / A converter according to claim 1, wherein the charges charged in the second and third capacitors are alternately supplied to the analog adder.