JP2003317026A - Signed product sum computing element and analog matched filter including the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signed product sum computing element using a capacitor and an analog matched filter which includes it. <P>SOLUTION: Provided are the signed product sum computing element, including the capacitor 326 holding a voltage for an input signal, switches connected to both the ends of the capacitors 326 respectively and operable with the signal clock to switch the capacitor polarities, and a power source 329 connected to both the ends of the capacitor 326 through one of the switches, and the analog matched filter including the same. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a portable mobile terminal, wireless LAN, Bluetooth or GPS.
DS-SS (direct sequence spread spectrum) or DS-CDMA (direct spread code division) used in systems etc.
multiple access: Also called W (wideband) -CDMA. ) Method, particularly, a matched filter (hereinafter, referred to as a matched filter) applied to an LSI for a mobile mobile terminal,
Call it "MF". ) Concerning.

[0002]

2. Description of the Related Art At present, since the number of users of mobile phones is rapidly increasing, the adoption of the DS-CDMA system (direct spread system CDMA) in mobile mobile terminals is progressing. DS-CD
In the MA method, a modulated digital signal obtained after analog / digital conversion (A / D conversion) is spread using a digital signal called a spread code (or PN code) to spread the power density distribution of the signal. . The band of the spread signal is wider than that of the frequency division multiple access (FDMA) system or the time division multiple access (TDMA) system, so that multiple people do not interfere even if they use the same frequency band. be able to. When the spread spectrum signal is received and demodulated, the original digital signal is demodulated by performing despreading using the same spreading code as the above spreading code. That is, the spreading code is used as a key on the transmitting side and the receiving side to perform spreading at the time of transmission and despreading at the time of reception. Therefore, in such a DS-CDMA system, M is used to acquire synchronization between the received signal and the spreading code.
Requires F. Therefore, at present, analog, CC
Various calculation methods such as D (charge coupled device), SAW (surface acoustic wave), or digital are used for MF.

Generally, in the DS-CDMA system, it is necessary to receive a signal which has been spread spectrum as described above and to perform a correlation calculation between the received signal and a spread code in order to demodulate the signal. . The basic arithmetic expression is f (t) =
Σ a (i) r (ti). Where a (i) is the spreading code and r (t) is the received signal. The sum is i = 1 to i
= N, where n represents the number of taps. The above equation has a peak value only when the timings of the spread code and the received signal match. The receiver utilizes this property to maintain the reception timing and demodulate the received signal.

Conventionally, a digital matched filter (hereinafter referred to as "DMF") using a digital method has been proposed. This structure is shown in FIGS.

In the case of the data cyclic type shown in FIG.
While sequentially storing the received signal in the shift register (for the received signal), the correlation calculation with the spread code (PN code) set in each tap is performed and output. This is because the number of taps is equal to the code length of the spreading code.
lse response: Hereinafter referred to as "FIR". ) This is the most direct and general configuration called a filter. But,
In the case of FIG. 8, all the shift registers for the reception signal operate every time the reception signal is sampled, so that the power consumption increases. In addition, power consumption and chip area increase as the number of quantization bits of the input signal increases.

Further, in the case of the code cyclic type shown in FIG. 9, a spread signal (PN code) for a spread code (PN code) is used without using a received signal shift register for storing the received signal used in the data cyclic type. The spread code is stored in the shift register for circulation. By adopting such a method that the received signal is distributed to each register for each sampling, the power consumption of the received signal register can be reduced. However, although the power consumption of the DMF alone is reduced in the case of FIG. 9, in addition to the MF, a high-speed and high-accuracy analog-digital converter (hereinafter, referred to as “ADC”) for quantizing the received signal with high accuracy Called). Therefore, the ADC consumes most of the power consumption and the chip area.

From such a background, an analog type MF has been proposed instead of the digital type. The analog MF and the digital MF have almost the same configuration, but the analog MF does not require an ADC. In the analog MF, a sample and hold (sample and hold) is used instead of the register for the received signal.
ld: Hereinafter referred to as "S / H". ) A low power consumption is achieved because a circuit is used. Such an analog type M
In F, in the data cyclic MF, it is difficult to increase the number of taps because an error accumulates for each transfer. On the other hand, the analog code cyclic MF is advantageous in that no error occurs due to transfer. An example of a product-sum calculator used in such an analog code cyclic MF is a product-sum calculator disclosed in Japanese Patent Laid-Open No. 10-124606.

[0008]

However, in the product-sum calculator described in Japanese Patent Laid-Open No. 10-124606, the sum calculation and the product calculation are performed separately, and the spread code is +.
Only the side can handle it. Furthermore, since there is a demand for higher speed and more taps for the MF in the future, it is expected that the power consumption and the chip area of the MF will further increase in the future.

[0009]

The present invention provides a product-sum calculator using capacitors and a low power consumption analog MF (analog matched filter: hereinafter referred to as "AMF") using the same. Specifically, a capacitor that holds a voltage for an input signal and both ends of the capacitor are connected to each other, operate according to a signal clock, have at least three terminals, and two terminals among them have a voltage corresponding to the signal clock. A signed sum-of-products arithmetic unit including a switch that performs a switching operation and a power supply connected to both ends of a capacitor via one of the switches.

Further, a capacitor for holding a voltage for an input signal, a switch connected in parallel to each of two ends of the capacitor, and operated by a signal clock, and both ends of the capacitor via two of the switches. A power supply connected to the capacitor, the switch operates in response to the signal clock to generate a first state and a second state, and in the first state, is connected to the capacitor and the power supply. Of the switches that are turned on, only one of them is turned on, and the remaining switch is connected to the capacitor, and is connected to the end opposite to the capacitor with respect to the turned-on switch. Only the switch is turned on to output the sum of the positive voltage of the capacitor and the voltage of the power supply, and in the second state, the switch connected to the capacitor and the power supply. Of the remaining switches connected to the capacitor that are turned on in the first state and are on the opposite side to the switch turned on in the second state. There is provided a signed sum-of-products arithmetic unit characterized by outputting only the sum of the negative voltage of the capacitor and the voltage of the power source by turning on only the switch connected to the end of the capacitor.

Here, at least one of the switches is a field effect transistor, and a mode further including a sample hold stage for supplying a voltage to a capacitor in response to a signal from a sampling clock generator. Is preferred. The present invention also provides an analog matched filter including a sampling clock generator that supplies a signal clock and a plurality of product-sum calculators of any one of the above aspects. Where at least 1
The capacitor capacity of the two multiply-accumulators or the voltage of the power supply is
An aspect characterized in that the capacitor capacity or the power supply voltage is different from that of any one of the other product-sum calculators is preferable. Further, the signed product-sum operation circuit of the present invention is an A / D
Filter and FIR filter (finite impulse response
filter) can also be used. As described above, the product-sum calculation circuit of the present invention switches the polarity of the capacitor by the switch and inverts it, so that the product-sum calculation of the positive polarity (+ side) and the negative polarity (− side) can be performed simultaneously.

Here, as a switch for switching the polarity of the capacitor, which is respectively connected to both ends of the above-mentioned capacitor, a switch such as CMOS which has low power consumption, high operation speed and easy miniaturization is used. It is preferable. Also, the switches connected to both ends of such a capacitor are, for example, two switches connected in parallel which are turned on or off according to a signal clock, or have at least three terminals. , A three-terminal switch whose two terminals are alternately switched according to a signal clock.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an outline of an analog matched filter (AMF) 1 according to the present invention. The AMF 1 according to the present invention receives a code shift register and sampling clock generator 2, a sampling clock generator 2 and an analog signal, and receives the sampling clock generator 2.
A plurality of tap units 3 for outputting analog signals in accordance with the signals from The code shift register stores the spread code, and the sampling clock generator 2
Applies a signal clock (hereinafter referred to as “sclk”) to each of the plurality of tap units 3 at different timings. Here, a timing chart of sclk1 to sclk15 given to each of the 15 tap units 3 is shown in FIG. 2 together with a signal clock φ ₀ described later. This signal clock φ ₀ is used to operate the switching so as to take in the respective analog output of each tap unit 3.

Next, FIG. 3 shows the structure of one tap of the above-mentioned tap portion 3. The tap unit 3 holds a sample and hold (hereinafter, referred to as “S
/ H ”) stage 30, and a sum of products (weighted-s) that simultaneously realizes a weighted operation and a signed operation using a diffusion coefficient.
um operation stage) stage 32. S
The / H stage 30 receives the input analog signal and is connected to the switch 300 and the sampling clock generator 2 using a CMOS-based switch 300 that performs a switching operation by the sclk from the sampling clock generator 2, and connects the sclk to Inverting inverter 3
01 and a capacitor 302 (C _hold = 0.36) that receives the charge of the input analog signal and holds the voltage V _in.
pF) and the source follower buffer (303, 304) using the FET connected to the capacitor 302, the output load (without being affected by the V _sf terminal,
V _sf , which is a constant voltage offset from V _in, is output.

The S / H stage of FIG. 3 samples the analog input once every 15 clocks by the sclk shown in FIG. 2 and holds the voltage V _in in the capacitor 302. In the present embodiment, when the voltage of the input signal to each switch was _{V dd (= 3.3V), 300mV} pp (3 about the V _dd /2(=1.65V)
Since the peak-to-peak voltage or signal strength width is 00 mV, the sampling switch is set to 25 MSPS (me
Sufficient gate voltage is secured to operate at ga samples per second).

Further, referring to FIG. 3, the sum of products operator 32
Is a switch 320 using a CMOS that operates by receiving the signal clock φ ₀ from the sampling clock generator 2 and the signal clock inverted by the inverter 323.
, A capacitor 326 that selectively receives and holds the voltage V _sf held in the capacitor 302 of the S / H stage by the switch 320, and two capacitors 326 that are connected in parallel to both ends of the capacitor 326 respectively. Switches 321 and 322 using CMOSs, switches 327 and 328 using FETs, and switches 3 operating with signal clocks φ ₁ , φ ₃ and φ _{4 from}
Inverters 324 and 325 connected to 21 and 322, respectively, for inverting the signal clocks φ ₄ and φ ₃ from the sampling clock generator 2, and the capacitor 3
26 (C _p = 0.08 pF), and a power supply 329 (V _off ) connected to switches 327 and 328, respectively connected to both ends. Here, the switches 321, 322, 327, 3 of the product-sum operation stage 32
CMOS or FET is used as 28. However, these switches are not limited to the above-described embodiments, and may include MOS transistors such as PMOS and NMOS, for example.

A switch 321 of the product-sum operation stage 32,
322 performs a switching operation according to three states generated by the signal clocks φ1, φ3, and φ4 from the sampling clock generator. As a result, a weighting calculation is performed on the voltage V _sf -V _off held in the capacitor 326 (in the present embodiment, the power supply 3 in each tap is used).
The offset voltage of 29, the capacitance of the capacitor 326, etc.) and the signed operation (corresponding to multiplying by +1 or -1 in this embodiment) are performed at the same time.
Therefore, the analog output that has been weighted and signed with respect to the input analog signal
There is a feature that you can get it without.

The signal clocks φ ₀ , φ ₁ , φ ₃ , and φ ₄ generated from the sampling clock generator 2 will be described with reference to the timing chart shown in FIG. here,
The following three states are generated by combining ON and OFF of φ ₀ , φ ₁ , φ ₃ , and φ ₄ , respectively. That is, a first state in which φ ₀ and φ ₁ are on and φ ₃ and φ ₄ are off (shown as in FIGS. 4 and 5), and φ ₁ and φ ₄ are on and φ ₀ and φ ₃ Is off (shown as in FIGS. 4 and 5) and a _{third state in} which φ ₃ is on and φ ₀ , φ ₁ and φ ₄ are off (in FIGS. 4 and 5). As shown) and.

Next, in the product-sum operation stage 32, the key
Voltage V held by capacitor 326 _{science fiction}-V_offAgainst
For operations that perform both weighted calculation and signed calculation at the same time,
The three states shown in FIG. 4 will be described separately. here
Corresponds to the first state, the second state, and the third state diagram.
The state of the product-sum calculation stage 32 is as shown in FIG.
Are shown respectively.

First, the first state in which φ ₀ and φ ₁ are on and φ ₃ and φ ₄ are off (that is, the state shown by in FIG. 5) will be described. In the first state, the switches 320 and 328 are turned on, so that the voltage V _sf supplied from the S / H stage 30 to the product sum operation stage 32 is held in the capacitor 326 via the switch 320. Next, the second state in which φ ₁ and φ ₄ are on and φ ₀ and φ ₃ are off (that is, the state shown by in FIG. 5) will be described. In the second state, the switch 320 is off and the switch 321 is on. As a result, when the PN code stored in the code shift register is 1 (corresponding to “pn () = 1” in FIG. 5), +1 by the PN code is obtained in each product-sum operation stage 32. The sum of the voltage of the power source 329 and the positive voltage as a result of multiplying the convenience and the capacitor voltage is calculated, and the analog voltage is output.

Next, the _{third state in} which φ ₃ is on and φ ₀ , φ ₁ and φ ₄ are off (state shown by in FIG. 5) will be described. In the third state, where the PN code is -1,
The switch 320 is turned off and the switches 322, 327
Turns on. As a result, the voltage V _sf -V _off supplied from the S / H stage 30 to the capacitor 326 of the product-sum operation stage 32 is inverted, and the sum is obtained with the voltage of the power supply 329 which is a weighting voltage. That is, the voltage V _sf −
An analog voltage corresponding to the difference between V _off and the power supply voltage is output. Even in this case, the weighting operation and the signed operation are performed at the same time as in the sum operation described in the first state.

In this way, when outputting the analog voltage obtained by summing the sums or differences of the taps, sclk1 to sclk15 from the sampling clock generator 2 are output.
And a positive or negative analog voltage according to the states of the signal clocks φ ₁ , φ ₃ , and φ ₄ , tap 1 to tap 1
It is understood that it is sufficient to output from 5 and take the total of those analog voltages.

When the signal clock φ ₀ is received, the product-sum operation stage 32 of each tap is returned to the first state in which the voltage V _sf -V _off held in the capacitor 326 is held.

In this embodiment, since the offset voltage of each power source 329 and the capacitance of the capacitors 302 and 326 in the taps 1 to 15 are equal, the analog outputs of the taps 1 to 15 are given the same weight. Will be there.

Here, the "weighting calculation" generally means multiplying the voltage output from each tap by a coefficient such as 0.1 or 3.0 according to the capacitor capacitance of each tap. . In the case of this embodiment, since the capacitances of the capacitors 302 and 326 and the voltage of the power supply 329 in each tap are all equal, it corresponds to multiplying the output of the analog voltage from each tap by 1 as a coefficient. However, such “weighting calculation” includes, for example, changing the voltage of the power source 329 and the capacitance of the capacitors 302 and 326 for each tap, and multiplying the analog voltage output for each tap by different coefficients. I'm out. Thus, it will be easily understood by those skilled in the art that the coefficient of the output of the analog voltage for each tap should not be limited to the coefficient of this embodiment.

The term "signed operation" generally means an operation in which positive and negative signs are added and the sum is calculated. In the case of the present embodiment, instead of multiplying the voltage stored in the capacitor 326 by -1 or +1, the direction in which the connection of the capacitor 326 is output is inverted to realize the above-mentioned signed operation. There is.

VLSI Design and Education Center: VLSI Design and Education Center, University of Tokyo
DEC) includes a code shift register and sampling clock generator 2, a S / H stage 30 and a multiply-accumulate operation stage 32 according to the present invention using a ROHM CMOS 0.35 μm poly 2-layer metal 3-layer process 15 An analog matched filter (AMF) including three taps 3 was prototyped. This A is shown in FIGS. 6A and 6B.
The schematic diagram of MF is shown. Here, in order to prevent the accumulation of errors, the AMF including the product-sum operation stage 32 according to the present invention.
Employs a code cyclic AMF. The chip size of the circuit part of the AMF using 15 taps including the product-sum operation stage 32 according to the present invention is about 0.2 mm.
^2, is expected to actually be about 1.6 mm ² even when the corresponding 128 taps when used.

In the above prototype, the circuit area is large because the capacitor, which is an important component, is designed by the capacitance between poly and metal due to the limitation of the design rule. However, by using the poly-poly capacitance instead of the poly-metal capacitance, the chip area can be significantly reduced as compared with the case of this embodiment. Furthermore, due to the reduction in wiring capacitance, further reduction in power consumption can be expected.

FIG. 7A shows the measurement result of the output waveform from the above-mentioned prototype AMF. A peak of the correlation value appears at a rate of once every 15 calculations, which shows that the function as the MF is realized. Table 1 shows the power supply voltage, the power consumption, the area, the number of taps, the chip rate, and the process of the prototype AMF including 15 taps of the product-sum operation stage 32 according to the present invention used for the calculation at this time. The result of simulating the output waveform of this AMF is shown in FIG. 7B. 1 at 25MHz operation
Since the peak of the correlation value (negative polarity) appears at a rate of once every five times, it can be seen that the function as the MF can be realized. Here, the correlation value is generally a value indicating the similarity of the waveforms of the functions, and is obtained by multiplying two target functions and integrating them over a certain section.

[Table 1]

In addition, the product-sum operation stage 32 of the present invention is
Table 2 shows the results of comparing the simulation results of the predicted chip area and power consumption characteristics of AMF with 28 taps with other mounting methods. From this, the AMF including 128 taps of the product-sum operation stage 32 of the present invention
Even when using the 0.35 μm process,
The power consumption is 30.2 mV (at 25 MHz and 3.3 V), and the area is about 1.6 mm ² . Therefore, it can be seen that the level is sufficient for mounting on the LSI for portable mobile terminals. Although it cannot be directly compared with the conventional DMF and AMF because the process and design rule used are different, the AMF including the product-sum operation stage 32 according to the present invention reduces the chip area and power consumption. It turns out to be effective.

[Table 2]

[0031]

As described above, the product-sum calculator according to the present invention can directly sample a received signal as an analog value. Therefore, it is possible to realize an AMF of a small area with low power consumption by using the product-sum calculation unit of the present invention without using a high-speed and highly accurate ADC.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing the overall configuration of an AMF of the present invention.

FIG. 2 is a signal scl that drives each S / H stage
It is a timing chart of k1-sclk15.

FIG. 3 is a schematic diagram showing components of an arithmetic circuit for one tap of the AMF of the present invention.

FIG. 4 is a timing chart showing timings of φ ₀ , φ ₁ , φ ₃ , and φ _{4 in} the product-sum operation stage.

5 is a simplified diagram of an arithmetic circuit including the S / H stage and the product-sum arithmetic stage of FIG. [Fig. 3] is a schematic diagram for explaining the operation of the arithmetic circuit when the portion of is a positive polarity (pn () = 1). Is a negative polarity part (pn ()
3 is a schematic diagram illustrating the operation of the arithmetic circuit of (= 0). FIG.

FIG. 6A is a schematic diagram of an AMF including 15 taps including a product-sum operation stage 32 of the present invention. B
4 is a partially enlarged view of a portion corresponding to the S / H stage 30 and the product-sum operation stage 32, which is indicated by a broken line portion of A and corresponds to one tap in FIG.

FIG. 7A is a schematic diagram showing a measurement result of an analog output of an AMF including 15 taps of the product sum operation stage 32 of the present invention. B is a schematic diagram showing the result of simulating the output waveform of the AMF when the product-sum operation stage 32 of the present invention is used for 128 taps actually used, based on the measurement result of A.

FIG. 8 is an operation block diagram of a data shift MF in a conventional DMF configuration.

FIG. 9 is an operation block diagram of a code shift MF in a conventional DMF configuration.

[Explanation of symbols]

1 analog matched filter (AMF) 2 code shift register and sampling clock generator 3 tap section 30 S / H stage 32 product-sum operation stage 300, 320, 321, 322, 327, 328 switch 302, 326 capacitor 303 source follower buffer Main follower device 304 Source follower buffer current source device 301, 323, 324, 325 Inverter

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Takashi Matsumoto             3-4-1 Okubo, Shinjuku-ku, Tokyo Waseda Univ.             Faculty of Science and Engineering Department of Electrical and Electronic Information Engineering F-term (reference) 5J023 CA01 CB13

Claims (8)

[Claims] 1. A capacitor (326) for holding a voltage for an input signal, a switch connected to both ends of the capacitor (326) and operated by a signal clock to switch the polarity of the capacitor (326), A signed sum-of-products arithmetic unit including a power supply (329) connected to both ends of the capacitor (326) through one of the switches. 2. The sum of products operation according to claim 1, wherein the switches are switches (321, 322, 327, 328) connected to both ends of the capacitor and operated by a signal clock. vessel. 3. The product-sum calculator according to claim 1, wherein the switch comprises a three-terminal switch connected to both ends of the capacitor. 4. A capacitor (326) for holding a voltage with respect to an input signal, and switches (321, 322, 327, 328) connected in parallel to each other at two ends of the capacitor (326) and operated by a signal clock. ), And a power supply (329) connected to both ends of the capacitor (326) through two of the switches (321, 322, 327, 328), depending on the signal clock. The switches (321, 322,
327, 328) to generate a first state and a second state, and in the first state, a switch (327) connected to the capacitor (326) and the power supply (329). ,
Of the remaining switches (321, 322) connected to the capacitor (326) by turning on only one of the switches (327) of the capacitors (328), the turned-on switch is the capacitor. Switch (321) connected to the opposite end of (326)
Only the power is turned on to output the sum of the positive voltage of the capacitor (326) and the voltage of the power supply (329), and in the second state, the capacitor (326) and the power supply (329) Switch connected to (327,
328), only the switch (328) that was off in the first state is turned on, and the capacitor (32)
6) the remaining switches (321, 32) connected to
2) in which the switch (328) turned on in the second state turns on only the switch (322) connected to the end opposite to the capacitor (326). A signed product-sum calculator (32) for outputting the sum of the negative voltage of the capacitor (326) and the voltage of the power supply (329). 5. The switches (321, 322, 32)
7. The product-sum calculator (32) according to any of claims 1 to 4, characterized in that at least one of 7, 328) is a field effect transistor. 6. The method according to claim 1, further comprising a sample and hold stage (30) for supplying a voltage to the capacitor (326) in response to a signal from the sampling clock generator 2. A product-sum calculator (32) according to any one of the above. 7. An analog matched filter (1) including a sampling clock generator (2) for supplying the signal clock and a plurality of product-sum calculators (32) according to any one of claims 1 to 6. . 8. At least one product-sum operator (3
8. The capacitance of the capacitor (326) or the voltage of the power supply (329) in 2) is a capacitor capacitance or a power supply voltage different from that of any one of the other product-sum calculators. Analog matched filter (1).