JP3784218B2 - Code division multiplexing communication device - Google Patents

Description

これに対して、この発明の実施の形態では、数Ｍと数Ｎとは任意に選択することが可能である。数Ｍと数Ｎを任意に決めたときに、電流転送の最大回数をＮ_{tr ans}とすると、
Ｎ_trans＝１入力多出力電流遅延フリップフロップＣＤＦＦｉ（ｉ＝１、２、…、Ｎ）による転送回数＋部分相関出力電流データ遅延回路ブロック部１０３による転送回数＝Ｎ＋（Ｍ−１）
で与えられる。
【０１２２】
相関器５の拡散チップ情報の配列個数Ｌが２５６個のとき

となり、数Ｎがチップ情報の配列個数Ｌの１／２乗のときに、転送回数が最小になる。直列に電流遅延フリップフロップを用いて遅延させたときの最大誤差の電流値が１２．６５×Ｉｉｎになるのに対して、Ｎ＝１６に設定した場合には、１．３８×Ｉｉｎ程度の電流値に抑えられるから、大幅に電流の転送誤差を抑えることができる。
【０１２３】
ここでは、拡散チップ情報の配列個数ＬをＬ＝２５６として説明を行ったが、例えば、Ｌ＝３２、６４、Ｌ＝１２８、Ｌ＞２５６であっても相関精度を向上させることができる。
【０１２４】
最大転送回数が最小となるＮは、Ｌの１／２乗に最も近い整数であり、そのときの転送回数は２×Ｌの１／２乗と見積もることができる。従って、チップ情報の配列個数が増えるに伴って、この発明の相関器５を用いることによって転送回数の低減、それに伴う転送誤差の累積の低減改善効果が著しくなる。
【０１２５】
この相関器５の回路構成による転送回数の低減は、部分相関出力電流遅延回路ブロック部１０３のＮチップ電流遅延回路Ｎｄｅｌａｙにおいて、ｎチップ分だけ部分相関電流を遅延させるときに、１回の部分相関電流の転送のみでｎ回転送遅延させたと同等の機能を与えることにより実現されている。
【０１２６】
ここでは、主要な電流源の数の見積もり比較を行う。
【０１２７】
電流遅延フリップフロップＣＤＦＦｉ１段当たりの構成では、電流サンプリングカレントミラーを二つ含んでいるから、
電流メモリＭＯＳトランジスタ ４つ
電流スイッチ ２つ
定電流源 ４つ
と見積もることができる。
【０１２８】
従来の電流遅延フリップフロップをＬ段直列に接続して電流信号を遅延させる回路構成の場合には、電流遅延フリップフロップがＬ個必要であるので、
電流メモリＭＯＳトランジスタ ４×Ｌ
電流スイッチ ２×Ｌ
定電流源 ４×Ｌ
となる。
【０１２９】
本発明の回路構成の場合には、
１入力Ｍ出力電流遅延フリップフロップＣＤＦＦｉ１個当たり、
電流メモリＭＯＳトランジスタの個数は６＋Ｍ、
電流スイッチの個数は ２
定電流源の個数は ６＋Ｍ
この電流フリップフロップをＮ個使用するから、
電流メモリＭＯＳトランジスタの個数は（６＋Ｍ）×Ｎ
電流スイッチの個数は ２×Ｎ
定電流源の個数は （６＋Ｍ）×Ｎ
また、部分相関出力電流遅延回路ブロック部１０３のＮチップ電流遅延回路Ｎｄｅｌａｙについて、
電流メモリＭＯＳトランジスタ （Ｎ＋１）×（Ｍ−１）
電流スイッチ （２×Ｎ）×（Ｍ−１）
定電流源 （Ｎ＋１）×（Ｍ−１）
である。
【０１３０】
以上の合計から、
電流メモリＭＯＳトランジスタの個数は、
（６＋Ｍ）×Ｎ＋（Ｎ＋１）×（Ｍ−１）＝２Ｍ×Ｎ＋５Ｎ＋Ｍ−１
電流スイッチの個数は、 （２×Ｎ）×Ｍ
定電流源の個数は、 ２Ｍ×Ｎ＋５Ｎ＋Ｍ−１
である。
【０１３１】
ここで、従来の電流遅延フリップフロップをＬ段直列に接続して電流信号を遅延させる構成の場合の電流源の個数とこの発明の実施の形態１の構成の定電流源の個数とを比較する。電流モード回路の場合には、定電流源から定常的に流れている定電流による消費電力が大部分を占めている。従って、定電流源の個数を減らすことが消費電力の低減と、回路構成の簡素化とに寄与する。
【０１３２】
従来構成の相関器の電流源の個数は４Ｌであり、この発明の実施の形態に係わる電流源の個数は、２Ｍ×Ｎ＋５Ｎ＋Ｍ−１である。
【０１３３】
ただし、ここで、Ｌ＝Ｍ×Ｎであり、
転送回数が最小になるＭ＝Ｎの場合について考察する。
式 ４Ｌ＞２Ｌ＋Ｌ^-1/2−１（Ｌ＞９（Ｌは実数））は下記の条件で成立し、Ｌが大きくなるほど、従来の相関器の電流源の個数に較べて、この発明の実施の形態の電流源の個数は急速に少なくなる。これは、チップ情報の配列個数Ｌが増大した場合に、その転送回数の低減の効果と、回路構成の簡略化の効果が顕著になることを示している。
【０１３４】
また、参照符号を固定して動作させる場合には、並列電流経路切り替えスイッチ回路ブロック部１０２のペアスイッチは常時一方が接続、一方が切断状態に保たれる。ここで、ペアスイッチを動作させる場合の消費電力は、スイッチをオンオフ動作させる際のゲート電極への電荷の蓄積により消費されることになるために、実質的にペアスイッチを固定する場合には、消費電力は生じないことになる。
【０１３５】
スイッチドキャパシタを用いたアナログマッチドフィルタでは、非常に厳密な値を持つ容量をＬＳＩプロセスに導入しなければならないが、この電流加算型マッチドフィルタでは、いわゆるＡＳＩＣファンドリーが通常提供しているデジタル用スタンダードプロセスを利用して全ての回路を構成することが可能である。
【０１３６】
この発明の実施の形態１によれば、電流信号の転送回数を大幅に低減すると同時に、回路を構成するうえでの電流源の個数、スイッチの個数を低減することが可能であり、回路構成の簡単化を図ることができる。また、電流源の総個数を減らすことができるので、従来の構成と較べて消費電力を節約できる。
【０１３７】
更に、アナログ電流データの転送回数を大幅に減らすことが可能となるために、相関出力の精度を向上させることができる。
【０１３８】
なお、１入力多出力電流遅延回路ブロック部１０１の電流遅延フリップフロップの個数は、転送誤差の発生割合と電流源の個数と回路素子の複雑化とを総合的に考慮して選択するのが望ましい。
【０１３９】
【発明の実施の形態２】
（１入力多出力電流遅延回路ブロック部１０１に１トランジスタ構造のカレントミラーを用いた場合の説明）
発明の実施の形態１では、２個の定電流源をそれぞれ用いて、サンプル制御スイッチ付きのカレントミラー回路ＣＭＲ１、ＣＭＲ２を構成した。しかしながら、消費電力の観点からは、電流源の個数をなるべく少なくすることが望ましい。
【０１４０】
図１７は定電流源を１個にした場合の１入力多出力電流遅延フリップフロップＣＤＦＦ１の具体例を示している。この図１７に示す１入力多出力電流遅延フリップフロップＣＤＦＦ１の構成は、カレントミラー回路ＣＭＲ１、ＣＭＲ２の構成が異なるのみであるので、他の回路については、同一構成要素に同一符号を付して、異なる部分についてのみ説明する。
【０１４１】
その図１７において、カレントミラー回路ＣＭＲ１は電流源Ｉ₁₀’と、メモリＭＯＳトランジスタＭ１０１’と、入力スイッチＳＷ1０と、制御スイッチＳＷ１１とから構成されている。ここで、入力スイッチＳＷ１０と制御スイッチＳＷ１１とは同一のタイミングでオン・オフする。カレントミラー回路ＣＭＲ２は電流源Ｉ₁₁’と、メモリＭＯＳトランジスタＭ１０２’と、入力スイッチＳＷ２０と、制御スイッチＳＷ２１とから構成されている。入力スイッチＳＷ２０と制御スイッチＳＷ２１とも同一のタイミングでオン・オフする。
【０１４２】
カレントミラー回路ＣＭＲ１のメモリＭＯＳトランジスタＭ１０１’のソースは電流源Ｉ₁₀’を介して電源電圧Ｖｄｄに接続されていると共に、入力スイッチＳＷ１０を介して入力端子Ｔ０１に接続されている。そのメモリＭＯＳトランジスタＭ１０１’のゲートは制御スイッチＳＷ１１を介してそのソースに接続されている。メモリＭＯＳトランジスタＭ１０１’のドレインは接地されている。
【０１４３】
カレントミラー回路ＣＭＲ２のメモリＭＯＳトランジスタＭ１０２’のソースは電流源Ｉ₁₁’を介して電源Ｖｄｄに接続されていると共に、入力スイッチＳＷ２０を介してカレントミラー回路ＣＭＲ１のメモリＭＯＳトランジスタＭ１０１’のソースに接続されている。そのメモリＭＯＳトランジスタＭ１０２’のゲートは制御スイッチＳＷ２１を介してそのソースに接続されると共に、カレントミラー回路ＣＭＲ３のメモリＭＯＳトランジスタＭ３０１のゲートに接続されている。そのメモリＭＯＳトランジスタＭ１０２’のドレインは接地されている。出力端子Ｔ０２は次段の入力端子Ｔ０１に接続されている。
【０１４４】
クロック信号ＳＡ、ＳＢ（図７参照）を用いてこの図１７に示す１入力多出力電流遅延回路フリップフロップＣＤＦＦ１の構成を説明する。
【０１４５】
クロック信号ＳＡの立ち上がりで、カレントミラー回路ＣＭＲ１の入力スイッチＳＷ１０、制御スイッチＳＷ１１がオンする。このとき、入力スイッチＳＷ２０はオフである。入力端子Ｔ０１に理想的な入力電流Ｉｉｎを出力する電流源が接続されていたとすると、メモリＭＯＳトランジスタＭ１０１’のソースとゲートとがオンしているために、メモリＭＯＳトランジスタＭ１０１’のソース−ドレイン間に電流源Ｉ₁₀’からの電流Ｊと入力端子Ｔ０１から流入する電流信号Ｉｉｎとの和の電流「Ｊ＋Ｉｉｎ」が流れるように、そのゲートの電圧が設定される。
【０１４６】
次に、クロック信号ＳＡの立ち下がりで、入力スイッチＳＷ１０と制御スイッチＳＷ１１とがオフする。すると、メモリＭＯＳトランジスタＭ１０１’のゲートは潜在的に電流「Ｊ＋Ｉｉｎ」を流すことのできる電圧に保持される。
【０１４７】
続いて、クロック信号ＳＢが立ち上がると、入力スイッチＳＷ２０と制御スイッチＳＷ２１とが同時にオンされる。すると、メモリＭＯＳトランジスタＭ１０２’のソースとゲートとが導通しているので、メモリＭＯＳトランジスタＭ１０２’のソース−ドレイン間に電流源Ｉ₁₁’からの電流Ｊと前段のカレントミラー回路ＣＭＲ１に流入する電流信号「−Ｉｉｎ」との和の電流「Ｊ−Ｉｉｎ」が流れるように、そのメモリＭＯＳトランジスタ１０２’のゲート電圧が設定される。このとき、メモリＭＯＳトランジスタ１０２’に並列に接続されているカレントミラー回路ＣＭＲ３のメモリＭＯＳトランジスタＭ３０１のゲート電圧も電流「Ｊ−Ｉｉｎ」が流れるように保持される。
【０１４８】
続いて、クロック信号ＳＡがオンすると、カレントミラー回路ＣＭＲ２のメモリＭＯＳトランジスタＭ１０２’に保持されていた電流信号が次段に転送され、同時に、カレントミラー回路ＣＭＲ１のメモリＭＯＳトランジスタＭ１０１’に電流信号Ｉｉｎが流入する。その後の動作は発明の実施の形態１と同じであるので、その詳細な説明は省略する。
（発明の実施の形態２の効果）
この発明の実施の形態２について、
１トランジスタ構成を用いた１入力Ｍ出力電流遅延回路フリップフロップＣＤＦＦｉ１個当たり、
電流メモリＭＯＳトランジスタの個数は４＋Ｍ、
電流スイッチ ４、
定電流源 ４＋Ｍ、
となり、
この電流遅延フリップフロップをＮ個使用するので、
電流メモリＭＯＳトランジスタの総個数は、（４＋Ｍ）×Ｎ、
電流スイッチの総個数は、 ４×Ｎ
定電流源の総個数は、 （４＋Ｍ）×Ｎ
となる。
【０１４９】
また、部分相関出力電流遅延回路ブロック部１０３のＮチップ電流遅延回路Ｎｄｅｌａｙについて、
電流メモリＭＯＳトランジスタの個数は、（Ｎ＋１）×（Ｍ−１）、
電流スイッチの個数は、（２×Ｎ）×（Ｍ−１）、
定電流源の個数は、（Ｎ＋１）×（Ｍ−１）、
である。
【０１５０】
以上により、
電流メモリＭＯＳトランジスタの総個数は、（４＋Ｍ）×Ｎ＋（Ｎ＋１）×（Ｍ−１）＝２Ｍ×Ｎ＋３Ｎ＋Ｍ−１
電流スイッチの総個数は、６×Ｎ
電流源の総個数は、２Ｍ×Ｎ＋３Ｎ＋Ｍ−１
となる。
【０１５１】
発明の実施の形態１では、定電流源の総個数が２Ｍ×Ｎ＋５Ｎ＋Ｍ−１であったのに対して、定電流源の総個数を２Ｍ×Ｎ＋３Ｎ＋Ｍ−１に減らすことができる。その代わりに、電流スイッチの個数は増えているが、全体の回路の構成要素数を減少させることができ、定電流源の個数が消費電力の主要な要素なので、定電流源の個数を減らすことができる効果は顕著である。
【０１５２】
【発明の実施の形態３】
（カスコードＭＯＳを用いて１入力Ｍ出力電流遅延回路を構成した場合の説明）ｎチャネルＭＯＳＦＥＴ、ｐチャネルＭＯＳＦＥＴは、チャネル長が充分に大きなとき、そのドレイン電流−ドレイン電圧特性の飽和領域におけるドレイン抵抗ｒｄは非常に大きな値であり、実質的に無限大（ｒｄ＝∞）と考えることができる。しかしながら、チャネル長が１μｍ以下に微細化されると、そのドレイン抵抗ｒｄを無限大として扱うことができなくなってくる。すなわち、有限のｒｄの効果が顕在化し、図１８（ロ）、（二）に示すような特性となる。
【０１５３】
図１８（イ）はｎチャネルＭＯＳＦＥＴを示し、図１８（ロ）はそのｎチャネルＭＯＳＦＥＴの動作特性を示す。また、図１８（ハ）はｐチャネルＭＯＳＦＥＴを示し、図１８（二）はそのｐチャネルＭＯＳＦＥＴの動作特性を示す。
【０１５４】
その図１８（イ）において、符号ＦＥＴＮ（ｎ）はｎチャネルＭＯＳＦＥＴであることを代表的に示す意味で用いている。その図１８（ハ）において、符号ＦＥＴＮ（ｐ）はｐチャネルＭＯＳＦＥＴであることを代表的に示す意味で用いている。ｎチャネルＭＯＳＦＥＴ（ＦＥＴＮ（ｎ））は、そのドレイン抵抗ｒｄが有限の場合、ゲート電圧Ｖｇを２Ｖ、３Ｖ、４Ｖと増加方向に変化させると、そのドレイン−ソース間に流れる電流Ｉｄｎがドレイン電圧Ｖｄｎの増加に伴って、図１８（ロ）に示すように増加する方向に変化する。
【０１５５】
ｐチャネルＭＯＳＦＥＴ（ＦＥＴＮ（ｐ））は、そのドレイン抵抗ｒｄが有限の場合、ゲート電圧Ｖｇを−１Ｖ、−２Ｖ、−３Ｖと減少方向に変化させると、そのドレイン−ソース間に流れる電流Ｉｄｐがドレイン電圧Ｖｄｐの減少に伴って、図１８（ニ）に示すように減少する方向に変化する。
【０１５６】
従って、図１８（ロ）、図１８（二）に示すＭＯＳトランジスタを用いて回路設計を行うと、相関器５から出力される相関電流信号が入力された電流信号Ｉｉｎに正確に対応しないことになる。
【０１５７】
そこで、これらの図１８（ロ）に示す動作特性を有する２個のｎチャネルＭＯＳＦＥＴ（ＦＥＴＮ（ｎ））の組み合わせ、図１８（二）に示す動作特性を有する２個のｐチャネルＭＯＳＦＥＴ（ＦＥＴＮ（ｐ））の組み合わせを用いて飽和特性が改善された等価ＭＯＳＦＥＴを構成することとする。
【０１５８】
図１９（イ）はｎチャネルＭＯＳＦＥＴに対応する等価ＭＯＳＦＥＴを示し、等価であるという意味で記号ＥＦＥＴＮ（ｎ）で示す。また、図２０（イ）はｐチャネルＭＯＳＦＥＴに対応する等価ＭＯＳＦＥＴを示し、等価であるという意味で記号ＥＦＥＴＮ（ｐ）で示す。
【０１５９】
ここでは、ｎチャネルＭＯＳ等価ＦＥＴ（ＥＦＥＴＮ（ｎ））には、ｎチャネルＭＯＳＦＥＴ（ＦＥＴＮ（ｎ））が２個用いられ、全体としてｎチャネルＭＯＳＦＥＴとして動作する。２個のｎチャネルＭＯＳＦＥＴ（ＦＥＴＮ（ｎ））を順に、ＦＥＴ１（ｎ）、ＦＥＴ２（ｎ）で示すことにし、その接続状態を次に説明する。
【０１６０】
ｎチャネルＭＯＳＦＥＴ（ＦＥＴ１（ｎ））のソースは接地され、そのドレインはｎチャネルＭＯＳＦＥＴ（ＦＥＴ２（ｎ））のソースに接続されている。ｎチャネルＭＯＳＦＥＴ（ＦＥＴ２（ｎ））のドレインは端子Ｖｏｕｔに接続されている。
【０１６１】
ここで、ｎチャネルＭＯＳＦＥＴ（ＦＥＴ１（ｎ））のゲートに電圧Ｖｇｎが印加され、ｎチャネルＭＯＳＦＥＴ（ＦＥＴ２（ｎ））のゲートに電圧Ｖｂｉａｓが印加されているものとする。
【０１６２】
Ｖｏｕｔの電圧が上昇すると、ｎチャネルＭＯＳＦＥＴ（ＦＥＴ２（ｎ））のドレインーソース間を流れる電流Ｉｄｎが増大する。すると、同一の電流ＩｄｎをｎチャネルＭＯＳＦＥＴ（ＦＥＴ１（ｎ））に同一の電流を流すために、Ｖｄｎの電位が上昇する。すると、ｎチャネルＭＯＳＦＥＴ（ＦＥＴ２（ｎ））のソース−ドレイン間の電位差（Ｖｏｕｔ−Ｖｄｎ）が減少するために、ｎチャネルＭＯＳＦＥＴのドレイン−ソース間を流れる電流Ｉｄｎが減少する。
【０１６３】
これによって、Ｖｏｕｔの変動によるＩｄｎの変動が、Ｖｄｎの電圧のフィードバック効果によって小さくなる。従って、Ｖｏｕｔの変動に対してＶｄｎの変動が小さくなるので、等価ＭＯＳＦＥＴ（ＥＦＥＴＮ（ｎ））のドレイン電圧の変動に対する耐性は、単体のＭＯＳＦＥＴを用いた場合のドレイン電圧の変動の大きさよりも小さくなり、実質的にドレイン抵抗ｒｄを大きくすることができる。この等価ＭＯＳＦＥＴ（ＥＦＥＴＮ（ｎ））はメモリＭＯＳトランジスタに用いられる。
【０１６４】
図２０（イ）に示すｐチャネル等価ＭＯＳＦＥＴ（ＥＦＥＴＮ（ｐ））には、ｐチャネルＭＯＳＦＥＴ（ＦＥＴＮ（ｐ））が２個用いられ、全体としてｐチャネルＭＯＳＦＥＴとして動作する。ここでは、２個のｐチャネルＭＯＳＦＥＴ（ＦＥＴＮ（ｐ））を順に（ＦＥＴ１（ｐ））、（ＦＥＴ２（ｐ））で示すことにし、次にその接続状態を説明する。
【０１６５】
ｐチャネルＭＯＳＦＥＴ（ＦＥＴ１（ｐ））のソースはＶｄｄに接続され、そのドレインはｐチャネルＭＯＳＦＥＴ（ＦＥＴ２（ｐ））のソースに接続されている。ｐチャネルＭＯＳＦＥＴ（（ＦＥＴ２（ｐ））のソースは端子Ｖｏｕｔに接続されている。
【０１６６】
ここで、ｐチャネルＭＯＳＦＥＴ（ＦＥＴ１（ｐ））のゲートに電圧Ｖｇｐ、ｐチャネルＭＯＳＦＥＴ（ＦＥＴ２（ｐ））のゲートに電圧Ｖｂｉａｓが印加されているものとする。
【０１６７】
Ｖｏｕｔの電圧が低下すると、ｐチャネルＭＯＳＦＥＴ（ＦＥＴ２（ｐ））のドレイン−ソース間の電位差（Ｖｄｐ−Ｖｏｕｔ）が減少するために、ｐチャネルＭＯＳＦＥＴのドレイン−ソース間に流れる電流Ｉｄｐが減少する。
【０１６８】
これによって、Ｖｏｕｔの変動によるＩｄｐの変動が、Ｖｄｐの電圧のフィードバック効果によって小さくなる。従って、Ｖｏｕｔの変動に対して、Ｖｄｐの変動が小さくなるので、等価ＭＯＳＦＥＴ（ＥＦＥＴＮ（ｐ））のドレイン電圧の変動に対する耐性は、単体のＭＯＳＦＥＴを用いた場合のドレイン電圧変動の大きさよりも小さくなり、実質的にドレイン抵抗ｒｄを大きくすることができる。この等価ＭＯＳＦＥＴ（ＥＦＥＴＮ（ｐ））は電流源に用いられる。このカスコードＭＯＳＦＥＴを電流源と電流メモリＭＯＳＦＥＴとを図１７に示す１入力Ｍ出力電流遅延フリップフロップＣＤＦＦ１に適用した具体例を図２１に示す。
【０１６９】
これによって、電流信号の遅延、電流源特性、電流保持特性を向上させることができる。
【０１７０】
【発明の実施の形態４】
（レギュレーティッドカスケード回路により部分相関電流出力遅延回路ブロック部１０３を構成した場合の説明）
図２２（イ）はｎチャネルＭＯＳＦＥＴに対応する等価ＭＯＳＦＥＴを示し、等価であるという意味で記号ＥＦＥＴＮ（ｎ）で示す。また、図２３（イ）はｐチャネルＭＯＳＦＥＴに対応する等価ＭＯＳＦＥＴを示し、等価であるという意味で記号ＥＦＥＴＮ（ｐ）で示す。
【０１７１】
ここでは、ｎチャネルＭＯＳ等価ＦＥＴ（ＥＦＥＴＮ（ｎ））には、ｎチャネルＭＯＳＦＥＴ（ＦＥＴＮ（ｎ））が３個用いられ、ｐチャネルＭＯＳＦＥＴ（ＦＥＴＮ（ｐ））が１個用いられ、全体としてｎチャネルＭＯＳＦＥＴとして動作する。３個のｎチャネルＭＯＳＦＥＴ（ＦＥＴＮ（ｎ））を順に、ＦＥＴ１（ｎ）、ＦＥＴ２（ｎ）、ＦＥＴ３（ｎ）で示すことにし、その接続状態を次に説明する。
【０１７２】
ｎチャネルＭＯＳＦＥＴ（ＦＥＴ１（ｎ））のソースは接地され、そのドレインはｎチャネルＭＯＳＦＥＴ（ＦＥＴ２（ｎ））のソースとｎチャネルＭＯＳＦＥＴ（ＦＥＴ３（ｎ））のゲートとに接続されている。ｎチャネルＭＯＳＦＥＴ（ＦＥＴ１（ｎ））のゲートにはゲート電圧Ｖｇｎが印加される。ｎチャネルＭＯＳＦＥＴ（ＦＥＴ２（ｎ））のドレインは端子Ｖｏｕｔに接続されている。端子Ｖｏｕｔは図１３に示す電流源に接続される。ｎチャネルＭＯＳＦＥＴ（ＦＥＴ２（ｎ））のゲートはｐチャネルＭＯＳＦＥＴ（ＦＥＴＮ（ｐ））のドレインとｎチャネルＭＯＳＦＥＴ（ＦＥＴ３（ｎ））のドレインとに接続されている。ｎチャネルＭＯＳＦＥＴ（ＦＥＴ３（ｎ））のソースは接地されている。ｐチャネルＭＯＳＦＥＴ（ＦＥＴＮ（ｐ））のソースは電源Ｖｄｄに接続され、ｐチャネルＭＯＳＦＥＴ（ＦＥＴＮ（ｐ））のゲートにはゲート電圧Ｖｒｅｇ_pが印加されている。
【０１７３】
ｎチャネルＭＯＳ等価ＦＥＴ（ＥＦＥＴＮ（ｎ））では、ｐチャネルＭＯＳＦＥＴ（ＦＥＴＮ（ｐ））が電流源として動作する。いま、端子Ｖｏｕｔに加わる電圧が上昇すると、ｎチャネルＭＯＳＦＥＴ（ＦＥＴ２（ｎ））のドレイン−ソース間に流れる電流Ｉｄｎが増加し、ｎチャネルＭＯＳＦＥＴ（ＦＥＴ１（ｎ））のドレイン側の電位Ｖｄｎが上昇しようとする。このドレイン側の電位Ｖｄｎが上昇すると、ｎチャネルＭＯＳＦＥＴ（ＦＥＴ３（ｎ））のゲート電圧が大きくなり、ｎチャネルＭＯＳＦＥＴ（ＦＥＴ３（ｎ））のドレイン−ソース間に流れる電流が増加しようとする。
【０１７４】
ところが、ｐチャネルＭＯＳＦＥＴ（ＦＥＴＮ（ｐ））によりｎチャネルＭＯＳＦＥＴ（ＦＥＴ３（ｎ））に流れる電流Ｉｒｅｇ_nは一定に保たれているので、ｎチャネルＭＯＳＦＥＴ（ＦＥＴ３（ｎ））のドレイン側の電位Ｖｄが下がり、これにより、ｎチャネルＭＯＳＦＥＴ（ＦＥＴ２（ｎ））のゲートに加わるゲート電位が低下する。ｎチャネルＭＯＳＦＥＴ（ＦＥＴ２（ｎ））のゲート電位が下がると、電流Ｉｄｎの増加が阻止され、結果としてｎチャネルＭＯＳＦＥＴ（ＦＥＴ２（ｎ））のドレイン−ソース間の電位差が大きくなり、ｎチャネルＭＯＳＦＥＴ（ＦＥＴ１（ｎ））のドレイン電圧Ｖｄｎが一定に保持され、ひいては、電流Ｉｄｎが一定に保たれることになる。
【０１７５】
これにより、ｎチャネル等価ＭＯＳＦＥＴはそのドレイン抵抗ｒｄが∞となり、図２２（ロ）に示す飽和特性が改善される。実際には、電流Ｉｄｎの大きさは概略５０〜１５０マイクロアンペア程度であり、電流Ｉｒｅｇ_nは２マイクロアンペア程度で良いので、ｐチャネルＭＯＳＦＥＴ（ＦＥＴＮ（ｐ））からｎチャネルＭＯＳＦＥＴ（ＦＥＴ３（ｎ））に向かって流れる電流Ｉｒｅｇ_nに基づく電力消費はほとんど無視できる。
【０１７６】
なお、この図２２（イ）に示すｎチャネル等価ＭＯＳＦＥＴ（ＥＦＥＴＮ（ｎ））はいわゆるレギュレーティッドカスケード回路と呼ばれ、この回路それ自体は公知である。このｎチャネル等価ＭＯＳＦＥＴ（ＥＦＥＴＮ（ｎ））は、メモリＭＯＳトランジスタＭ１００_p（ｐ＝１、２、…、ｎ＋１）に用いることができる。
【０１７７】
図２３（イ）に示すｐチャネル等価ＭＯＳＦＥＴ（ＥＦＥＴＮ（ｐ））は全体としてｐチャネルＭＯＳＦＥＴとして動作する。ｐチャネル等価ＭＯＳＦＥＴ（ＥＦＥＴＮ（ｐ））には、ｐチャネルＭＯＳＦＥＴ（ＦＥＴＮ（ｐ））が３個用いられ、ｎチャネルＭＯＳＦＥＴ（ＦＥＴＮ（ｎ））が１個用いられる。ここでは、３個のｐチャネルＭＯＳＦＥＴ（ＦＥＴＮ（ｐ））を順に（ＦＥＴ１（ｐ））、（ＦＥＴ２（ｐ））、（ＦＥＴ３（ｐ））で示すことにし、次にその接続状態を説明する。
【０１７８】
ｐチャネルＭＯＳＦＥＴ（ＦＥＴ１（ｐ））のドレインは端子Ｖｏｕｔに接続されている。ｐチャネルＭＯＳＦＥＴ（ＦＥＴ１（ｐ））のソースはｐチャネルＭＯＳＦＥＴ（ＦＥＴ２（ｐ））のドレインとｐチャネルＭＯＳＦＥＴ（ＦＥＴ３（ｐ））のゲートに接続されている。ｐチャネルＭＯＳＦＥＴ（ＦＥＴ１（ｐ））のゲートはｎチャネルＭＯＳＦＥＴ（ＦＥＴＮ（ｎ））のドレインとｐチャネルＭＯＳＦＥＴ（ＦＥＴ３（ｐ））のドレインとに接続されている。ｐチャネルＭＯＳＦＥＴ（ＦＥＴ２（ｐ））のソースは電源Ｖｄｄに接続され、そのゲートにはゲート電圧Ｖｇｐが印加されている。ｐチャネルＭＯＳＦＥＴ（ＦＥＴ３（ｐ））のソースは電源Ｖｄｄに接続されている。ｎチャネルＭＯＳＦＥＴ（ＦＥＴＮ（ｎ））のソースは接地され、そのゲートにはゲート電圧Ｖｒｅｇ_nが印加されている。その図２３（イ）において、ＶｄｐはｐチャネルＭＯＳＦＥＴ（ＦＥＴ１（ｐ））のソース側の電位であり、ＩｄｐはｐチャネルＭＯＳＦＥＴ（ＦＥＴ１（ｐ））のソース−ドレイン間に流れる電流を示している。このｐチャネル等価ＭＯＳＦＥＴ（ＥＦＥＴＮ（ｐ））の飽和特性は図２３（ロ）に示すようになる。その理由は、ｎチャネル等価ＭＯＳＦＥＴ（ＥＦＥＴＮ（ｎ））の動作特性の説明から容易に類推できるので割愛する。このｐチャネル等価ＭＯＳＦＥＴは電流源Ｉ１００_p（ｐ＝１、２、…、ｎ＋１）として用いることができる。
【０１７９】
図２４は実際に図１３に示すＮチップ電流遅延回路Ｎｄｅｌａｙ₁に等価ＭＯＳＦＥＴを適用した場合を示している。この構造を用いることによって、Ｎチップ電流遅延回路Ｎｄｅｌａｙ_kの電流源特性と電流保持特性とを向上させることができる。
【０１８０】
【発明の実施の形態５】
（１入力多出力電流遅延回路ブロック部１０１に電流カットを適用した場合の説明）
図２５は１入力多出力電流遅延回路ブロック部１０１において、動作上不必要な時間に、電流源Ｉ₁₀〜Ｉ₁₅、Ｉ_16jを停止若しくは定電流Ｊが流れる経路上に電流停止スイッチを設けて、定常電流が流れない構成とした場合を示すタイムチャートである。例えば、電流停止スイッチは図６（ａ）において、経路ｚ₁〜ｚ₆、ｚ_16jに設けられる。
【０１８１】
１チップ時間内で、電流信号をメモリＭＯＳトランジスタにサンプリングし又はメモリＭＯＳトランジスタから出力するのに必要な最低限の時間のみ、電流源Ｉ₁₀〜Ｉ₁₃を動作させる。これは、メモリＭＯＳトランジスタが一度情報を記憶すると、電流源Ｉ₁₀〜Ｉ₁₅、Ｉ_16jを停止しても電流情報を記憶しておくことができるという性質を利用している。１入力多出力電流遅延回路ブロック部１０１の場合には、電流信号の記憶と出力時間以外の時間には電流源Ｉ₁₀〜Ｉ₁₃を停止させることが可能である。
【０１８２】
１チップ時間をＴｃｈｉｐ、電流の入出力に必要な時間をＴｉｎｏｕｔとすると、電流源から電流を流すのに必要な時間は、全体の動作時間のうちの、１チップ時間当たり、
Ｔｉｎｏｕｔ／Ｔｃｈｉｐとなり、
電流源Ｉ₁₀、Ｉ₁₁を停止させておくことが可能な時間は、全体の動作時間のうちの、１チップ時間当たり、
（Ｔｃｈｉｐ−Ｔｉｎｏｕｔ）／Ｔｃｈｉｐとなり、
常時電流源の電流を流した場合に対して、対象とする電流源の総個数をＫとすると、電流源を停止させることが可能な時間は、
Ｊ×Ｋ×（Ｔｃｈｉｐ−Ｔｉｎｏｕｔ）／Ｔｃｈｉｐとなり、
この分だけ消費電流を低減することができる。
【０１８３】
電流モード素子の場合には、定常的な電流が消費電流の主体であるので、電流源の定常的な電流を抑えることは、消費電力を抑えるうえで非常に効果がある。また、電流の入出力に必要な時間Ｔｉｎｏｕｔは、ＭＯＳＦＥＴのスケーリング則によって、微細化が進むほど短くなり、それに伴って、電流源を停止することが可能な時間が増えることによって、更なる消費電力の低減が可能である。
【０１８４】
【発明の実施の形態６】
（Ｎチップ電流遅延回路Ｎｄｅｌａｙ_kに電流カットを行った場合の例）
図２６はＮチップ電流遅延回路Ｎｄｅｌａｙ_kにおいて、動作上不必要な時間に、電流源を停止もしくは電流の経路上にスイッチを設けて、定常的な電流が流れない構成にした場合を示すタイムチャートである。
【０１８５】
１チップ時間内で、部分相関電流をメモリＭＯＳにサンプリングし又はメモリＭＯＳトランジスタから出力するのに必要な最小限の時間のみ電流源を動作させる。これはメモリＭＯＳトランジスタが一度情報を記憶すると、電流源を停止しても電流情報を記憶保持することができるという性質を利用している。
【０１８６】
このＮチップ電流遅延回路Ｎｄｅｌａｙでは、Ｎ回遅延させる間に１回ずつ相関電流の入力と出力とを行うので、１チップ時間をＴｃｈｉｐ、遅延回数をＮ、相関電流の入出力に必要な時間をＴｉｎｏｕｔとすると、電流源から電流を流すのに必要な時間は、全体の動作時間のうちの、（Ｎ＋１）チップ時間当たり、
Ｔｉｎｏｕｔ／（Ｔｃｈｉｐ×（Ｎ＋１））時間であり、
電流源を停止しておくことが可能な時間は、全体の動作時間のうちの、（Ｎ＋１）チップ時間当たり、
（Ｔｃｈｉｐ×（Ｎ＋１）−Ｔｉｎｏｕｔ）／（Ｔｃｈｉｐ×（Ｎ＋１））時間となり、常時電流源の電流を流した場合に対して、対象とする電流源の総数をＮ＋１とすると、電流源を停止させることが可能な時間は、
Ｊ×（Ｎ＋１）×（Ｔｃｈｉｐ×（Ｎ＋１）−Ｔｉｎｏｕｔ）／Ｔｃｈｉｐとなり、この分だけ、消費電流を低減することができる。
【０１８７】
Ｎチップ電流遅延回路Ｎｄｅｌａｙでは、電流源は（Ｎ＋１）チップ時間のうちに、１チップ時間だけ動作させれば良いので、電流カットの効果が非常に大きく、消費電力の低減の効果が大きい。１個のＮチップ電流遅延回路Ｎｄｅｌａｙ回路では、Ｎ＋１個の電流メモリー回路を並列に持っているが、実質的にカレントカットをチップ単位で行うことによって、２個の電流メモリー相当の電流源消費電力で済むので、回路全体に占める消費電力は高々Ｍ×２個の電流メモリー程度となり、消費電力の低減効果が大きい。
【０１８８】
ここでは、チップ単位でのカレントカットを説明したが、発明の実施の形態４で説明したように、チップ時間内でもカレントカットを動作させる場合には、１個の電流メモリー相当の電流源消費電力で済むので、回路全体に占める消費電力は高々Ｍ×１個の電流メモリー程度となり、より消費電力の低減効果が大きい。
【０１８９】
電流モード素子の場合には、定常的な電流が消費電流の主体であるために、電流源の定常的な電流を抑えることは、消費電力を抑えるうえで非常に効果がある。また、電流の入出力に必要な時間Ｔｉｎｏｕｔは、ＭＯＳＦＥＴのスケーリング則によって、微細化が進むほど短くなり、それにともなって、電流源を停止させることが可能な時間が増えることによって、更なる消費電力の低減が可能である。
【０１９０】
【発明の実施の形態７】
（１入力多出力電流遅延回路ブロック部１０１のメモリー制御スイッチＳＷ₁₁、ＳＷ₂₁にダミーＭＯＳトランジスタを用いた実施例の説明）
図１７に示す１入力多出力電流遅延回路ブロック部１０１のメモリー制御スイッチＳＷ₁₁、ＳＷ₂₁は、図２７（イ）に示すように一般にｎ型ＭＯＳＦＥＴＤＭ₀から構成されている。そのｎ型ＭＯＳＦＥＴＤＭ₀のドレインはメモリＭＯＳトランジスタＭ₁₀₁’、Ｍ₁₀₂’のドレインに接続されると共に、Ｖｏｕｔ端子に接続されている。Ｖｏｕｔ端子は電流源Ｉ₁₀’、Ｉ₁₁’に接続されている。
【０１９１】
ｎ型ＭＯＳＦＥＴＤＭ₀のソースはメモリＭＯＳトランジスタＭ₁₀₁’、Ｍ₁₀₂’のゲートに接続されている。ｎ型ＭＯＳＦＥＴＤＭ₀のゲートにはタイミングクロックパルス（クロック信号ＳＡ、ＳＢに相当）φが入力される。電流信号Ｉｉｎが入力される際にはｎ型ＭＯＳＦＥＴＤＭ₀はオン（ソースードレイン間は導通）であり、電流信号を保持する際にはオフである。
【０１９２】
ここで、メモリＭＯＳトランジスタＭ₁₀₁’、Ｍ₁₀₂’に電流信号Ｉｉｎが入力される際には、メモリＭＯＳトランジスタＭ₁₀₁’、Ｍ₁₀₂’のソース−ドレイン間に電流Ｊが流れるように、ｎ型ＭＯＳＦＥＴＤＭ₀を介して、メモリＭＯＳトランジスタＭ₁₀₁’、Ｍ₁₀₂’のゲートの電圧がＶｇｎに設定される。このとき、メモリＭＯＳトランジスタＭ₁₀₁’、Ｍ₁₀₂’のソースに寄生的に存在している寄生容量Ｃ₁₀₁は接地に対してＶｇｎの電圧で充電状態となっている。
【０１９３】
メモリＭＯＳトランジスタＭ₁₀₁’、Ｍ₁₀₂’に電流信号Ｉｉｎを入力する状態から電流信号Ｉｉｎを保持する状態に変化させる際、ｎ型ＭＯＳＦＥＴＤＭ₀が理想状態のときには、メモリＭＯＳトランジスタＭ₁₀₁’、Ｍ₁₀₂’のゲートの電圧はＶｇｎに保持される。
【０１９４】
ところが、一般的には、ｎ型ＭＯＳＦＥＴＤＭ₀は、オフ状態になるときに、そのゲートが正の電圧から０Ｖに変化するために、そのゲート−ソース間の寄生容量Ｃ₁₀₂から電荷が放出され、その電荷がメモリＭＯＳトランジスタＭ₁₀₁’、Ｍ₁₀₂’のゲートとメモリＭＯＳトランジスタＭ₁₀₁’、Ｍ₁₀₂’のゲート−ソース寄生容量Ｃ₁₀₁とに分配され、結果的にメモリＭＯＳトランジスタＭ₁₀₁’、Ｍ₁₀₂’のゲート電圧Ｖｇｎが変動する。この電荷の変動はクロックフィールドスルーと呼ばれ、この構成の電流信号の転送誤差の主要原因となる。このメモリＭＯＳトランジスタＭ₁₀₁’、Ｍ₁₀₂’のゲートの電圧の変動によって、そのメモリＭＯＳトランジスタＭ₁₀₁’、Ｍ₁₀₂’のドレイン−ソース間を流れる電流が変動し、メモリＭＯＳトランジスタＭ₁₀₁’、Ｍ₁₀₂’から出力される電流信号に誤差が入り込むことになる。
【０１９５】
そこで、メモリＭＯＳトランジスタＭ₁₀₁’、Ｍ₁₀₂’のゲートの電極を大きくし、そのゲートの容量とソース−ゲート間の寄生容量を大きくすること、又は、ｎ型ＭＯＳＦＥＴＤＭ₀の寄生容量を小さくすることによって、この電荷の分配による影響を抑えることが考えられるが、これによって誤差を全て抑制することはできない。
【０１９６】
図２７（ロ）はダミーＭＯＳトランジスタＤＭ₁を用いて、この転送誤差を低減する構成を示している。
【０１９７】
ここでは、メモリ制御スイッチＳＷ₁₁、ＳＷ₂₁はｎ型ＭＯＳＦＥＴＤＭ₀とダミーＭＯＳトランジスタＤＭ₁とから構成されている。ｎ型ＭＯＳＦＥＴＤＭ₀のソースはダミーＭＯＳトランジスタＤＭ₁のドレインに接続され、ダミーＭＯＳトランジスタＤＭ₁のソースはメモリＭＯＳトランジスタＭ₁₀₁’、Ｍ₁₀₂’のゲートに接続されている。そのダミーＭＯＳトランジスタＤＭ₁のソースとドレインとは短絡されている。そのダミーＭＯＳトランジスタＤＭ₁のゲートにはｎ型ＭＯＳＦＥＴＤＭ₀のゲートに入力されるタイミングクロックパルスφと逆位相のタイミングクロックパルスφ’が入力される。
【０１９８】
電流情信号Ｉｉｎが入力されるときには、ｎ型ＭＯＳＦＥＴＤＭ₀はオンであり、ダミーＭＯＳトランジスタＤＭ₁はオフ（ゲートにオフに相当する通常０Ｖの電圧）が印加されている。メモリＭＯＳトランジスタＭ₁₀₁’、Ｍ₁₀₂’に流すべき電流値がＪとなるように、ゲート電圧Ｖｇｎは設定される。
【０１９９】
このとき、メモリＭＯＳトランジスタＭ₁₀₁’、Ｍ₁₀₂’のゲートソース間の寄生容量Ｃ₁₀₁はＶｇｎで充電状態になっている。また、ダミーＭＯＳトランジスタＤＭ₁のソース−ゲート間の寄生容量Ｃ₁₀₃、ドレインーゲート間の寄生容量Ｃ₁₀₄はダミーＭＯＳトランジスタＤＭ₁のゲートの電圧（通常、電流信号をメモリーする状態では０Ｖ）とＶｇｎとの電位差（ほぼ１Ｖ）であるために、ほぼ放電状態になっている。
【０２００】
この状態で、電流信号の保持状態が変化した場合を考える。
【０２０１】
ｎ型ＭＯＳＦＥＴＤＭ₀がオンからオフになると、そのゲート電圧はほぼ０Ｖになって、寄生容量Ｃ₁₀₂は放電状態となる。一方、ダミーＭＯＳトランジスタＤＭ₁のゲートがオンになると、寄生容量Ｃ₁₀₃、Ｃ₁₀₄は充電状態になる。このとき、寄生容量Ｃ₁₀₂から放出される電荷量と寄生容量Ｃ₁₀₃、Ｃ₁₀₄に充電される電荷量を同じにすると、寄生容量Ｃ₁₀₁を介した電荷の再分配は起こらないので、メモリー電圧Ｖｇｎは変動しないことになる。
【０２０２】
ｎ型ＭＯＳＦＥＴＤＭ₀とダミーＭＯＳトランジスタＤＭ₁とを同一のｎＭＯＳＦＥＴで製作した場合には、同一のゲート長Ｌに対してダミーＭＯＳトランジスタＤＭ₁のゲート幅Ｗを約半分にすれば良い。この構成を採用することによって、単体のメモリＭＯＳトランジスタＭ₁₀₁’、Ｍ₁₀₂’の電流信号の転送誤差を減らすことが可能である。
【０２０３】
このダミーゲート構造を図１７に示す１入力多出力電流遅延フリップフロップＣＤＦＦ１に適用した場合の回路構成を図２８に示す。このように単体の転送誤差を減少させることによって、相関器全体の特性を改善することが可能である。
【０２０４】
なお、ここでは、ダミーゲートとしてｎＭＯＳＦＥＴを用いる場合について説明したが、ダミーゲートをｐＭＯＳＦＥＴを用いて構成することも可能である。
【０２０５】
【発明の実施の形態８】
（入力された電流信号の実数倍の電流値を出力することが可能な１入力多出力電流遅延フリップフロップＣＤＦＦｉの説明）
相関処理を行う際に、相関が取れたときには、全ての入力信号が同一の符号で加算されるために、例えば、チップ情報の配列個数がＬであるとすると、入力電流ＩｉｎのＬ倍の電流値が最終的に相関器から出力されることになる。
【０２０６】
この発明の実施の形態では、部分相関を行っているが、この相関電流が大きくなると、Ｎチップ電流遅延回路Ｎｄｅｌａｙの電流源の電流値を大きくする必要がある。線形性を保つためには、遅延させる電流値の２倍以上の電流値が必要である。
【０２０７】
電流モードの相関器では、システムとして要求されるダイナミックレンジを維持する範囲の中で、電流値を一定の割合で縮小することが可能である。図２９は１入力多出力電流遅延フリップフロップＣＤＦＦｉの構造を示している。この図２９に示す１入力多出力電流遅延フリップフロップＣＤＦＦｉの電流信号Ｉｉｎが入力されたときの電流カレントミラー回路ＣＭＲ１、ＣＭＲ２の動作は図１７に示す１入力多出力電流遅延フリップフロップＣＤＦＦｉの動作と同一である。電流信号Ｉｉｎに対して出力電流ＩｏｕｔをＭ倍（Ｍはここでは「１」以下の数であるが、「１」以上でも良い）にしたい場合には、電流源Ｉの電流値をＪ×Ｍに設定し、メモリＭＯＳトランジスタのサイズＬを一定に保ったままゲート幅ＷをＷ×Ｍに設定する。図２９にはＭ＝１／２の場合が示されている。
【０２０８】
この回路構成を採用することによって、次段への転送電流をＩｉｎに維持したまま、各並列電流経路切り替えスイッチ回路ブロック部１０１への遅延転送電流をＩｉｎ×Ｍとして出力することが可能である。全ての並列電流経路切り替えスイッチブロック部１０１への遅延転送電流がＭ倍になるように回路を作成した場合には、相関器の出力は入力電流Ｉｉｎから期待される相関出力に対してＭ倍の比例関係を保ったまま得ることが可能である。Ｍの値は相関器のノイズや非線形性、歪みによるダイナミックレンジを維持できる範囲でなるべく小さくすることによって、電流源の個数を一定に保ったまま、設定する電流値Ｊを小さくすることが可能であり、消費電力を抑えることが可能である。
【０２０９】
【発明の実施の形態９】
発明の実施の形態１から発明の実施の形態８までは、情報の１単位（１ビット）に対して丁度１周期が対応する拡散データ、すなわち、拡散符号としてチップ長Ｌの長周期のものを用いたが、１種類以上の短周期の拡散符号を２回以上の回数繰り返すか、又は、組み合わせて情報の１単位を構成して、この１情報分の符号を単位として相関を取る相関器がある。本発明は、この種の相関器にも適用できるものであり、以下にこの相関器の構成を図３０、図３１を用いて説明する。
【０２１０】
ここで、想定する短周期の拡散符号はＡ１、Ａ２、…、Ａｑのｑ種類の短周期の拡散符号であるとする。ただし、ｑは正の整数である。各短周期の拡散符号の内容を以下の通りとする。
Ａ１＝（ａ１１、ａ１２、ａ１３、…、ａ１Ｎ₁）
Ａ２＝（ａ２１、ａ２２、ａ２３、…、ａ２Ｎ₂）
… …
Ａｑ＝（ａｑ１、ａｑ２、ａｑ３、…、ａｑＮ_q）
情報の１単位に相当する拡散符号Ｙは、これらの短周期の拡散符号を組み合わせて作成される。すなわち、Ｙ＝（Ａ１、Ａ２、…、Ａｑ）
なお、同一の短周期の拡散符号を２回以上繰り返して、例えば、短周期の拡散符号Ａ１を二度繰り返して情報の１単位を構成する場合も、組み合わせということとする。また、短周期の拡散符号のうち、互いに逆の関係にある拡散符号、例えば、拡散符号Ａ１と拡散符号Ａ２とが、Ａ１＝−Ａ２の関係にある場合には、同一の拡散符号であるとして取り扱うものとする。
【０２１１】
ここで、各短周期の拡散符号の長さ（チップ長Ｎ）は同じで合っても良いし、異なっていても良いが、以下の説明では、拡散符号の長さＮは同一であるとして説明する。
【０２１２】
図３０は短周期の拡散符号を用いた相関器の一例を示す図であって、この図３０は、１種類の短周期の拡散符号Ａ＝（ａ１、ａ２、ａ３、…、ａＮ）をＭ個組み合わせて情報の１単位を構成する拡散符号Ｙの信号系列の相関をとる場合を示している。
【０２１３】
例えば、拡散符号の構成を、Ｙ＝（Ａ、Ａ、Ａ、…、−Ａ、Ａ）とする。この拡散符号Ｙを説明の便宜のため、各拡散符号の種類が異なっているものとして、Ｙ＝（Ａ１、Ａ２、Ａ３、…、Ａ（Ｍ−１）、ＡＭ）として表現する。
【０２１４】
この図３０では、１入力多出力電流遅延回路ブロック部１０１がＮ個の１入力２出力電流遅延フリップフロップＣＤＦＦｉから構成されている。互いに異なるｑ種類の短周期の拡散符号から拡散符号Ｙが構成されている場合には、１入力多出力電流遅延回路ブロック部１０１はＮ個の１入力（ｑ＋１）出力電流遅延フリップフロップＣＤＦＦｉから構成される。
【０２１５】
部分相関電流出力手段１０５_kは短周期の拡散符号の種類が１種類であるので１個である。部分相関電流出力手段１０５_kの部分相関出力電流は、１入力Ｍ出力電流分配回路１５０に入力される。この１入力Ｍ出力電流分配回路１５０は、入力された部分相関出力電流と同一の部分相関出力電流をＭ個の出力端子Ｔｐ₁、Ｔｐ₂、…、Ｔｐ_m-1、Ｔｐ_mから出力する役割を果たす。
【０２１６】
この部分相関出力電流は部分相関出力符号処理回路１５１に入力される。この部分相関出力符号処理回路１５１は入力端子Ｐ（１）ａ、Ｐ（２）ａ、…、Ｐ（Ｍ−１）ａ、Ｐ（Ｍ）ａと出力端子Ｐ（１）ｂ、Ｐ（２）ｂ、…、Ｐ（Ｍ−１）ｂ、Ｐ（Ｍ）ｂとを有し、拡散符号Ｙを構成する短周期の拡散符号Ａ１、Ａ２、…、Ａ（Ｍ−１）、ＡＭの符号に対応する処理を行う役割を果たす。例えば、拡散符号Ａ（Ｍ−１）を除く他の拡散符号はここでは「＋」であるので、そのまま、入力端子Ｐ（１）ａ、Ｐ（２）ａ、…、Ｐ（Ｍ）ａと出力端子Ｐ（１）ｂ、Ｐ（２）ｂ、…、Ｐ（Ｍ）ｂとを接続し、短周期の拡散符号Ｐ（Ｍ−１）は「−Ａ」であるので、入力端子Ｐ（Ｍ−１）ａと出力端子Ｐ（Ｍ−１）ｂとはカレントインバータ１５２を介在させて接続する。これによって、短周期の拡散符号Ｐ（Ｍ−１）は符号が逆転されて出力される。
【０２１７】
その部分相関出力符号処理回路１５１の出力は部分相関出力電流遅延回路ブロック部１０３のＮチップ電流遅延回路Ｎｄｅｌａｙ_kに入力される。例えば、符号Ａ１に相当する部分相関出力電流は、部分相関出力符号処理回路１５１によって符号処理が行われた後、Ｎチップ電流遅延回路Ｎｄｅｌａｙ₁に入力され、符号Ａ２に相当する部分相関出力電流は、部分相関出力符号処理回路１５１によって符号処理が行われた後、Ｎチップ電流遅延回路Ｎｄｅｌａｙ₂に入力され、これらを順次加算してＮチップ電流遅延回路Ｎｄｅｌａｙ_M-1から出力される加算電流に出力端子ＴＭから出力される部分相関出力電流を加算することによって、情報の１単位に相当する長さＬを有する拡散符号Ｙの相関処理が行われ、これによって、全体としての相関出力電流が得られる。
【０２１８】
短周期の拡散符号が２種類からなる場合には、１入力（２＋１）出力電流遅延フリップフロップＣＤＦＦｉを用いて電流信号の遅延が行われ、２個の部分相関電流出力手段１０５_kが用いられて、２個の部分相関電流出力手段１０５_kによって２種類の部分相関処理が行われる。その部分相関出力電流はそれぞれ各１入力多出力電流分配回路１５０に入力され、各１入力多出力電流分配回路１５０はその短周期の拡散符号のチップ長の個数分の部分相関電流信号を出力し、この各１入力多出力電流分配回路１５０から出力された部分相関出力電流信号は、拡散符号Ｙの情報に従って部分相関出力符号処理回路１５１によって符号処理が行われた後、部分相関出力電流遅延回路ブロック部１０３に入力される。
【０２１９】
一般に、１種類以上の短周期の拡散符号を繰り返し用いて又は組み合わせて用いて、情報の１単位を構成するチップ情報の配列個数がＬ個の拡散データを形成する場合には、部分相関電流出力手段の段数は短周期の拡散符号の種類の数に等しい。
【０２２０】
一般に、短周期の拡散符号の種類が１種類である場合には、１入力多出力電流遅延フリップフロップＣＤＦＦｉの構造を１入力２出力の構造とするのみで良く、また、部分相関電流出力手段１０５_kも唯１個で良いので、短周期の拡散符号の個数を１周類としてその繰り返し回数をＭ個とした場合の電流源の個数を見積もると以下のようになる。
【０２２１】
１入力２出力電流遅延フリップフロップＣＤＦＦｉ１個当たりの定電流源の個数は、
４＋２＝６
である。
【０２２２】
この電流遅延フリップフロップＣＤＦＦｉをＮ個用いるので、定電流源の総数は６×Ｎ＝６Ｎである。
【０２２３】
１入力Ｍ出力電流分配回路１５０に用いる定電流源の個数はＭ＋１個である。
【０２２４】
部分相関出力電流遅延回路ブロック部１０３の定電流源の個数は、
（Ｎ＋１）×（Ｍ−１）個である。
【０２２５】
従って、この場合の電流源の総個数は、Ｍ×Ｎ＋２Ｍ−５Ｎ＋６個である。
【０２２６】
発明の実施の形態２では、定電流源の個数が、２Ｍ×Ｎ＋３Ｎ−Ｍ−１個であったが、この発明の実施の形態９によれば、Ｍ×Ｎ＋２Ｍ−５Ｎ＋６個であるので、近似的に定電流源の個数をＭ×Ｎ程度削減することができ、実質的に電流源の個数を約半分に削減できる。電流モードの相関器では消費電力が定常的に流れる電流が支配的であるので、定電流源の個数を約半分にできるということは、大幅に電流値を削減できることを意味している。また、部分相関出力電流遅延回路ブロック部１０３のＮチップ電流遅延回路Ｎｄｅｌａｙ_kに電流カットを適用すれば、更にこの部分相関出力電流遅延回路ブロック部１０３の消費電力を少なくすることができるので、回路全体としての消費電力をより一層少なくすることができる。
【０２２７】
なお、１入力Ｍ出力電流分配回路１５０を設けなければならないために、この回路は増えるが、この回路規模は微々たるものであり、このように、短周期の拡散符号の組み合わせからなる拡散符号に対して、図３０に示す回路構成を採用すれば、大幅に回路規模を削減できると共に、その消費電力を抑制できる。
【０２２８】
図３１は図３０に示す部分相関出力電流遅延回路ブロック部１０３の変形例を示す図である。この図３０では、電流加算回路ｉａｄｄ_kの出力が部分相関出力電流遅延回路ブロック部１０３に入力されている。１入力多出力電流遅延回路ブロック部の構成、部分相関電流出力手段の構成は、図３０に示すものと同一であるので、その詳細な説明は省略されている。
【０２２９】
この図３１では、部分相関出力電流遅延回路ブロック部１０３は、１入力２出力電流分配回路Ｂ２０_kとＮチップ電流遅延回路Ｎｄｅｌａｙ_kと部分相関出力符号処理回路１５１とを有し、１入力２出力電流分配回路Ｂ２０_kとＮチップ電流遅延回路Ｎｄｅｌａｙ_kとは交互に接続されている。電流加算回路ｉａｄｄ_kの出力は１入力２出力電流分配回路Ｂ２０₁に入力されている。
【０２３０】
１入力２出力電流分配回路Ｂ２０_kは、その入力端子に入力された部分相関電流を各出力端子から出力し、その一方の出力端子から出力された電流は次段のＮチップ電流遅延回路Ｎｄｅｌａｙ_kに入力され、その他方の出力端子から出力された電流は部分相関出力符号処理回路１５１の入力端子Ｐ（ｋ）ａに入力される。部分相関出力符号処理回路１５１は短周期の拡散符号の符号（＋又は−）に従って、相関電流の符号処理を図３０に示す構成のものと同様に行う。符号が「＋」のときは、入力端子Ｐ（ｋ）ａと出力端子Ｐ（ｋ）ｂとを配線のみを介して接続し、符号が「−」のときはカレントインバータを介してその入力端子Ｐ（ｋ）ａとその出力端子Ｐ（ｋ）ｂとを接続する。各出力端子Ｐ（ｋ）ｂから出力された部分相関電流はワイヤー加算若しくは電流加算回路１５３を介して加算されて相関処理がが実行され、この相関電流信号は電流・電圧変換手段１０８に入力される。
【０２３１】
この図３１に示す変形例は、拡散符号の種類が１種類の場合にのみ用いることができる。図３０に示す回路構成のものでは、１入力Ｍ出力電流分配回路が必要であるが、この図３１に示す回路構成の場合には１入力２出力電流分配回路がＭ−１個必要である。
【０２３２】
しかしながら、１つの回路ブロックを小さく可能であるために、図３０に示す回路構成のものに較べて、分配数の増加による電流信号の誤差を抑制することが可能である。なお、回路規模の大きさと電流源の個数とは、図３０に示すものとほぼ同じである。
【０２３３】
【発明の効果】
本発明は以上説明したように、全体としての回路構成の簡略化を図ったので、電流転送誤差の累積の低減化と同時に消費電力の低減化とを図りつつ、相関検出精度の向上を図ることができるという効果を奏する。
【図面の簡単な説明】
【図１】 本発明に係わる符号分割多重通信装置のブロック図である。
【図２】 送信電波の生成を説明するためのタイミングチャートである。
【図３】 受信電波に基づく電圧信号と相関電流信号との関係を説明するためのタイミングチャートである。
【図４】 図１に示す相関器の内部構成を示すブロック図である。
【図５】 図４に示す電流・電圧変換手段の構成の一例を示す回路図である。
【図６】 図４に示す１入力多出力電流遅延フリップフロップの基本構成を示し、（ａ）はその詳細回路図、（ｂ）はそのタイミングチャートである。
【図７】 図６に示す１入力多出力電流遅延フリップフロップの電流信号のサンプルの順序を説明するためのタイミングチャートである。
【図８】 図４に示す部分相関電流出力手段のスイッチ接続状態の一例を示す図である。
【図９】 図４に示すぺアスイッチの一例を示す詳細回路図である。
【図１０】 図４に示す電流加算回路の詳細構成を示す回路図である。
【図１１】 図４に示すＮチップ電流遅延回路の内部構成を示すブロック図である。
【図１２】 図１１に示すＮチップ電流遅延回路の制御スイッチに与えられるタイミングクロックを示すタイムチャートである。
【図１３】 図１１に示すＮチップ電流遅延回路の詳細回路図である。
【図１４】 図４に示す電流・電圧変換手段の構成の一例を示す図である。
【図１５】 本発明の相関処理の原理を説明するための図であって、（イ）は従来通りＬ個の電流遅延フリップフロップを直列に配列して相関処理を行う場合を示し、（ロ）はその電流遅延フリップフロップをＭ等分してＮ個ずつ配列して部分的に相関処理を行う場合を示す。
【図１６】 図６（ａ）に示す電流源の回路構成の詳細を説明するための図であって、（ａ）は電流源を等価記号で表現し、（ｂ）は電流源をｎチャネルＭＯＳトランジスタにより構成した場合を示している。
【図１７】 １入力多出力電流遅延フリップフロップの他の発明の実施の形態を示す詳細回路図である。
【図１８】 ＭＯＳトランジスタの動作特性を説明するための図であり、（イ）はｎチャネルＭＯＳトランジスタを代表的に示し、（ロ）はその動作特性を示し、（ハ）はｐチャネルＭＯＳトランジスタを代表的に示し、（二）はその動作特性を示す。
【図１９】 ２個のｎチャネルＭＯＳトランジスタが組み合わされたカスコードＭＯＳトランジスタの説明図であり、（イ）はそのカスコードＭＯＳトランジスタを示し、（ロ）は改善された動作特性を示す。
【図２０】 ２個のｐチャネルＭＯＳトランジスタが組み合わされたカスコードＭＯＳトランジスタの説明図であり、（イ）はそのカスコードＭＯＳトランジスタを示し、（ロ）は改善された動作特性を示す。
【図２１】 図１７に示す電流源に図２０に示すカスコードＭＯＳトランジスタを用い、図１７に示すｎチャネルＭＯＳトランジスタに図１９に示すカスコードＭＯＳトランジスタを用いた場合の回路図である。
【図２２】 ｎチャネル等価ＭＯＳＦＥＴの一例を示し、（イ）はｎチャネル等価ＭＯＳＦＥＴの回路構成であり、（ロ）は改善された動作特性を示す図である。
【図２３】 ｐチャネル等価ＭＯＳＦＥＴの一例を示し、（イ）はｐチャネル等価ＭＯＳＦＥＴの回路構成であり、回路構成の一例を示し、（ロ）は改善された動作特性を示す図である。
【図２４】 図１３に示すＮチップ電流遅延回路にレギュレーティッドカスケード回路を適用した場合の回路図である。
【図２５】 図６に示す１入力多出力電流遅延フリップフロップに電流カットを行う場合を説明するためのタイミングチャート図である。
【図２６】 図１３に示すＮチップ電流遅延回路に電流カットを行う場合を説明するためのタイミングチャート図である。
【図２７】 図１７に示すメモリー制御スイッチの存在に起因する電流転送誤差の改善を図るための説明図であり、（イ）は図１７に示すメモリー制御スイッチの詳細回路図であり、（ロ）は図１７に示すメモリー制御スイッチにダミーＭＯＳトランジスタを設けてメモリー制御スイッチの動作特性の改善を図った詳細回路図である。
【図２８】 図１７に示すメモリー制御スイッチに図２７（ロ）に示すメモリー制御スイッチを適用した場合の１入力多出力電流遅延フリップフロップの詳細回路図である。
【図２９】 図１７に示す１入力多出力電流遅延フリップフロップのメモリＭＯＳトランジスタのゲート幅を変更して入力された電流信号の実数倍の電流値を出力することが可能なの回路構成を示す図である。
【図３０】 短周期の拡散符号を用いた相関器の一例を示すブロック図である。
【図３１】 図３０に示す部分相関出力電流遅延回路ブロック部１０３の変形例を示す図である。
【符号の説明】
７…相関器
１００…電圧・電流変換手段
１０１…１入力多出力電流遅延回路ブロック部
１０３…部分相関出力電流遅延回路ブロック部
１０５_k…部分相関電流出力手段[0001]
BACKGROUND OF THE INVENTION
The present invention relates to spread spectrum communication, and more particularly to a low power consumption type code division multiplexing communication apparatus capable of high-speed synchronization.
[0002]
[Prior art]
Conventionally, a code division multiplex communication apparatus has received receiving means for receiving a transmission radio wave generated by multiplying an information signal by spread data consisting of an array of chip information and outputting a voltage signal, and converting the voltage signal into a current signal. Voltage / current conversion means and the same number of sample / hold circuits as the number of chip information arrays, and the current signal is input to the head sample / hold circuit and the current signal is sampled / held based on the clock signal and the previous sample Current delay means for generating a time series of current signals in which an array of chip information is potentially included by sequentially delaying and transferring the current signals held by the hold circuit to the subsequent sample hold circuit; An array of chip information potentially inherent in the time series of the current signal is despread in advance corresponding to the array of chip information. Has been known which is constructed such that the correlation is obtained when consistent with the sequence of chip information over data.
[0003]
[Problems to be solved by the invention]
However, this conventional code division multiplexing communication device fixes the despread data and sequentially transfers the current signal to the sample-and-hold circuit at the subsequent stage to generate a time series of the current signal in which the chip information array is inherently contained. Therefore, there is a problem in that the current transfer error of the sample and hold circuit for each stage is accumulated at each transfer.
[0004]
The present invention has been made in view of the above circumstances, and is a code division multiplexing communication apparatus capable of improving correlation detection accuracy while reducing accumulation of current transfer errors and power consumption. I will provide a.
[0005]
[Means for Solving the Problems]
The code division multiplex communication apparatus according to claim 1, receiving means for receiving a transmission radio wave generated by multiplying an information signal by spreading data composed of an array of chip information and outputting a voltage signal; and Voltage / current conversion means for converting into current signals, N current delay flip-flops obtained by dividing the number L of arrayed chip information by an integer M, and current signals held in each current delay flip-flop are 1 At the same time, transfer to the current delay flip-flop at the next stage every chip time, and at the same time, M currents that arrive during N chip time and are held in time series in each current delay flip-flop are output in parallel. A one-input multi-output current delay circuit block having a current signal output terminal, and current signals from the current delay flip-flops are input in parallel and correspond to the spread data M parts that switch current connection paths so as to obtain a partial correlation output current based on the reference data and add a current signal output from each of the current delay flip-flops to output a partial correlation current Correlated current output means and a portion for adding M partial correlation currents output from each of the partial correlation current output means and delayed in time series by N chip time for each chip time in order to obtain a correlation current signal A correlation output current delay circuit block unit, and a demodulator that receives the correlation current signal and demodulates the original information signal based on the correlation current signal are provided.
[0006]
The code division multiplex communication apparatus according to claim 2, wherein the voltage / current conversion unit outputs a negative current signal when the voltage signal is positive and outputs a positive current signal when the voltage signal is negative. As described above, the circuit is configured by a circuit in which a differential amplifier circuit and a voltage follower circuit are connected.
[0007]
The code division multiplexing communication device according to claim 3, wherein the partial correlation current output unit is connected to the current signal output terminal and the connection state is changed based on the reference data, and the connection state of the switch row And a current adding means for adding the current signals output from the respective current signal output terminals to output the partial correlation current.
[0008]
The code division multiplexing communication apparatus according to claim 4, wherein each of the current delay flip-flops includes a first data holding unit and a second data holding unit, and the first clock signal, the first clock signal, The current signal is sampled by the first data holding unit at the rising edge of the first clock signal, and the current signal at the falling edge of the first clock signal. Held in the first data holding unit, the current signal is transferred to the second data holding unit at the rising edge of the second clock signal, and the second data holding unit is transferred to the second data holding unit at the falling edge of the second clock signal. While holding the current signal, the sampled current signal is transferred to the current delay flip-flop of the next stage, and the current delay flip-flop of the next stage is transferred from the second data holding unit. The same current signal and the current signal output and outputs toward the M switch array.
[0009]
The code division multiplexing communication apparatus according to claim 5 is characterized in that the current delay flip-flop has a current mirror circuit including a current source and a memory MOS transistor.
[0010]
The code division multiple communication apparatus according to claim 6 is characterized in that the number of the memory MOS transistors is one.
[0011]
The code division multiple communication apparatus according to claim 7 is characterized in that the memory MOS transistor is composed of an n-channel MOS transistor.
[0012]
The code division multiplex communication apparatus according to claim 8 is characterized in that the current source is constituted by a p-channel MOS transistor.
[0013]
The code division multiple communication apparatus according to claim 9 is characterized in that the n-channel MOS transistor is configured by connecting two n-channel MOS transistors in series in order to improve saturation characteristics.
[0014]
The code division multiple communication apparatus according to claim 10 is characterized in that the n-channel MOS transistor is composed of an equivalent MOSFET in which an n-channel MOSFET and a p-channel MOSFET are combined in order to improve saturation characteristics.
[0015]
The code division multiplex communication apparatus according to claim 11, wherein the equivalent MOSFET includes three n-channel MOSFETs and one p-channel MOSFET, and operates as an n-channel MOSFET as a whole. To do.
[0016]
According to a twelfth aspect of the present invention, the p-channel MOS transistor is configured by connecting two p-channel MOS transistors in series in order to improve saturation characteristics.
[0017]
The code division multiple communication apparatus according to claim 13 is characterized in that the p-channel MOS transistor is composed of an equivalent MOSFET in which an n-channel MOSFET and a p-channel MOSFET are combined in order to improve saturation characteristics.
[0018]
The code division multiplex communication apparatus according to claim 14, wherein the equivalent MOSFET includes three p-channel MOSFETs and one n-channel MOSFET, and operates as a p-channel MOSFET as a whole. To do.
[0019]
The code division multiple communication apparatus according to claim 15 is characterized in that a current signal that is a real number multiple of the current signal input to each of the current delay flip-flops is output from the current signal output terminal.
[0020]
17. The code division multiplexing communication apparatus according to claim 16, wherein the M switch trains have N pair switches, and the reference data is assigned to each pair switch, and a partial correlation current is changed by switching a current path. It is characterized by obtaining.
[0021]
18. The code division multiplexing communication apparatus according to claim 17, wherein the partial correlation current based on the current signal that arrives during the N chip time and is held in each of the current delay flip-flops is sequentially delayed by N chip time. A correlation current signal is obtained by adding in time series.
[0022]
The code division multiplex communication apparatus according to claim 18, wherein the partial correlation output current delay circuit block unit has N + 1 current delay elements, and receives a partial correlation current signal delayed by N chips for each chip time. It is characterized by outputting.
[0023]
The code division multiple communication apparatus according to claim 19 is characterized in that the current delay element includes one memory MOS transistor and one current source.
[0024]
The code division multiplex communication apparatus according to claim 20 is characterized in that the current delay element comprises a cascode MOS transistor circuit or a regulated cascade circuit.
[0025]
The code division multiplexing communication apparatus according to claim 21, wherein each current delay flip-flop causes a steady current to flow through the current source only during a time required for sampling the current signal and outputting the current signal. During this time, the steady current is cut off.
[0026]
In the code division multiplexing communication device according to claim 22, the current source of the partial correlation output current delay circuit block unit allows a steady current to flow only during the time between sampling of the partial correlation current and its output, and at other times. During this time, the steady current is cut off.
[0028]
  Claim 23In the code division multiplex communication device described in (2), current / voltage conversion means for converting the correlation current signal into a voltage signal is provided between the partial correlation output current delay circuit block unit and the demodulator. Features.
[0029]
  Claim 24In the code division multiplex communication device described in (1), the current / voltage conversion means receives the correlation current signal and is applied with a bias voltage to output a voltage signal of the sum of the current signal conversion voltage and the bias voltage. Corresponding to the correlation current signal by inputting the sum voltage signal and applying a bias voltage having the same value as the bias voltage and removing the bias voltage from the sum voltage signal. And a second differential amplifier circuit that outputs a voltage signal to be output.
[0030]
  Claim 25In the code division multiplex communication apparatus described in 1), the spreading code is one or more types of short-period spreading codes, and the one or more types of short-period spreading codes are used repeatedly or in combination to make one unit of information. The number of arrangements of chip information constituting L is spread data, and the number of partial correlation current output means is equal to the number of types of short-cycle spreading codes.
[0031]
DETAILED DESCRIPTION OF THE INVENTION
[0032]
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1
(Explanation of block diagram of receiving side code division multiplexing communication device)
FIG. 1 is a block diagram showing a configuration of a receiving side code division multiplexing communication apparatus according to the present invention. In FIG. 1, 1 is a receiving antenna, 2 is a mixer, 3 is a local oscillator, 4 is a detector, 5 is a correlator, 6 is a reference data sequence generating means, and 7 is a demodulator. The reception antenna 1 receives a transmission radio wave transmitted by a transmission device (not shown). This transmission radio wave is generated by multiplying the information signal by spread data composed of an array of chip information. The information signal is bit information in this embodiment. The bit information consists of “0” and “1”. This bit information is generated in time series, and the frequency that is the reciprocal of the generation period of this bit information is the baseband frequency. The bit information “1” corresponds to, for example, a positive voltage, and the bit information “0” corresponds to a negative voltage (a reverse-phase voltage).
[0033]
(Explanation of transmitted radio waves)
FIG. 2A shows a section of bit information “1” (data packet 1 symbol). The bit information “1” is multiplied by spread data including an array of chip information “0” and chip information “1”. A PN code (pseudo-noise code) is used for the spread data. The PN code includes an M-sequence code, a Gold code, an orthogonal M-sequence code, an orthogonal Gold code, an orthogonal code generated by a Walsh function, and the like. Any of these may be used. The orthogonal M-sequence code, the orthogonal Gold code, and the orthogonal code generated by the Walsh function have correlation characteristics described below and are suitable for channel division of the code division multiplexing communication apparatus. That is, in the case of an orthogonal code, the autocorrelation function has a maximum correlation value when the phase difference is zero. The cross-correlation function has a correlation value of zero when the phase difference is zero. In this embodiment, description will be made assuming that an M-sequence code is used as the PN code.
[0034]
The array number L of chip information is, for example, 128. Note that the number L of arrangements of chip information may be referred to as “chip length”. FIG. 2B shows signal voltages corresponding to the chip information array, where “+1” corresponds to the chip information “1” and “−1” corresponds to the chip information “0”. The signal shown in FIG. 2 (b) is multiplied by the signal shown in FIG. 1 (a) to generate the spread modulated wave shown in FIG. 2 (c). The spread modulated wave shown in FIG. ) Is multiplied by the carrier wave shown in FIG. 2 to generate a spectrum-spread transmission radio wave as shown in FIG. 2B, whereby the bit information “1” is divided into 128 chips and transmitted.
[0035]
In this embodiment, the information bits are described as being divided into 128 chips. However, for convenience of understanding, bit information “1” and chips are used for the case where the number of chip information arrays is seven. The relationship between information and signal voltage is shown in FIGS. 2 (f) and 2 (g). Here, “1110010” in FIG. 2G is one of the 7-chip M series. When transmitting bit information “0”, since bit information “0” corresponds to a negative voltage, the spread modulated wave has an opposite phase to the spread modulated wave shown in FIG.
[0036]
In the description of FIG. 2, “code 1 sequence” is assigned to one data packet symbol, but two or more “code sequences” may be assigned to one data packet symbol.
[0037]
The mixer 2 mixes the received radio wave with the signal output from the local oscillator 3 and outputs an IF (intermediate frequency) signal, and the detector 4 synchronously detects the output of the mixer 2.
[0038]
Here, the detector only needs to extract a spread information signal inherent in the IF signal, such as a carrier synchronous detector, a delay detector, an IQ detector, or the like.
[0039]
The reception antenna 1, the mixer 2, the local oscillator 3, and the detector 4 constitute reception means. The detector 4 outputs a voltage signal corresponding to the received radio wave toward the correlator 5. FIG. 3A shows the received radio wave. FIG. 3B shows a voltage signal corresponding to the spread modulated wave detected by the detector 4.
[0040]
(Description of Correlator 5)
As shown in FIG. 4, the correlator 5 includes a voltage / current conversion means (V / IC) 100, a one-input multiple-output current delay circuit block unit 101, and a parallel current path switching switch circuit block unit 102 in this embodiment. And a partial correlation output current delay circuit block unit 103 and a current / voltage conversion means 108.
[0041]
(Description of voltage / current conversion means 100)
As shown in FIG. 5, the voltage / current converting means 100 outputs a negative current signal Iout when the voltage signal Vin is positive, and outputs a positive current signal Iout when the voltage signal Vin is negative. The differential amplifier circuit 100A and the voltage follower circuit 100B are connected to each other.
[0042]
The differential amplifier circuit 100A includes an operation amplifier (hereinafter abbreviated as an operational amplifier) OP1. The voltage signal Vin input to the terminal T1 is applied to the negative input terminal of the operational amplifier OP1 via the resistor R1. The plus input terminal of the operational amplifier OP1 is grounded through a resistor R4. The output terminal of the operational amplifier OP1 is connected to its negative input terminal via a resistor R2.
[0043]
The voltage follower circuit 100B includes an operational amplifier OP2. The output terminal of the operational amplifier OP1 is connected to the positive input terminal of the operational amplifier OP2 through the resistor R5. The output terminal of the operational amplifier OP2 is connected to its negative input terminal, and is connected to the positive input terminal of the operational amplifier OP1 through a resistor R3. The operational amplifier OP1 operates as a differential amplifier, the operational amplifier OP2 operates as a voltage follower, and the current signal Iout is output from the output terminal T2 to the one-input multiple-output current delay circuit block unit 101 as the current signal Iin. .
[0044]
Here, when the ratio R2 / R1 of the resistors R1 and R2 is (R2 / R1 = 1) and the ratio R4 / R3 of the resistors R3 and R4 is (R4 / R3 = β), the current signal Iout is expressed by the following equation: Is required.
[0045]
Iout = − (2β / (1 + β)) × (Vin / R5)
The above equation holds true whether the voltage signal Vin is positive or negative, and R4 / R3 = β = 1.
It is transformed into the following formula.
[0046]
Iout =-(Vin / R5)
For example, when the amplitude value of Vin is ± 1 volt and the resistance value of the resistor R5 is 20 kilohms, the current signal Iout becomes a current of minus plus 50 microamperes. The voltage / current converting means 100 may be provided in the receiving means.
[0047]
Note that the voltage-current converter can be configured using a differential amplifier in addition to using an operational amplifier.
[0048]
(Description of 1-input multiple-output current delay circuit block unit 101)
As shown in FIG. 4, the 1-input multiple-output current delay circuit block unit 101 includes N 1-input multiple-output current delay flip-flops CDFFi (i = 1, 2,..., N). Each one-input multiple-output current delay flip-flop CDFFi (i = 1, 2,..., N) has one current signal input terminal T01 and a current signal output terminal T02 that outputs a current signal to the next stage. The current signal input terminal T01 of the one-input multi-output current delay flip-flop CDFF1 is connected to the output terminal T2 of the voltage / current conversion means 100.
[0049]
The current signal output terminal T02 of the one-input multi-output current delay flip-flop CDFF1 is connected to the current signal input terminal T01 of the next-stage one-input multi-output current delay flip-flop CDFF2, and each one-input multi-output current delay flip-flop CDFFi ( The current signal input terminal T01 of i = 3,..., N) is connected to the current signal output terminal T02 of the preceding one-input multi-output current delay flip-flop CDFFi (i = 2,..., N−1). The current signal output terminal T02 of the multi-output current delay flip-flop CDFFi (i = 3,..., N−1) is the current signal input terminal of the subsequent one-input multi-output current delay flip-flop CDFFi (i = 4,..., N). Connected to T01.
[0050]
Each of the one-input multi-output current delay flip-flops CDFFi (i = 1, 2,..., N) outputs M output terminals T1 that output current signals in parallel to the parallel current path switching circuit block unit 102._ij(J = 1, 2,..., M). Accordingly, the 1-input multiple-output current delay flip-flop CDFFi has one input terminal and (M + 1) output terminals.
[0051]
When the arrangement number L of chip information is 128, the arrangement number N of 1-input multi-output current delay flip-flop CDFFi and its output terminal T1_ijThe product (N × M) of the number M of (j = 1, 2,..., M) is 128 times P (P is an integer of 1 or more, P = 2 in the case of double sampling). Number N of 1-input multiple-output current delay flip-flop CDFFi and its output terminal T1_ijDetermine the number of Unless otherwise specified, the following description will be made assuming that P = 1.
[0052]
An example of the structure of the one-input multiple-output current delay flip-flop CDFFi is shown in FIG. Here, the structure of the first-stage multiple-input current delay flip-flop CDFF1 in the first stage will be described as an example, but other single-input multiple-output current delay flip-flops CDFFi (i = 2,..., N) are also described. Its structure is the same as the one-input multiple-output current delay flip-flop CDFF1.
[0053]
As shown in FIG. 6A, the one-input multiple-output current delay flip-flop CDFF1 includes a front-stage current mirror circuit (first data holding unit) CMR1, and a rear-stage current mirror circuit (second data holding unit) CMR2. And a current mirror circuit CMR3. The current mirror circuit CMR1 is a memory MOS transistor (n-channel MOS transistor) M₁₀₁, M₁₀₂Sample control switch S_Ten, Constant current source I_Ten, I₁₁Have
[0054]
Memory MOS transistor M₁₀₁Source of constant current I_TenAnd is connected to a power source Vdd and to a current signal input terminal T01. The memory MOS transistor M₁₀₁Of the memory MOS transistor M₁₀₁Is connected to its source and the sample control switch S_TenThrough the memory MOS transistor M₁₀₂Connected to the gate. Memory MOS transistor M₁₀₂Is drained to ground and its source is a constant current source I.₁₁Is connected to the power supply Vdd via the memory MOS transistor M₁₀₂Parasitic capacitance Cp between the gate and drain of₁Exists.
[0055]
The current mirror circuit CMR2 includes a memory MOS transistor M₂₀₁, M₂₀₂Sample control switch S₂₀, Constant current source I₁₂, I₁₃Have Memory MOS transistor M₂₀₁Source of constant current I₁₂Is connected to the power supply Vdd via the memory MOS transistor M₁₀₂Connected to the source.
[0056]
Memory MOS transistor M₂₀₁The drain of is grounded. The memory MOS transistor M₂₀₁The gate of the memory MOS transistor M₂₀₁Connected to the source of the sample control switch S₂₀Through the memory MOS transistor M₂₀₂Connected to the gate of the memory MOS transistor M₂₀₂Parasitic capacitance Cp between the gate and drain of₂Exists.
ing. Memory MOS transistor M₂₀₂The drain of is grounded. The memory MOS transistor M₂₀₂Source of constant current I₁₃And is connected to the power supply Vdd and to the current signal output terminal T02.
[0057]
Sample control switch S_Ten, S₂₀Is controlled to be turned on and off by the clock signals SA and SB shown in FIG. 6B, and the phases of the clock signals SA and SB are shifted so as not to overlap each other, and the clock signals SA and SB are within a time corresponding to one chip. Is generated once for each sample control switch S_TenIs turned on by the rising edge of the clock signal SA, and the sample control switch S₂₀Is turned on at the rising edge of the clock signal SB.
[0058]
The current mirror circuit CMR3 includes a memory MOS transistor M₃₀₁, M₃₀₂, Constant current source I₁₄, I₁₅Have Memory MOS transistor M₃₀₁The gate of the memory MOS transistor M₂₀₂Connected to the gate. Memory MOS transistor M₃₀₁Of the memory MOS transistor M₃₀₁Source of constant current I₁₄And is connected to the power supply Vdd via the memory MOS transistor M₃₀₂Connected to the source. Memory MOS transistor M₃₀₂Source of constant current I₁₅Is connected to the power supply Vdd via the memory MOS transistor M₃₀₂Connected to the gate. Memory MOS transistor M₃₀₂The drain of is grounded.
[0059]
Memory MOS transistor M₃₀₂Is gated with M memory MOS transistors M₄₀₁, M₄₀₂... M_40j... M_40MConnected in parallel to the gate. Each memory MOS transistor M_40jSource of constant current I_16j(J = 1, 2,..., M) and connected to the power supply Vdd, and each output terminal T1_1jAnd their drains are grounded.
[0060]
For convenience of the following explanation, each memory MOS transistor M₁₀₁, M₁₀₂, M₂₀₁, M₂₀₂, M₃₀₁, M₃₀₂, M_40jIt is assumed that the sizes of (j = 1, 2,..., M) are all equal.
[0061]
Next, the operation of the 1-input multiple-output current delay flip-flop CDFF1 will be described with reference to the operation timing chart of FIG.
[0062]
Here, for convenience of explanation, the constant current source I_Ten~ I₁₅, I_16jIt is assumed that the current value flowing through (j = 1, 2,..., M) is “J”.
[0063]
Now, it is assumed that the current signal Iin is input from the voltage / current conversion unit 100 to the current mirror circuit CMR1 of the one-input multiple-output current delay flip-flop CDFF1 through the current signal input terminal T01 at time t = t0. This current signal Iin is supplied from the memory MOS transistor M.₁₀₁Into the source of the memory MOS transistor M₁₀₁The current flowing between the drain and source of the_TenIs an ideal current source, it is “J + Iin”.
[0064]
Next, when the clock signal SA becomes high at time t = t1, the sample control switch S_TenIs turned on. At this time, since the clock signal SB is low, the sample control switch S₂₀Remains off. Sample control switch S_TenIs turned on, the memory MOS transistor M₁₀₁Gate and memory MOS transistor M₁₀₂Is connected to the gate. At this time, the memory MOS transistor M₂₀₁Gate and memory MOS transistor M₂₀₂The gate is disconnected.
[0065]
Memory MOS transistor M₁₀₁Current system and memory MOS transistor M₁₀₂Current control system of the sample control switch S_TenIs turned on to form a current mirror circuit, and the memory MOS transistor M₁₀₂Between the drain and source of the memory MOS transistor M₁₀₁The voltage necessary for flowing the same current “J + Iin” as the current “J + Iin” flowing in the memory MOS transistor M₁₀₂Applied to the gate.
[0066]
Next, at time t = t2, the clock signal SA goes low. At this time, the clock signal SB remains low. When the clock signal SA goes low, the sample control switch S_TenIs turned off and the memory MOS transistor M₁₀₁Gate and memory MOS transistor M₁₀₂The gate is disconnected.
[0067]
At this time, the memory MOS transistor M₁₀₂The charge necessary for the current “J + Iin” to flow between the gate and the drain of the memory MOS transistor Mp is kept due to the presence of the parasitic capacitance Cp.₁₀₂The gate voltage of the memory MOS transistor M is maintained constant.₁₀₂The current “J + Iin” continues to flow between the drain and the source. The current Iin is the memory MOS transistor M₁₀₁Gate and memory MOS transistor M₁₀₂Is disconnected from the gate of the memory MOS transistor MMR of the current mirror circuit CMR2.₂₀₁From the source of the memory MOS transistor M₁₀₂Will flow into the source.
[0068]
For this reason, the memory MOS transistor M₂₀₁The current flowing between the drain and the source is maintained at “J-Iin”. Next, when the clock signal SB becomes high at time t = t3, the memory MOS transistor M₂₀₁Gate and memory MOS transistor M₂₀₂Is connected to the gate of the memory MOS transistor M₂₀₁Gate voltage and memory MOS transistor M₂₀₂Is equal to the gate voltage. As a result, the memory MOS transistor M₂₀₂The current flowing between the source and drain of the memory MOS transistor M₂₀₁This is the same as the current “J-Iin” that flows between the source and drain of each other. Therefore, the current Iout = + Iin is output from the current output terminal T02 to the next-stage 1-input multiple-output current delay flip-flop CDFF2.
[0069]
Also, the memory MOS transistor M₂₀₁Gate voltage and memory MOS transistor M₃₀₁Is equal to the gate voltage of the memory MOS transistor M₃₀₁The current flowing between the source and drain of the transistor also becomes “J-Iin”. Therefore, the memory MOS transistor M₃₀₁From the current system of memory MOS transistor M₃₀₂A current signal Iin flows toward the current system of the memory MOS transistor M₃₀₂A current of “J + Iin” flows between the source and the drain. Memory MOS transistor M₃₀₂The gate of each memory MOS transistor M_40jEach memory MOS transistor M is connected to the gate of (j = 1, 2,..., M)._40jThe gate voltage of (j = 1, 2,..., M) is the memory MOS transistor M₃₀₂Is equal to the gate voltage of each memory MOS transistor M_40jA current “J + Iin” flows between the source and drain of (j = 1, 2,..., M). Therefore, each output terminal T_1j(J = 1, 2,..., M), the current signal “Iin” is transferred from each memory MOS transistor M._40j(J = 1, 2,..., M), and each output terminal T_1jA current signal of “−Iin” flows out from (j = 1, 2,..., M).
[0070]
Next, when the clock signal SB is turned off at time t = t4, the sample control switch S₂₀Turns off and the memory MOS transistor M₂₀₁Gate and memory MOS transistor M₂₀₂The gate is disconnected. At this time, the memory MOS transistor M₂₀₂The charge necessary for the current “J-Iin” to flow between the gate and the drain of the memory MOS transistor Mp due to the presence of the parasitic capacitance Cp.₂₀₂The gate voltage of the memory MOS transistor M is kept constant.₂₀₂Thus, the current “J-Iin” continues to flow between the drain and source.
[0071]
Next, when the clock signal SA becomes high again at time t = t5, a new current signal Iin is generated by the memory MOS transistor M.₁₀₁The current signal Iin is sampled and held between time t = t6 and t = t8. In this way, the one-input multiple-output current delay flip-flop CDFF1 samples the current signal Iin at the timing of the clock signal SA, holds the current signal Iin at the timing of the clock signal SB, and receives the current signal Iin from the current output terminal T02. While outputting to the next-stage 1-input multiple-output current delay flip-flop CDFF2, each output terminal T1_ijThe current signal “−Iin” is output from (j = 1, 2,..., M) toward the parallel current path changeover switch circuit block unit 102.
[0072]
Therefore, the 1-input multiple-output current delay flip-flop CDFFi (i = 1, 2,..., N−1) holds the current signal Iin with the clock signal SA within one chip time and temporarily holds with the clock signal SB. Then, the current signal Iin is transferred to the next-stage multi-input current delay flip-flop CDFFi (i = 2,..., N), and the current signal “−Iin” is directed toward the parallel current path switch circuit block unit 102. Is output.
[0073]
Therefore, the current signal Iin is delayed by one chip time and transferred to the next-stage 1-input multiple-output current delay flip-flop CDFFi, and at the same time, the current signal “−Iin” is directed to the parallel current path switching circuit block unit 102. Is output.
[0074]
(Description of parallel current path switching switch circuit block unit 102)
As shown in FIG. 4, the parallel current path changeover switch circuit block unit 102 includes M stages of partial correlation current output means 105._k(K = 1, 2,..., M).
[0075]
The partial correlation current output means 105_kIs switch row 105S_kAnd current adding circuit iadd_kIt consists of and. The switch row 105S_kN current input terminals T2_ik(I = 1, 2,..., N) and the pair switch 104_ikAnd two signal output lines T31_k, T32_k(K = 1, 2,..., M). Pair switch 104_ikHas a pair of switches S1 and S2, and each switch S1 has an output terminal T32._kEach switch S2 is connected to the output terminal T31._kIt is connected to the. Thus, the j-th terminal of each one-input multiple-output current delay flip-flop CDFFi (i = 1, 2,..., N) is connected to each pair switch 104ik (i = 1, 2,..., N) in the k-th stage. T1_ijThe current signal “−Iin” output from (j = k) is input.
[0076]
For example, one switch S1 of the pair of switches S1 and S2 is turned on when the reference data is “0” and turned off when the reference data is “1”. The other switch S2 is turned on when the reference data is “1” and turned off when the reference data is “0”. For example, as shown in FIG._kWhen the reference data “100... 0... 0” is assigned to “1” (only the head is “1” and the others are “0”), the switches S1 and S2 operate as shown in FIG.
[0077]
Current adding circuit iadd_kIs the current inverter CR_k(K = 1, 2,..., M) and each current inverter CR_kThe input terminals (k = 1, 2,..., M) are output terminals T31._kConnected to each current inverter CR_kThe output terminals (k = 1, 2,..., M) are output terminals T32._kSignal line T41 connected to_k(K = 1, 2,..., M). Here, each current inverter CR_kEach output terminal T31 through which a current signal corresponding to the reference sign “1” flows._kEach current inverter CR_kEach output terminal T32 through which a current signal corresponding to the reference sign “0” flows._kIt is good also as connecting to.
[0078]
Here, in the one-input multiple-output current delay flip-flop CDFFi (i = 1, 2,..., N), the old current signal Iin is held in order from the left to the right._ikIn (i = 1, 2,..., N), old current signals Iin flow simultaneously from left to right. The current signal Iin corresponding to the reference data “1” is supplied to each current inverter CR._kIs inverted and added to the current signal Iin corresponding to the reference data “0”.
[0079]
(Pair switch 104_ikSpecific composition)
Each pair switch 104_ik(I = 1, 2,..., N) includes, for example, an n-type MOS transistor M20 and a p-type MOS transistor M21 shown in FIG. The gate of the n-type MOS transistor M20 and the gate of the p-type MOS transistor M21 are connected to the output terminal T9 of the reference data series generating means 6._ikThe drain of the n-type MOS transistor M20 and the source of the p-type MOS transistor M21 are connected to the output terminal T1._ij(I = 1, 2,..., N), and the source of the n-type MOS transistor M20 is the output terminal T32._kThe drain of the p-type MOS transistor M21 is connected to the output terminal T31._kIt is connected to the.
[0080]
Output terminal T9_ikWhen the reference data “0” is input from the n-type MOS transistor M20, the n-type MOS transistor M20 is turned on (drain-source is conductive), and the p-type MOS transistor M21 is turned off (drain-source is non-conductive). When the data is “0”, the output terminal T1_ijAnd output terminal T132_kAre connected. The output terminal T9_ikWhen the reference data “1” is input from the n-type MOS transistor M20, the n-type MOS transistor M20 is turned off (drain-source is non-conductive), and the p-type MOS transistor M21 is turned on (drain-source is conductive). When the data is “1”, the output terminal T1_ijAnd output terminal T31_kAre connected.
[0081]
(Current adding circuit iadd_kDescription)
Current adding circuit iadd_kThe time-series current signals held in the current delay flip-flops CDFFi are simultaneously input to output a partial correlation current signal. This current adding circuit iadd_kComprises a first addition system 106A and a second addition system 106B. As shown in FIG. 10, the first addition system 106A includes n-type MOS transistors M32 and M33 with common source and constant current sources A32 and A33. The second addition system 106B includes common-source n-type MOS transistors M30 and M31 and constant current sources A30 and A31.
[0082]
The drain of the n-type MOS transistor M30 is the output terminal T32_kAnd is connected to the power supply Vdd via the current source A30. The gate of the n-type MOS transistor M30 is connected to its drain. The drain of the n-type MOS transistor M31 is connected to the power supply Vdd via the current source A31 and is connected to the drain of the n-type MOS transistor M32. The gate of the n-type MOS transistor M31 is connected to the gate of the n-type MOS transistor M30.
[0083]
The drain of the n-type MOS transistor M32 is the output terminal T31._kAnd is connected to the power source Vdd via the current source A32. The gate of the n-type MOS transistor M32 is connected to its drain. The gate of the n-type MOS transistor M33 is connected to the gate of the n-type MOS transistor M32. The drain of the n-type MOS transistor M33 is connected to the power supply Vdd via the current source A33 and the output terminal T51._kIt is connected to the.
[0084]
The output terminal T32 is connected to the drain of the n-type MOS transistor M30 of the second addition system 106B._kCurrent Im flows from the output terminal T31 to the n-type MOS transistor M32 of the first addition system 106A._kCurrent Ip flows in.
[0085]
The current system of the n-type MOS transistor M30 and the current system of the n-type MOS transistor M31 form a current mirror circuit, and the same current “J + Im” as the current “J + Im” flowing between the drain and source of the n-type MOS transistor M30 Flows between the drain and source of the n-type MOS transistor M31. Similarly, the current system of the n-type MOS transistor M32 and the current system of the n-type MOS transistor M33 also constitute a current mirror circuit. An output terminal T31 is provided between the drain and source of the n-type MOS transistor M32._kThe current “J + (Ip−Im)” obtained by adding the current J from the current source A32 to the current “(Ip−Im)” obtained by subtracting the current Im from the current Ip flowing into the current Ip flows into the drain − of the n-type MOS transistor M33. The same current “J + (Ip−Im)” that flows between the drain and source of the n-type MOS transistor M32 flows between the sources, and as a result, the output terminal T51_kThe output current Iout output from is “− (Ip−Im)”. This output current Iout is a partial correlation current.
[0086]
Reference code assignment will be described later. Next, the partial correlation output current delay circuit block unit 103 will be described.
[0087]
(Description of Partial Correlation Output Current Delay Circuit Block 103)
As shown in FIG. 4, the partial correlation output current delay circuit block unit 103 includes M−1 N-chip current delay circuits Ndelay._k(K = 1, 2,..., M−1). N chip current delay circuit Ndelay_lInput terminal T51_k(K = 1, 2,..., M−1) is the partial correlation current output means 105._k(K = M−1,..., 2) signal output line T41_kIt is connected to the. The N-chip current delay circuit Ndelay_k(K = 1, 2,..., M-2) output terminal T52_l(L = 1, 2,..., M−2) is the next stage N-chip current delay circuit Ndelay_k(K = 2,..., M−1) input terminal T51_k(K = 2,..., M−1). N chip current delay circuit Ndelay_M-1Output terminal T52_M-1The signal output line T41₁Output terminal T51_MAt the same time, it is connected to the input terminal T61 of the current / voltage conversion circuit 108.
[0088]
Each N-chip current delay circuit Ndelay_k(K = 1, 2,..., M−1) represents “N + 1” current memory elements D as shown in FIG.₁, D₂... D_p... D_{n + 1}Have Each current memory element D_pOn the input side of (p = 1, 2,..., N + 1), an input control switch Sdin for controlling the input of the partial correlation current Iin._p(P = 1, 2,..., N + 1) are connected to each current memory element D._pOn the output side of (p = 1, 2,..., N + 1), an output control switch Sdout for controlling the output of the current signal Iout._p(P = 1, 2,..., N + 1) are connected. Input control switch Sdin_p(P = 1, 2,..., N + 1), output control switch Sdout_p(P = 1, 2,..., N + 1) are turned on and off by timing clock pulses PC and PC ′ shown in FIG. The timing clock pulses PC and PC 'are input control switch Sdin for a time corresponding to one chip time._p(P = 1, 2,..., N + 1), output control switch Sdout_p(P = 1, 2,..., N + 1) is turned on. Each input control switch Sdin_pFor (p = 1, 2,..., N + 1), the timing clock pulse PC is generated every time corresponding to n + 1 chip time, and each current memory element D_p(P = 1, 2,..., N + 1) holds the input partial correlation current Iin for n chip times.
[0089]
Each input control switch Sdout_pFor (p = 1, 2,..., N + 1), the timing clock pulse PC 'is also generated every time corresponding to n + 1 chip time._pFor (p = 1, 2,..., N + 1), there is an n chip time delay between the timing clock pulse PC and the timing clock pulse PC ', and thus each current memory element D_p(P = 1, 2,..., N + 1) holds the partial correlation current Iin for n chip times, then outputs the partial correlation current Iin, and captures and holds the new partial correlation current Iin again. .
[0090]
That is, each current memory element D_p(P = 1, 2,..., N + 1) holds a partial correlation current shifted every one chip time, and each N chip current delay circuit Ndelay_k(K = 1, 2,..., M−1), after the current memory element holding the oldest partial correlation current outputs the partial correlation current, a new partial correlation current is taken in and stored. It will be.
[0091]
FIG. 13 shows each N-chip current delay circuit Ndelay._kSpecific examples of (k = 1, 2,..., M−1) are shown. Each current memory element D_pIs constant current source I100_pAnd memory MOS transistor M100_pIt consists of and. Memory MOS transistor M100_pIs the switch SdSw between its gate and source_pConnected through. The memory MOS transistor M100_pIs the constant current source I100_pConnected to the memory MOS transistor M100_pThe drain of is grounded. Input control switch Sdin_pAnd output control switch Sdout_pIs the signal line L100_pConnected through. Each output control switch Sdout_p(P = 1, 2,..., N + 1) are connected to the current inverter 109. Switch SdSw_pIs the input control switch Sdin_pIt is turned on at the same time.
[0092]
Each constant current source I100_pThe current J flows through (p = 1, 2,..., N + 1), for example, the input control switch Sdin.₁Output control switch Sdout when₁Is off. Input control switch Sdin₁Is turned on, the partial correlation current Iin is changed to the signal line L100.₁And the switch SdSw₁Are simultaneously turned on, the memory MOS transistor M100₁Is set such that a current of J + Iin flows between the source and the drain.
[0093]
Input control switch Sdin₁At the same time the switch SdSw₁Is turned off, so that the memory MOS transistor M100₁Are held at a voltage necessary to pass a current of J + Iin. This gate voltage continues to be held for n chip times. After the n chip time has elapsed, the output control switch Sdout₁Is turned on, the memory MOS transistor M100₁Output control switch Sdout because the voltage of the gate of the output is held at a voltage necessary to pass the current of J + Iin.₁The partial correlation current Iin passes through the memory MOS transistor M100 via₁Will be drawn into the current system. Therefore, the N-chip current delay circuit Ndelay shown in FIG._kAccording to a specific example (k = 1, 2,..., M−1), each current memory element D₁, D₂... D_p... D_{n + 1}Respectively outputs the partial correlation current Iin held after the elapse of n chip time. According to this specific example, the partial correlation current Iin is equal to each current memory element D.₁, D₂... D_p... D_{n + 1}Sdin_pThe partial correlation current Iin as an input signal input via the output control switch Sdout_pThe sign of the partial correlation current Iin output via the signal is inverted. Therefore, the current inverter 109 is provided on the output side in order to make the sign of the output signal Iout coincide with the sign of the partial correlation current Iin.
[0094]
(Current / voltage conversion means)
The output current Iout as the correlation current signal is input to the current / voltage conversion means (I / VC) 108 via the output terminal T61. This current / voltage conversion means 108 exists between the partial correlation output current delay circuit block unit 103 and the demodulator 7 and converts the correlation current signal into a voltage signal. As shown in FIG. 14, the current / voltage conversion means 108 includes a first differential amplifier circuit 108A and a second differential amplifier circuit 108B. The first differential amplifier circuit 108A has an operation amplifier OP3 and a resistor R10. The second differential amplifier circuit 108B has an operation amplifier OP4 and resistors R11 to R14. A bias voltage Vbias is applied to the positive terminal of the operational amplifier OP3.
[0095]
The negative terminal of the operational amplifier OP3 is connected to the output terminal T61, and the output current Iout flows. The resistor R10 is connected between the output terminal and the negative terminal of the operational amplifier OP3. The plus terminal of the operational amplifier OP4 is connected to one end of the resistor R11. The other end of the resistor R11 is applied with a bias voltage Vbias having the same value as the bias voltage Vbias applied to the plus terminal of the operational amplifier OP3. One end of the resistor R12 is connected to the plus terminal of the operational amplifier OP4, and the other end of the resistor R12 is grounded. One end of the resistor R13 is connected to the output terminal of the operational amplifier OP3, and the other end of the resistor R13 is connected to the negative terminal of the operational amplifier OP4. The output terminal of the operational amplifier OP4 is connected to the input side of the demodulator 7 through the output terminal T62, and is connected to the negative terminal through the resistor R14. The resistance value of the resistor R13 and the resistance value of the resistor R11 are the same value, and the resistance value of the resistor R14 and the resistance value of the resistor R12 are the same value.
[0096]
Assuming that the bias voltage Vbias is not applied to the positive terminal of the operational amplifier OP3, the voltage applied to the negative terminal of the operational amplifier OP3 is equivalently grounded. It will not flow. Therefore, the bias voltage Vbias is applied to the plus terminal of the operational amplifier OP4 so that the output current Iout (= Ip−Im) flows through the resistor R10. As a result, the drain voltage of the n-type MOS transistor M33 is clamped to the bias voltage Vbias, and the output current Iout (= Ip−Im) flows through the resistor R10. The current flowing between the drain and source of the n-type MOS transistor M33 hardly changes even when the drain voltage changes, and the value of the bias voltage Vbias may be about ½ of the power supply voltage Vdd. Here, when the output voltage of the operational amplifier OP3 is V1,
V1 = Vbias− (R10 × Iout) = Vbias−R10 (Ip−Im).
[0097]
This output voltage V1 is obtained by adding a bias voltage to the output voltage corresponding to the output current Iout. In order to change the output voltage Vout generated at the output terminal T62 to an output voltage corresponding to the output current Iout. Vbias must be removed from the output voltage V1.
[0098]
Therefore, if the ratio of the resistors R11 and R12 (the ratio of the resistors R13 and R14) of the second differential amplifier circuit 108B is designed so that the current flowing through the resistors R12 and R14 is (Ip−Im), the operational amplifier An output voltage Vout (= R14 ((Ip−Im))) from which the bias voltage Vbias has been removed can be applied to the output terminal of OP4.
[0099]
Accordingly, the first differential amplifier circuit 108A receives the correlation current signal and is applied with the bias voltage to output a voltage signal that is the sum of the current signal conversion voltage and the bias voltage, and the second differential amplifier circuit 108B. When a sum voltage signal is input, a bias voltage having the same value as the bias voltage is applied, the bias voltage is removed from the sum voltage signal, and a correlation voltage signal corresponding to the correlation current signal is output from the output terminal T62. The waveform of this correlation voltage signal is shown in FIG.
[0100]
Note that an operational amplifier is not necessarily used for the current / voltage conversion means (I / VC) 108, and other current-voltage conversion means may be used.
[0101]
(Explanation of correlation processing)
Next, the correlation processing will be described with reference to FIG. Current signal series S including chip information₁, S₂, ..., S_MNIs time t₁, Time t₂, ..., time t_MNAnd the current time is t_MNAnd
[0102]
When the arrangement number M × N of current delay flip-flops is the same as the arrangement number L of chip information (L = M × N) as shown in FIG.₁, S₂, ..., S_MNAre stored in order from right to left. This current signal S₁, S₂, ..., S_MNAre held in each current delay flip-flop in order from the old current signal to the new current signal from right to left.
[0103]
Reference data R as despread data corresponding to each current delay flip-flop₁, R₂... R_MNgive. At this time, the current signal S₁, S₂, ..., S_MNSign and reference data R₁, R₂... R_MNIf the codes coincide with each other, the correlation becomes maximum, and the reference data R₁, R₂... R_MNIs used to switch the output path of the current signal held in each current delay flip-flop so that the correlation current is maximized, and the current signal S held in each current delay flip-flop.₁, S₂, ..., S_MNIs reference data R₁, R₂... R_MNIt is added according to the connection path switching logic.
[0104]
In FIG. 15 (a), the arrangement number M × N of each current delay flip-flop and the arrangement number L of chip information are the same, and each current delay flip-flop is arranged in M × N stages in series, and each current delay flip-flop is arranged. The current signal output from the delay flip-flop is added at the same time to obtain the correlation. The arrangement of the current delay flip-flop shown in FIG. 15 (a) and the current delay shown in FIG. The flip-flops are divided into M equal parts and arranged in units of N. The flip-flops are arranged in parallel in M stages as shown in FIG. 15B, and the current signals output from the N current delay flip-flops are This is equivalent to a configuration in which the partial correlation current is obtained for each stage and the partial correlation current obtained for each stage is added simultaneously to obtain the correlation current.
[0105]
By the way, in FIG. 15 (b), when it is considered that the first stage, the second stage,..._MN, The partial correlation current output from the Mth stage is the time t₁To time t_NIs the partial correlation current based on the current signal that has been received until and held in the array of the M-th stage current delay flip-flops, and the partial correlation current output from the (M−1) -th stage is the time t_{N + 1}To time t_2NIs a partial correlation current based on the current signal that has arrived until and held in the array of the current delay flip-flops of the (M−1) th stage, and the partial correlation currents from the N current delay flip-flops of the first stage are Time t_MNTo time t_{M (M-1) +1}Is a partial correlation current based on the current signal that has arrived until and held in the first-stage current delay flip-flop array, and the partial correlation current output from the current-delay flip-flop array in each stage is N chips It is delayed by time.
[0106]
Therefore, as shown in FIG. 4, when the partial correlation current is obtained by the N current delay flip-flops CDFFi (i = 1, 2,..., N) as shown in FIG.₁To time t_NA partial correlation current based on the current signal which has arrived until and held in the array of current delay flips CDFFi, time t_{N + 1}To time t_2N, Time t, based on the current signal that has been received until and held in the array of current delay flips CDFFi (i = 1, 2,..., N)_MNTo time t_{M (M-1) +1}Parallel current path switching circuit so that the partial correlation currents based on the current signals that have arrived between and held in the array of current delay flip-flops CDFFi (i = 1, 2,..., N) are added. In addition to configuring the connection path switching logic of the unit 102, the partial correlation current delay circuit block unit 103 may be configured.
[0107]
In FIG.₁, R₂... R_NIs the M-th stage partial correlation current output means 105S._MIs reference data as a connection path switching logic given to_{N (MK-2) +1}... R_{N (M-K + 1) -1}, R_{N (M-K + 1)}Is the K-th stage partial correlation current output means 105S_kIs reference data as a connection path switching logic given to_{N (Mk-2) +1}... R_{N (M-1) -1}, R_{N (M-1)}Is the second-stage partially correlated current output means 105S₂Is reference data as a connection path switching logic given to_{N (M-1) +1}... R_NM-1, R_NMIs the first-stage partially correlated current output means 105S₁Reference data as connection path switching logic given to.
[0108]
For example, time t₁To time t_nCurrent signal sequence S that has been held until 1 input multiple output current delay flip-flop CDFFi₁~ S_NAnd reference data series R₁~ R_NAnd the time t = t_N, M-th partial correlation current output means 105_MThe partial correlation current output from is maximized. This partial correlation current output means 105_MThe partial correlation current output from the N-chip current delay circuit Ndelay₁Is held for N chip time. This partial correlation current output means 105_MAfter the partial correlation current output from N is delayed by N chip time, the N chip current delay circuit Ndelay of the next stage₂Is output.
[0109]
Next, time t_{N + 1}To time t_2NCurrent signal sequence S that has been held until 1 input multiple output current delay flip-flop CDFFi_{N + 1}~ S_2NAnd reference data series R_{N +}~ R_2NAnd the time t = t_2N, M-1 stage partial correlation current output means 105_M-1The partial correlation current output from is maximized. This partial correlation current output means 105_M-1The partial correlation current output from the N-chip current delay circuit Ndelay₂Is input. This N-chip current delay circuit Ndelay₂Includes a partial correlation current output means 105._M-1Simultaneously with the partial correlation current output from the partial correlation current output means 105_MThe partial correlation current output from the output and delayed by N chips is input and added, and this added partial correlation current is converted into N chip current delay circuit Ndelay.₂For N chips. Partial correlation current output means 105_M-1Is the partial correlation current output means 105_MIs output with the partial correlation current before N chip time and delayed for N chip time, and then delayed for the next N chip current delay circuit Ndelay_ThreeIs output.
[0110]
In this way, M partial correlation current output means 105_kThe correlation current signal as a whole can be obtained by sequentially adding the partial correlation currents output from the above and delayed by N chip times for each chip time in chronological order.
[0111]
(Description of minimum components of correlator 5)
In this embodiment, the correlator 5 includes a voltage / current conversion unit 100, a one-input multiple-output current delay circuit block unit 101, a parallel current path switching switch block unit 102, a partial correlation current delay block unit 103, and a current / voltage conversion unit 108. However, the correlator 5 only needs to include the voltage-current converter 100, the one-input multiple-output current delay circuit block unit 101, the parallel current path switching switch block unit 102, and the partial correlation current delay block unit 103. . When the correlation output processing is performed in the current mode, the current / voltage conversion means 108 may not be provided.
[0112]
This correlator 5 outputs a peak voltage on the plus side when the bit information is “1”, and outputs a peak voltage on the minus side when the bit information is “0”. A correlation voltage signal that is output and generated in time series is input to the demodulator 7. The demodulator 7 integrates this correlation voltage signal and demodulates the information signal (raw information signal) of the original baseband frequency.
[0113]
(Description of current source configuration)
In the above description, each current source has been described using an equivalent circuit, but a p-type MOS transistor M303 shown in FIG. 16 can be used for each current source. FIG. 16A shows an equivalent symbol I as a current source.₁₀₁This equivalent symbol I₁₀₁N-type MOS transistor M for current memory₁₀₁The connection state is shown. This n-type MOS transistor M₁₀₁Here, n-type MOS transistors are representatively shown. FIG. 16B shows the equivalent symbol I.₁₀₁Is represented again by a p-type MOS transistor M303. The drain of the p-type MOS transistor M303 is the n-type MOS transistor M₁₀₁The source of the p-type MOS transistor M303 is connected to the power supply Vdd, and a gate voltage VEE is appropriately applied to the gate of the p-type MOS transistor M303. The p-type MOS transistor M303 operates as a constant current source when a voltage VEE is applied to its gate.
[0114]
The current J is determined by the gate length L of the p-type MOS transistor, the gate width W, the ratio W / L of the gate width W to the gate length L, and the gate voltage VEE, and the current J can be adjusted and controlled by changing the gate voltage VEE. .
[0115]
(Explanation of double sampling)
In the above description, the total number N × M of pair switches of each parallel current path switching circuit block unit 102 is equal to the number L of chip information arrays (N × M = the number L = 128 of chip information arrays). 128), that is, P = 1. This sampling method is called a single sampling method. The total number of pair switches in the parallel current path switching switch circuit block unit 102 may be P times (P is an integer of 2 or more) with respect to the arrangement number L = 128 of chip information. In particular, the sampling method when P is “2” is called a double sampling method. In this case, the total number of pair switches in the current path switching switch circuit block unit 102 is 256, and the frequency of the clock signal of the double sampling method is twice the frequency f of the clock signal used in the single sampling method.
[0116]
In the case of the double sampling method, when the correlation is obtained, the correlation current signal becomes twice that of the single sampling method, and if the time series of the current signal is shifted by two or more, the correlation current output as the peak output is not output.
[0117]
(Effect of Embodiment 1 of the Invention)
The partially correlated current correlator 5 according to the above-described embodiment transfers an analog current signal as compared with a matched filter having a structure in which a current signal is sequentially delayed by the number of chip information using a current delay flip-flop. The number of times can be greatly reduced, the accumulation of errors during current signal transfer can be greatly suppressed, and the effect is particularly remarkable when the number of arrangements of chip information increases.
[0118]
In addition, the one-input multiple-output current delay flip-flop CDFFi of the partial correlation type correlator 5 can reduce the number of circuit components per output as the number of output paths increases. When the number of arrangements increases, it contributes to further reduction of the circuit load.
[0119]
Here, the current value of the current signal input to the correlator 5 is Iin. The transfer error σ per one time is approximately σ = 1 (%) when a flip-flop based on a normal current current mirror circuit and an input / output of a current memory circuit are used for an input signal. The occurrence of errors under this condition is estimated.
[0120]
For example, when considering the operation of a single-sampling matched filter with 256 arrayed diffusion chip information, when using current delay flip-flops connected in series by the number of arrays in a conventional correlator configuration, n stages Let the output of the current delay flip-flop be In,
In = Iin × (1 + σ)ⁿ
A transfer error model expressed by the following equation is assumed.
[0121]
In this case, using the number of transfers as a parameter and comparing the input current at each stage,

On the other hand, in the embodiment of the present invention, the number M and the number N can be arbitrarily selected. When the number M and the number N are arbitrarily determined, the maximum number of current transfers is set to N_{tr ans}Then,
N_trans= Number of transfers by one-input multiple-output current delay flip-flop CDFFi (i = 1, 2,..., N) + Number of transfers by partial correlation output current data delay circuit block unit 103 = N + (M−1)
Given in.
[0122]
When the arrangement number L of the spread chip information of the correlator 5 is 256

Thus, when the number N is the half power of the number L of chip information arrays, the number of transfers is minimized. The current value of the maximum error when delayed using a current delay flip-flop in series is 12.65 × Iin, whereas when N = 16, a current of about 1.38 × Iin Since the value can be suppressed, current transfer errors can be greatly suppressed.
[0123]
Although the description has been given here assuming that the number L of the arrayed diffusion chip information is L = 256, for example, even if L = 32, 64, L = 128, and L> 256, the correlation accuracy can be improved.
[0124]
N that minimizes the maximum number of transfers is an integer closest to L to the 1/2 power, and the number of transfers at that time can be estimated as 2 × L to the 1/2 power. Therefore, as the number of arrangements of chip information increases, the use of the correlator 5 according to the present invention reduces the number of transfers, and the effect of reducing and accumulating the transfer errors associated therewith becomes remarkable.
[0125]
The reduction in the number of transfers due to the circuit configuration of the correlator 5 is that when the partial correlation current is delayed by n chips in the N chip current delay circuit Ndelay of the partial correlation output current delay circuit block unit 103, one partial correlation is performed. This is realized by providing a function equivalent to a transfer delay n times only by current transfer.
[0126]
Here, the number of main current sources is estimated and compared.
[0127]
Since the configuration per stage of current delay flip-flop CDFFi includes two current sampling current mirrors,
4 current memory MOS transistors
2 current switches
4 constant current sources
Can be estimated.
[0128]
In the case of a circuit configuration that delays a current signal by connecting conventional current delay flip-flops in L stages in series, L current delay flip-flops are required.
Current memory MOS transistor 4 × L
Current switch 2 × L
Constant current source 4 × L
It becomes.
[0129]
In the case of the circuit configuration of the present invention,
Per one input M output current delay flip-flop CDFFi,
The number of current memory MOS transistors is 6 + M,
The number of current switches is 2
The number of constant current sources is 6 + M
Since N current flip-flops are used,
The number of current memory MOS transistors is (6 + M) × N
The number of current switches is 2 × N
The number of constant current sources is (6 + M) × N
Further, regarding the N-chip current delay circuit Ndelay of the partial correlation output current delay circuit block unit 103,
Current memory MOS transistor (N + 1) × (M−1)
Current switch (2 x N) x (M-1)
Constant current source (N + 1) × (M−1)
It is.
[0130]
From the total above,
The number of current memory MOS transistors is
(6 + M) × N + (N + 1) × (M−1) = 2M × N + 5N + M−1
The number of current switches is (2 x N) x M
The number of constant current sources is 2M × N + 5N + M−1
It is.
[0131]
Here, the number of current sources in the configuration in which the current signal is delayed by connecting the current delay flip-flops in series in L stages is compared with the number of constant current sources in the configuration of the first embodiment of the present invention. . In the case of a current mode circuit, most of the power consumption is a constant current flowing from a constant current source. Therefore, reducing the number of constant current sources contributes to reduction of power consumption and simplification of circuit configuration.
[0132]
The number of current sources in the correlator having the conventional configuration is 4L, and the number of current sources according to the embodiment of the present invention is 2M × N + 5N + M−1.
[0133]
Where L = M × N,
Consider the case of M = N where the number of transfers is minimized.
Formula 4L> 2L + L^-1/2−1 (L> 9 (L is a real number)) is established under the following conditions. As L increases, the number of current sources according to the embodiment of the present invention is smaller than the number of current sources of the conventional correlator. Decreases rapidly. This indicates that when the number L of arrangements of chip information increases, the effect of reducing the number of transfers and the effect of simplifying the circuit configuration become significant.
[0134]
When operating with the reference numerals fixed, one of the pair switches of the parallel current path switching switch circuit block unit 102 is always connected and the other is kept disconnected. Here, since the power consumption when operating the pair switch is consumed by the accumulation of electric charges in the gate electrode when the switch is turned on / off, when the pair switch is substantially fixed, There will be no power consumption.
[0135]
In an analog matched filter using a switched capacitor, a capacitor having a very strict value must be introduced into the LSI process. However, in this current sum type matched filter, a so-called ASIC foundry usually provides for digital use. All circuits can be configured using a standard process.
[0136]
According to the first embodiment of the present invention, the number of current signal transfers can be greatly reduced, and at the same time, the number of current sources and the number of switches in configuring the circuit can be reduced. Simplification can be achieved. In addition, since the total number of current sources can be reduced, power consumption can be saved compared to the conventional configuration.
[0137]
Furthermore, since the number of analog current data transfers can be greatly reduced, the accuracy of correlation output can be improved.
[0138]
The number of current delay flip-flops in the one-input multiple-output current delay circuit block unit 101 is preferably selected in consideration of the transfer error generation rate, the number of current sources, and the complexity of circuit elements. .
[0139]
Second Embodiment of the Invention
(Explanation when 1-transistor current mirror is used for the 1-input multiple-output current delay circuit block unit 101)
In the first embodiment of the present invention, current mirror circuits CMR1 and CMR2 with sample control switches are configured by using two constant current sources, respectively. However, from the viewpoint of power consumption, it is desirable to reduce the number of current sources as much as possible.
[0140]
FIG. 17 shows a specific example of the one-input multiple-output current delay flip-flop CDFF1 when one constant current source is used. Since the configuration of the one-input multiple-output current delay flip-flop CDFF1 shown in FIG. 17 is different only in the configurations of the current mirror circuits CMR1 and CMR2, the same components are denoted by the same reference numerals, Only the different parts will be described.
[0141]
In FIG. 17, the current mirror circuit CMR1 includes a current source I._Ten', A memory MOS transistor M101', an input switch SW10, and a control switch SW11. Here, the input switch SW10 and the control switch SW11 are turned on / off at the same timing. The current mirror circuit CMR2 is a current source I₁₁', A memory MOS transistor M102', an input switch SW20, and a control switch SW21. The input switch SW20 and the control switch SW21 are turned on / off at the same timing.
[0142]
The source of the memory MOS transistor M101 'of the current mirror circuit CMR1 is the current source I._TenThe power source voltage Vdd is connected to the input terminal T01 via the input switch SW10. The gate of the memory MOS transistor M101 'is connected to its source via the control switch SW11. The drain of the memory MOS transistor M101 'is grounded.
[0143]
The source of the memory MOS transistor M102 'of the current mirror circuit CMR2 is the current source I.₁₁'Is connected to the power supply Vdd via' and to the source of the memory MOS transistor M101 'of the current mirror circuit CMR1 via the input switch SW20. The gate of the memory MOS transistor M102 'is connected to the source of the memory MOS transistor M102' via the control switch SW21, and is connected to the gate of the memory MOS transistor M301 of the current mirror circuit CMR3. The drain of the memory MOS transistor M102 'is grounded. The output terminal T02 is connected to the input terminal T01 at the next stage.
[0144]
The configuration of the one-input multiple-output current delay circuit flip-flop CDFF1 shown in FIG. 17 will be described using the clock signals SA and SB (see FIG. 7).
[0145]
At the rising edge of the clock signal SA, the input switch SW10 and the control switch SW11 of the current mirror circuit CMR1 are turned on. At this time, the input switch SW20 is off. If a current source that outputs an ideal input current Iin is connected to the input terminal T01, the source and the gate of the memory MOS transistor M101 ′ are on because the source and the gate of the memory MOS transistor M101 ′ are on. Current source I_TenThe gate voltage is set so that a current “J + Iin”, which is the sum of the current J from ′ and the current signal Iin flowing from the input terminal T01, flows.
[0146]
Next, the input switch SW10 and the control switch SW11 are turned off at the falling edge of the clock signal SA. Then, the gate of the memory MOS transistor M101 'is held at a voltage that can potentially pass the current "J + Iin".
[0147]
Subsequently, when the clock signal SB rises, the input switch SW20 and the control switch SW21 are simultaneously turned on. Then, since the source and gate of the memory MOS transistor M102 'are conductive, the current source I is connected between the source and drain of the memory MOS transistor M102'.₁₁The gate voltage of the memory MOS transistor 102 'is set so that a current "J-Iin" that is the sum of the current J from' and the current signal "-Iin" flowing into the previous stage current mirror circuit CMR1 flows. At this time, the gate voltage of the memory MOS transistor M301 of the current mirror circuit CMR3 connected in parallel to the memory MOS transistor 102 'is also held so that the current "J-Iin" flows.
[0148]
Subsequently, when the clock signal SA is turned on, the current signal held in the memory MOS transistor M102 ′ of the current mirror circuit CMR2 is transferred to the next stage, and at the same time, the current signal Iin is sent to the memory MOS transistor M101 ′ of the current mirror circuit CMR1. Flows in. Since the subsequent operation is the same as that of the first embodiment, detailed description thereof will be omitted.
(Effect of Embodiment 2 of the Invention)
Regarding Embodiment 2 of the present invention,
Per 1-input M-output current delay circuit flip-flop CDFFi using 1-transistor configuration,
The number of current memory MOS transistors is 4 + M,
Current switch 4,
Constant current source 4 + M,
And
Since N current delay flip-flops are used,
The total number of current memory MOS transistors is (4 + M) × N,
The total number of current switches is 4 x N
The total number of constant current sources is (4 + M) × N
It becomes.
[0149]
Further, regarding the N-chip current delay circuit Ndelay of the partial correlation output current delay circuit block unit 103,
The number of current memory MOS transistors is (N + 1) × (M−1),
The number of current switches is (2 × N) × (M−1),
The number of constant current sources is (N + 1) × (M−1),
It is.
[0150]
With the above,
The total number of current memory MOS transistors is (4 + M) × N + (N + 1) × (M−1) = 2M × N + 3N + M−1.
The total number of current switches is 6 x N
The total number of current sources is 2M × N + 3N + M−1.
It becomes.
[0151]
In the first embodiment of the invention, the total number of constant current sources is 2M × N + 5N + M−1, whereas the total number of constant current sources can be reduced to 2M × N + 3N + M−1. Instead, the number of current switches is increasing, but the total number of circuit components can be reduced, and the number of constant current sources is a major factor in power consumption, so the number of constant current sources should be reduced. The effect that can be achieved is remarkable.
[0152]
Embodiment 3 of the Invention
(Explanation when 1-input M-output current delay circuit is configured using cascode MOS) When the channel length is sufficiently large, the drain resistance in the saturation region of the drain current-drain voltage characteristics of the n-channel MOSFET and p-channel MOSFET rd is a very large value and can be considered to be substantially infinite (rd = ∞). However, if the channel length is reduced to 1 μm or less, the drain resistance rd cannot be handled as infinite. That is, the effect of the finite rd becomes obvious, and the characteristics shown in FIGS. 18B and 18B are obtained.
[0153]
18A shows an n-channel MOSFET, and FIG. 18B shows operating characteristics of the n-channel MOSFET. FIG. 18C shows a p-channel MOSFET, and FIG. 18B shows operating characteristics of the p-channel MOSFET.
[0154]
In FIG. 18 (a), the symbol FETN (n) is used to indicate that it is an n-channel MOSFET. In FIG. 18 (c), the symbol FETN (p) is used to indicate that it is a p-channel MOSFET. When the drain resistance rd of the n-channel MOSFET (FETN (n)) is finite, when the gate voltage Vg is changed to 2V, 3V, and 4V in the increasing direction, the current Idn flowing between the drain and the source becomes the drain voltage Vdn. As shown in FIG. 18 (b), the direction of increase changes.
[0155]
When the drain resistance rd of the p-channel MOSFET (FETN (p)) is finite, when the gate voltage Vg is changed to −1V, −2V, −3V in the decreasing direction, the current Idp flowing between the drain-source is As the drain voltage Vdp decreases, it changes in a decreasing direction as shown in FIG.
[0156]
Accordingly, when circuit design is performed using the MOS transistors shown in FIGS. 18B and 18B, the correlation current signal output from the correlator 5 does not accurately correspond to the input current signal Iin. Become.
[0157]
Therefore, a combination of these two n-channel MOSFETs (FETN (n)) having the operating characteristics shown in FIG. 18B, and two p-channel MOSFETs having the operating characteristics shown in FIG. An equivalent MOSFET with improved saturation characteristics is configured using the combination of p)).
[0158]
FIG. 19 (a) shows an equivalent MOSFET corresponding to an n-channel MOSFET, which is indicated by the symbol EFETN (n) in the sense of being equivalent. FIG. 20 (a) shows an equivalent MOSFET corresponding to a p-channel MOSFET, which is represented by the symbol EFETN (p) in the sense of being equivalent.
[0159]
Here, two n-channel MOSFETs (FETN (n)) are used for the n-channel MOS equivalent FET (EFETN (n)), and operate as an n-channel MOSFET as a whole. Two n-channel MOSFETs (FETN (n)) will be sequentially denoted by FET1 (n) and FET2 (n), and the connection state will be described next.
[0160]
The source of the n-channel MOSFET (FET1 (n)) is grounded, and its drain is connected to the source of the n-channel MOSFET (FET2 (n)). The drain of the n-channel MOSFET (FET2 (n)) is connected to the terminal Vout.
[0161]
Here, it is assumed that the voltage Vgn is applied to the gate of the n-channel MOSFET (FET1 (n)) and the voltage Vbias is applied to the gate of the n-channel MOSFET (FET2 (n)).
[0162]
When the voltage of Vout increases, the current Idn flowing between the drain and source of the n-channel MOSFET (FET2 (n)) increases. Then, the same current Idn flows through the n-channel MOSFET (FET1 (n)), so that the potential of Vdn rises. Then, since the potential difference (Vout−Vdn) between the source and drain of the n-channel MOSFET (FET2 (n)) decreases, the current Idn flowing between the drain and source of the n-channel MOSFET decreases.
[0163]
Thereby, the fluctuation of Idn due to the fluctuation of Vout is reduced by the feedback effect of the voltage of Vdn. Therefore, since the fluctuation of Vdn is small with respect to the fluctuation of Vout, the resistance to the fluctuation of the drain voltage of the equivalent MOSFET (EFETN (n)) is smaller than the magnitude of the fluctuation of the drain voltage when a single MOSFET is used. Thus, the drain resistance rd can be substantially increased. This equivalent MOSFET (EFETN (n)) is used for a memory MOS transistor.
[0164]
Two p-channel MOSFETs (FETN (p)) are used for the p-channel equivalent MOSFET (EFETN (p)) shown in FIG. 20 (a), and operate as a p-channel MOSFET as a whole. Here, two p-channel MOSFETs (FETN (p)) are sequentially indicated by (FET1 (p)) and (FET2 (p)), and the connection state will be described next.
[0165]
The source of the p-channel MOSFET (FET1 (p)) is connected to Vdd, and its drain is connected to the source of the p-channel MOSFET (FET2 (p)). The source of the p-channel MOSFET ((FET2 (p)) is connected to the terminal Vout.
[0166]
Here, it is assumed that the voltage Vgp is applied to the gate of the p-channel MOSFET (FET1 (p)) and the voltage Vbias is applied to the gate of the p-channel MOSFET (FET2 (p)).
[0167]
When the voltage of Vout decreases, the potential difference (Vdp-Vout) between the drain and source of the p-channel MOSFET (FET2 (p)) decreases, so that the current Idp flowing between the drain and source of the p-channel MOSFET decreases.
[0168]
Thereby, the fluctuation of Idp due to the fluctuation of Vout is reduced by the feedback effect of the voltage of Vdp. Therefore, since the fluctuation of Vdp is small with respect to the fluctuation of Vout, the resistance to the fluctuation of the drain voltage of the equivalent MOSFET (EFETN (p)) is smaller than the magnitude of the fluctuation of the drain voltage when a single MOSFET is used. Thus, the drain resistance rd can be substantially increased. This equivalent MOSFET (EFETN (p)) is used as a current source. FIG. 21 shows a specific example in which this cascode MOSFET is applied to a 1-input M-output current delay flip-flop CDFF1 shown in FIG.
[0169]
Thereby, the delay of the current signal, the current source characteristic, and the current holding characteristic can be improved.
[0170]
Embodiment 4 of the Invention
(Explanation when the partially correlated current output delay circuit block unit 103 is constituted by a regulated cascade circuit)
FIG. 22 (a) shows an equivalent MOSFET corresponding to an n-channel MOSFET, which is indicated by the symbol EFETN (n) in the sense of being equivalent. FIG. 23 (a) shows an equivalent MOSFET corresponding to a p-channel MOSFET, which is represented by the symbol EFETN (p) in the sense of being equivalent.
[0171]
Here, for the n-channel MOS equivalent FET (EFETN (n)), three n-channel MOSFETs (FETN (n)) are used, and one p-channel MOSFET (FETN (p)) is used. Operates as a channel MOSFET. Three n-channel MOSFETs (FETN (n)) will be denoted by FET1 (n), FET2 (n), and FET3 (n) in order, and the connection state will be described next.
[0172]
The source of the n-channel MOSFET (FET1 (n)) is grounded, and its drain is connected to the source of the n-channel MOSFET (FET2 (n)) and the gate of the n-channel MOSFET (FET3 (n)). A gate voltage Vgn is applied to the gate of the n-channel MOSFET (FET1 (n)). The drain of the n-channel MOSFET (FET2 (n)) is connected to the terminal Vout. Terminal Vout is connected to the current source shown in FIG. The gate of the n-channel MOSFET (FET2 (n)) is connected to the drain of the p-channel MOSFET (FETN (p)) and the drain of the n-channel MOSFET (FET3 (n)). The source of the n-channel MOSFET (FET3 (n)) is grounded. The source of the p-channel MOSFET (FETN (p)) is connected to the power supply Vdd, and the gate voltage Vreg is connected to the gate of the p-channel MOSFET (FETN (p))._pIs applied.
[0173]
In the n-channel MOS equivalent FET (EFETN (n)), the p-channel MOSFET (FETN (p)) operates as a current source. Now, when the voltage applied to the terminal Vout increases, the current Idn flowing between the drain and source of the n-channel MOSFET (FET2 (n)) increases, and the potential Vdn on the drain side of the n-channel MOSFET (FET1 (n)) increases. try to. When the drain-side potential Vdn rises, the gate voltage of the n-channel MOSFET (FET3 (n)) increases, and the current flowing between the drain and source of the n-channel MOSFET (FET3 (n)) tends to increase.
[0174]
However, the current Ireg flowing in the n-channel MOSFET (FET3 (n)) by the p-channel MOSFET (FETN (p))._nIs kept constant, the potential Vd on the drain side of the n-channel MOSFET (FET3 (n)) is lowered, thereby lowering the gate potential applied to the gate of the n-channel MOSFET (FET2 (n)). When the gate potential of the n-channel MOSFET (FET2 (n)) decreases, the current Idn is prevented from increasing, and as a result, the potential difference between the drain and source of the n-channel MOSFET (FET2 (n)) increases, and the n-channel MOSFET (FET The drain voltage Vdn of the FET1 (n)) is held constant, and as a result, the current Idn is kept constant.
[0175]
As a result, the drain resistance rd of the n-channel equivalent MOSFET becomes ∞, and the saturation characteristics shown in FIG. Actually, the magnitude of the current Idn is approximately 50 to 150 microamperes, and the current Ireg_nCan be about 2 microamperes, so that the current Ireg flowing from the p-channel MOSFET (FETN (p)) to the n-channel MOSFET (FET3 (n))_nThe power consumption based on is almost negligible.
[0176]
The n-channel equivalent MOSFET (EFETN (n)) shown in FIG. 22 (a) is called a so-called regulated cascade circuit, and this circuit itself is known. The n-channel equivalent MOSFET (EFETN (n)) is a memory MOS transistor M100._p(P = 1, 2,..., N + 1).
[0177]
The p-channel equivalent MOSFET (EFETN (p)) shown in FIG. 23 (a) operates as a p-channel MOSFET as a whole. For the p-channel equivalent MOSFET (EFETN (p)), three p-channel MOSFETs (FETN (p)) are used, and one n-channel MOSFET (FETN (n)) is used. Here, three p-channel MOSFETs (FETN (p)) are sequentially indicated by (FET1 (p)), (FET2 (p)), and (FET3 (p)), and the connection state will be described next. .
[0178]
The drain of the p-channel MOSFET (FET1 (p)) is connected to the terminal Vout. The source of the p-channel MOSFET (FET1 (p)) is connected to the drain of the p-channel MOSFET (FET2 (p)) and the gate of the p-channel MOSFET (FET3 (p)). The gate of the p-channel MOSFET (FET1 (p)) is connected to the drain of the n-channel MOSFET (FETN (n)) and the drain of the p-channel MOSFET (FET3 (p)). The source of the p-channel MOSFET (FET2 (p)) is connected to the power supply Vdd, and the gate voltage Vgp is applied to its gate. The source of the p-channel MOSFET (FET3 (p)) is connected to the power supply Vdd. The source of the n-channel MOSFET (FETN (n)) is grounded and the gate thereof has a gate voltage Vreg._nIs applied. In FIG. 23 (a), Vdp is the potential on the source side of the p-channel MOSFET (FET1 (p)), and Idp indicates the current flowing between the source and drain of the p-channel MOSFET (FET1 (p)). . The saturation characteristic of this p-channel equivalent MOSFET (EFETN (p)) is as shown in FIG. The reason is omitted because it can be easily analogized from the description of the operating characteristics of the n-channel equivalent MOSFET (EFETN (n)). This p-channel equivalent MOSFET is a current source I100._p(P = 1, 2,..., N + 1).
[0179]
FIG. 24 shows the actual N-chip current delay circuit Ndelay shown in FIG.₁The case where an equivalent MOSFET is applied is shown. By using this structure, an N-chip current delay circuit Ndelay_kCurrent source characteristics and current holding characteristics can be improved.
[0180]
Embodiment 5 of the Invention
(Description when current cut is applied to the 1-input multiple-output current delay circuit block unit 101)
FIG. 25 shows the current source I at a time unnecessary for operation in the one-input multiple-output current delay circuit block unit 101._Ten~ I₁₅, I_16jIs a time chart showing a case in which a steady-state current does not flow by providing a current stop switch on a path through which the constant current J flows. For example, the current stop switch is shown in FIG.₁~ Z₆, Z_16jIs provided.
[0181]
The current source I is only required for the minimum time required to sample or output the current signal to the memory MOS transistor within one chip time._Ten~ I₁₃To work. This is because once the memory MOS transistor stores information, the current source I_Ten~ I₁₅, I_16jThe current information can be stored even if the operation is stopped. In the case of the one-input multiple-output current delay circuit block unit 101, the current source I is not used for a time other than the current signal storage and output time._Ten~ I₁₃Can be stopped.
[0182]
Assuming that one chip time is Tchip, and the time required for current input / output is Tinout, the time required to flow current from the current source is one chip time out of the total operation time.
Tinout / Tchip,
Current source I_Ten, I₁₁The time that can be stopped is 1 chip time out of the total operation time,
(Tchip-Tinout) / Tchip,
When the total number of target current sources is K, when the current of the current source is always flowing, the time during which the current source can be stopped is
J × K × (Tchip-Tinout) / Tchip,
Current consumption can be reduced by this amount.
[0183]
In the case of a current mode element, a steady current is the main current consumption. Therefore, suppressing the steady current of the current source is very effective in reducing power consumption. In addition, the time Tinout required for current input / output becomes shorter as the miniaturization progresses due to the scaling law of the MOSFET, and as a result, the time during which the current source can be stopped increases, thereby further increasing the power consumption. Can be reduced.
[0184]
Embodiment 6 of the Invention
(N-chip current delay circuit Ndelay_kExample of current cut in
FIG. 26 shows an N-chip current delay circuit Ndelay._k2 is a time chart showing a case where a current source is stopped or a switch is provided on a current path so that a steady current does not flow at a time unnecessary for operation.
[0185]
Within one chip time, the current source is operated only for the minimum time necessary for sampling the partial correlation current into the memory MOS or outputting it from the memory MOS transistor. This utilizes the property that once the memory MOS transistor stores information, the current information can be stored and held even if the current source is stopped.
[0186]
In this N-chip current delay circuit Ndelay, the correlation current is input and output once every N delays, so that one chip time is Tchip, the number of delays is N, and the time required for input / output of the correlation current is set. Assuming Tinout, the time required to flow current from the current source is (N + 1) chip time of the total operating time,
Tinout / (Tchip × (N + 1)) time,
The time during which the current source can be stopped is (N + 1) chip time of the total operation time,
(Tchip × (N + 1) −Tinout) / (Tchip × (N + 1)) time, and when the current of the current source is constantly supplied, if the total number of target current sources is N + 1, the current source is stopped. The possible time is
J × (N + 1) × (Tchip × (N + 1) −Tinout) / Tchip, and the current consumption can be reduced by this amount.
[0187]
In the N-chip current delay circuit Ndelay, the current source has only to be operated for one chip time within (N + 1) chip time, so that the current cut effect is very large and the power consumption reduction effect is large. One N-chip current delay circuit Ndelay circuit has N + 1 current memory circuits in parallel. However, by substantially performing current cut in units of chips, current source power consumption equivalent to two current memories. Therefore, the power consumption of the entire circuit is at most about M × 2 current memories, and the effect of reducing power consumption is great.
[0188]
Here, the current cut in units of chips has been described. However, as described in the fourth embodiment of the present invention, when the current cut is operated even within the chip time, the current source power consumption corresponding to one current memory is used. Therefore, the power consumption in the entire circuit is at most about M × 1 current memory, and the effect of reducing the power consumption is greater.
[0189]
In the case of a current mode element, since a steady current is a main current consumption, suppressing the steady current of the current source is very effective in reducing power consumption. Further, the time Tinout required for current input / output becomes shorter as the miniaturization progresses due to the scaling law of the MOSFET, and accordingly, the time for which the current source can be stopped increases, thereby further increasing the power consumption. Can be reduced.
[0190]
Embodiment 7 of the Invention
(1-input multiple-output current delay circuit block 101 memory control switch SW₁₁, SW_{twenty one}Description of an embodiment using a dummy MOS transistor
Memory control switch SW of 1-input multiple-output current delay circuit block unit 101 shown in FIG.₁₁, SW_{twenty one}In general, as shown in FIG.₀It is composed of The n-type MOSFET DM₀The drain of the memory MOS transistor M₁₀₁', M₁₀₂'And the Vout terminal. The Vout terminal is the current source I_Ten’、 I₁₁'It is connected to the.
[0191]
n-type MOSFETDM₀The source of the memory MOS transistor M₁₀₁', M₁₀₂It is connected to the gate of '. n-type MOSFETDM₀A timing clock pulse (corresponding to clock signals SA and SB) φ is input to the gate of. When the current signal Iin is input, the n-type MOSFET DM₀Is on (conduction between source and drain), and is off when holding a current signal.
[0192]
Here, the memory MOS transistor M₁₀₁', M₁₀₂When the current signal Iin is input to ′, the memory MOS transistor M₁₀₁', M₁₀₂N-type MOSFET DM so that current J flows between the source and drain of₀Through the memory MOS transistor M₁₀₁', M₁₀₂The voltage at the gate of 'is set to Vgn. At this time, the memory MOS transistor M₁₀₁', M₁₀₂Parasitic capacitance C parasitically present at the source of₁₀₁Is charged with a voltage of Vgn with respect to ground.
[0193]
Memory MOS transistor M₁₀₁', M₁₀₂When changing from a state in which the current signal Iin is input to 'to a state in which the current signal Iin is held, the n-type MOSFET DM₀Is in the ideal state, the memory MOS transistor M₁₀₁', M₁₀₂The voltage at the gate of 'is held at Vgn.
[0194]
However, in general, n-type MOSFET DM₀Has a gate-source parasitic capacitance C because its gate changes from a positive voltage to 0 V when it is turned off.₁₀₂From the memory MOS transistor M.₁₀₁', M₁₀₂'Gate and memory MOS transistor M₁₀₁', M₁₀₂′ Gate-source parasitic capacitance C₁₀₁As a result, the memory MOS transistor M₁₀₁', M₁₀₂The gate voltage Vgn of 'varies. This variation in charge is called clock field through and is a major cause of current signal transfer errors in this configuration. This memory MOS transistor M₁₀₁', M₁₀₂And the memory MOS transistor M₁₀₁', M₁₀₂The current flowing between the drain and source of the ′ fluctuates, and the memory MOS transistor M₁₀₁', M₁₀₂An error is introduced into the current signal output from ′.
[0195]
Therefore, the memory MOS transistor M₁₀₁', M₁₀₂'And the gate capacitance and the source-gate parasitic capacitance are increased, or the n-type MOSFET DM₀It is conceivable to reduce the influence of this charge distribution by reducing the parasitic capacitance of the capacitor, but it is not possible to suppress all errors.
[0196]
FIG. 27B shows a dummy MOS transistor DM.₁A configuration for reducing this transfer error is shown.
[0197]
Here, the memory control switch SW₁₁, SW_{twenty one}Is an n-type MOSFET DM₀And dummy MOS transistor DM₁It consists of and. n-type MOSFETDM₀The source of the dummy MOS transistor DM₁Connected to the drain of the dummy MOS transistor DM₁The source of the memory MOS transistor M₁₀₁', M₁₀₂It is connected to the gate of '. The dummy MOS transistor DM₁The source and drain of each are short-circuited. The dummy MOS transistor DM₁N-type MOSFET DM at the gate of₀The timing clock pulse φ ′ having the opposite phase to the timing clock pulse φ input to the gate is input.
[0198]
When the current information signal Iin is input, the n-type MOSFET DM₀Is on and the dummy MOS transistor DM₁Is turned off (usually a voltage of 0 V corresponding to off) is applied to the gate. Memory MOS transistor M₁₀₁', M₁₀₂The gate voltage Vgn is set so that the current value to be supplied to ′ is J.
[0199]
At this time, the memory MOS transistor M₁₀₁', M₁₀₂'Parasitic capacitance C between gate and source₁₀₁Is charged with Vgn. The dummy MOS transistor DM₁Source-gate parasitic capacitance C₁₀₃, Drain-gate parasitic capacitance C₁₀₄Is a dummy MOS transistor DM₁Because of the potential difference between the gate voltage (usually 0 V in the state where the current signal is stored in memory) and Vgn (approximately 1 V), the battery is almost discharged.
[0200]
Consider a case where the current signal holding state changes in this state.
[0201]
n-type MOSFETDM₀Is turned off from on, its gate voltage becomes almost 0V, and the parasitic capacitance C₁₀₂Is discharged. On the other hand, dummy MOS transistor DM₁When the gate is turned on, the parasitic capacitance C₁₀₃, C₁₀₄Will be charged. At this time, the parasitic capacitance C₁₀₂Charge discharged from the battery and parasitic capacitance C₁₀₃, C₁₀₄When the same amount of charge is charged, the parasitic capacitance C₁₀₁Since no charge redistribution occurs through the memory voltage Vgn, the memory voltage Vgn does not fluctuate.
[0202]
n-type MOSFETDM₀And dummy MOS transistor DM₁Are manufactured with the same nMOSFET, the dummy MOS transistor DM for the same gate length L₁The gate width W may be halved. By adopting this configuration, a single memory MOS transistor M₁₀₁', M₁₀₂It is possible to reduce the transfer error of the current signal '.
[0203]
FIG. 28 shows a circuit configuration when this dummy gate structure is applied to the one-input multiple-output current delay flip-flop CDFF1 shown in FIG. Thus, by reducing the single transfer error, it is possible to improve the characteristics of the entire correlator.
[0204]
Although the case where an nMOSFET is used as a dummy gate has been described here, the dummy gate can also be configured using a pMOSFET.
[0205]
Embodiment 8 of the Invention
(Description of 1-input multiple-output current delay flip-flop CDFFi that can output a current value that is a real multiple of the input current signal)
When performing correlation processing, when correlation is obtained, all input signals are added with the same sign. For example, assuming that the number of chip information arrays is L, the current is L times the input current Iin. The value will eventually be output from the correlator.
[0206]
In the embodiment of the present invention, partial correlation is performed. When the correlation current increases, the current value of the current source of the N-chip current delay circuit Ndelay needs to be increased. In order to maintain the linearity, a current value more than twice the current value to be delayed is required.
[0207]
In the current mode correlator, it is possible to reduce the current value at a certain rate within the range that maintains the dynamic range required for the system. FIG. 29 shows the structure of a 1-input multiple-output current delay flip-flop CDFFi. The operation of the current current mirror circuits CMR1 and CMR2 when the current signal Iin of the one-input multiple-output current delay flip-flop CDFFi shown in FIG. Are the same. When it is desired to make the output current Iout M times as large as the current signal Iin (M is a number of “1” or less here, but may be “1” or more), the current value of the current source I is set to J × M. And the gate width W is set to W × M while keeping the size L of the memory MOS transistor constant. FIG. 29 shows a case where M = 1/2.
[0208]
By adopting this circuit configuration, it is possible to output the delayed transfer current to each parallel current path switching circuit block unit 101 as Iin × M while maintaining the transfer current to the next stage at Iin. When the circuit is created so that the delay transfer current to all the parallel current path switching switch block units 101 is M times, the output of the correlator is M times the correlation output expected from the input current Iin. It is possible to obtain it while maintaining the proportional relationship. By setting the value of M as small as possible within the range that can maintain the dynamic range due to the noise, nonlinearity, and distortion of the correlator, it is possible to reduce the current value J to be set while keeping the number of current sources constant. Yes, it is possible to reduce power consumption.
[0209]
Ninth Embodiment
In the first to eighth embodiments of the present invention, spread data corresponding to exactly one cycle per unit of information (1 bit), that is, a spread code having a long cycle of chip length L is used. A correlator that repeats one or more types of short-cycle spreading codes two or more times or combines them to form one unit of information and takes a correlation with this one information code as a unit. is there. The present invention can also be applied to this type of correlator, and the configuration of this correlator will be described below with reference to FIGS.
[0210]
Here, it is assumed that the short-period spreading codes assumed are q types of short-period spreading codes of A1, A2,. However, q is a positive integer. The contents of each short cycle spread code are as follows.
A1 = (a11, a12, a13,..., A1N₁)
A2 = (a21, a22, a23, ..., a2N₂)
……
Aq = (aq1, aq2, aq3, ..., aqN_q)
A spreading code Y corresponding to one unit of information is created by combining these short-cycle spreading codes. That is, Y = (A1, A2,..., Aq)
Note that the same short-cycle spreading code is repeated twice or more, for example, a short-cycle spreading code A1 is repeated twice to form one unit of information. Also, among the short-cycle spreading codes, spreading codes having the opposite relationship to each other, for example, when spreading code A1 and spreading code A2 are in the relation of A1 = −A2, are the same spreading code. It shall be handled.
[0211]
Here, the lengths (chip lengths N) of the short cycle spreading codes may be the same or different, but may be different, but in the following description, the lengths N of the spreading codes are assumed to be the same. To do.
[0212]
FIG. 30 is a diagram showing an example of a correlator using a short cycle spreading code. FIG. 30 shows a single short cycle spreading code A = (a1, a2, a3,..., AN) as M. The case where the correlation of the signal sequence of the spreading code Y which constitutes one unit of information by combining them is shown.
[0213]
For example, the configuration of the spreading code is Y = (A, A, A,..., -A, A). For convenience of explanation, this spreading code Y is expressed as Y = (A1, A2, A3,..., A (M−1), AM) assuming that the types of spreading codes are different.
[0214]
In FIG. 30, the 1-input multiple-output current delay circuit block unit 101 is composed of N 1-input 2-output current delay flip-flops CDFFi. When the spreading code Y is composed of different q types of short-period spreading codes, the 1-input multiple-output current delay circuit block unit 101 is composed of N 1-input (q + 1) output current delay flip-flops CDFFi. Is done.
[0215]
Partial correlation current output means 105_kIs one because there is only one kind of short-cycle spreading code. Partial correlation current output means 105_kAre output to the 1-input M-output current distribution circuit 150. The 1-input M-output current distribution circuit 150 supplies the same partial correlation output current as the input partial correlation output current to M output terminals Tp.₁, Tp₂... Tp_m-1, Tp_mIt plays a role to output from.
[0216]
This partial correlation output current is input to the partial correlation output code processing circuit 151. The partial correlation output code processing circuit 151 includes input terminals P (1) a, P (2) a,..., P (M-1) a, P (M) a and output terminals P (1) b, P (2 ) B,..., P (M-1) b, P (M) b, and short-cycle spreading codes A1, A2,. It plays a role of performing processing corresponding to. For example, since the other spreading codes except the spreading code A (M−1) are “+” here, the input terminals P (1) a, P (2) a,. Since the output terminals P (1) b, P (2) b,..., P (M) b are connected and the short cycle spread code P (M−1) is “−A”, the input terminal P ( M-1) a and the output terminal P (M-1) b are connected via a current inverter 152. As a result, the short cycle spread code P (M−1) is output with the code reversed.
[0217]
The output of the partial correlation output code processing circuit 151 is the N chip current delay circuit Ndelay of the partial correlation output current delay circuit block unit 103._kIs input. For example, the partial correlation output current corresponding to the code A1 is subjected to code processing by the partial correlation output code processing circuit 151, and then the N-chip current delay circuit Ndelay.₁The partial correlation output current corresponding to the code A2 is subjected to the code processing by the partial correlation output code processing circuit 151, and then the N-chip current delay circuit Ndelay.₂N chip current delay circuit Ndelay_M-1By adding the partial correlation output current output from the output terminal TM to the addition current output from the output terminal TM, the correlation process of the spread code Y having a length L corresponding to one unit of information is performed. As a result, a correlation output current is obtained.
[0218]
When the short-cycle spreading codes are of two types, the current signal is delayed by using the one-input (2 + 1) output current delay flip-flop CDFFi, and the two partial correlation current output means 105_kAre used, and two partial correlation current output means 105 are used._kTwo types of partial correlation processing are performed. Each of the partial correlation output currents is input to each one-input multiple-output current distribution circuit 150, and each one-input multiple-output current distribution circuit 150 outputs partial correlation current signals corresponding to the number of chip lengths of the short cycle spread code. The partial correlation output current signal output from each one-input multiple-output current distribution circuit 150 is subjected to code processing by the partial correlation output code processing circuit 151 according to the information of the spread code Y, and then the partial correlation output current delay circuit. Input to the block unit 103.
[0219]
In general, when one or more types of short-period spread codes are used repeatedly or in combination to form spread data with L pieces of chip information constituting one unit of information, partial correlation current output The number of stages of means is equal to the number of types of short-cycle spreading codes.
[0220]
In general, when there is only one kind of short-cycle spreading code, the structure of the 1-input multi-output current delay flip-flop CDFFi only needs to be a 1-input 2-output structure, and the partial correlation current output means 105_kHowever, since only one is sufficient, the number of current sources when the number of short-cycle spreading codes is one round and the number of repetitions is M is estimated as follows.
[0221]
The number of constant current sources per 1-input 2-output current delay flip-flop CDFFi is
4 + 2 = 6
It is.
[0222]
Since N current delay flip-flops CDFFi are used, the total number of constant current sources is 6 × N = 6N.
[0223]
The number of constant current sources used in the 1-input M-output current distribution circuit 150 is M + 1.
[0224]
The number of constant current sources of the partial correlation output current delay circuit block unit 103 is
(N + 1) × (M−1).
[0225]
Therefore, the total number of current sources in this case is M × N + 2M−5N + 6.
[0226]
In the second embodiment of the present invention, the number of constant current sources is 2M × N + 3N−M−1, but according to the ninth embodiment of the present invention, there are M × N + 2M−5N + 6. Thus, the number of constant current sources can be reduced by about M × N, and the number of current sources can be substantially reduced to about half. In the current mode correlator, since the current in which power consumption constantly flows is dominant, the fact that the number of constant current sources can be reduced to about half means that the current value can be greatly reduced. Further, the N-chip current delay circuit Ndelay of the partial correlation output current delay circuit block unit 103_kIf the current cut is applied, the power consumption of the partial correlation output current delay circuit block unit 103 can be further reduced, so that the power consumption of the entire circuit can be further reduced.
[0227]
This circuit increases because the 1-input M-output current distribution circuit 150 must be provided, but the circuit scale is very small. Thus, a spread code composed of a combination of short-cycle spread codes is used. On the other hand, if the circuit configuration shown in FIG. 30 is adopted, the circuit scale can be greatly reduced and the power consumption can be suppressed.
[0228]
FIG. 31 is a diagram showing a modification of the partial correlation output current delay circuit block unit 103 shown in FIG. In FIG. 30, the current adding circuit iadd_kIs input to the partial correlation output current delay circuit block unit 103. Since the configuration of the 1-input multiple-output current delay circuit block unit and the configuration of the partial correlation current output unit are the same as those shown in FIG. 30, detailed description thereof is omitted.
[0229]
In FIG. 31, the partial correlation output current delay circuit block unit 103 includes a 1-input 2-output current distribution circuit B20._kAnd N-chip current delay circuit Ndelay_kAnd a partial correlation output code processing circuit 151, a 1-input 2-output current distribution circuit B20_kAnd N-chip current delay circuit Ndelay_kAnd are connected alternately. Current adding circuit iadd_kOutput is 1-input 2-output current distribution circuit B20₁Has been entered.
[0230]
1-input 2-output current distribution circuit B20_kOutputs the partial correlation current input to the input terminal from each output terminal, and the current output from one of the output terminals is the N-chip current delay circuit Ndelay in the next stage._kThe current output from the other output terminal is input to the input terminal P (k) a of the partial correlation output code processing circuit 151. The partial correlation output code processing circuit 151 performs the correlation current code processing in the same manner as that of the configuration shown in FIG. 30 according to the code (+ or −) of the short-cycle spread code. When the sign is “+”, the input terminal P (k) a and the output terminal P (k) b are connected via the wiring only, and when the sign is “−”, the input terminal is connected via the current inverter. P (k) a and its output terminal P (k) b are connected. The partial correlation currents output from the output terminals P (k) b are added via a wire addition or current addition circuit 153 to perform correlation processing, and this correlation current signal is input to the current / voltage conversion means 108. The
[0231]
The modification shown in FIG. 31 can be used only when the number of types of spreading codes is one. In the circuit configuration shown in FIG. 30, a 1-input M-output current distribution circuit is required, but in the case of the circuit configuration shown in FIG. 31, M-1 1-input 2-output current distribution circuits are required.
[0232]
However, since one circuit block can be made smaller, an error in the current signal due to an increase in the number of distributions can be suppressed as compared with the circuit configuration shown in FIG. The circuit scale and the number of current sources are substantially the same as those shown in FIG.
[0233]
【The invention's effect】
As described above, the present invention simplifies the circuit configuration as a whole, so that it is possible to improve the correlation detection accuracy while simultaneously reducing the accumulation of current transfer errors and reducing power consumption. There is an effect that can be.
[Brief description of the drawings]
FIG. 1 is a block diagram of a code division multiplexing communication apparatus according to the present invention.
FIG. 2 is a timing chart for explaining generation of transmission radio waves.
FIG. 3 is a timing chart for explaining a relationship between a voltage signal based on a received radio wave and a correlation current signal.
4 is a block diagram showing an internal configuration of the correlator shown in FIG. 1. FIG.
FIG. 5 is a circuit diagram showing an example of the configuration of the current / voltage conversion means shown in FIG. 4;
6 shows a basic configuration of the one-input multiple-output current delay flip-flop shown in FIG. 4, (a) is a detailed circuit diagram thereof, and (b) is a timing chart thereof.
7 is a timing chart for explaining the order of current signal samples of the one-input multiple-output current delay flip-flop shown in FIG. 6; FIG.
8 is a diagram showing an example of a switch connection state of the partial correlation current output means shown in FIG.
FIG. 9 is a detailed circuit diagram showing an example of the pair switch shown in FIG. 4;
10 is a circuit diagram showing a detailed configuration of the current adding circuit shown in FIG. 4;
11 is a block diagram showing an internal configuration of the N-chip current delay circuit shown in FIG. 4. FIG.
12 is a time chart showing a timing clock applied to the control switch of the N-chip current delay circuit shown in FIG. 11. FIG.
13 is a detailed circuit diagram of the N-chip current delay circuit shown in FIG.
14 is a diagram showing an example of a configuration of a current / voltage conversion unit shown in FIG. 4. FIG.
FIG. 15 is a diagram for explaining the principle of correlation processing according to the present invention. FIG. 15A shows a case where L current delay flip-flops are arranged in series as in the past, and correlation processing is performed. ) Shows a case where the current delay flip-flops are equally divided into M and arranged in units of N to perform partial correlation processing.
16A and 16B are diagrams for explaining the details of the circuit configuration of the current source shown in FIG. 6A, in which FIG. 16A represents the current source with an equivalent symbol, and FIG. The case where it comprises with a MOS transistor is shown.
FIG. 17 is a detailed circuit diagram showing another embodiment of the invention of a one-input multiple-output current delay flip-flop.
FIGS. 18A and 18B are diagrams for explaining operating characteristics of a MOS transistor, in which FIG. 18A representatively shows an n-channel MOS transistor, FIG. 18B shows its operating characteristics, and FIG. 18C shows a p-channel MOS transistor; Is representatively shown, and (2) shows its operating characteristics.
19 is an explanatory diagram of a cascode MOS transistor in which two n-channel MOS transistors are combined. FIG. 19A shows the cascode MOS transistor, and FIG. 19B shows improved operating characteristics.
FIG. 20 is an explanatory diagram of a cascode MOS transistor in which two p-channel MOS transistors are combined. FIG. 20A shows the cascode MOS transistor, and FIG. 20B shows improved operating characteristics.
21 is a circuit diagram when the cascode MOS transistor shown in FIG. 20 is used for the current source shown in FIG. 17 and the cascode MOS transistor shown in FIG. 19 is used for the n-channel MOS transistor shown in FIG.
FIG. 22 shows an example of an n-channel equivalent MOSFET, (A) shows the circuit configuration of the n-channel equivalent MOSFET, and (B) shows improved operating characteristics.
FIG. 23 shows an example of a p-channel equivalent MOSFET, (A) shows the circuit configuration of the p-channel equivalent MOSFET, shows an example of the circuit configuration, and (B) shows improved operating characteristics.
24 is a circuit diagram in the case of applying a regulated cascade circuit to the N-chip current delay circuit shown in FIG.
FIG. 25 is a timing chart for explaining a case where current cut is performed on the one-input multiple-output current delay flip-flop shown in FIG. 6;
26 is a timing chart for explaining a case where current cut is performed in the N-chip current delay circuit shown in FIG. 13; FIG.
27 is an explanatory diagram for improving current transfer error due to the presence of the memory control switch shown in FIG. 17, and FIG. 27A is a detailed circuit diagram of the memory control switch shown in FIG. FIG. 18 is a detailed circuit diagram in which dummy MOS transistors are provided in the memory control switch shown in FIG. 17 to improve the operation characteristics of the memory control switch.
28 is a detailed circuit diagram of a 1-input multiple-output current delay flip-flop when the memory control switch shown in FIG. 27B is applied to the memory control switch shown in FIG.
FIG. 29 is a diagram showing a circuit configuration capable of outputting a current value that is a real number multiple of the input current signal by changing the gate width of the memory MOS transistor of the one-input multiple-output current delay flip-flop shown in FIG. 17; It is.
FIG. 30 is a block diagram illustrating an example of a correlator using a short-cycle spreading code.
31 is a diagram showing a modification of the partial correlation output current delay circuit block unit 103 shown in FIG. 30;
[Explanation of symbols]
7 ... Correlator
100: Voltage / current conversion means
101... 1 input multiple output current delay circuit block unit
103 ... Partial correlation output current delay circuit block unit
105_k... Partial correlation current output means

Claims (25)

Receiving means for receiving a transmission radio wave generated by multiplying an information signal by spread data composed of an array of chip information and outputting a voltage signal;
Voltage / current converting means for converting the voltage signal into a current signal;
Current delay flip-flops of the same number as N obtained by dividing the number L of array of chip information by the integer M, and the current signal held in each current delay flip-flop are current delay flip-flops of the next stage every one chip time. And M current signal output terminals that output current signals held in time series in each of the current delay flip-flops in parallel at the same time as N. An output current delay circuit block unit;
The current connection path is switched so that the current signal from each of the current delay flip-flops is inputted in parallel and the correlation current is partially obtained based on the reference data corresponding to the spread data, and each of the current delay flip-flops M partial correlation current output means for adding the current signals output from the outputs and outputting the partial correlation current;
A partial correlation output current delay circuit for adding M partial correlation output currents output from the partial correlation current output means and delayed in time series by N chip times for each chip time in order to obtain a correlation current signal A block part;
A code division multiplex communication apparatus comprising: a demodulator that receives the correlation current signal and demodulates an original information signal based on the correlation current signal.   The voltage / current conversion means includes a differential amplifier circuit and a voltage follower circuit so that a negative current signal is output when the voltage signal is positive and a positive current signal is output when the voltage signal is negative. The code division multiple communication apparatus according to claim 1, comprising: a circuit connected to each other.   The partial correlation current output means is connected to the current signal output terminal and the connection state is changed based on the reference data, and output from each current signal output terminal based on the connection state of the switch row 2. The code division multiplexing communication apparatus according to claim 1, further comprising current adding means for adding the current signals to output the partial correlation current.   Each of the current delay flip-flops has a first data holding unit and a second data holding unit, and is controlled by a first clock signal and a second clock signal having a phase opposite to that of the first clock signal, The current signal is sampled by the first data holding unit at the rising edge of the first clock signal, and the current signal is held in the first data holding unit at the falling edge of the first clock signal. The current signal is transferred to the second data holding unit at the rising edge of the clock signal, the current signal is held in the second data holding unit at the falling edge of the second clock signal, and the sampled current signal is subsequently transferred. And transferring the same current signal as the current signal output from the second data holding unit to the next current delay flip-flop. Code division multiple access communication system according to claim 3, characterized in that the output to the M switches column.   2. The code division multiplexing communication apparatus according to claim 1, wherein the current delay flip-flop includes a current mirror circuit including a current source and a memory MOS transistor.   6. The code division multiple communication apparatus according to claim 5, wherein the number of the memory MOS transistors is one.   7. The code division multiplexing communication apparatus according to claim 5, wherein the memory MOS transistor is an n-channel MOS transistor.   6. The code division multiple communication apparatus according to claim 5, wherein the current source is composed of a p-channel MOS transistor.   8. The code division multiple communication apparatus according to claim 7, wherein the n-channel MOS transistor is configured by connecting two n-channel MOS transistors in series in order to improve saturation characteristics.   8. The code division multiple communication apparatus according to claim 7, wherein the n-channel MOS transistor is composed of an equivalent MOSFET in which an n-channel MOSFET and a p-channel MOSFET are combined in order to improve saturation characteristics.   The code division multiple communication apparatus according to claim 10, wherein the equivalent MOSFET includes three n-channel MOSFETs and one p-channel MOSFET, and operates as an n-channel MOSFET as a whole. .   9. The code division multiple communication apparatus according to claim 8, wherein the p-channel MOS transistor is configured by connecting two p-channel MOS transistors in series in order to improve saturation characteristics.   9. The code division multiple communication apparatus according to claim 8, wherein the p-channel MOS transistor is composed of an equivalent MOSFET in which an n-channel MOSFET and a p-channel MOSFET are combined in order to improve saturation characteristics.   14. The code division multiplexing communication apparatus according to claim 13, wherein the equivalent MOSFET includes three p-channel MOSFETs and one n-channel MOSFET, and operates as a p-channel MOSFET as a whole. .   2. The code division multiple communication apparatus according to claim 1, wherein a current signal that is a real number multiple of the current signal input to each of the current delay flip-flops is output from the current signal output terminal.   4. The code according to claim 3, wherein the M switch rows include N pair switches, and the partial correlation current is obtained by assigning the reference data to each pair switch and switching a current path. 5. Division multiplexing communication device.   A correlation current signal is obtained by delaying the partial correlation current based on the current signal which has arrived during the N chip time and held in the current delay flip-flops by N chip time and sequentially adding them in time series. The code division multiple communication apparatus according to claim 16.   2. The partial correlation output current delay circuit block unit includes N + 1 current delay elements, and outputs a partial correlation current signal delayed by N chip time every chip time. Code division multiplex communication device.   19. The code division multiplex communication apparatus according to claim 18, wherein the current delay element includes one memory MOS transistor and one current source.   19. The code division multiple communication apparatus according to claim 18, wherein the current delay element comprises a cascode MOS transistor circuit or a regulated cascade circuit.   Each of the current delay flip-flops flows a steady current through the current source only during a time required for sampling the current signal and outputting the current signal, and the steady current is cut during the other time. The code division multiple communication apparatus according to claim 1.   The current source of the partial correlation output current delay circuit block unit supplies a steady current only during a time between sampling of the partial correlation current and its output, and the steady current is cut during the other time. The code division multiple communication apparatus according to claim 1.   2. The code according to claim 1, wherein current-voltage conversion means for converting the correlation current signal into a voltage signal is provided between the partial correlation output current delay circuit block unit and the demodulator. Division multiplexing communication device. The current / voltage conversion means includes a first differential amplifier circuit that receives the correlation current signal and is applied with a bias voltage to output a voltage signal of the sum of the current signal conversion voltage and the bias voltage; And a bias voltage having the same value as the bias voltage is applied, and the bias voltage is removed from the sum voltage signal and a voltage signal corresponding to the correlation current signal is output. 2. The code division multiplex communication apparatus according to claim 1 , comprising an amplifier circuit.   The spread code is one or more types of short-cycle spread codes, and the number of chip information arrays constituting one unit of information is L by using the one or more types of short-cycle spread codes repeatedly or in combination. 2. The code division multiplexing communication apparatus according to claim 1, wherein the spread data is formed, and the number of the partial correlation current output units is equal to the number of types of the short-cycle spread codes.

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