JP2007027650A - Multi-layer wiring board and its manufacturing method - Google Patents

Multi-layer wiring board and its manufacturing method Download PDF

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JP2007027650A
JP2007027650A JP2005211592A JP2005211592A JP2007027650A JP 2007027650 A JP2007027650 A JP 2007027650A JP 2005211592 A JP2005211592 A JP 2005211592A JP 2005211592 A JP2005211592 A JP 2005211592A JP 2007027650 A JP2007027650 A JP 2007027650A
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cavity
wiring board
pattern
low noise
matching inductor
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JP4701896B2 (en
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Tomoya Bando
知哉 坂東
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Murata Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Parts Printed On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a multi-layer wiring board which is finely adjustable in gain and has superior strain characteristics, and to provide its manufacturing method. <P>SOLUTION: The multi-layer wiring board is equipped with a ceramic laminated substrate 7 having a down cavity 17 mounted with an opening down, two low-noise amplifiers 2 mounted in the down cavity 17, a surface acoustic wave filter 3 mounted on the top surface 7a of the ceramic laminated substrate 7, etc. Inductors SL1 and SL2 for fine matching corresponding to frequencies of the low-noise amplifies 2 are interposed between emitters and grounds of the two low-noise amplifiers 2. The inductors SL1 and SL2 for matching are formed in the same layer and arranged on a wall surrounding the cavity 17 of the ceramic laminated substrate 7. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、多層配線基板、特に、携帯電話などの移動体通信機器などに組み込まれて用いられる多層配線基板及びその製造方法に関する。   The present invention relates to a multilayer wiring board, and more particularly to a multilayer wiring board used by being incorporated in a mobile communication device such as a mobile phone and a manufacturing method thereof.

従来より、この種の多層配線基板として、特許文献１に記載のものが知られている。特許文献１に記載の多層配線基板は、それぞれ異なる帯域中心周波数を有する二つの弾性表面波フィルタチップと、二つの弾性表面波フィルタ同士の位相を整合させる位相整合用回路（ストリップ線路）とを内蔵した多層パッケージ基板である。   Conventionally, as this type of multilayer wiring board, the one described in Patent Document 1 is known. The multilayer wiring board described in Patent Document 1 includes two surface acoustic wave filter chips each having a different band center frequency and a phase matching circuit (strip line) for matching the phases of the two surface acoustic wave filters. The multilayer package substrate.

そして、この多層配線基板は、前記位相整合用回路（ストリップ線路）を、弾性表面波フィルタチップ実装面の上方に位置するフィルタチップ用のキャビティを構成する層に形成している。しかし、この多層配線基板は、複数の位相整合用回路（ストリップ線路）を、それぞれ異なる層に配置しているので、各周波数帯間の特性ばらつきが大きいという問題点があった。
特開平１０−１２６２１３号公報 In this multilayer wiring board, the phase matching circuit (strip line) is formed in a layer constituting a filter chip cavity located above the surface where the surface acoustic wave filter chip is mounted. However, this multilayer wiring board has a problem in that the characteristic variation between the frequency bands is large because a plurality of phase matching circuits (strip lines) are arranged in different layers.
JP-A-10-126213

そこで、本発明の目的は、ゲインの微調整が可能で、歪み特性の優れた多層配線基板及びその製造方法を提供することにある。   SUMMARY OF THE INVENTION An object of the present invention is to provide a multilayer wiring board capable of fine adjustment of gain and excellent distortion characteristics, and a method for manufacturing the same.

前記目的を達成するため、本発明に係る多層配線基板は、
複数のセラミック層を積み重ねて構成し、かつ、キャビティを有した積層基板と、
キャビティ内に搭載された低ノイズ増幅器と、
積層基板の内部に形成された配線導体パターン、グランド電極パターン及び整合用インダクタパターンと、を備え、
整合用インダクタパターンが、低ノイズ増幅器のエミッタとグランド電極パターンとの間に電気的に接続されるとともに、積層基板のキャビティを囲む壁部に配置されていること、
を特徴とする。 In order to achieve the above object, a multilayer wiring board according to the present invention comprises:
A multilayer substrate having a plurality of ceramic layers stacked and having a cavity;
A low-noise amplifier mounted in the cavity;
A wiring conductor pattern formed inside the multilayer substrate, a ground electrode pattern and a matching inductor pattern,
The matching inductor pattern is electrically connected between the emitter of the low noise amplifier and the ground electrode pattern, and is disposed on the wall surrounding the cavity of the multilayer substrate;
It is characterized by.

本発明に係る多層配線基板においては、互いに異なる周波数に対応する複数の低ノイズ増幅器と、低ノイズ増幅器のそれぞれに対応する複数の整合用インダクタパターンとを備えていてもよい。この整合用インダクタパターンは、同一セラミック層上に形成されていることが好ましい。   The multilayer wiring board according to the present invention may include a plurality of low noise amplifiers corresponding to different frequencies and a plurality of matching inductor patterns corresponding to the low noise amplifiers. This matching inductor pattern is preferably formed on the same ceramic layer.

また、本発明に係る多層配線基板の製造方法は、
複数のセラミック層を積み重ねて構成し、かつ、キャビティを有した積層基板と、
キャビティ内に搭載された低ノイズ増幅器と、
積層基板の内部に形成された配線導体パターン、グランド電極パターン及び整合用インダクタパターンと、を備えた多層配線基板の製造方法であって、
整合用インダクタパターンを、低ノイズ増幅器のエミッタとグランド電極パターンとの間に電気的に接続するとともに、積層基板のキャビティを囲む壁部に配置し、
整合用インダクタパターンの線路長及び／又はパターン幅を異ならせることで低ノイズ増幅器のゲインバランスを調整すること、
を特徴とする。 In addition, a method for manufacturing a multilayer wiring board according to the present invention includes:
A multilayer substrate having a plurality of ceramic layers stacked and having a cavity;
A low-noise amplifier mounted in the cavity;
A method for manufacturing a multilayer wiring board comprising a wiring conductor pattern, a ground electrode pattern and a matching inductor pattern formed inside a multilayer board,
The matching inductor pattern is electrically connected between the emitter of the low noise amplifier and the ground electrode pattern, and disposed on the wall portion surrounding the cavity of the multilayer substrate,
Adjusting the gain balance of the low noise amplifier by varying the line length and / or pattern width of the matching inductor pattern;
It is characterized by.

本発明によれば、整合用インダクタパターンを、積層基板のキャビティを囲む壁部に配置したので、余分な引き回しがなく、低ノイズ増幅器とグランド電極パターン間を最短の長さで電気的に接続することができる。従って、微調整可能な整合用インダクタパターンを形成することができ、ゲインの微調整が可能で、歪み特性の優れた多層配線基板を得ることができる。   According to the present invention, since the matching inductor pattern is disposed on the wall portion surrounding the cavity of the multilayer substrate, there is no extra routing, and the low noise amplifier and the ground electrode pattern are electrically connected with the shortest length. be able to. Therefore, a matching inductor pattern that can be finely adjusted can be formed, a gain can be finely adjusted, and a multilayer wiring board having excellent distortion characteristics can be obtained.

さらに、複数の低ノイズ増幅器のそれぞれに対応する複数の整合用インダクタパターンを同一セラミック層上に形成することにより、各周波数帯間での特性ばらつきを少なくすることができる。   Further, by forming a plurality of matching inductor patterns corresponding to each of the plurality of low noise amplifiers on the same ceramic layer, it is possible to reduce the characteristic variation between the frequency bands.

また、整合用インダクタパターンの線路長及び／又はパターン幅を異ならせることで、低ノイズ増幅器のゲインバランスを容易に調整することができる。   Further, by changing the line length and / or pattern width of the matching inductor pattern, the gain balance of the low noise amplifier can be easily adjusted.

以下、本発明に係る多層配線基板及びその製造方法の一実施例について添付図面を参照して説明する。   Hereinafter, an embodiment of a multilayer wiring board and a manufacturing method thereof according to the present invention will be described with reference to the accompanying drawings.

本実施例ではＷ−ＣＤＭＡデュアルバンド用モジュールを例にして説明する。図１はその低ノイズ増幅器及び弾性表面波フィルタの部分の多層配線基板１を模式的な断面として示す。多層配線基板１は、実装状態で開口部が下向きとなるダウンキャビティ１７を有するセラミック積層基板７と、ダウンキャビティ１７内に搭載された二つの低ノイズ増幅器２と、セラミック積層基板７の上面７ａに搭載された弾性表面波フィルタ３や抵抗などのチップ部品５などを備えている。   In this embodiment, a W-CDMA dual band module will be described as an example. FIG. 1 is a schematic cross-sectional view of the multilayer wiring board 1 in the low noise amplifier and the surface acoustic wave filter. The multilayer wiring board 1 includes a ceramic multilayer substrate 7 having a down cavity 17 whose opening is downward in a mounted state, two low noise amplifiers 2 mounted in the down cavity 17, and an upper surface 7 a of the ceramic multilayer substrate 7. A surface acoustic wave filter 3 mounted and a chip component 5 such as a resistor are provided.

二つの低ノイズ増幅器２は互いに異なる周波数に対応する。これらの低ノイズ増幅器は、セラミック積層基板７に設けた２段の凹形状のキャビティ１７内に収容され、ワイヤボンディング８などで所定の内部導体と電気的に接続されている。この後、キャビティ１７内はエポキシなどの封止樹脂９が充填される。   The two low noise amplifiers 2 correspond to different frequencies. These low noise amplifiers are accommodated in a two-stage concave cavity 17 provided on the ceramic multilayer substrate 7 and are electrically connected to a predetermined internal conductor by wire bonding 8 or the like. Thereafter, the cavity 17 is filled with a sealing resin 9 such as epoxy.

弾性表面波フィルタ３は、周囲に自由空間を必要とするため、セラミックパッケージ内に封入された状態や金属ケースに封入された状態で、セラミック積層基板７の上面７ａにはんだ付けで搭載されている。チップ部品５も、フィルタ３と同様に、セラミック積層基板７の上面７ａにはんだ付けで搭載されている。   Since the surface acoustic wave filter 3 requires a free space around it, the surface acoustic wave filter 3 is mounted on the upper surface 7a of the ceramic multilayer substrate 7 in a state of being enclosed in a ceramic package or a metal case by soldering. . Similarly to the filter 3, the chip component 5 is also mounted on the upper surface 7 a of the ceramic multilayer substrate 7 by soldering.

ところで、Ｗ−ＣＤＭＡデュアルバンド方式は、他の通信方式と比較して、より細かなゲイン（Ｇａｉｎ）調整及び歪み調整が必要とされる。このため、二つの低ノイズ増幅器２のそれぞれのエミッタ及びグランド間に、低ノイズ増幅器２のそれぞれの周波数に対応する微小な（代表値：０．１〜２ｎＨ）整合用インダクタＳＬ１，ＳＬ２を挿入する方法が従来より採られている。   By the way, the W-CDMA dual-band method requires finer gain adjustment and distortion adjustment than other communication methods. For this reason, minute (representative values: 0.1 to 2 nH) matching inductors SL1 and SL2 corresponding to the respective frequencies of the low noise amplifier 2 are inserted between the respective emitters and grounds of the two low noise amplifiers 2. The method is taken conventionally.

そこで、本実施例では、この整合用インダクタＳＬ１，ＳＬ２をセラミック積層基板７のキャビティ１７を囲む壁部に配置している。これにより、余分な引き回しがなく、低ノイズ増幅器２とグランド間を最短の長さで電気的に接続することができる。即ち、低ノイズ増幅器２とセラミック積層基板７の電気的接続は、ワイヤボンディング８で行われているため、セラミック積層基板７側の最初の接続箇所はキャビティ１７内となる。そのため、整合用インダクタＳＬ１，ＳＬ２をセラミック積層基板７のキャビティ１７を囲む壁部に配置することで、余分な引き回しがなくなり、他の配線との結合が少なくなる。この結果、微調整可能な整合用インダクタＳＬ１，ＳＬ２を形成することができ、ゲインの微調整可能で、歪み特性の優れた多層配線基板１を得ることができる。   Therefore, in this embodiment, the matching inductors SL1 and SL2 are disposed on the wall portion surrounding the cavity 17 of the ceramic multilayer substrate 7. Thereby, there is no extra routing, and the low noise amplifier 2 and the ground can be electrically connected with the shortest length. That is, since the electrical connection between the low noise amplifier 2 and the ceramic multilayer substrate 7 is performed by the wire bonding 8, the first connection portion on the ceramic multilayer substrate 7 side is in the cavity 17. For this reason, by arranging the matching inductors SL1 and SL2 on the wall portion surrounding the cavity 17 of the ceramic multilayer substrate 7, there is no extra routing and the coupling with other wirings is reduced. As a result, the matching inductors SL1 and SL2 that can be finely adjusted can be formed, the gain can be finely adjusted, and the multilayer wiring board 1 having excellent distortion characteristics can be obtained.

より詳細に整合用インダクタＳＬ１，ＳＬ２について説明する。図２は、図１のセラミック積層基板７を構成する主要なセラミックシート２１ａ〜２１ｇを示す。セラミックシート２１ａ〜２１ｇは、例えば、セラミック粉末を溶剤に分散させてセラミックスラリーを調整し、これをドクターブレード法、ダイコーター法などによりシート状に成形することにより得る。   The matching inductors SL1 and SL2 will be described in more detail. FIG. 2 shows main ceramic sheets 21a to 21g constituting the ceramic laminated substrate 7 of FIG. The ceramic sheets 21a to 21g are obtained by, for example, preparing ceramic slurry by dispersing ceramic powder in a solvent, and forming the ceramic slurry into a sheet shape by a doctor blade method, a die coater method, or the like.

次に、セラミックシート２１ａ〜２１ｆの所定の位置にビアホール用穴やキャビティ用穴をレーザ光などを用いて形成した後、セラミックシート２１ａ〜２１ｇのそれぞれにスクリーン印刷法によって、導電ペーストで電極パターンを形成するとともに、ビアホール用穴に導電ペーストを充填してビアホール導体ＶＨを形成する。導電ペーストはＡｇ，Ｐｄ，Ｃｕ，Ａｕやこれらの合金などからなる。   Next, via holes and cavity holes are formed at predetermined positions of the ceramic sheets 21a to 21f by using laser light or the like, and then electrode patterns are formed on the ceramic sheets 21a to 21g with a conductive paste by screen printing. At the same time, a via hole conductor VH is formed by filling the via hole with a conductive paste. The conductive paste is made of Ag, Pd, Cu, Au, or an alloy thereof.

本実施例の場合、セラミック積層基板７は１５層からなる。図２（ａ）は、図１において矢印Ａ方向から見た第１層目のセラミックシート２１ａであり、外部端子電極３０とビアホール導体ＶＨと２段キャビティ１７の大開口部１７ａが形成されている。図２（ｂ）は、第５層目のセラミックシート２１ｂであり、配線導体パターン２６とビアホール導体ＶＨと２段キャビティ１７の小開口部１７ｂが形成されている。   In this embodiment, the ceramic laminated substrate 7 is composed of 15 layers. FIG. 2A shows a first-layer ceramic sheet 21 a as viewed from the direction of arrow A in FIG. 1, in which the external terminal electrode 30, the via-hole conductor VH, and the large opening 17 a of the two-stage cavity 17 are formed. . FIG. 2B shows a fifth-layer ceramic sheet 21 b in which a wiring conductor pattern 26, a via-hole conductor VH, and a small opening 17 b of the two-step cavity 17 are formed.

図２（ｃ）は、第７層目のセラミックシート２１ｃであり、整合用インダクタパターンＳＬ１，ＳＬ２とビアホール導体ＶＨと２段キャビティ１７の小開口部１７ｂが形成されている。整合用インダクタパターンＳＬ１，ＳＬ２は、同一セラミックシート上に形成され、二つの低ノイズ増幅器２の互いに異なる周波数に対応して、その線路長を異ならせている。   FIG. 2C shows a seventh-layer ceramic sheet 21 c in which the matching inductor patterns SL 1 and SL 2, the via-hole conductor VH, and the small opening 17 b of the two-stage cavity 17 are formed. The matching inductor patterns SL1 and SL2 are formed on the same ceramic sheet and have different line lengths corresponding to different frequencies of the two low noise amplifiers 2.

図２（ｄ）は、第９層目のセラミックシート２１ｄであり、ビアホール導体ＶＨと２段キャビティ１７の小開口部１７ｂが形成されている。図２（ｅ）は、第１０層目のセラミックシート２１ｅであり、グランド電極パターンＧとビアホール導体ＶＨが形成されている。図２（ｆ）は、第１４層目のセラミックシート２１ｆであり、配線導体パターン２６とビアホール導体ＶＨが形成されている。   FIG. 2D shows a ninth-layer ceramic sheet 21 d in which a via-hole conductor VH and a small opening 17 b of the two-stage cavity 17 are formed. FIG. 2E shows a tenth-layer ceramic sheet 21e on which a ground electrode pattern G and a via-hole conductor VH are formed. FIG. 2F shows a 14th-layer ceramic sheet 21 f in which a wiring conductor pattern 26 and a via-hole conductor VH are formed.

図２（ｇ）は、第１５層目のセラミックシート２１ｇであり、セラミック積層基板７の上面７ａに搭載される弾性表面波フィルタ３を実装するためのランド２４と、チップ部品５を実装するためのランド２５が形成されている。なお、図２（ｇ）だけは図１において矢印Ａ方向とは反対の方向から見た状態を示す。   FIG. 2G shows a fifteenth layer ceramic sheet 21 g for mounting the land 24 for mounting the surface acoustic wave filter 3 mounted on the upper surface 7 a of the ceramic multilayer substrate 7 and the chip component 5. The land 25 is formed. FIG. 2 (g) only shows a state seen from the direction opposite to the arrow A direction in FIG.

各セラミックシート２１ａ〜２１ｇは他のセラミックシートと共に積層された後、圧着されて積層体ブロックとする。積層体ブロックは所定のサイズにカットされた後、焼成される。これにより、セラミック積層基板７とされる。   Each ceramic sheet 21a-21g is laminated | stacked with another ceramic sheet | seat, and is crimped | bonded to make a laminated body block. The laminate block is fired after being cut into a predetermined size. Thereby, the ceramic laminated substrate 7 is obtained.

こうして得られたセラミック積層基板７内において、整合用インダクタパターンＳＬ１，ＳＬ２が同一セラミックシート上に形成されているので、整合用インダクタパターンＳＬ１，ＳＬ２を異なる層に配置したときに生じる両者間の結合によるばらつきを低減することができる。この結果、多層配線基板１は、各周波数帯間の特性ばらつきが小さいＷ−ＣＤＭＡデュアルバンド用モジュールとなる。   Since the matching inductor patterns SL1 and SL2 are formed on the same ceramic sheet in the ceramic multilayer substrate 7 thus obtained, the coupling between the two that occurs when the matching inductor patterns SL1 and SL2 are arranged in different layers. The variation due to can be reduced. As a result, the multilayer wiring board 1 becomes a W-CDMA dual band module with small variations in characteristics between the frequency bands.

また、各低ノイズ増幅器２のゲインバランスを調整する際には、整合用インダクタパターンＳＬ１，ＳＬ２の線路長やパターン幅を異ならせることで、容易に調整することができる。即ち、整合用インダクタパターンＳＬ１，ＳＬ２の線路長を長くしたり、パターン幅を細くしたりすれば、低ノイズ増幅器２のゲインが小さくなる。逆に、整合用インダクタパターンＳＬ１，ＳＬ２の線路長を短くしたり、パターン幅を太くしたりすれば、低ノイズ増幅器２のゲインが大きくなる。   Further, when adjusting the gain balance of each low noise amplifier 2, it is possible to easily adjust the line length and pattern width of the matching inductor patterns SL1 and SL2. That is, if the line length of the matching inductor patterns SL1 and SL2 is increased or the pattern width is reduced, the gain of the low noise amplifier 2 is reduced. Conversely, if the line length of the matching inductor patterns SL1 and SL2 is shortened or the pattern width is increased, the gain of the low noise amplifier 2 is increased.

なお、本発明に係る多層配線基板及びその製造方法は前記実施例に限定するものではなく、その要旨の範囲内で種々に変更することができる。   The multilayer wiring board and the manufacturing method thereof according to the present invention are not limited to the above-described embodiments, and various modifications can be made within the scope of the gist.

本発明に係る多層配線基板の一実施例を示す模式的断面図である。It is typical sectional drawing which shows one Example of the multilayer wiring board which concerns on this invention. 図１のセラミック積層基板７を構成する主要なセラミックシートを示す平面図である。It is a top view which shows the main ceramic sheets which comprise the ceramic laminated substrate 7 of FIG.

符号の説明Explanation of symbols

１…多層配線基板
２…低ノイズ増幅器
７…積層基板
１７…キャビティ
２１ａ〜２１ｇ…セラミックシート
２６…配線導体パターン
Ｇ…グランド電極パターン
ＳＬ１，ＳＬ２…整合用インダクタパターン
DESCRIPTION OF SYMBOLS 1 ... Multilayer wiring board 2 ... Low noise amplifier 7 ... Laminated board 17 ... Cavity 21a-21g ... Ceramic sheet 26 ... Wiring conductor pattern G ... Ground electrode pattern SL1, SL2 ... Matching inductor pattern

Claims (4)

複数のセラミック層を積み重ねて構成し、かつ、キャビティを有する積層基板と、
前記キャビティ内に搭載された低ノイズ増幅器と、
前記積層基板の内部に形成された配線導体パターン、グランド電極パターン及び整合用インダクタパターンと、を備え、
前記整合用インダクタパターンが、前記低ノイズ増幅器のエミッタと前記グランド電極パターンとの間に電気的に接続されるとともに、前記積層基板のキャビティを囲む壁部に配置されていること、
を特徴とする多層配線基板。 A laminated substrate having a plurality of ceramic layers stacked and having a cavity;
A low noise amplifier mounted in the cavity;
A wiring conductor pattern formed inside the multilayer substrate, a ground electrode pattern and a matching inductor pattern,
The matching inductor pattern is electrically connected between the emitter of the low noise amplifier and the ground electrode pattern, and is disposed on a wall portion surrounding the cavity of the multilayer substrate;
A multilayer wiring board characterized by 互いに異なる周波数に対応する複数の前記低ノイズ増幅器と、前記低ノイズ増幅器のそれぞれに対応する複数の前記整合用インダクタパターンとを備えたことを特徴とする請求項１に記載の多層配線基板。   2. The multilayer wiring board according to claim 1, further comprising a plurality of the low noise amplifiers corresponding to different frequencies and a plurality of the matching inductor patterns corresponding to the low noise amplifiers. 前記整合用インダクタパターンが同一セラミック層上に形成されていることを特徴とする請求項１又は請求項２に記載の多層配線基板。   The multilayer wiring board according to claim 1, wherein the matching inductor pattern is formed on the same ceramic layer. 複数のセラミック層を積み重ねて構成し、かつ、キャビティを有する積層基板と、
前記キャビティ内に搭載された低ノイズ増幅器と、
前記積層基板の内部に形成された配線導体パターン、グランド電極パターン及び整合用インダクタパターンと、を備えた多層配線基板の製造方法であって、
前記整合用インダクタパターンを、前記低ノイズ増幅器のエミッタと前記グランド電極パターンとの間に電気的に接続するとともに、前記積層基板のキャビティを囲む壁部に配置し、
前記整合用インダクタパターンの線路長及び／又はパターン幅を異ならせることで前記低ノイズ増幅器のゲインバランスを調整すること、
を特徴とする多層配線基板の製造方法。
A laminated substrate having a plurality of ceramic layers stacked and having a cavity;
A low noise amplifier mounted in the cavity;
A method of manufacturing a multilayer wiring board comprising a wiring conductor pattern, a ground electrode pattern and a matching inductor pattern formed inside the multilayer board,
The matching inductor pattern is electrically connected between the emitter of the low noise amplifier and the ground electrode pattern, and disposed on a wall portion surrounding the cavity of the multilayer substrate,
Adjusting the gain balance of the low noise amplifier by varying the line length and / or pattern width of the matching inductor pattern;
A manufacturing method of a multilayer wiring board characterized by the above.
JP2005211592A 2005-07-21 2005-07-21 Multilayer wiring board and manufacturing method thereof Active JP4701896B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009016501A (en) * 2007-07-03 2009-01-22 Shinko Electric Ind Co Ltd Wiring board with inductor having shielding function

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06310979A (en) * 1993-04-26 1994-11-04 Fujitsu Ltd Branching filter package
JP2000312103A (en) * 1999-04-28 2000-11-07 Mitsubishi Electric Corp Microwave circuit package and manufacture thereof
JP2003283263A (en) * 2002-03-26 2003-10-03 Sharp Corp High frequency amplifier
JP2004364068A (en) * 2003-06-06 2004-12-24 Nippon Telegr & Teleph Corp <Ntt> Frequency band variable amplifier

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06310979A (en) * 1993-04-26 1994-11-04 Fujitsu Ltd Branching filter package
JP2000312103A (en) * 1999-04-28 2000-11-07 Mitsubishi Electric Corp Microwave circuit package and manufacture thereof
JP2003283263A (en) * 2002-03-26 2003-10-03 Sharp Corp High frequency amplifier
JP2004364068A (en) * 2003-06-06 2004-12-24 Nippon Telegr & Teleph Corp <Ntt> Frequency band variable amplifier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009016501A (en) * 2007-07-03 2009-01-22 Shinko Electric Ind Co Ltd Wiring board with inductor having shielding function

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