JP3510971B2 - High frequency power amplifier - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency power amplifier for transmission used in a mobile communication device such as a mobile phone, and in particular, it is possible to reduce the number of manufacturing steps of the product, improve the yield rate and reduce the size. The present invention relates to a high frequency power amplifier.

[0002]

2. Description of the Related Art In recent years, there has been a strong demand for miniaturization and weight reduction of semiconductor devices and electronic parts used in mobile communication devices such as analog or digital mobile phones.

With the miniaturization, the area occupied by the drain line of the high-frequency power amplifier transistor, which is conventionally formed on the substrate, cannot be ignored in the high-frequency power amplifier used in the transmitting section. Miniaturization has been implemented by forming the inner layer.

In addition, the line width and length of the microstrip line that constitutes the high frequency circuit in the substrate of the high frequency power amplifier varies depending on the manufacturing lot of the substrate, and as a result, the electrical characteristics vary and the yield rate decreases. In order to obtain the desired characteristics, change the capacitance value of the chip capacitor used to adjust the electrical characteristics for each board lot or prepare multiple mounting points for the adjustment chip capacitor on the board in advance. It has been attempted to improve the non-defective product rate by mounting it at a mounting location.

A conventional high frequency power amplifier will be described below with reference to FIGS. 6 and 7. FIG. 6 is a plan view of a conventional high frequency power amplifier 1, and FIG.
It is a sectional view taken along the line A-A '.

As shown in FIGS. 6 and 7, in the conventional high frequency power amplifier 1, a microstrip line 3 is formed on the upper surface of a multilayer substrate 2 made of a dielectric material, and the microstrip line 3 is formed on the microstrip line 3. Chip components such as the chip capacitor 4, the chip resistor 5 and the trimmable resistor 6 are mounted and electrically connected, and an input matching circuit 7 and an output matching circuit 8 are formed.

Reference numeral 11 denotes a power amplifying transistor, and the drain line 9 thereof has a length of about 1/4 wavelength (about λ / 4) of the used frequency (for example, a ratio of 4: 1) to prevent leakage of high frequency. This is a transmission line that uses an alumina ceramics substrate with a dielectric constant of about 9.6 and a frequency of about 940 MHz and has a width of about 30 mm. Since the line conductor occupies a large area, it is layered inside and above and below the drain line 9. A ground electrode layer 10 is arranged in the.

The power amplifying transistor 11 is bare-chip mounted on the substrate with silver paste or the like, the electrode thereof is connected to the electrode pad 13 on the multilayer substrate 2 by the bonding wire 12, and further sealed by the sealing resin 14. ing. Further, in order to dissipate the heat generated in the power amplification transistor 11, a large number of heat dissipation via conductors 15 that connect the bottom surface of the transistor mounting portion and the back surface of the multilayer substrate 2 are provided.

In the high frequency power amplifier 1 having such a configuration, there is a problem that the line width and line length of the microstrip line 3 are varied depending on the manufacturing lot of the substrate, and thus the electrical characteristics are varied. The influence of the variation of the microstrip line 3 forming the circuit 8 is large.

Such a microstrip line 3 is usually formed by a printing technique, and if the printing accuracy is improved, the variation in characteristics can be reduced.
Actually, even if the soil has an accuracy of 20 to 30 μm, it is not possible to absorb the characteristic variation for each substrate lot. Therefore, in order to absorb the characteristic variation, it is desired that the capacitance value of the chip capacitor 4 used for adjusting the electrical characteristics be adjusted for each substrate lot or that a plurality of mounting electrodes 59 be prepared in advance on the substrate. By mounting the chip capacitor 3 at a mounting position where characteristics can be obtained, the mounting position of the chip capacitor 3 for adjustment is changed, whereby the microstrip line 3
By adjusting the line length of the output matching circuit 8, the impedance deviation of the output matching circuit 8 is corrected to absorb the characteristic variation,
We have improved the rate of non-defective products.

[0011]

However, in the conventional high frequency power amplifier 1 having the above structure, only the drain line 9 is formed as an inner layer, so that the high frequency power amplifier 1 is provided.
In order to achieve further miniaturization, the area occupied by the microstrip line 3 conventionally formed on the multilayer substrate 2 cannot be ignored. Therefore, a method for realizing miniaturization by also innerizing these as strip lines is also used. Can be considered. However, according to this method, the inductance component of the via conductor that connects the strip line and the electrode pad or the like on the upper surface of the multilayer substrate 2 and the distance between the upper and lower ground electrode layers that sandwich the strip line vary from lot to lot, and There is a problem that the electrical characteristics vary.

Therefore, in order to adjust the variation of the electrical characteristics by changing the capacitance value of the adjusting chip capacitor as in the conventional case, the optimum capacitor capacitance value for each manufacturing lot of the multilayer substrate 2 is determined. It is necessary to check and adjust the product in advance and optimize the mounting position of the adjustment chip capacitor for each manufacturing lot. When mass production is performed by this method, the multilayer substrate 2 is manufactured. Since it is necessary to determine the optimum capacitor capacitance value and its mounting position for each lot, the number of man-hours for manufacturing the product becomes large, the manufacturing process becomes complicated, and it is difficult to increase the yield rate of the product. There was a point. In addition, it is necessary to prepare the capacitance value of the chip capacitors for adjustment in small increments of, for example, 0.1 pF, and it is difficult to manage the inventory of them, which also causes the problem of increasing the number of product manufacturing processes. It was

The present invention has been devised in view of the above circumstances. An object of the present invention is to enable miniaturization, and to easily adjust electric characteristics with respect to variations in characteristics of a multilayer substrate while reducing the number of manufacturing steps. It is an object of the present invention to provide a high-frequency power amplifier suitable for mass production, which can be performed, and thereby can improve the non-defective product rate.

[0014]

A first high frequency power amplifier of the present invention comprises a plurality of insulating layers containing glass as a main component, and has a cavity on the top surface and a cavity for radiating heat from the cavity to the bottom surface. A via conductor is formed below the ground electrode layer around the multilayer substrate having a ground electrode layer on the lower surface of the uppermost layer of the insulating layer and around the cavity and the heat dissipation via conductor in the multilayer substrate. Strip line, a microstrip line formed around the cavity on the upper surface of the multilayer substrate and electrically connected to a connection conductor extending from the strip line to the upper surface of the multilayer substrate, and the heat radiation for the cavity. Power amplification transistor mounted on via conductor and electrically connected to the microstrip line, and the multilayer substrate A chip component mounted on the upper surface,
A pad electrode that is formed in addition to the microstrip line around the cavity on the upper surface of the multilayer substrate and that faces the ground electrode layer through the uppermost layer of the insulating layer. is there.

The second high frequency power amplifier of the present invention is composed of a plurality of insulating layers containing glass as a main component, and has a cavity on the upper surface and a heat dissipation via conductor which penetrates from the cavity to the lower surface inside. A multi-layer substrate having a ground electrode layer on the lower surface of the uppermost layer of the insulating layer, and formed around the cavity and the heat dissipation via conductor in the multi-layer substrate below the ground electrode layer and electrically connected to each other. Electrically connected to the first and second strip lines connected to the first connection conductor and the first connection conductor that is mounted on the heat dissipation via conductor of the cavity and extends from the first strip line to the upper surface of the multilayer substrate. The connected power amplification transistor and the second strip line which is mounted on the upper surface of the multilayer substrate and extends from the second strip line to the upper surface of the multilayer substrate. A chip component electrically connected to the connection conductor and a third connection conductor formed around the cavity on the upper surface of the multilayer substrate and led out from the second strip line to the upper surface of the multilayer substrate. A pad electrode connected to and facing the ground electrode layer through the uppermost layer of the insulating layer.

According to the high frequency power amplifier of the present invention, a drain bias line having a length of about one-quarter wavelength (about λ / 4) of the power amplification transistor is conventionally formed on the upper surface of the multilayer substrate. Instead of the microstrip line,
By forming a strip line inside the multilayer board using glass as the main component and lining the drain bias line that occupied a large surface area on the top surface of the board inside the multilayer board, The size of the high frequency power amplifier can be greatly reduced.

Further, since the drain bias line, which is a transmission line for high-frequency signals, is internally layered on the multilayer substrate as a strip line, there are ground electrode layers above and below the signal lines of those transmission lines. Therefore, it becomes difficult to be influenced by the electromagnetic noise that intrudes into the transmission line from the outside, and the isolation characteristic becomes good. Furthermore, by arranging the ground electrode layers above and below the transmission line that is a signal line, the magnetic field of the high-frequency signal transmitted is blocked between the ground electrode layers, which results in a structure with less signal loss and a drain bias. The Q characteristic is improved compared to the case where the line is formed by the microstrip line on the upper surface of the multilayer substrate (for example, from about 70
It will be about 90).

According to the first high-frequency power amplifier of the present invention, the upper surface of the multi-layer substrate is connected in parallel to the microstrip line of the output matching circuit or the input matching circuit formed by the microstrip line and the chip parts. Since the pad electrode is added, the pad electrode forms a capacitor between the pad electrode and the ground electrode layer inside the multi-layer substrate facing the uppermost layer of the insulating layer. The capacitance value can be changed by selectively shaving or cutting by using a luteer or the like. Further, by adding a plurality of such pad electrodes, the length of the microstrip line can be adjusted by selectively cutting the connection part between them and the microstrip line with a laser, a lute, or the like. Therefore, by combining these, the electrical characteristics of the output matching circuit and the input matching circuit can be easily adjusted to the desired electrical characteristics even after the product is assembled. It becomes a high frequency power amplifier in which variations in characteristics can be easily adjusted after product assembly.

According to the second high frequency power amplifier of the present invention, the output matching circuit and the input matching circuit are constituted by the strip line formed inside the multi-layer substrate and the chip parts mounted on the upper surface of the substrate. It is possible to achieve further miniaturization compared to the case where it is configured with a strip line, and since a pad electrode connected in parallel to the strip line in a circuit is formed and added on the upper surface of the substrate, this pad electrode is used. A capacitor is formed between this and the ground electrode layer inside the multi-layered substrate facing through the uppermost layer of the insulating layer, and the electrical characteristics of the output matching circuit and the input matching circuit are similar to those of the first high frequency power amplifier. Even after assembling the product, etc., it can be easily adjusted to the desired electrical characteristics. The high-frequency power amplifier can be easily adjusted to variations in the sex after assembly of the product.

As described above, according to the high frequency power amplifier of the present invention, a selected product such as a chip capacitor or a chip resistor, in which a constant is determined for each manufacturing lot of a multi-layered board and selected in fine units of 0.1 pF as in the prior art. Since the process to be used is unnecessary and the electrical characteristics can be adjusted by using a normal chip capacitor, etc., it is possible to reduce the manufacturing man-hours and material costs, and The non-defective rate can also be improved.

Further, it is not necessary to change the mounting position of the chip capacitor or the like for each manufacturing lot of the multi-layer substrate, the manufacturing process is simplified, and so-called prior confirmation is not necessary, and the number of manufacturing steps can be reduced. At the same time, the rate of non-defective products can be improved.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to the drawings. Note that the following is merely an example of the present invention, and the present invention is not limited thereto, and various modifications and improvements may be made without departing from the scope of the present invention.

FIG. 1 is a sectional view similar to FIG. 7 showing an example of an embodiment of a first high frequency power amplifier of the present invention, and FIG. 2 is an external view showing the state of the upper surface with the case removed. It is a perspective view. In the high frequency power amplifier 21 shown in these figures, 22 is a multilayer substrate formed by laminating a plurality of insulating layers containing glass as a main component, and 23 is a lower surface of the uppermost layer 22a of the insulating layers of the multilayer substrate 22. Formed ground electrode layer, 24
Is a strip line formed below the ground electrode layer 23 in the multilayer substrate 22, and 25 is a strip line from the strip line 24 to the multilayer substrate 22.
, A microstrip line formed on the multilayer substrate 22 and electrically connected to the connection conductor 25, and a microchip line 27 mounted on the multilayer substrate 22 and electrically connected to the microstrip line 26. The power amplification transistor 28 is a chip component such as a chip resistor or a chip capacitor that is mounted on the multilayer substrate 22 and electrically connected to the microstrip line 26.29 is added to the microstrip line 26 on the multilayer substrate 22. The uppermost layer 22a of the insulating layer formed by
The pad electrode is opposed to the ground electrode layer 23 via the. A capacitor is formed by the pad electrode 29 and the ground electrode layer 23 inside the multilayer substrate 22 facing the pad electrode 29 with the uppermost layer 22a of the insulating layer interposed therebetween. By changing the area of the pad electrode 29 on the upper surface of the multilayer substrate 22 by using a laser, a lutor, or the like, it is possible to change the capacitance value of the capacitor formed between the opposing ground electrode layer 23 and the microstrip. The output matching circuit or the input matching circuit configured by the line 26 and the chip component 28 can be adjusted to desired electrical characteristics, and thus the characteristic variation due to the variation of each manufacturing lot of the multilayer substrate 22 can be reduced by the number of manufacturing steps. Adjustments can be made while reducing the amount.

Further, 30 is a bonding wire, which connects each electrode (source / gate / drain) of the power amplification transistor 27 and the strip line 24 as a drain bias line via a connection conductor 25 (for example, to the connection conductor 25). They are electrically connected (bonded to a conductor layer or the like electrically connected to the microstrip line 26, at least a part of which is exposed on the upper surface of the connected multilayer substrate 22).

In this example, the power amplification transistor 27 is fixed to the mounting cavity 31 on the multilayer substrate 22 with a resin or solder-based connection paste 32 and sealed with a sealing resin 33. Note that the cavity 31 has a depth of 0.3 mm in a stepwise manner according to the size of the power amplification transistor 27, for example, by stacking several sheets on the upper surface side of the multi-layer substrate 22 with an opening having a predetermined shape and stacking them. It is formed with a degree. Reference numeral 34 is a heat dissipation via conductor formed inside the multilayer substrate 22 below the power amplification transistor 27.

Further, in the high frequency power amplifier 21 of this example, the strip line 24 as the drain bias line is used.
Is formed between the upper and lower ground electrode layers 35 and 36 below the ground electrode layer 23. Stripline 24
Alternatively, the ground electrode layer 23 may be an inner layer as the upper ground electrode layer.

Reference numeral 37 denotes a case, which is used to mount and mount the power amplification transistor 27 and the chip component 28 on the multilayer substrate 22 and then to apply a sealing resin or the like (not shown) so as to cover the upper surface of the multilayer substrate 22. The high frequency power amplifier 21 is completed by this, and electrically connected to the connection land of the external electric circuit via the terminal electrode 38 formed by utilizing the castellation on the upper surface periphery and the side surface of the multilayer substrate 22. Connected to.

If desired, a conductor layer, a ground electrode layer 36, or the like may be extended from the terminal electrode 38 to the lower surface or the upper surface of the multi-layer substrate 22, so that the external layer can be mounted on an external circuit board such as a mother board. The electrical connection with the connection land on the circuit board can be made more reliable.

The multi-layer substrate 22 is a so-called low temperature firing multi-layer substrate containing glass as a main component. For example, an internal wiring pattern is printed on a green sheet made of glass ceramics having a thickness of about 0.14 to 0.16 mm, and through holes and via holes are processed. A laminate obtained by laminating a plurality of layers subjected to the above and firing is used, and one having an effective relative dielectric constant of about 8.1 is preferably used.

The strip line 24, the microstrip line 26, the ground electrode layers 23, 35, 36, etc. are printed in a desired pattern on the green sheet of the multi-layer substrate 22 before firing, for example, by using an Ag-based conductive paste and firing at the same time. By doing so, it is formed inside and on the front surface or the back surface of the multilayer substrate 22. The thickness is set to, for example, about 10 to 20 μm according to desired transmission characteristics.

The connection conductor 25 is formed by being led out from the strip line 24 to the upper surface of the multilayer substrate 22 to form the strip line 24 and the microstrip line 26, and the strip line 24, the power amplification transistor 27 and the chip component 28.
Various shapes and structures can be used as long as they are electrically connected to each other. For example, a method such as plating or printing / sintering of a conductive paste inside the through hole provided in the multilayer substrate 22. A through hole formed by depositing a conductive metal containing Ag or the like as a main component, or a via hole filled with the conductive metal by a method such as printing or sintering of a conductive paste inside the through hole. Conductor),
It is possible to use various shapes such as elliptical shapes, rectangular shapes, polygonal shapes, and plate shapes for the cross-sectional shapes of the through holes and the via holes instead of the circular shapes.

The power amplification transistor 27 is, for example, a high frequency power amplification FET (field effect transistor).
Is used to mount Au / Si in the cavity 31.
It is fixed and electrically connected by a connection paste 32 as a die attach material such as solder or Ag paste, and is led to the upper surface of the multilayer substrate 22 by a bonding wire 30 made of Au and having a thickness of about 25 μm. It is electrically connected to the strip line 24 and the microstrip line 26 via the connected connection conductor 25 or a conductor layer extended to the connection conductor 25.

As the chip component 28, a surface mount type chip resistor or chip capacitor generally used as a circuit of the high frequency power amplifier 21 is used.

To form the terminal electrode 38, a width of 0.6 to 0.6 mm is provided at the end of each green sheet at a desired position of the multilayer substrate 22 according to the circuit arrangement of the external circuit substrate on which the high frequency power amplifier 21 is mounted. A multi-layer substrate 22 after stacking these sheets while forming a recess by forming a notch with a depth of 0.8 mm and a depth of 0.6 to 0.8 mm 22
The conductive paste may be formed in the concave portion (side surface) by printing / sintering of the above-described conductive paste, a metallizing method, or the like.

As the heat radiating via conductor 34, the same via conductor as the above-mentioned connecting conductor 25 may be used, and the multilayer substrate 22 from the cavity 31 to the opposing multilayer substrate 22 at the mounting location of the power amplifying transistor 27. A large number are formed so as to penetrate to the back surface of the power amplification transistor 27, and the heat generated from the power amplification transistor 27 is conducted to the external circuit base via the conductor layer 36 serving as the ground electrode layer on the back surface of the multilayer substrate 22 and radiated.

The heat-dissipating via conductor 34 is provided under the power amplifying transistor 27 as shown in FIG.
You may arrange the same number from the top to the bottom of 22,
The number may be sequentially increased from the bottom of the power amplification transistor 27 to the lower surface of the multilayer substrate 22 according to the diffusion of heat from the power amplification transistor 27.

Further, since the heat dissipation becomes better as the heat dissipation via conductors 34 are provided as many as possible, the heat dissipation can be efficiently performed by arranging the via conductors 34 in a staggered manner so that the maximum number can be set in the same area. Being able to do this is preferable.

Next, the adjustment of electric characteristics by the pad electrode 29 for adjusting characteristics will be described in detail. FIG. 3 is an equivalent circuit diagram showing a circuit configuration of an output matching circuit portion constituted by the microstrip line 26, the chip component 28, the pad electrode 29, the ground electrode layer 23, etc. in the high frequency power amplifier 21. The same parts as those in FIG. 2 are denoted by the same reference numerals.

In FIG. 3, C _{1 to} C ₄ are pad electrodes 29.
Is a pattern capacitor formed by facing the ground electrode layer 23 through the uppermost layer 22a of the insulating layer.

When the width and length of the strip line 24 and the distance between the strip line 24 and the ground electrode layers 35 and 36 sandwiching the strip line 24 from above and below vary depending on the manufacturing lot of the multilayer substrate 22, the high frequency power amplifier Among the 21 electrical characteristics, adjacent channel leakage power characteristics, current consumption characteristics, output power, etc. vary. Therefore, in order to absorb and adjust these variations, the pattern capacitor C formed by the pad electrode 29 and the ground electrode layer 23 added to the microstrip line 26 in circuit parallel with the strip line 24.
_{1 to} C ₄ capacitance value and these pattern capacitors C
Adjusting the electrical characteristics by adjusting the presence or absence of connection ₁ -C _4. For example, in order to cope with the variation in the ACP (adjacent channel leakage power) characteristic due to the variation in the length of the strip line 24, the connecting portion between the microstrip line 26 and the pad electrode 29 is selectively used by using a laser or a luteer. By disconnecting the pad electrode 29, the connection of the pad electrode 29 is lost and the microstrip line 26 is lengthened and the length is adjusted, whereby the output matching impedance can be adjusted. Similarly, in order to suppress variation in ACP characteristics, the capacitance formed by the pad electrode 29 is changed by selectively shaving or cutting the area of the pad electrode 29 by using a laser or a luteer. The output matching impedance can be adjusted by changing the value.

Next, a second high frequency power amplifier of the present invention will be described with reference to FIGS. 3 and 4. FIG. 4 is a sectional view similar to FIG. 1 showing an example of an embodiment of a second high frequency power amplifier of the present invention, and FIG. 5 is similar to FIG. 2 showing the state of the upper surface with the case removed. FIG.

In the high frequency power amplifier 41 shown in FIGS. 4 and 5, 42 is a multilayer substrate formed by laminating a plurality of insulating layers containing glass as a main component, and 43 is the maximum of the insulating layers of the multilayer substrate 42. A ground electrode layer formed on the lower surface of the upper layer 42a, 44
Is a first strip line formed below the ground electrode layer 43 in the multilayer substrate 42, 45 is a first connecting conductor led from the first strip line 44 to the upper surface of the multilayer substrate 42, and 46 is a multilayer substrate A second strip line formed inside 42 and electrically connected to the first strip line 44, and 47 is a power amplifier mounted on the multilayer substrate 42 and electrically connected to the first connection conductor 45. Transistor, 48 is a second connection conductor led from the second strip line 46 to the upper surface of the multilayer substrate 42, and 49 is a second connection conductor mounted on the multilayer substrate 42.
Chip parts such as chip resistors and chip capacitors electrically connected to the second connecting conductor 48 derived from the strip line 46 of the above, and 50 is a multilayer substrate from the second strip line 46.
A third connecting conductor 51 led out to the upper surface of 42 is formed on the multilayer substrate 42, is electrically connected to the third connecting conductor 50, and is opposed to the ground electrode layer 43 via the uppermost layer 42a of the insulating layer. Pad electrode. A capacitor is formed by the pad electrode 51 and the ground electrode layer 43 inside the multilayer substrate 42 facing the pad electrode 51 with the uppermost layer 42a of the insulating layer interposed therebetween. By changing the area of the pad electrode 51 on the upper surface of the multi-layer substrate 42 by using a laser, a lutor or the like, it is possible to change the capacitance value of the capacitor formed between the opposing ground electrode layer 43 and the second electrode. It is possible to adjust the output matching circuit or the input matching circuit configured by the strip line 46 and the chip component 49 of the above to the desired electrical characteristics,
As a result, it is possible to adjust the characteristic variation due to the variation in the manufacturing lot of the multilayer substrate 42 while reducing the number of manufacturing steps.

Further, 52 is a bonding wire, which connects each electrode (source / gate / drain) of the power amplification transistor 47 and the first strip line 44 as a drain bias line via the first connection conductor 45. (For example, first
Electrically connected to a conductor layer or the like electrically connected to the second strip line 46, which is connected to the connection conductor 45 of which at least a part thereof is exposed on the upper surface of the multilayer substrate 42). There is.

In this example, the power amplification transistor 47 is fixed to the mounting cavity 53 on the multilayer substrate 42 with a resin or solder-based connection paste 54, and is sealed with a sealing resin 55. The cavity 53 is formed in the same manner as the cavity 31 described above. Reference numeral 56 denotes a heat dissipation via conductor formed inside the multilayer substrate 42 below the power amplification transistor 47.

Further, in the high frequency power amplifier 41 of this example, the first strip line 44 as the drain bias line is formed below the ground electrode layer 43 and between the upper and lower ground electrode layers 57 and 58. ing. Similarly to the strip line 24 described above, the first strip line 44 may be internally layered with the ground electrode layer 43 as an upper ground electrode layer.

The second strip line 46 is also formed with the ground electrode layer 43 as the upper ground electrode layer in this example, but like the first strip line 44, other ground electrode layers 57 and the like are formed on the upper side. The first strip line 44 and the second strip line 46 may be formed in the same layer to form an inner layer.

Reference numeral 59 denotes a case. After mounting the power amplifying transistor 47 and the chip component 49 on the multilayer substrate 42, a sealing resin or the like (not shown) is provided to cover the upper surface of the multilayer substrate 42. The high frequency power amplifier 41 is completed by this, and electrically connected to the connection land of the external electric circuit via the terminal electrode 60 formed by utilizing the castellation on the upper surface periphery and the side surface of the multilayer substrate 42. Connected to.

If desired, a conductor layer, a ground electrode layer 58, etc. may be extended from the terminal electrode 60 to the lower surface or the upper surface of the multilayer substrate 42.

The multilayer substrate 42 is similar to the multilayer substrate 22 described above,
Further, the first strip line 44, the second strip line 46, the ground electrode layers 43, 57, 58, etc.
Similarly to the strip line 24, the micro strip line 26, and the ground electrode layers 23, 35, and 36, the first connecting conductor 45, the second connecting conductor 48, and the third connecting conductor 50 are the above-mentioned first connecting conductors. Similar to 45, the terminal electrode 60 may be formed similarly to the terminal electrode 38 described above, and the heat dissipation via conductor 56 may be formed similar to the heat dissipation via conductor 34 described above.

The power amplifying transistor 47 is mounted in the cavity 53, fixed by a connection paste 54 as a die attach material, and electrically connected, and is bonded to the multilayer substrate 42 by a bonding wire 52. It is electrically connected to the first strip line 44 and the second strip line 46 via the first connection conductor 45 led out to the upper surface or a conductor layer extended to the first connection conductor 45.

The characteristic adjusting pad electrode 51 thus formed can easily adjust the characteristic similarly to the pad electrode 29 described above, and the high frequency power amplifier can be obtained.
In 41, the equivalent circuit diagram showing the circuit configuration of the output matching circuit portion constituted by the second strip line 46, the chip component 49, the pad electrode 51, the ground electrode layer 43, etc. is similar to that of FIG. It is similar to that described above. In FIG. 3, reference numerals corresponding to the respective parts of the high frequency power amplifier 41 are also attached.

In this way, according to the high frequency power amplifiers 21 and 41 of the present invention, the high frequency power amplifiers 21 and 41 are formed on the multilayer substrates 22 and 42, and the uppermost layers 22a and 42a of the insulating layers of the multilayer substrates 22 and 42 are grounded. By combining the adjustment of the capacitance values of the pattern capacitors C _{1 to} C ₄ by the pad electrodes 29 and 51 facing the electrode layers 23 and 43 and the selection of connection of the pattern capacitors C _{1 to} C ₄ , the high frequency power amplifiers 21 and 41 are combined. Even after assembling, it is possible to easily absorb and adjust the characteristic variation between the manufacturing lots of the multilayer substrates 22 and 42.

[0053]

As described above, according to the high frequency power amplifier of the present invention, the drain bias line of the power amplifying transistor is formed into the strip line around the cavity inside the multilayer substrate and around the heat radiating via conductor. , The internal structure of the drain bias line, which used to occupy a large area on the upper surface of the substrate in the past, allows the heat generated from the power amplification transistor to be dissipated well while allowing the substrate to be significantly downsized. The power amplifier for high frequency can be significantly downsized, and since the drain bias line is striplined inside the multilayer substrate, it is less susceptible to electromagnetic noise, resulting in better isolation characteristics and less signal loss. The Q characteristic can be improved as compared with the case where the microstrip line is used.

According to the first high frequency power amplifier of the present invention, it is connected in parallel to the microstrip line of the output matching circuit or the input matching circuit constituted by the microstrip line and the chip component on the upper surface of the multilayer substrate. Since the pad electrode is added, the pad electrode forms a pattern capacitor between the pad electrode and the ground electrode layer inside the multilayer substrate facing the uppermost layer of the insulating layer,
By changing the area of this pad electrode by selectively shaving or cutting it by using a laser or a lute, it becomes possible to change the capacitance value of the pattern capacitor. The length of the microstrip line can be adjusted by adding multiple units and selectively cutting the connection between them and the microstrip line with a laser or a router.By combining these, an output matching circuit or an input matching circuit can be used. The electrical characteristics of the circuit can be easily adjusted to desired electrical characteristics even after the product is assembled.

According to the second high frequency power amplifier of the present invention, the output matching circuit and the input matching circuit are constituted by the strip line formed inside the multilayer substrate and the chip parts mounted on the upper surface of the substrate. It is possible to achieve further miniaturization compared to the case where it is configured with a strip line, and since a pad electrode connected in parallel to the strip line in a circuit is formed and added on the upper surface of the substrate, this pad electrode is used. A pattern capacitor is formed between this and the ground electrode layer inside the multi-layered substrate facing through the uppermost layer of the insulating layer, and like the first high-frequency power amplifier, the electrical characteristics of the output matching circuit and the input matching circuit are reduced. The characteristics can be easily adjusted to the desired electrical characteristics even after the product is assembled, and variations in manufacturing lots of multilayer boards can be avoided. The high-frequency power amplifier can be easily adjusted variation in electrical characteristics that after assembly of the product.

As described above, according to the present invention, it is possible to further reduce the size, and it is possible to easily adjust the electric characteristics with respect to the variation of the characteristics of the multilayer substrate for each manufacturing lot while reducing the number of manufacturing steps. It was possible to provide a high-frequency power amplifier suitable for mass production, which can improve the non-defective product rate.

[Brief description of drawings]

FIG. 1 is a sectional view showing an example of an embodiment of a first high frequency power amplifier of the present invention.

FIG. 2 is an external perspective view showing a state of the upper surface of the high frequency power amplifier of FIG. 1 with a case removed.

FIG. 3 is a cross-sectional view showing an example of an embodiment of a second high frequency power amplifier of the present invention.

4 is an external perspective view showing a state of the upper surface of the high frequency power amplifier of FIG. 3 with a case removed.

FIG. 5 is an equivalent circuit diagram showing a circuit configuration of an output matching circuit in an example of the embodiment of the high-frequency power amplifier of the present invention.

FIG. 6 is a plan view showing an example of a conventional high frequency power amplifier.

7 is a cross-sectional view taken along the line A-A ′ of FIG.

[Explanation of symbols]

21, 41 ・ ・ ・ ・ ・ High frequency power amplifier 22, 42 ... Multilayer substrate 22a, 42a ... the uppermost layer of the insulating layer 23, 43 ... Ground electrode layer 24 ・ ・ ・ ・ Strip line 44 ........ First strip line 46 ... Second strip line 25 ... Connection conductor 45 ........ First connection conductor 48 ... Second connecting conductor 50 --- The third connecting conductor 26 ... Microstrip line 27, 47 ・ ・ ・ ・ ・ Power amplification transistor 28,49 ・ ・ ・ ・ ・ Chip parts 29, 51 ・ ・ ・ ・ ・ Pad electrodes

Claims (2)

(57) [Claims] 1. A plurality of insulating layers containing glass as a main component , wherein a cavity is provided on an upper surface and the cavity is provided inside.
The heat radiation via conductors penetrating to the lower surface, the a multilayer substrate having an insulating layer lower surface of the top layer to the ground electrode layer of each of said cavities and bi for the heat radiation of the multilayer substrate
A strip line formed below the ground electrode layer a surrounding A conductor, said upper surface of said multilayer substrate key
A microstrip line formed around the cavity and electrically connected to a connection conductor extending from the strip line to the upper surface of the multilayer substrate ;
A chip component mounted on the upper surface of the mounted on the heat radiation via conductor said microstrip line electrically connected to the power amplifying transistor and the multilayer substrate, the periphery of the cavity of the upper surface of the multilayer substrate A high-frequency power amplifier, comprising: a pad electrode that is formed in addition to the microstrip line and faces the ground electrode layer with the uppermost layer of the insulating layer interposed therebetween. 2. A plurality of insulating layers containing glass as a main component , wherein a cavity is provided on the upper surface and the cavity is provided inside.
The heat radiation via conductors penetrating to the lower surface, the a multilayer substrate having an insulating layer lower surface of the top layer to the ground electrode layer of each of said cavities and bi for the heat radiation of the multilayer substrate
A first and second strip lines that are formed around the conductor and below the ground electrode layer and are electrically connected to each other; and the first and second strip lines that are mounted on the heat dissipation via conductor in the cavity . a power amplifying transistor which is electrically connected to the first connecting conductor deriving from the stripline toward the upper surface of the multilayer substrate, is mounted on the upper surface <br/> of the multilayer substrate from said second stripline a second connecting conductor electrically connected to the chip component to derive toward the upper surface of the multilayer substrate, the cavity of the upper surface of the multilayer substrate
Pad formed around the tee and electrically connected to a third connection conductor extending from the second strip line to the upper surface of the multilayer substrate and facing the ground electrode layer via the uppermost layer of the insulating layer. A high-frequency power amplifier comprising an electrode.