JP2007027600A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device, preventing a scribe line from having an abnormal appearance with respect to overetching for opening a pad, and to provide the semiconductor device. <P>SOLUTION: An SiO<SB>2</SB>film 105 is etched while controlling so that no etching time exceeding a thickness of an SiO<SB>2</SB>film 104 of Fig. (a) is provided. The SiO<SB>2</SB>film 105 is etched to be stopped at the arbitrary depth of the SiO<SB>2</SB>film 104 above a buffer film 103 with overetching time taken into consideration. A margin for overetching may be determined to be in a range of a thickness value smaller than that of the SiO<SB>2</SB>film 104. Thereafter, an SF<SB>6</SB>/He gas system is used to remove a TiN protective film 204 to expose a part of an Al wiring pad pattern 203. Thus, the pad 15 can be opened. In addition, the scribe line 16, that is etch-stopped at the arbitrary depth of the SiO<SB>2</SB>film 104, is formed simultaneously. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor wafer process. In particular, the present invention relates to a method for manufacturing a semiconductor device in which a wide region such as a scribe line is simultaneously etched in a pad etching process.

  The periphery of the pad in the semiconductor wafer is protected by a passivation film. The passivation film is coated on the entire surface of the wafer before the pad opening. The pad opening is achieved by selectively removing the passivation film by a dry etching process. The pad opening and the scribe line are formed simultaneously. That is, the boundary with the chip region is formed in a line by removing the insulating film having a predetermined depth.

While the scribe line is exposed to the formation process of the multilayer wiring of the semiconductor wafer, a wide region of the insulating film is formed. For this reason, in the scribe line, lamination and removal of metal and insulating film are repeated, and there is a concern about roughness and residue. For example, a technique for solving such a problem by adding an etching protective film is disclosed (for example, see Patent Document 1).
Japanese Patent Laid-Open No. 7-50278 (paragraph numbers [0015]-[0028], FIGS. 1-5)

  At the time of opening the pad, in order to make the outline clear, the over-etching is performed somewhat for the purpose of completely removing the insulating film (oxide film) on the pad surface. This is because even if excessive dry etching is performed, TiN or Al, which is the pad metal surface, serves as an etching stopper and does not hinder. However, at the stage of opening the pad, even if the configuration of [Patent Document 1] is applied, only the structure of the insulating film stack is removed on the scribe line.

  The insulating film stack of the scribe line has a main structure of a collection of interlayer insulating films stacked by a silane system or a TEOS (tetraethoxysilane) system and a nitride film used for the uppermost passivation film. In some cases, an SOG (spin on glass) film is mixed in such an insulating film. Since the SOG film is inserted for the purpose of flattening the stacking step, it hardly remains in a wide flat region such as a scribe line.

  However, in reality, in the SOG film, there are scattered several nm portions in the form of residue in the laminated insulating film of the scribe line. These are mainly minute residues such as C, H, Si, O, and F. The residue film of the slight and sparse SOG film is exposed to the etching atmosphere in the over-etching when the pad is opened. Then, the residue film of the SOG film remains as a fine residue state due to the difference in etching rate. As a result, the scribe line has a large number of foreign matter generation sites with the SOG film layer as a boundary, resulting in an appearance abnormality.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device in which a scribe line does not become abnormal in appearance with respect to overetching when a pad is opened. is there.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming a top passivation film on each chip region of a semiconductor wafer in which an integrated circuit is configured with multilayer wiring, and pads and scribe lines in each chip region. And a dry etching step of selectively removing the passivation film to form an over-etching, wherein the dry etching step is overetching to suppress an etching depth of an insulating film configured in the scribe line within a predetermined value. Be controlled.

  According to the method of manufacturing a semiconductor device according to the present invention, a control condition is set for over-etching when the pad is opened. Conventionally, since the etching depth of the scribe line is in an allowable range with respect to the overetching at the time of opening the pad, the degree of overetching has hardly been considered. For this reason, the number of occurrences of foreign matter increases from the SOG film forming portion, resulting in abnormal appearance. Therefore, over-etching is controlled so that the etching depth of the insulating film formed on the scribe line is kept within a predetermined value. That is, the SOG film forming portion that causes the generation of foreign matter is not exposed.

  In the semiconductor device manufacturing method according to the present invention, more specifically, the insulating film configured in the scribe line includes an SOG film or a buffer film including a residue film derived from the SOG film, In the dry etching process, the etching time is controlled so as to stop at the insulating film above the buffer film.

  In the semiconductor device manufacturing method according to the present invention, more specifically, the insulating film formed in the scribe line includes a non-doped oxide film including a SOG film or a residue film derived from the SOG film. A buffer film is present, and the etching time is controlled so that the dry etching process stops at the non-doped oxide film above the buffer film.

  A method of manufacturing a semiconductor device according to the present invention includes a buffer film having a second etching rate that is thinner than the insulating film so as to be sandwiched between insulating films having a first etching rate in a scribe region of a semiconductor integrated circuit wafer. A step of forming an insulating film stack including a passivation film as an uppermost layer, and a pad area in a chip region of the semiconductor integrated circuit wafer with selective removal of the passivation film, thereby controlling the etching time to control the etching time. The insulating film stacking in the scribe region includes a dry etching process for retaining the insulating film disposed on the buffer film at an arbitrary depth.

  According to the semiconductor device manufacturing method of the present invention, the etching time is controlled so that the insulating film stacked in the scribe region can be held at an arbitrary depth of the insulating film disposed on the buffer film when the pad is formed. Over-etching at the time of pad opening is limited with higher accuracy. As a result, the buffer film forming portion that causes the generation of foreign matter is not exposed.

  The method of manufacturing a semiconductor device according to the present invention includes: a step of forming an interlayer insulating film for the multilayer wiring in a scribe region of a semiconductor wafer in which an integrated circuit is configured with multilayer wiring; and the scribe region, A step of removing an SOG film or a residual film derived from the SOG film disposed in order to flatten a step related to the integrated circuit in an arbitrary layer of the interlayer insulating film; and a protection related to the integrated circuit on the interlayer insulating film The insulating film stack in the scribe region is selectively removed at a predetermined depth along with the step of forming a passivation film for the semiconductor wafer and the selective removal of the passivation film accompanying the pad opening in the chip region of the semiconductor wafer. And a dry etching process for achieving formation of a scribe line.

According to the semiconductor device manufacturing method of the present invention, at least the SOG film forming portion in the scribe region is removed. As a result, there is no SOG film forming part causing foreign matter. Therefore, there is no time limit with high accuracy for over-etching when the pad is opened.
Note that the step of removing the SOG film in the scribe region or the residual film derived from the SOG film is achieved through a physical etching process.
Further, the step of removing the SOG film in the scribe region or the residual film derived from the SOG film is achieved through a physical etching process, and the SOG film in a portion other than the scribe region is the physical layer. The surface modification is achieved through a simple etching process.

  A semiconductor device according to the present invention relates to a stack of interlayer insulating films provided in a scribe region of a semiconductor integrated circuit wafer, and the semiconductor integrated circuit wafer between arbitrary layers of the interlayer insulating film provided in the scribe region. A buffer film including an SOG film for leveling the step or a residue film derived from the SOG film, a passivation film for protecting the semiconductor integrated circuit wafer provided on the uppermost layer of the scribe region, and the scribe And a scribe line provided in a region and having an arbitrary etching depth to the interlayer insulating film above the buffer film.

  According to the semiconductor device of the present invention, the etching depth of the scribe line is limited to the SOG film or the interlayer insulating film above the buffer film including the residue film derived from the SOG film. By not exposing the formation part of the SOG film on the surface, the appearance abnormality of the scribe line is prevented.

BEST MODE FOR CARRYING OUT THE INVENTION

FIGS. 1A and 1B and FIGS. 2A and 2B are cross-sectional views showing the main part of the method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps. FIG. 3 is a plan view of the semiconductor wafer, showing the positional relationship of the parts shown in FIG. Each figure (a) is a scribe area S1,
Each figure (b) represents the pad region P1 (see FIG. 3).
As shown in FIGS. 1A, 1 </ b> B, and 3, the semiconductor wafer 11 includes an integrated circuit 13 with a multilayer wiring 12. In forming the integrated circuit 13, the scribe region S1 has a laminated structure of an interlayer insulating film to be described later. An uppermost passivation film 14 is formed for each chip region CHIP of the semiconductor wafer 11.

As shown in FIG. 1A, the inter-layer insulating film in the scribe region S1 is, for example, a BPSG (boro-phosphosilicate glass) film 101 of about 800 nm and a non-doped silicon oxide of about 700 nm laminated with a silane or TEOS system. A film (SiO ₂ film) 102, a buffer film 103 based on an SOG film scattered in several nm, and a non-doped silicon oxide film (SiO ₂ film) 104 of about 500 nm are stacked in this order. Further, a non-doped silicon oxide film (SiO ₂ film) 105 of about 300 nm and a silicon nitride film 106 of about 700 nm formed by a plasma method are stacked as the uppermost passivation film 14.

As shown in FIG. 1B, the interlayer insulating film in the pad region P1 omits the lower wiring layer, but the upper Al wiring pad pattern 203 connected to the integrated circuit, the upper TiN protective film 204, and the uppermost layer. As the passivation film 14, a non-doped silicon oxide film (SiO ₂ film) 105 of about 300 nm and a silicon nitride film 106 of about 700 nm formed by a plasma method are laminated as described above.

  Next, as shown in FIGS. A dry etching process for selectively removing the passivation film 14 having the above-described configuration is performed. In order to form the pad 15 and the scribe line 16 in each chip region CHIP, a dry etching process for selectively removing the passivation film 14 is performed. That is, the resist pattern 17 is a pattern for etching the shape of the scribe line 16 formed in the scribe region S1 and a pattern for etching the shape of the pad 15 formed in the pad region P1.

The silicon nitride film 106 is etched using a CF ₄ / O ₂ gas system. Subsequently, the SiO ₂ film 105 is etched using a CHF ₃ / CF ₄ / Ar gas system. At this time, it is important to avoid excessive overetching. In the pad region P1, since the TiN protective film 204 or the Al wiring pad pattern 203 functions as an etching stopper, overetching is not a problem. However, since all the scribe regions S1 are oxide films, the buffer film 103 and further the SiO ₂ film 102 are etched depending on the overetching time. The buffer film 103 includes an SOG film or a residue film derived from the SOG film. If the buffer film 103 is exposed, the buffer film 103 cannot be removed and causes an appearance abnormality (dashed residue 303).

Therefore, the etching of the SiO ₂ film 105 is controlled so as not to provide an etching time exceeding the thickness of the SiO ₂ film 104 in FIG. In the etching of the SiO ₂ film 105, the etching is stopped at an arbitrary depth of the SiO ₂ film 104 on the buffer film 103 in consideration of the over-etching time. The SiO ₂ film 104 is about 500 nm, and the over-etching margin may be determined within a range of values smaller than 500 nm. Thereafter, using a gas system of SF ₆ / He, the TiN protective film 204 is removed, and a portion of the Al wiring pad pattern 203 is exposed. Thereby, the opening of the pad 15 is achieved. At the same time, a scribe line 16 in which etching is stopped at an arbitrary depth of the SiO ₂ film 104 is formed.

According to the method of the above embodiment and the configuration obtained by this, control conditions are attached to the over-etching when the pad 15 is opened. Conventionally, since the etching depth of the scribe line 16 is in an allowable range with respect to the over-etching when the pad 15 is opened, the degree of over-etching has hardly been considered. For this reason, the number of occurrences of foreign matters increases at the boundary of the SOG film (buffer film 103) forming portion, resulting in an appearance abnormality. Therefore, over-etching is time-controlled so that the etching depth of the insulating film formed on the scribe line 16 is kept within a predetermined value. That is, the etching is stopped at an arbitrary depth of the SiO ₂ film 104 so as not to expose the formation part of the SOG film (buffer film 103) that causes the generation of foreign matter. Thereby, the appearance abnormality of the scribe line 16 can be reliably reduced.

  FIG. 4 is a cross-sectional view showing the main part of the method for manufacturing a semiconductor device according to the second embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals. The SOG film in the scribe region S1, that is, the buffer film 103, is several nm and has a small remaining amount compared to other regions having a step such as an integrated circuit region. The scribe region S1 is a wide flat region, and hardly remains in the etch back after the SOG film is formed. Therefore, after the SOG film is formed and etched back, the SOG film (buffer film 103) in the scribe region S1 is removed by physical etching. The physical etching is, for example, Ar sputtering.

  According to the method for manufacturing a semiconductor device of the present invention, at least the formation part of the SOG film (buffer film 103) in the scribe region S1 is removed. This eliminates the formation of the SOG film (buffer film 103) that causes the generation of foreign matter. Therefore, there is no time limit for accuracy required for over-etching when the pad is opened as in the first embodiment.

  Further, in the physical etching process for the SOG film (buffer film 103) in the scribe region S1, surface modification is achieved for the SOG film in a portion other than the scribe region S1. The SOG film in a portion other than the scribe region S1 is not removed even after the physical etching process. Sputtering of the SOG surface contributes to improving the adhesion with the upper layer.

  As described above, according to the present invention, first, a control condition is set for over-etching when the pad is opened. Conventionally, since the etching depth of the scribe line is in an allowable range with respect to the overetching at the time of opening the pad, the degree of overetching has hardly been considered. For this reason, the number of occurrences of foreign matter increases from the SOG film forming portion, resulting in abnormal appearance. Therefore, over-etching is controlled so that the etching depth of the insulating film formed on the scribe line is kept within a predetermined value. That is, the SOG film forming portion that causes the generation of foreign matter is not exposed.

  Second, paying attention to the small amount of the SOG film in the scribe line, the SOG film forming part is removed by physical etching. This eliminates the relationship between over-etching at the time of pad opening and appearance abnormality in the scribe line. In addition, the other region where the SOG film exists is physically sputtered and the surface is modified. This contributes to improved adhesion with the upper layer. As a result, it is possible to provide a semiconductor device manufacturing method and a semiconductor device in which the scribe line does not become abnormal in appearance with respect to over-etching when the pad is opened.

  The present invention is not limited to the above-described embodiments and methods, and various modifications and applications can be implemented without departing from the spirit of the present invention.

FIG. 6 is a first cross-sectional view showing the main part of the method for manufacturing the semiconductor device according to the first embodiment. Each 2nd sectional view following FIG. The top view of a semiconductor wafer. Sectional drawing which shows the principal part of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Semiconductor wafer, 12 ... Multilayer wiring, 13 ... Integrated circuit, 14 ... Passivation film, 15 ... Pad, 16 ... Scribe line, 17 ... Resist pattern, 101 ... BPSG film, 102, 104, 105, 106 ... Silicon oxide film , 103 ... buffer film, 203 ... Al wiring pad pattern, 204 ... TiN protective film, S1 ... scribe area, P1 ... pad area.

Claims (8)

Forming an uppermost passivation film for each chip region of a semiconductor wafer in which an integrated circuit is configured with multilayer wiring; and
A dry etching step of selectively removing the passivation film to form pads and scribe lines in each chip region,
The method for manufacturing a semiconductor device, wherein the dry etching step is such that over-etching is controlled so as to suppress an etching depth of an insulating film formed in the scribe line within a predetermined value. The insulating film configured in the scribe line includes an SOG film or a buffer film including a residue film derived from the SOG film, and the dry etching process is performed with an etching time to stop at the insulating film above the buffer film. The method of manufacturing a semiconductor device according to claim 1, wherein the method is controlled. The insulating film configured in the scribe line includes a buffer film including a SOG film or a residue film derived from the SOG film in a non-doped oxide film, and the dry etching step includes the non-doped film above the buffer film. The method of manufacturing a semiconductor device according to claim 1, wherein the etching time is controlled so as to stop at the oxide film. An insulating film including a buffer film having a second etching rate thinner than the insulating film and having a passivation film as the uppermost layer so as to be sandwiched between the insulating films having the first etching rate in the scribe region of the semiconductor integrated circuit wafer Forming a laminate;
The insulating layer disposed on the buffer film in the insulating film stack in the scribe region by controlling an etching time during pad formation of the chip region in the semiconductor integrated circuit wafer with selective removal of the passivation film. A dry etching process that stops at an arbitrary depth of the film;
A method of manufacturing a semiconductor device including: Forming an interlayer insulating film for the multilayer wiring in a scribe region of a semiconductor wafer comprising an integrated circuit with the multilayer wiring;
Removing an SOG film disposed in an arbitrary layer of the interlayer insulating film in the scribe region to flatten a step related to the integrated circuit or a residual film derived from the SOG film;
Forming a protective passivation film related to the integrated circuit on the interlayer insulating film;
A dry etching step of selectively forming the passivation film along with the pad opening in the chip area of the semiconductor wafer and simultaneously forming the scribe line by selectively removing the insulating film stack in the scribe area at a predetermined depth. When,
A method of manufacturing a semiconductor device including: 6. The method of manufacturing a semiconductor device according to claim 5, wherein the step of removing the SOG film in the scribe region or the residual film derived from the SOG film is achieved through a physical etching process. The step of removing the SOG film in the scribe region or the residual film derived from the SOG film is achieved through a physical etching process, and the SOG film in a portion other than the scribe region is subjected to the physical etching. The method for manufacturing a semiconductor device according to claim 5, wherein the surface modification is achieved through the steps. A stack of interlayer insulating films provided in a scribe region of a semiconductor integrated circuit wafer;
A buffer film provided in the scribe region, including an SOG film for planarizing a step related to the semiconductor integrated circuit wafer between arbitrary layers of the interlayer insulating film, or a residue film derived from the SOG film;
A passivation film for protection related to the semiconductor integrated circuit wafer provided in the uppermost layer of the scribe region;
A scribe line provided in the scribe region and having an arbitrary etching depth to the interlayer insulating film above the buffer film;
A semiconductor device comprising:

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