JP2007003909A - Display device, array substrate, and driving method of display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress a display device, which controls a gray scale that each pixel displays with the level of a video signal, from becoming insufficient in gray scale reproducibility. <P>SOLUTION: The display device according to the present invention includes a plurality of pixels PX each having a driving transistor DR whose source is connected to a power supply terminal ND1, a display element OLED including a pixel electrode, a counter electrode connected to the power supply terminal ND2, and an active layer interposed between them, a switch SWa connected between the drain of the driving transistor and the pixel electrode, a switching transistor SWc connected between the drain and gate of the driving transistor, a switch SWe connected between the drain of the driving transistor DR and the gate of the switching transistor SWc, and a switch SWd connected between the gate of the switching transistor SWc and a switching signal output terminal ND3. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a display device, an array substrate, and a method for driving the display device.

  When displaying an image on an active matrix organic electroluminescence (EL) display device, for example, pixels are selected for each row. In the selection period in which a pixel is selected, a video signal is written to that pixel. In each non-selection period, each pixel passes a driving current having a magnitude corresponding to the video signal to the organic EL element. The organic EL element emits light with a luminance corresponding to the magnitude of the drive current. As described above, in the active matrix organic EL display device, the gradation displayed in each pixel is controlled by the magnitude of the video signal.

  By the way, in an active matrix organic EL display device, a current signal and a voltage signal can be used as a video signal.

  Patent Document 1 describes an active matrix organic EL display device that uses a current signal as a video signal. The pixel of this display device includes a drive transistor that is an n-channel field effect transistor, an organic EL element, a capacitor, and first to third switching transistors. The drive transistor, the first switching transistor, and the organic EL element are connected in series in this order between the low-potential power line and the high-potential power line. The capacitor is connected between the low potential power line and the gate of the driving transistor. The second switching transistor is connected between the drain and gate of the driving transistor. The third switching transistor is connected between the drain of the driving transistor and the video signal line.

  Patent Document 2 describes an active matrix organic EL display device that uses a voltage signal as a video signal. The pixel of the display device includes a drive transistor that is a p-channel field effect transistor, an organic EL element, first and second capacitors, and first to third switching transistors. . The drive transistor, the first switching transistor, and the organic EL element are connected in series in this order between the high-potential power line and the low-potential power line. The first capacitor is connected between the high potential power supply line and the gate of the driving transistor. The second switching transistor is connected between the drain and gate of the driving transistor. One electrode of the second capacitor is connected to the gate of the driving transistor. The third switching transistor is connected between the video signal line and one electrode of the second capacitor.

  In the organic EL display device described in Patent Document 1, even if the threshold voltage and mobility of the drive transistor vary between pixels, the magnitude of the drive current passed through the organic EL element is caused by the variation. There is no variation. Further, in the organic EL display device described in Patent Document 2, even if the threshold voltage of the drive transistor varies between pixels, the magnitude of the drive current flowing through the organic EL element varies due to the variation. There is no. Therefore, according to these organic EL display devices, high gradation reproducibility should be realized.

However, the present inventors have found that even these organic EL display devices may not be able to realize sufficiently high gradation reproducibility.
US Pat. No. 6,373,454 US Pat. No. 6,229,506

  An object of the present invention is to suppress insufficient gradation reproducibility in a display device that controls the gradation displayed by each pixel by the magnitude of a video signal.

  According to the first aspect of the present invention, the display includes a driving transistor whose source is connected to the first power supply terminal, a counter electrode connected to the pixel electrode and the second power supply terminal, and an active layer interposed therebetween. An element; a first switch connected between the drain of the driving transistor and the pixel electrode; a switching transistor connected between the drain and gate of the driving transistor; and the drain and switching of the driving transistor. A plurality of pixels each including a second switch connected between a gate of the transistor and a third switch connected between a gate of the switching transistor and a switching signal output terminal. A display device is provided.

  According to a second aspect of the present invention, a driving transistor having a source connected to a first power supply terminal, a pixel electrode, a first switch connected between a drain of the driving transistor and the pixel electrode, and the driving A switching transistor connected between the drain and gate of the transistor, a second switch connected between the drain of the driving transistor and the gate of the switching transistor, a gate of the switching transistor and a switching signal output terminal There is provided an array substrate comprising a plurality of pixel circuits each including a third switch connected therebetween.

  According to the third aspect of the present invention, the display includes a driving transistor whose source is connected to the first power supply terminal, a pixel electrode, a counter electrode connected to the second power supply terminal, and an active layer interposed therebetween. A driving method of a display device including a plurality of pixels each including an element and a switching transistor connected between a drain and a gate of the driving transistor, the pixel electrode, a drain of the driving transistor, A first operation of connecting the gate of the switching transistor to a switching signal output terminal and setting the potential of the switching signal output terminal to an on-potential that closes the switching transistor in a selection period in which the switching transistor is disconnected; A second operation for disconnecting the switching signal output terminal from the gate of A third operation of temporarily connecting the drain of the precursor driving transistor and the gate of the switching transistor and setting the potential of the switching signal output terminal to an off-potential that opens the switching transistor; and switching the gate of the switching transistor There is provided a driving method characterized in that the fourth operation connected to the signal output terminal is performed in this order.

  According to the present invention, it is possible to prevent the gradation reproducibility from becoming insufficient in a display device that controls the gradation displayed in each pixel by the magnitude of the video signal.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in each figure, the same referential mark is attached | subjected to the component which exhibits the same or similar function, and the overlapping description is abbreviate | omitted.

  FIG. 1 is a plan view schematically showing a display device according to a first aspect of the present invention. FIG. 2 is a cross-sectional view schematically showing an example of a structure that can be employed in the display device of FIG. FIG. 3 is an equivalent circuit diagram of a pixel included in the display device of FIG. In FIG. 2, the display device is drawn such that its display surface, that is, the front surface or the light emitting surface faces downward, and the back surface faces upward.

  This display device is a bottom emission type organic EL display device adopting an active matrix driving method. As shown in FIG. 1, the organic EL display device includes a display panel DP, a video signal line driver XDR, and a scanning signal line driver YDR.

  As illustrated in FIGS. 1 and 2, the display panel DP includes an insulating substrate SUB such as a glass substrate, for example.

On the substrate SUB, as shown in FIG. 2, an undercoat layer UC is formed. For example, the undercoat layer UC is formed by laminating a SiN _x layer and a SiO _x layer in this order on the substrate SUB.

On the undercoat layer UC, the semiconductor layers SC shown in FIG. 2 are arranged corresponding to the pixels PX described later. Each semiconductor layer SC is, for example, a polysilicon layer including a p-type region and an n-type region. In this example, in the semiconductor layer SC, the region facing the member indicated by the reference symbol G is an intrinsic type region, and the other region is a p ⁺ type region.

On the undercoat layer UC, lower electrodes (not shown) are further arranged corresponding to the pixels PX. The lower electrode is, for example, an n ⁺ type polysilicon layer.

  The semiconductor layer SC and the lower electrode are covered with the gate insulating film GI shown in FIG. The gate insulating film GI can be formed using, for example, TEOS (TetraEthyl OrthoSilicate).

  Scan signal lines SL1 to SL5 shown in FIGS. 1 and 3 are formed on the gate insulating film GI. As shown in FIG. 1, each of the scanning signal lines SL1 to SL5 extends in the row direction (X direction) of the pixels PX, and is arranged in the column direction (Y direction) of the pixels PX. The scanning signal lines SL1 to SL5 are made of, for example, MoW.

  An upper electrode (not shown) is further arranged on the gate insulating film GI. The upper electrodes are arranged corresponding to the pixels PX. The upper electrode is made of, for example, MoW. The upper electrode can be formed in the same process as the scanning signal lines SL1 to SL5.

  In each pixel PX, the conductor pattern including the scanning signal lines SL1 to SL5 and the upper electrode intersects the semiconductor layer at six locations. These intersections constitute the drive transistor DR and the switches SWa to SWe shown in FIGS.

  In each pixel PX, the upper electrode faces the lower electrode. The upper electrode and the lower electrode and the insulating film GI interposed therebetween constitute the capacitor C shown in FIGS.

  In this example, the drive transistor DR and the switches SWa to SWe are top-gate p-channel thin film transistors. Further, a portion indicated by reference numeral G in FIG. 2 is a gate of the thin film transistor.

The gate insulating film GI, the scanning signal lines SL1 to SL5, and the upper electrode are covered with an interlayer insulating film II shown in FIG. The interlayer insulating film II is made of, for example, SiO _x formed by a plasma CVD method or the like.

  On the interlayer insulating film II, the video signal line DL and the power supply line PSL shown in FIGS. 1 and 3 are formed. As shown in FIG. 1, each video signal line DL extends in the Y direction and is arranged in the X direction. In this example, the power supply lines PSL extend in the Y direction and are arranged in the X direction.

  On the interlayer insulating film II, a source electrode SE and a drain electrode DE shown in FIG. 2 are further formed. The source electrode SE and the drain electrode DE are connected to the source and drain of the thin film transistor through contact holes provided in the interlayer insulating film II and the gate insulating film GI, respectively.

  The video signal line DL, the power supply line PSL, the source electrode SE, and the drain electrode DE have, for example, a three-layer structure of Mo / Al / Mo. These can be formed in the same process.

The video signal line DL, the power supply line PSL, the source electrode SE, and the drain electrode DE are covered with a passivation film PS shown in FIG. The passivation film PS is made of, for example, SiN _x .

  On the passivation film PS, the pixel electrodes PE shown in FIG. 2 are arranged corresponding to the pixels PX. Each pixel electrode PE is connected to the drain electrode DE through a contact hole provided in the passivation film PS.

  In this example, the pixel electrode PE is a light-transmitting front electrode. Further, the pixel electrode PE is an anode in this example. As a material of the pixel electrode PE, for example, a transparent conductive oxide such as ITO (Indium Tin Oxide) can be used.

  A partition insulating layer PI shown in FIG. 2 is further formed on the passivation film PS. In the partition insulating layer PI, a through hole is provided at a position corresponding to the pixel electrode PE, or a slit is provided at a position corresponding to a column or row formed by the pixel electrode PE. Here, as an example, the partition insulating layer PI is provided with a through hole at a position corresponding to the pixel electrode PE.

  The partition insulating layer PI is, for example, an organic insulating layer. The partition insulating layer PI can be formed using, for example, a photolithography technique.

  On the pixel electrode PE, an organic layer ORG including a light emitting layer is formed as an active layer. The light emitting layer is, for example, a thin film containing a luminescent organic compound whose emission color is red, green, or blue. The organic layer ORG can further include a hole injection layer, a hole transport layer, a hole blocking layer, an electron transport layer, an electron injection layer, and the like in addition to the light emitting layer.

  The partition insulating layer PI and the organic layer ORG are covered with the counter electrode CE. In this example, the counter electrode CE is an electrode connected to each other between the pixels PX, that is, a common electrode. In this example, the counter electrode CE is a cathode and a light-reflecting back electrode. The counter electrode CE is electrically connected to an electrode wiring (not shown) formed on the same layer as the video signal line DL through, for example, a contact hole provided in the passivation film PS and the partition insulating layer PI. It is connected. Each organic EL element OLED includes a pixel electrode PE, an organic layer ORG, and a counter electrode CE.

  Each pixel PX includes a driving transistor DR, switches SWa to SWe, an organic EL element OLED, and a capacitor C as shown in FIGS. As described above, in this example, the drive transistor DR and the switches SWa to SWe are p-channel thin film transistors.

  The drive transistor DR, the switch SWa, and the organic EL element OLED are connected in series between the first power supply terminal ND1 and the second power supply terminal ND2. In this example, the power supply terminal ND1 is a high potential power supply terminal, and the power supply terminal ND2 is a low potential power supply terminal.

  The gate of the switch SWa is connected to the scanning signal line SL1. The switch SWb is connected between the drain of the driving transistor DR and the video signal line DL, and its gate is connected to the scanning signal line SL2. The switch SWc is connected between the drain and gate of the drive transistor DR. The switch SWd is connected between the scanning signal line SL3 and the gate of the switch SWc, and the gate is connected to the scanning signal line SL4. The switch SWe is connected between the drain and gate of the switch SWc, and its gate is connected to the scanning signal line SL5. In FIGS. 1 and 3, reference numeral ND3 indicates a switching signal output terminal.

  The capacitor C is connected between the gate of the driving transistor DR and the constant potential terminal ND1 '. In this example, the constant potential terminal ND1 'is connected to the power supply terminal ND1.

  A structure obtained by removing the counter electrode CE and the organic layer ORG from the display panel DP corresponds to the array substrate. Further, the pixel circuit obtained by removing the counter electrode CE and the organic layer ORG from the pixel PX corresponds to a pixel circuit.

  In this example, the video signal line driver XDR and the scanning signal line driver YDR are mounted on the display panel DP by COG (chip on glass). The video signal line driver XDR and the scanning signal line driver YDR may be mounted by TCP (tape carrier package) instead of COG mounting.

  A video signal line DL is connected to the video signal line driver XDR. In this example, a power supply line PSL is further connected to the video signal line driver XDR. The video signal line driver XDR outputs a current signal as a video signal to the video signal line DL and supplies a power supply voltage to the power supply line PSL.

  The scanning signal lines SL1 to SL5 are connected to the scanning signal line driver YDR. The scanning signal line driver YDR outputs voltage signals as first to fifth scanning signals to the scanning signal lines SL1 to SL5, respectively.

  FIG. 4 is a timing chart showing an example of a method for driving the display device shown in FIG. In the figure, the horizontal axis indicates time and the vertical axis indicates potential.

In FIG. 4, among the “XDR output”, a period denoted as “I _sig (M)” indicates a period during which the video signal line driver XDR outputs the video signal I _sig (M) to the video signal line DL. In FIG. 4, waveforms indicated by “SL1 potential” to “SL5 potential” indicate the potentials of the scanning signal lines SL1 to SL5, respectively.

In the method of FIG. 4, the pixels PX included in the display device of FIG. 1 are line-sequentially driven.
For example, when displaying a certain gradation with the m-th pixel PX, in the m-th pixel selection period, that is, the m-th selection period, the m-th pixel PX is first connected. The scanning signal line SL1 is set to an off potential. Thereby, the switch SWa is opened (non-conducting state). The following writing operation is performed during the period when the switch SWa is open.

  First, the scanning signal line SL2 to which the pixel PX in the m-th row is connected is set to an on potential. Further, the scanning signal line SL3 connected to the m-th row pixel PX is set to an on potential. At this time, the potential of the scanning signal line SL4 to which the m-th row pixel PX is connected is kept on, and the potential of the scanning signal line SL5 to which the m-th row pixel PX is connected is kept off. . That is, the switch SWd remains closed (conducting state), and the switch SWe remains open. Thereby, the switches SWb and SWc are closed.

In this state, the video signal is output as a current signal from the video signal line driver XDR to the scanning signal line DL. That is, the current I _sig (m) flows from the first power supply terminal ND1 to the video signal line DL. As a result, the gate-source voltage V _gs of the driving transistor DR is set to a value when the driving transistor DR passes the current I _sig (m).

  Next, the scanning signal line SL4 connected to the pixel PX in the m-th row is set to an off potential, and the switch SWd is opened. Within the period when the switch SWd is open, the potential of the scanning signal line SL3 to which the pixel PX in the m-th row is connected is changed from the on potential to the off potential. Further, the potential of the scanning signal line SL5 connected to the pixel PX in the m-th row is changed from the off potential to the on potential within the period in which the switch SWd is opened, and is further returned to the off potential. That is, the switch SWe is temporarily closed. As a result, the gate potential of the switch SWc is made equal to the drain potential of the drive transistor DR, and the switch SWc is opened.

  Next, the scanning signal line SL4 connected to the pixel PX in the m-th row is set to an on potential, and the switch SWd is closed. Since the scanning signal line SL3 to which the pixel PX in the m-th row is connected is set to an off potential, the switch SWc is kept open.

  Further, the scanning signal line SL2 connected to the pixel PX in the m-th row is set to an off potential, and the switch SWb is opened. Thereafter, the scanning signal line SL1 connected to the pixel PX in the m-th row is set to the on potential, and the switch SWa is closed. The m-th row selection period ends when the switch SWa is closed.

In the non-selection period following this selection period, the pixel PX in the m-th row holds the gate-source voltage V _gs of the drive transistor DR set in the m-th row selection period. Note that, in the non-selection period of the pixel PX in the m-th row, the potentials of the scanning signal lines SL1 and SL4 to which the pixel PX is connected are kept on and the potentials of the scanning signal lines SL2, SL3, and SL5 are off potentials. Leave as it is. A drive current I _drv (m) having a magnitude corresponding to the video signal I _sig (m) flows through the organic EL element OLED. The organic EL element OLED emits light with a luminance corresponding to the magnitude of the drive current I _drv (m).

  Now, according to this driving method, excellent gradation reproducibility can be realized. This will be described below.

  For example, when the switches SWd and SWe and the scanning signal lines SL4 and SL5 are omitted from the display device of FIG. 1, and the display device in which the gate of the switch SWc is connected to the scanning signal line SL3 is driven by the method of FIG. think of. In this case, the gate-source voltage of the drive transistor DR changes as the potential of the scanning signal line SL3 is changed from the on potential to the off potential in the m-th row selection period. More specifically, the gate potential of the drive transistor DR changes with the potential change of the scanning signal line SL3 due to the influence of the parasitic capacitance formed between the gate and the channel of the switch SWc.

  When the switching operation of the switch SWc is fast, the charge hardly moves between the source and drain of the switch SWc in the process of closing the switch SWc. Therefore, when the switching operation is controlled by supplying a scanning signal to the gate of the switch SWc, the potential change of the driving transistor DR accompanying the potential change of the scanning signal line SL3 is large. The magnitude of this potential change depends on the threshold voltage of the switch SWc.

  Therefore, when the threshold voltage of the switch SWc varies between the pixels PX, the magnitude of the gate potential change of the drive transistor DR accompanying the potential change of the scanning signal line SL3 varies between the pixels PX, and as a result, the luminance Unevenness may occur. That is, in this case, it is impossible to realize excellent gradation reproducibility.

  As described above, in the display device of FIG. 1, the gate of the switch SWc and the scanning signal line SL3 are connected via the switch SWd, and the switch SWe is connected between the drain and gate of the switch SWc. In the driving method of FIG. 4, the potential of the scanning signal line SL3 is changed from the on potential to the off potential within the period in which the switch SWd is open. Further, in the driving method of FIG. 4, the switch SWc is opened by closing the switch SWe and connecting the drain of the driving transistor DR and the gate of the switch SWc within the period in which the switch SWd is open.

  When opening the switch SWc by closing the switch SWe, the channel resistance of the switch SWe serves to slow down the switching operation of the switch SWc. Therefore, in the period from when the switch SWe is closed until the gate-source voltage of the switch SWc reaches its threshold voltage, the charge can sufficiently move between the source and drain of the switch SWc. The source of SWc is maintained at the same potential as the drain of drive transistor DR. Further, when the gate-source voltage of the switch SWc reaches the threshold voltage, the parasitic capacitance disappears, so that the gate potential change of the driving transistor DR accompanying the gate potential change of the switch SWc does not occur.

  Therefore, according to the method of FIG. 4, even if the threshold voltage of the switch SWc varies between the pixels PX, luminance unevenness caused by this does not occur. That is, excellent gradation reproducibility can be realized.

  Next, the second aspect of the present invention will be described.

FIG. 5 is a plan view schematically showing a display device according to the second aspect of the present invention. FIG. 6 is an equivalent circuit diagram of a pixel included in the display device of FIG.

  This display device is a bottom emission type organic EL display device adopting an active matrix driving method. This display device uses a video signal line driver XDR that outputs a voltage signal as a video signal, and is substantially the same as the display device according to the first aspect, except that the following structure is adopted for the display panel DP. It has a structure.

  In this display panel DP, instead of arranging one capacitor C for each pixel PX, two capacitors C1 and C2 are arranged for each pixel PX. Each pixel PX includes a drive transistor DR, switches SWa to SWe, an organic EL element OLED, and capacitors C1 and C2.

  The drive transistor DR, the switch SWa, and the organic EL element OLED are connected in series between the first power supply terminal ND1 and the second power supply terminal ND2. The gate of the switch SWa is connected to the scanning signal line SL1. The capacitor C1 is connected between the gate of the driving transistor DR and the constant potential terminal ND1 '. In this example, the constant potential terminal ND1 'is connected to the power supply terminal ND1. The switch SWb and the capacitor C2 are connected in series in this order between the video signal line DL and the drain of the drive transistor DR. The gate of the switch SWb is connected to the scanning signal line SL2. The switch SWc is connected between the drain and gate of the drive transistor DR. The switch SWd is connected between the scanning signal line SL3 and the gate of the switch SWc, and the gate is connected to the scanning signal line SL4. The switch SWe is connected between the drain of the driving transistor DR and the gate of the switch SWc, and the gate thereof is connected to the scanning signal line SL5.

  The structure excluding the counter electrode CE and the organic layer ORG described with reference to FIG. 2 from the display panel DP corresponds to the array substrate. Further, the pixel circuit obtained by removing the counter electrode CE and the organic layer ORG from the pixel PX corresponds to a pixel circuit.

  FIG. 7 is a timing chart showing an example of a method for driving the display device shown in FIG. In the figure, the horizontal axis indicates time and the vertical axis indicates potential.

In FIG. 7, among the “XDR output”, a period denoted as “V _sig (M)” indicates a period during which the video signal line driver XDR outputs the video signal V _sig (M) to the video signal line DL. _The period labeled “ _rst ” indicates a period during which the video signal line driver XDR outputs the reset signal V _rst to the video signal line DL. In FIG. 7, waveforms indicated by “SL1 potential” to “SL5 potential” indicate the potentials of the scanning signal lines SL1 to SL5, respectively.

In the method of FIG. 7, the pixels PX included in the display device of FIG. 5 are line-sequentially driven.
For example, when displaying a certain gradation with the m-th pixel PX, in the m-th pixel selection period, that is, the m-th selection period, the m-th pixel PX is first connected. The scanning signal line SL1 is set to an off potential. Thereby, the switch SWa is opened (non-conducting state). The following reset operation and write operation are sequentially performed within a period during which the switch SWa is opened.

First, the scanning signal line SL2 to which the pixel PX in the m-th row is connected is set to an on potential. Further, the scanning signal line SL3 connected to the m-th row pixel PX is set to an on potential. At this time, the potential of the scanning signal line SL4 to which the m-th row pixel PX is connected is kept on, and the potential of the scanning signal line SL5 to which the m-th row pixel PX is connected is kept off. . That is, the switch SWd remains closed (conducting state), and the switch SWe remains open. Thereby, the switches SWb and SWc are closed. At this time, a reset signal is output as a voltage signal from the video signal line driver XDR to the scanning signal line DL. That is, the potential of the video signal line DL is set to the reset potential _Vrst . Thus, the gate-source voltage V _gs of the drive transistor DR is set to the threshold voltage V _th .

Next, the scanning signal line SL4 connected to the pixel PX in the m-th row is set to an off potential, and the switch SWd is opened. Within the period when the switch SWd is open, the potential of the scanning signal line SL3 to which the pixel PX in the m-th row is connected is changed from the on potential to the off potential. Further, the potential of the scanning signal line SL5 to which the pixel PX in the m-th row is connected is changed from the off potential to the on potential within the period in which the switch SWd is opened, and then returned to the off potential. That is, the switch SWe is temporarily closed. As a result, the gate potential of the switch SWc is made equal to the drain potential of the drive transistor DR, and the switch SWc is opened. During this period, the potential of the video signal line DL is set to the reset potential _Vrst .

  Next, the scanning signal line SL4 connected to the pixel PX in the m-th row is set to an on potential, and the switch SWd is closed. Since the scanning signal line SL3 to which the pixel PX in the m-th row is connected is set to an off potential, the switch SWc is kept open.

Subsequently, the video signal V _sig (m) is output as a voltage signal from the video signal line driver XDR to the scanning signal line DL. For example, if the capacitances of the capacitor C1 and the capacitor C2 are equal, the gate-source voltage V _gs of the driving transistor DR is thereby set to the voltage V _th + 1/2 × [V _sig (m) −V _rst ]. The

  Further, the scanning signal line SL2 connected to the pixel PX in the m-th row is set to an off potential, and the switch SWb is opened. Thereafter, the scanning signal line SL1 connected to the pixel PX in the m-th row is set to the on potential, and the switch SWa is closed. The m-th row selection period ends when the switch SWa is closed.

In the non-selection period following this selection period, the pixel PX in the m-th row holds the gate-source voltage V _gs of the drive transistor DR set in the m-th row selection period. Note that, in the non-selection period of the pixel PX in the m-th row, the potentials of the scanning signal lines SL1 and SL4 to which the pixel PX is connected are kept on and the potentials of the scanning signal lines SL2, SL3, and SL5 are off potentials. Leave as it is. A drive current I _drv (m) having a magnitude corresponding to the voltage V _th + 1/2 × [V _sig (m) −V _rst ] flows through the organic EL element OLED. The organic EL element OLED emits light with a luminance corresponding to the magnitude of the drive current I _drv (m).

  In this driving method, the same method as described in the first aspect is adopted for the switching operation of the switch SWc. Therefore, in this aspect, the same effect as described in the first aspect can be obtained.

1 is a plan view schematically showing a display device according to a first aspect of the present invention. FIG. 2 is a cross-sectional view schematically illustrating an example of a structure that can be employed in the display device of FIG. 1. FIG. 2 is an equivalent circuit diagram of a pixel included in the display device of FIG. 1. 3 is a timing chart illustrating an example of a method for driving the display device illustrated in FIG. 1. The top view which shows roughly the display apparatus which concerns on the 2nd aspect of this invention. FIG. 6 is an equivalent circuit diagram of a pixel included in the display device of FIG. 5. 6 is a timing chart illustrating an example of a method for driving the display device illustrated in FIG. 5.

Explanation of symbols

  C ... Capacitor, C1 ... Capacitor, C2 ... Capacitor, CE ... Counter electrode, DE ... Drain electrode, DL ... Video signal line, DP ... Display panel, DR ... Drive transistor, G ... Gate, GI ... Gate insulating film, II ... Interlayer insulating film, ND1 ... power supply terminal, ND1 '... constant potential terminal, ND2 ... power supply terminal, ND3 ... switching signal output terminal, OLED ... organic EL element, ORG ... organic substance layer, PE ... pixel electrode, PI ... partition insulating layer, PS ... passivation film, PSL ... power supply line, PX ... pixel, SC ... semiconductor layer, SE ... source electrode, SL1 ... scanning signal line, SL2 ... scanning signal line, SL3 ... scanning signal line, SL4 ... scanning signal line, SL5 ... Scan signal line, SUB ... insulating substrate, SWa ... switch, SWb ... switch, SWc ... switch, SWd ... switch, SWe ... switch, UC Undercoat layer, XDR ... the video signal line driver, YDR ... scanning signal line driver.

Claims (6)

A drive transistor having a source connected to the first power supply terminal;
A display element including a pixel electrode, a counter electrode connected to the second power supply terminal, and an active layer interposed therebetween;
A first switch connected between the drain of the driving transistor and the pixel electrode;
A switching transistor connected between a drain and a gate of the driving transistor;
A second switch connected between the drain of the driving transistor and the gate of the switching transistor;
A display device comprising a plurality of pixels each including a third switch connected between a gate of the switching transistor and a switching signal output terminal. A plurality of video signal lines arranged corresponding to columns formed by the plurality of pixels, and each of the plurality of pixels includes:
A capacitor connected between a constant potential terminal and the gate of the driving transistor;
The display device according to claim 1, further comprising a fourth switch connected between the video signal line and a gate of the driving transistor. A plurality of video signal lines arranged corresponding to columns formed by the plurality of pixels, and each of the plurality of pixels includes:
A first capacitor connected between a constant potential terminal and the gate of the driving transistor;
A second capacitor having one electrode connected to the gate of the driving transistor;
The display device according to claim 1, further comprising a fourth switch connected between the other electrode of the second capacitor and the video signal line.   The display device according to claim 1, wherein the display element is an organic EL element. A drive transistor having a source connected to the first power supply terminal;
A pixel electrode;
A first switch connected between the drain of the driving transistor and the pixel electrode;
A switching transistor connected between a drain and a gate of the driving transistor;
A second switch connected between the drain of the driving transistor and the gate of the switching transistor;
An array substrate comprising a plurality of pixel circuits each including a third switch connected between a gate of the switching transistor and a switching signal output terminal. A display element including a drive transistor having a source connected to the first power supply terminal; a pixel electrode; a counter electrode connected to the second power supply terminal; and an active layer interposed therebetween; a drain of the drive transistor; A driving method of a display device including a plurality of pixels each including a switching transistor connected between a gate and a switching transistor,
In a selection period in which the connection between the pixel electrode and the drain of the driving transistor is disconnected, the gate of the switching transistor is connected to a switching signal output terminal, and the potential of the switching signal output terminal is set to an ON potential that closes the switching transistor. A first operation to be set, a second operation for disconnecting the gate of the switching transistor and the switching signal output terminal, a drain of the precursor driving transistor and a gate of the switching transistor are temporarily connected and the switching signal A third operation for setting the potential of the output terminal to an off potential for opening the switching transistor and a fourth operation for connecting the gate of the switching transistor to the switching signal output terminal are performed in this order. Method.

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