JP2006284943A - Display device, array substrate, and driving method of display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a display device which supplies a current signal as a video signal to pixels from respective gradations in a low-gradation region from being displayed as gradations higher than the original gradations. <P>SOLUTION: The display device is characterized in that each pixel PX includes a reset transistor RST which has the source connected to a constant-potential terminal ND<SB>ps</SB>1 and the drain connected to the gate, a reset switch SWd connected between a reset signal output terminal ND<SB>rst</SB>and a video signal DL, a capacitor C2 connected between the terminal ND<SB>ps</SB>1 and terminal ND<SB>rst</SB>, and a capacitor C3 connected between the terminal ND<SB>rst</SB>and the gate of the reset transistor RST. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a display device, an array substrate, and a method for driving the display device.

  In a display device in which the optical characteristics of a display element are controlled by a drive current applied to the display element, such as an organic electroluminescence (EL) display device, image quality defects such as luminance unevenness occur when the drive current varies. Therefore, when the active matrix driving method is adopted in such a display device, the characteristics of the driving transistor that controls the magnitude of the driving current are required to be substantially the same between the pixels. However, in this display device, since the drive transistor is usually formed on an insulator such as a glass substrate, the characteristics are likely to vary.

  Patent Document 1 below describes an organic EL display device that employs a current copy type circuit as a pixel circuit.

  This current copy type pixel circuit includes an n-channel field effect transistor which is a driving transistor, an organic EL element, and a capacitor. The source of the n-channel field effect transistor is connected to a low-potential power line, and the capacitor is connected between the gate of the n-channel field effect transistor and the previous power line. The anode of the organic EL element is connected to a higher potential power line.

This pixel circuit is driven by the following method.
First, the drain and gate of the n-channel field effect transistor are connected, and in this state, a current _Isig having a magnitude corresponding to the video signal is passed between the drain and source of the n-channel field effect transistor. By this operation, the voltage between both electrodes of the capacitor is set to the gate-source voltage necessary for flowing the current _Isig through the channel of the n-channel field effect transistor.

Next, the connection between the drain and gate of the n-channel field effect transistor is disconnected, and the voltage between both electrodes of the capacitor is maintained. Subsequently, the drain of the n-channel field effect transistor is connected to the cathode of the organic EL element. As a result, a drive current I _drv having a magnitude substantially equal to the previous current I _sig flows through the organic EL element. The organic EL element emits light with a luminance corresponding to the magnitude of the drive current I _drv .

As described above, when the current copy type circuit is employed in the pixel circuit, the drive current I _drv having a magnitude almost equal to the current I _sig supplied as the video signal in the writing period is also applied in the holding period following the writing period. It can flow between the drain and source of the n-channel field effect transistor. Therefore, not only the threshold value V _th of the n-channel field effect transistor but also the influence of mobility and size on the drive current I _drv can be eliminated.

However, a display device that employs the current copy type circuit as a pixel circuit has a problem that it is difficult to write a video signal I _sig corresponding to a small drive current I _drv . Therefore, in this display device, each gradation in the low gradation range is easily displayed as a gradation higher than the original gradation, and it is difficult to realize a designed contrast ratio.
US Pat. No. 6,373,454

  An object of the present invention is to prevent each gradation in a low gradation range from being displayed as a gradation higher than an original gradation in a display device that supplies a current signal as a video signal to a pixel.

  According to the first aspect of the present invention, a plurality of pixels and a plurality of video signal lines arranged along the columns formed by the pixels are provided, and each of the plurality of pixels has a source connected to the first power supply terminal. Switch for switching the connected drive transistor, the drain and gate of the drive transistor, and the video signal line between a first state in which they are connected to each other and a second state in which they are disconnected from each other A group, a first capacitor connected between the first constant potential terminal and the gate of the driving transistor, a reset transistor having a source connected to the second constant potential terminal and a drain connected to the gate, and a reset A reset switch connected between a signal output terminal and the video signal line; and a second capacitor connected between a third constant potential terminal and the reset signal output terminal. A third capacitor connected between the reset signal output terminal and the gate of the reset transistor, a counter electrode connected to the pixel electrode and the second power supply terminal, and an active layer interposed therebetween. There is provided a display device comprising: a display element; and an output control switch connected between the drain of the driving transistor and the pixel electrode.

  According to a second aspect of the present invention, a plurality of pixels and a plurality of video signal lines arranged along a column formed by the pixels are provided, and each of the plurality of pixels has a source connected to the first power supply terminal. A drive transistor, a drain and a gate of the drive transistor, and a connection between the video signal line, a first state in which they are connected to each other, a second state in which they are disconnected from each other, A switch group for switching between a third state in which a drain and a gate are connected and the video signal line is disconnected therefrom; a reset switch connected between a reset signal output terminal and the video signal line; A first capacitor connected between a constant potential terminal and the reset signal output terminal, and connected between the reset signal output terminal and the gate of the driving transistor. A display element comprising a second capacitor, a pixel electrode, a counter electrode connected to the second power supply terminal, and an active layer interposed therebetween, and is connected between the drain of the driving transistor and the pixel electrode And a display device characterized in that it includes an output control switch.

  According to a third aspect of the present invention, it comprises a plurality of pixel circuits and a plurality of video signal lines arranged along a column formed by the pixel circuits, each of the plurality of pixel circuits having a source connected to a first power supply terminal. A drive transistor connected to each other, and a connection between the drain and gate of the drive transistor and the video signal line between a first state in which they are connected to each other and a second state in which they are disconnected from each other A switch group for switching, a first capacitor connected between the first constant potential terminal and the gate of the drive transistor, a reset transistor having a source connected to the second constant potential terminal and a drain connected to the gate; A reset switch connected between the reset signal output terminal and the video signal line, and a second switch connected between the third constant potential terminal and the reset signal output terminal. A capacitor, a third capacitor connected between the reset signal output terminal and the gate of the reset transistor, a pixel electrode, an output control switch connected between the drain of the drive transistor and the pixel electrode, An array substrate is provided.

  According to a fourth aspect of the present invention, the pixel circuit includes a plurality of pixel circuits and a plurality of video signal lines arranged along a column formed by the pixel circuits. A drive transistor connected to the drain, a gate of the drive transistor and the video signal line, a first state in which they are connected to each other, a second state in which they are disconnected from each other, and the drive A switch group for switching between a third state in which the drain and gate of the transistor are connected and the video signal line is disconnected therefrom; and a reset switch connected between the reset signal output terminal and the video signal line A first capacitor connected between the constant potential terminal and the reset signal output terminal; and between the reset signal output terminal and the gate of the driving transistor. And connected second capacitor, and the pixel electrodes, an array substrate, characterized in that contained connected and an output control switch between the drain and the pixel electrode of the driving transistor is provided.

  According to a fifth aspect of the present invention, the apparatus includes a plurality of pixels, a plurality of video signal lines arranged along columns formed by the pixels, and a video signal line driver connected to the video signal lines. Each of the pixels includes a driving transistor having a source connected to a first power supply terminal, a first capacitor connected between the first constant potential terminal and the gate of the driving transistor, and a source having a second constant potential terminal. A reset transistor having a drain connected to the gate, a second capacitor connected between the third constant potential terminal and the reset signal output terminal, the reset signal output terminal and the gate of the reset transistor, A display element including a third capacitor connected between the pixel electrode, a counter electrode connected to the pixel electrode and the second power supply terminal, and an active layer interposed therebetween. In the reset method, in the reset period, the video signal line is disconnected from the video signal line driver, the reset signal output terminal is connected to the video signal line, and in the writing period following the reset period. The reset signal output terminal is disconnected from the video signal line, the video signal line and the drain and gate of the driving transistor are connected to each other, and in the effective display period following the writing period, the video signal line and the A driving method is provided, wherein the drain and gate of the driving transistor are disconnected from each other, and the drain of the driving transistor is connected to the pixel electrode.

  According to a sixth aspect of the present invention, the apparatus includes a plurality of pixels, a plurality of video signal lines arranged along a column formed by the pixels, and a video signal line driver connected to the video signal lines. Each of the pixels includes a driving transistor whose source is connected to the first power supply terminal, a first capacitor connected between the constant potential terminal and the reset signal output terminal, the reset signal output terminal, and the driving transistor. A display device driving method including a second capacitor connected between the gate, a display element including a pixel electrode, a counter electrode connected to the second power supply terminal, and an active layer interposed therebetween In the reset period, the drain of the drive transistor is connected to the gate, the video signal line is disconnected from the video signal line driver, and the reset signal is connected to the video signal line. In the writing period following the reset period, the reset signal output terminal is disconnected from the video signal line, the drain of the driving transistor is connected to the video signal line, and the writing period is continued. In the effective display period, there is provided a driving method characterized in that the video signal line and the drain and gate of the driving transistor are disconnected from each other and the drain of the driving transistor is connected to the pixel electrode.

  According to the present invention, in a display device that supplies a current signal as a video signal to a pixel, it is possible to prevent each gradation in the low gradation range from being displayed as a gradation higher than the original gradation. .

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in each figure, the same referential mark is attached | subjected to the component which exhibits the same or similar function, and the overlapping description is abbreviate | omitted.

  FIG. 1 is a plan view schematically showing a display device according to a first aspect of the present invention. FIG. 2 is a cross-sectional view schematically showing an example of a structure that can be employed in the display device of FIG. FIG. 3 is an equivalent circuit diagram of a pixel included in the display device of FIG. In FIG. 2, the display device is drawn such that its display surface, that is, the front surface or the light emitting surface faces downward, and the back surface faces upward.

  This display device is a bottom emission type organic EL display device adopting an active matrix driving method. This organic EL display device includes, for example, an insulating substrate SUB such as a glass substrate.

On the substrate SUB, as shown in FIG. 2, for example, a SiN _x layer and a SiO _x layer are sequentially stacked as the undercoat layer UC.

  On the undercoat layer UC, for example, a gate insulating film GI that can be formed using a semiconductor layer SC which is a polysilicon layer in which a channel and a source / drain are formed, for example, TEOS (TetraEthyl OrthoSilicate), etc., and MoW, for example, The gates G are sequentially stacked, and they constitute a top gate type thin film transistor. In this example, these thin film transistors are p-channel thin film transistors, and are used as the drive transistor DRT, the reset transistor RST, and the switches SWa to SWd included in the pixel PX of FIGS.

  On the gate insulating film GI, one electrode of each of the capacitors C1 to C3 shown in FIGS. 1 and 3 and the scanning signal lines SL1 to SL3 are further arranged. These can be formed in the same process as the gate G.

  As shown in FIG. 1, each of the scanning signal lines SL1 to SL3 extends in the row direction (X direction) of the pixels PX, and is alternately arranged in the column direction (Y direction) of the pixels PX. These scanning signal lines SL1 to SL3 are connected to the scanning signal line driver YDR.

One electrode of each of the gate insulating film GI, the gate G, the scanning signal lines SL1 to SL3, and the capacitors C1 to C3 is covered with an interlayer insulating film II shown in FIG. The interlayer insulating film II is made of, for example, SiO _x formed by a plasma CVD method or the like. A part of the interlayer insulating film II is used as a dielectric layer of the capacitors C1 to C3.

  On the interlayer insulating film II, the other electrode of each of the capacitors C1 to C3 shown in FIGS. 1 and 3, the source electrode SE and the drain electrode DE shown in FIG. 2, and the video signal shown in FIGS. A line DL and a power supply line PSL are arranged. These can be formed in the same process and have, for example, a three-layer structure of Mo / Al / Mo.

  The source electrode SE and drain electrode DE are electrically connected to the source and drain of the thin film transistor through contact holes provided in the interlayer insulating film II.

As shown in FIG. 1, each video signal line DL extends in the Y direction and is arranged in the X direction. These video signal lines DL are connected to a video signal line driver XDR.
In this example, the power supply lines PSL extend in the Y direction and are arranged in the X direction.

The other electrode of each of the source electrode SE, the drain electrode DE, the video signal line DL, the power supply line PSL, and the capacitors C1 to C3 is covered with the passivation film PS shown in FIG. The passivation film PS is made of, for example, SiN _x .

  On the passivation film PS, as shown in FIG. 2, light-transmitting first electrodes PE are juxtaposed apart from each other as a front electrode. Each first electrode PE is a pixel electrode, and is connected to the drain electrode DE of the switch SWa through a through hole provided in the passivation film PS.

  The first electrode PE is an anode in this example. As a material of the first electrode PE, for example, a transparent conductive oxide such as ITO (Indium Tin Oxide) can be used.

  A partition insulating layer PI shown in FIG. 2 is further disposed on the passivation film PS. In the partition insulating layer PI, a through hole is provided at a position corresponding to the first electrode PE, or a slit is provided at a position corresponding to a column or row formed by the first electrode PE. Here, as an example, the partition insulating layer PI is provided with a through hole at a position corresponding to the first electrode PE.

  The partition insulating layer PI is, for example, an organic insulating layer. The partition insulating layer PI can be formed using, for example, a photolithography technique.

  On the first electrode PE, an organic layer ORG including a light emitting layer is disposed as an active layer. The light emitting layer is, for example, a thin film containing a luminescent organic compound whose emission color is red, green, or blue. The organic layer ORG may further include a hole injection layer, a hole injection layer, a hole blocking layer, an electron transport layer, an electron injection layer, and the like in addition to the light emitting layer.

  The partition insulating layer PI and the organic layer ORG are covered with the second electrode CE with a counter electrode. The second electrode CE is a common electrode connected to each other between the pixels PX, and is a light-reflective cathode provided as a back electrode in this example. For example, the second electrode CE is electrically connected to an electrode wiring (not shown) formed on the same layer as the video signal line DL through a contact hole provided in the passivation film PS and the partition insulating layer PI. It is connected to the. Each organic EL element OLED includes a first electrode PE, an organic layer ORG, and a second electrode CE.

  Each pixel PX includes an organic EL element OLED and a pixel circuit. In this example, as shown in FIGS. 1 and 3, the pixel circuit includes a drive transistor DRT, a reset transistor RST, an output control switch SWa, a video signal supply control switch SWb, a diode connection switch SWc, and a reset switch. SWd and capacitors C1 to C3 are included. As described above, in this example, the drive transistor DRT, the reset transistor RST, and the switches SWa to SWd are p-channel thin film transistors. The switches SWb and SWc switch the connection between the drain and gate of the driving transistor DRT and the video signal line DL between a first state in which they are connected to each other and a second state in which they are disconnected from each other. It constitutes a group.

The driving transistor DRT, the output control switch SWa, and the organic EL element OLED are connected in series in this order between the first power supply terminal ND _ps 1 and the second power supply terminal ND _ps 2. In this example, the first power supply terminal ND _ps 1 is a high potential power supply terminal, and the second power supply terminal ND _ps 2 is a low potential power supply terminal.

  The gate of the output control switch SWa is connected to the scanning signal line SL1. The video signal supply control switch SWb is connected between the video signal line DL and the drain of the drive transistor DRT, and its gate is connected to the scanning signal line SL2. The diode connection switch SWc is connected between the drain and gate of the driving transistor DRT, and the gate is connected to the scanning signal line SL2.

The capacitor C1 is connected between the first constant potential terminal and the gate of the drive transistor DRT. In this example, the first constant potential terminal is connected to the first power supply terminal ND _ps 1.

The source of the reset transistor RST is connected to the second constant potential terminal, and the drain is connected to the gate. In this example, the second constant potential terminal is connected to the first power supply terminal ND _ps 1.

The reset switch SWd is connected between the video signal line DL and the reset signal output terminal _NDrst . The gate of the reset switch SWd is connected to the scanning signal line SL3.

The capacitor C2 is connected between the third constant potential terminal and the reset signal output terminal _NDrst . The capacitor C3 is connected between the reset signal output terminal _NDrst and the gate of the reset transistor RST. In this example, the third constant potential terminal is connected to the first power supply terminal ND _ps 1.

  Note that the organic EL display device in which the organic layer ORG and the second electrode CE are omitted and the partition insulating layer PI, the organic layer ORG, and the second electrode CE are omitted correspond to the array substrate.

This organic EL display device is driven by the following method, for example.
FIG. 4 is a timing chart schematically showing an example of a method for driving the display device shown in FIG.

In FIG. 4, the horizontal axis indicates time, and the vertical axis indicates potential. In FIG. 4, among “XDR output”, a period denoted as “I _sig (m + M)” indicates a period during which the video signal line driver XDR outputs the video signal I _sig (m + M) to the video signal line DL. The hatched portion indicates, for example, a period in which the video signal line DL is disconnected from the video signal line driver XDR. Further, in FIG. 4, waveforms indicated by “SL1 potential” to “SL3 potential” indicate the potentials of the scanning signal lines SL1 to SL3, respectively.

  When a certain gradation is displayed by the pixel PX in the m-th row, the output control switch SWa is first opened (non-conducting state) in the period for selecting the pixel PX in the m-th row, that is, the m-th row selection period. . The following reset operation and write operation are performed during the reset period and write period in which the output control switch SWa is open.

In the reset period, a reset operation is performed. That is, the video signal line DL is disconnected from the video signal line driver XDR to be in a floating state. At the same time, the switch SWd is closed (conducting state), and the floating video signal line DL is connected to the reset signal output terminal _NDrst . At this time, the switches SWa to SWc are kept open (non-conductive state). After a certain time has elapsed, the switch SWd is opened. This ends the reset period.

Here, the potential of the first power supply terminal ND _ps 1 is V _dd , the threshold voltage of the reset transistor RST is V _th 2, the capacitance of the capacitor C ₂ is C ₂ , and the capacitance of the capacitor C ₃ is C ₃ . Thus, immediately before the reset operation is started, the potential of the reset signal output terminal _NDrst , that is, the reset potential _Vrst can be expressed by the following equation (1). Therefore, by this reset operation, the potential of the video signal line DL becomes equal to the reset potential _Vrst .

In the writing period following the reset period, a writing operation is performed. That is, the video signal line DL is connected to the video signal line driver XDR. At the same time, the switches SWb and SWc are closed. At this time, the switches SWa and SWd are kept open. In this state, a video signal is output from the video signal line driver XDR to the video signal line DL. That is, the video signal line driver XDR causes the write current I _sig (m) to flow from the first power supply terminal ND _ps 1 to the video signal line DL. After a certain time elapses, the switches SWb and SWc are opened. This ends the writing period. When this write operation is performed, the gate-source voltage of the drive transistor DRT is set to a value at which the write current I _sig (m) flows.

In the effective display period following the writing period, the switch SWa is closed. Further, the switches SWb to SWd are kept open. When the switch SWa is closed, a drive current I _drv (m) having a magnitude corresponding to the write current I _sig (m) flows through the organic EL element OLED. The organic EL element OLED emits light with a luminance corresponding to the magnitude of the drive current I _drv (m).

By the way, for example, when the gradation in the high gradation region is displayed by the pixel PX in the m-th row, the potential of the video signal line DL is the potential of the first power supply terminal ND _ps 1 at the time of starting the m-th row selection period. The potential is set to be much lower than the sum V _dd + V _th 1 (potential corresponding to the lowest gradation) of V _dd and the threshold voltage V _th 1 of the driving transistor DRT. Therefore, in the case where the above reset operation is not performed, in order to display the gradation in the low gradation region by the pixel PX in the (m + 1) th row, the potential of the video signal line DL is set by the writing operation in the (m + 1) th row selection period. It must be greatly increased. That is, although the write current I _sig is small, the potential of the video signal line DL must be changed greatly. Therefore, when the reset operation is not performed, it is difficult to accurately set the gate potential of the drive transistor DRT to a value corresponding to the write current I _sig by the write operation in the (m + 1) th row selection period.

On the other hand, when the above reset operation is performed, the potential of the video signal line DL at the time of starting the write operation in the m-th row selection period regardless of the gradation displayed by the pixel PX in the m-th row is The reset potential V _rst represented by the above equation (1) is set. As is apparent from equation (1), this reset potential V _rst is approximately equal to the sum V _dd + V _th 1 by appropriately setting the capacitances C ₂ and C ₃ and the threshold voltage V _th 2, or , The sum V _dd + V _th 1 can be made lower. Therefore, according to this driving method, it is possible to prevent each gradation in the low gradation range from being displayed as a gradation higher than the original gradation.

Further, in this display device, a reset transistor RST for generating the reset potential V _rst is provided for each pixel PX, and these reset transistors RST are respectively disposed in the pixels PX. Even the driving transistor threshold voltage V _th 2 of DRT threshold voltage V _th 1, and the reset transistor RST was varied between pixels PX, and the difference V _th 1-V _th 2 never vary greatly between the pixels PX . That is, the relationship between the potential V _dd + V _th 1 of the video signal line DL corresponding to the lowest gradation and the reset potential V _rst is almost equal between the pixels PX. Therefore, this display device can display each gradation in the low gradation range with high reproducibility.

  In this aspect, the structure of FIG. 3 is employed for the pixel PX, but other structures may be employed for the pixel PX. For example, the diode connection switch SWc may be connected in series with the drive transistor DRT between the drain of the drive transistor DRT and the video signal line DL when connected between the drain and gate of the drive transistor DRT. Alternatively, the video signal supply control switch SWb may be connected between the gate of the drive transistor DRT and the video signal line DL instead of being connected between the drain of the drive transistor DRT and the video signal line DL.

  Further, for the purpose of separating the circuit that performs the reset operation from the circuit that performs signal writing, a switch element formed of a thin film transistor may be provided between the capacitor C1 and the source of the reset transistor RST.

  Further, the drain and gate of the reset transistor RST can be connected through a video signal control switch SWb and a wiring connected to the video signal wiring. In this case, a switch element made of a thin film transistor may be further provided between the source of the diode connection switch and the output control switch SWb. Thereby, even if the drain of the reset transistor RST and the drain of the drive transistor DRT are connected, the light emitting operation can be performed in parallel with respect to the pixel during the reset operation. However, considering the writing stability at the time of writing the video signal, it is desirable that the drain of the reset transistor RST is not connected to the drain of the driving transistor DRT as shown in FIG.

Next, the second aspect of the present invention will be described.
FIG. 5 is a plan view schematically showing a display device according to the second aspect of the present invention. FIG. 6 is an equivalent circuit diagram of a pixel included in the display device of FIG.

  This display device is a bottom emission type organic EL display device adopting an active matrix driving method. This organic EL display device has the same structure as the organic EL display device shown in FIGS. 1 and 2 except for the following points.

  That is, in this organic EL display device, the scanning signal line SL4 is further provided in addition to the scanning signal lines SL1 to SL3. As shown in FIG. 5, the scanning signal line SL4 extends in the row direction (X direction) of the pixels PX, and is arranged in the column direction (Y direction) of the pixels PX. These scanning signal lines SL4 are connected to the scanning signal line driver YDR.

  A pixel PX of this organic EL display device includes a drive transistor DRT, switches SWa to SWd, and capacitors C1 and C2. That is, in the pixel PX of the organic EL display device, the reset transistor RST and the capacitor C3 of the pixel PX shown in FIGS. 1 and 3 are omitted.

The driving transistor DRT, the output control switch SWa, and the organic EL element OLED are connected in series in this order between the first power supply terminal ND _ps 1 and the second power supply terminal ND _ps 2. In this example, the first power supply terminal ND _ps 1 is a high potential power supply terminal, and the second power supply terminal ND _ps 2 is a low potential power supply terminal.

The gate of the output control switch SWa is connected to the scanning signal line SL1. The video signal supply control switch SWb is connected between the video signal line DL and the drain of the drive transistor DRT, and its gate is connected to the scanning signal line SL2. The diode connection switch SWc is connected between the drain and gate of the drive transistor DRT, and the gate thereof is connected to the scanning signal line SL3. The switches SWb and SWc connect the drain and gate of the driving transistor DRT to the video signal line DL, the first state in which they are connected to each other, the second state in which they are disconnected from each other, and the driving transistor DRT. A switch group is configured to switch between the third state in which the drain and the gate are connected and the video signal line DL is disconnected therefrom. The reset switch SWd is connected between the video signal line DL and the reset signal output terminal _NDrst, and its gate is connected to the scanning signal line SL4.

The capacitor C1 is connected between the constant potential terminal and the reset signal output terminal _NDrst . In this example, the constant potential terminal is connected to the first power supply terminal ND _ps 1. The capacitor C2 is connected between the reset signal output terminal _NDrst and the gate of the drive transistor DRT.

  Note that the organic EL display device in which the organic layer ORG and the second electrode CE are omitted and the partition insulating layer PI, the organic layer ORG, and the second electrode CE are omitted correspond to the array substrate.

This organic EL display device is driven by the following method, for example.
FIG. 7 is a timing chart schematically showing an example of a method of driving the display device shown in FIG.

In FIG. 7, the horizontal axis represents time, and the vertical axis represents potential. In FIG. 4, among “XDR output”, a period denoted as “I _sig (m + M)” indicates a period during which the video signal line driver XDR outputs the video signal I _sig (m + M) to the video signal line DL. The hatched portion indicates, for example, a period in which the video signal line DL is disconnected from the video signal line driver XDR. Further, in FIG. 4, waveforms indicated by “SL1 potential” to “SL4 potential” indicate the potentials of the scanning signal lines SL1 to SL4, respectively.

  When a certain gradation is displayed by the pixel PX in the m-th row, the output control switch SWa is first opened (non-conducting state) in the period for selecting the pixel PX in the m-th row, that is, the m-th row selection period. . The following reset operation and write operation are performed during the reset period and write period in which the output control switch SWa is open.

In the reset period, a reset operation is performed. That is, the video signal line DL is disconnected from the video signal line driver XDR to be in a floating state. At the same time, the switches SWc and SWd are closed (conductive state), the drain and gate of the driving transistor are connected, and the floating video signal line DL is connected to the reset signal output terminal _NDrst . At this time, the switches SWa and SWb are kept open (non-conductive state). After a certain time has elapsed, the switch SWd is opened. This ends the reset period. Note that the switch SWc and the switch SWd may be closed at the same time, or the switch SWd may be closed after the switch SWc is closed.

Here, the potential of the first power supply terminal ND _ps 1 is V _dd , the threshold voltage of the driving transistor DRT is V _th , the capacitance of the capacitor C ₁ is C ₁ , and the capacitance of the capacitor C ₂ is C ₂ . Thus, the potential of the reset signal output terminal ND _rst at the time when the reset operation is completed, that is, the reset potential V _rst can be expressed by the following equation (2). That is, by this reset operation, the potential of the video signal line DL becomes equal to the reset potential _Vrst .

In the writing period following the reset period, a writing operation is performed. That is, the video signal line DL is connected to the video signal line driver XDR. At the same time, the switch SWb is closed. At this time, the switch SWc is kept closed, and the switches SWa and SWd are kept open. In this state, a video signal is output from the video signal line driver XDR to the video signal line DL. That is, the video signal line driver XDR causes the write current I _sig (m) to flow from the first power supply terminal ND _ps 1 to the video signal line DL. After a certain time elapses, the switches SWb and SWc are opened. This ends the writing period. When this write operation is performed, the gate-source voltage of the drive transistor DRT is set to a value at which the write current I _sig (m) flows.

In the effective display period following the writing period, the switch SWa is closed. Further, the switches SWb to SWd are kept open. When the switch SWa is closed, a drive current I _drv (m) having a magnitude corresponding to the write current I _sig (m) flows through the organic EL element OLED. The organic EL element OLED emits light with a luminance corresponding to the magnitude of the drive current I _drv (m).

In this driving method, the potential of the video signal line DL is expressed by the above equation (2) at the time of starting the writing operation in the m-th row selection period, regardless of the gradation displayed by the pixel PX in the m-th row. The reset potential V _rst represented is set. As is apparent from equation (2), this reset potential V _rst is lower than the sum V _dd + V _th 1. Therefore, according to this driving method, it is possible to prevent each gradation in the low gradation range from being displayed as a gradation higher than the original gradation.

Further, in this display device, a driving transistor DRT is used as a transistor for generating the reset potential _Vrst . Therefore, the relationship between the potential V _dd + V _th of the video signal line DL corresponding to the lowest gradation and the reset potential V _rst is almost equal between the pixels PX. Therefore, this display device can display each gradation in the low gradation range with high reproducibility.

  In this aspect, the structure of FIG. 6 is employed for the pixel PX, but other structures may be employed for the pixel PX. For example, the video signal supply control switch SWb may be connected between the gate of the drive transistor DRT and the video signal line DL instead of being connected between the drain of the drive transistor DRT and the video signal line DL.

1 is a plan view schematically showing a display device according to a first aspect of the present invention. FIG. 2 is a cross-sectional view schematically illustrating an example of a structure that can be employed in the display device of FIG. 1. FIG. 2 is an equivalent circuit diagram of a pixel included in the display device of FIG. 1. 2 is a timing chart schematically showing an example of a method for driving the display device shown in FIG. 1. The top view which shows roughly the display apparatus which concerns on the 2nd aspect of this invention. FIG. 6 is an equivalent circuit diagram of a pixel included in the display device of FIG. 5. 6 is a timing chart schematically showing an example of a method for driving the display device shown in FIG. 5.

Explanation of symbols

C1 ... Capacitor, C2 ... Capacitor, C3 ... Capacitor, CE ... Counter electrode, DE ... Drain electrode, DL ... Video signal line, DRT ... Drive transistor, G ... Gate, GI ... Gate insulating film, II ... Interlayer insulating film, ND _ps 1 ... first power supply terminal, ND _ps 2 ... second power supply terminal, ND _rst ... reset signal output terminal, OLED ... organic EL element, ORG ... organic material layer, PE ... pixel electrode, PI ... partition insulating layer, PS ... passivation Membrane, PSL ... Power supply line, PX ... Pixel, RST ... Reset transistor, SC ... Semiconductor layer, SE ... Source electrode, SL1 ... Scanning signal line, SL2 ... Scanning signal line, SL3 ... Scanning signal line, SL4 ... Scanning signal line, SUB ... Insulating substrate, SWa ... Output control switch, SWb ... Video signal supply control switch, SWc ... Diode connection switch, SWd ... Resets Switch, UC ... Undercoat layer, XDR ... Video signal line driver, YDR ... Scanning signal line driver.

Claims (11)

Comprising a plurality of pixels and a plurality of video signal lines arranged along a column formed by them, each of the plurality of pixels,
A drive transistor having a source connected to the first power supply terminal;
A switch group for switching the connection between the drain and gate of the driving transistor and the video signal line between a first state in which they are connected to each other and a second state in which they are disconnected from each other;
A first capacitor connected between a first constant potential terminal and a gate of the driving transistor;
A reset transistor having a source connected to the second constant potential terminal and a drain connected to the gate;
A reset switch connected between a reset signal output terminal and the video signal line;
A second capacitor connected between a third constant potential terminal and the reset signal output terminal;
A third capacitor connected between the reset signal output terminal and the gate of the reset transistor;
A display element comprising a pixel electrode, a counter electrode connected to the second power supply terminal, and an active layer interposed therebetween;
A display device comprising: an output control switch connected between a drain of the driving transistor and the pixel electrode. Comprising a plurality of pixels and a plurality of video signal lines arranged along a column formed by them, each of the plurality of pixels,
A drive transistor having a source connected to the first power supply terminal;
The drive transistor drain, gate and video signal line are connected to each other in a first state in which they are connected to each other, a second state in which they are disconnected from each other, and a drain and gate in the drive transistor are connected to each other. And a switch group for switching between them and a third state in which the video signal line is disconnected,
A reset switch connected between a reset signal output terminal and the video signal line;
A first capacitor connected between a constant potential terminal and the reset signal output terminal;
A second capacitor connected between the reset signal output terminal and the gate of the driving transistor;
A display element comprising a pixel electrode, a counter electrode connected to the second power supply terminal, and an active layer interposed therebetween;
A display device comprising: an output control switch connected between a drain of the driving transistor and the pixel electrode.   The video signal line driver further connected to the plurality of video signal lines, wherein the video signal line is disconnected from the video signal line driver in a reset period in which the reset switch is closed. Or the display apparatus of 2.   The display device according to claim 1, wherein the first to third constant potential terminals are connected to the first power supply terminal.   The display device according to claim 2, wherein the first and second constant potential terminals are connected to the first power supply terminal.   The switch group includes a video signal supply control switch connected between the drain of the driving transistor and the video signal line, and a diode connection switch connected between the drain and gate of the driving transistor. The display device according to claim 1 or 2.   The display device according to claim 1, wherein the display element is an organic EL element. A plurality of pixel circuits, and a plurality of video signal lines arranged along a column formed by the pixel circuits, and each of the plurality of pixel circuits includes:
A drive transistor having a source connected to the first power supply terminal;
A switch group for switching the connection between the drain and gate of the driving transistor and the video signal line between a first state in which they are connected to each other and a second state in which they are disconnected from each other;
A first capacitor connected between a first constant potential terminal and a gate of the driving transistor;
A reset transistor having a source connected to the second constant potential terminal and a drain connected to the gate;
A reset switch connected between a reset signal output terminal and the video signal line;
A second capacitor connected between a third constant potential terminal and the reset signal output terminal;
A third capacitor connected between the reset signal output terminal and the gate of the reset transistor;
A pixel electrode;
An array substrate comprising: an output control switch connected between the drain of the driving transistor and the pixel electrode. A plurality of pixel circuits, and a plurality of video signal lines arranged along a column formed by the pixel circuits, and each of the plurality of pixel circuits includes:
A drive transistor having a source connected to the first power supply terminal;
The drive transistor drain, gate and video signal line are connected to each other in a first state in which they are connected to each other, a second state in which they are disconnected from each other, and a drain and gate in the drive transistor are connected to each other. And a switch group for switching between them and a third state in which the video signal line is disconnected,
A reset switch connected between a reset signal output terminal and the video signal line;
A first capacitor connected between a constant potential terminal and the reset signal output terminal;
A second capacitor connected between the reset signal output terminal and the gate of the driving transistor;
A pixel electrode;
An array substrate comprising: an output control switch connected between the drain of the driving transistor and the pixel electrode. A plurality of pixels, a plurality of video signal lines arranged along a column formed by the pixels, and a video signal line driver connected to the video signal lines. A driving transistor connected to one power supply terminal; a first capacitor connected between the first constant potential terminal and the gate of the driving transistor; a source connected to the second constant potential terminal and a drain connected to the gate; A connected reset transistor; a second capacitor connected between a third constant potential terminal and a reset signal output terminal; and a third capacitor connected between the reset signal output terminal and the gate of the reset transistor. And a display element comprising a pixel electrode, a counter electrode connected to a second power supply terminal, and an active layer interposed therebetween, ,
In the reset period, disconnect the video signal line from the video signal line driver, connect the reset signal output terminal to the video signal line,
In the writing period following the reset period, the reset signal output terminal is disconnected from the video signal line, and the video signal line and the drain and gate of the driving transistor are connected to each other,
In the effective display period following the writing period, the video signal line and the drain and gate of the driving transistor are disconnected from each other, and the drain of the driving transistor is connected to the pixel electrode. A plurality of pixels, a plurality of video signal lines arranged along a column formed by the pixels, and a video signal line driver connected to the video signal lines. A driving transistor connected to one power supply terminal; a first capacitor connected between the constant potential terminal and the reset signal output terminal; and a first capacitor connected between the reset signal output terminal and the gate of the driving transistor. A display device driving method including a display element including two capacitors, a pixel electrode, a counter electrode connected to a second power supply terminal, and an active layer interposed therebetween,
In the reset period, the drain of the driving transistor is connected to the gate, the video signal line is disconnected from the video signal line driver, the reset signal output terminal is connected to the video signal line,
In the writing period following the reset period, the reset signal output terminal is disconnected from the video signal line, and the drain of the driving transistor is connected to the video signal line,
In the effective display period following the writing period, the video signal line and the drain and gate of the driving transistor are disconnected from each other, and the drain of the driving transistor is connected to the pixel electrode.

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