JP2006522406A - データ・フロー・マシン - Google Patents

データ・フロー・マシン Download PDF

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JP2006522406A
JP2006522406A JP2006507967A JP2006507967A JP2006522406A JP 2006522406 A JP2006522406 A JP 2006522406A JP 2006507967 A JP2006507967 A JP 2006507967A JP 2006507967 A JP2006507967 A JP 2006507967A JP 2006522406 A JP2006522406 A JP 2006522406A
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data
data flow
flow machine
digital control
digital
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JP2006507967A
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Japanese (ja)
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JP2006522406A5 (enExample
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メール、ステファン
ボルグ、ポントゥス
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マイトリオニクス エービー
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44Arrangements for executing specific programs
    • G06F9/448Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4494Execution paradigms, e.g. implementations of programming paradigms data driven

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Devices For Executing Special Programs (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Stored Programmes (AREA)
  • Aerodynamic Tests, Hydrodynamic Tests, Wind Tunnels, And Water Tanks (AREA)
  • General Factory Administration (AREA)
JP2006507967A 2003-03-17 2004-03-17 データ・フロー・マシン Pending JP2006522406A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE0300742A SE0300742D0 (sv) 2003-03-17 2003-03-17 Data Flow Machine
PCT/SE2004/000394 WO2004084086A1 (en) 2003-03-17 2004-03-17 Data flow machine

Publications (2)

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JP2006522406A true JP2006522406A (ja) 2006-09-28
JP2006522406A5 JP2006522406A5 (enExample) 2007-05-17

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JP2006507967A Pending JP2006522406A (ja) 2003-03-17 2004-03-17 データ・フロー・マシン

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US (1) US20060101237A1 (enExample)
EP (1) EP1609078B1 (enExample)
JP (1) JP2006522406A (enExample)
CN (1) CN1781092A (enExample)
SE (1) SE0300742D0 (enExample)
WO (1) WO2004084086A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022522177A (ja) * 2019-02-27 2022-04-14 コミッサリア ア レネルジー アトミーク エ オ ゼネルジ ザルタナテイヴ データフローシステムを検証するための方法

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7571303B2 (en) * 2002-10-16 2009-08-04 Akya (Holdings) Limited Reconfigurable integrated circuit
WO2006025062A2 (en) 2004-09-02 2006-03-09 Logiccon Design Automation Ltd. Method and system for designing a structural level description of an electronic circuit
CN101179516B (zh) * 2006-11-10 2010-06-09 北京航空航天大学 基于有向图的数据分发方法
US8510709B2 (en) * 2009-06-01 2013-08-13 National Instruments Corporation Graphical indicator which specifies parallelization of iterative program code in a graphical data flow program
US9733914B2 (en) * 2009-06-01 2017-08-15 National Instruments Corporation Loop parallelization analyzer for data flow programs
US9152668B1 (en) * 2010-01-29 2015-10-06 Asana, Inc. Asynchronous computation batching
US10157060B2 (en) 2011-12-29 2018-12-18 Intel Corporation Method, device and system for control signaling in a data path module of a data stream processing engine
US10331583B2 (en) 2013-09-26 2019-06-25 Intel Corporation Executing distributed memory operations using processing elements connected by distributed channels
CN110149801A (zh) * 2015-05-05 2019-08-20 华为技术有限公司 用于在处理系统中进行数据流图转换的系统和方法
CN106155755B (zh) * 2015-06-03 2020-06-23 上海红神信息技术有限公司 程序编译方法和程序编译器
US10572376B2 (en) 2016-12-30 2020-02-25 Intel Corporation Memory ordering in acceleration hardware
US10558575B2 (en) 2016-12-30 2020-02-11 Intel Corporation Processors, methods, and systems with a configurable spatial accelerator
US10515049B1 (en) 2017-07-01 2019-12-24 Intel Corporation Memory circuits and methods for distributed memory hazard detection and error recovery
US10515046B2 (en) 2017-07-01 2019-12-24 Intel Corporation Processors, methods, and systems with a configurable spatial accelerator
US10469397B2 (en) 2017-07-01 2019-11-05 Intel Corporation Processors and methods with configurable network-based dataflow operator circuits
US11086816B2 (en) 2017-09-28 2021-08-10 Intel Corporation Processors, methods, and systems for debugging a configurable spatial accelerator
US10496574B2 (en) 2017-09-28 2019-12-03 Intel Corporation Processors, methods, and systems for a memory fence in a configurable spatial accelerator
US11307873B2 (en) 2018-04-03 2022-04-19 Intel Corporation Apparatus, methods, and systems for unstructured data flow in a configurable spatial accelerator with predicate propagation and merging
US10564980B2 (en) * 2018-04-03 2020-02-18 Intel Corporation Apparatus, methods, and systems for conditional queues in a configurable spatial accelerator
US10891240B2 (en) 2018-06-30 2021-01-12 Intel Corporation Apparatus, methods, and systems for low latency communication in a configurable spatial accelerator
US10853073B2 (en) 2018-06-30 2020-12-01 Intel Corporation Apparatuses, methods, and systems for conditional operations in a configurable spatial accelerator
US11200186B2 (en) 2018-06-30 2021-12-14 Intel Corporation Apparatuses, methods, and systems for operations in a configurable spatial accelerator
US10678724B1 (en) 2018-12-29 2020-06-09 Intel Corporation Apparatuses, methods, and systems for in-network storage in a configurable spatial accelerator
WO2020168474A1 (zh) * 2019-02-20 2020-08-27 深圳大学 提升数据流机运行效率的方法、装置、设备及存储介质
US10915471B2 (en) 2019-03-30 2021-02-09 Intel Corporation Apparatuses, methods, and systems for memory interface circuit allocation in a configurable spatial accelerator
US10965536B2 (en) 2019-03-30 2021-03-30 Intel Corporation Methods and apparatus to insert buffers in a dataflow graph
US11029927B2 (en) 2019-03-30 2021-06-08 Intel Corporation Methods and apparatus to detect and annotate backedges in a dataflow graph
US10817291B2 (en) 2019-03-30 2020-10-27 Intel Corporation Apparatuses, methods, and systems for swizzle operations in a configurable spatial accelerator
US11037050B2 (en) 2019-06-29 2021-06-15 Intel Corporation Apparatuses, methods, and systems for memory interface circuit arbitration in a configurable spatial accelerator
US11907713B2 (en) 2019-12-28 2024-02-20 Intel Corporation Apparatuses, methods, and systems for fused operations using sign modification in a processing element of a configurable spatial accelerator
WO2021211911A1 (en) * 2020-04-16 2021-10-21 Blackswan Technologies Inc. Artificial intelligence cloud operating system
US12086080B2 (en) 2020-09-26 2024-09-10 Intel Corporation Apparatuses, methods, and systems for a configurable accelerator having dataflow execution circuits
US20250077244A1 (en) * 2023-08-30 2025-03-06 Intel Corporation Device, method and system to support a synchronous data flow with an identification of an executable task

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11120210A (ja) * 1997-10-21 1999-04-30 Toshiba Corp 再構成可能な回路の設計装置、及び再構成可能な回路装置
JP2001306546A (ja) * 2000-04-27 2001-11-02 Sharp Corp データ駆動型情報処理装置

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61276032A (ja) * 1985-05-31 1986-12-06 Matsushita Electric Ind Co Ltd 情報処理装置
JPH0632056B2 (ja) * 1985-05-31 1994-04-27 松下電器産業株式会社 デ−タ処理装置
US5021947A (en) * 1986-03-31 1991-06-04 Hughes Aircraft Company Data-flow multiprocessor architecture with three dimensional multistage interconnection network for efficient signal and data processing
US4814978A (en) * 1986-07-15 1989-03-21 Dataflow Computer Corporation Dataflow processing element, multiprocessor, and processes
US4972315A (en) * 1987-03-10 1990-11-20 Mitsubishi Denki Kabushiki Kaisha Data flow machine
JPH03500461A (ja) * 1988-07-22 1991-01-31 アメリカ合衆国 データ駆動式計算用のデータ流れ装置
US5530841A (en) * 1990-12-21 1996-06-25 Synopsys, Inc. Method for converting a hardware independent user description of a logic circuit into hardware components
US5666296A (en) * 1991-12-31 1997-09-09 Texas Instruments Incorporated Method and means for translating a data-dependent program to a data flow graph with conditional expression
US5491640A (en) * 1992-05-01 1996-02-13 Vlsi Technology, Inc. Method and apparatus for synthesizing datapaths for integrated circuit design and fabrication
US5297073A (en) * 1992-08-19 1994-03-22 Nec Electronics, Inc. Integer divide using shift and subtract
JP3706397B2 (ja) * 1994-06-06 2005-10-12 シャープ株式会社 データ駆動型情報処理装置
JPH08101861A (ja) * 1994-09-30 1996-04-16 Toshiba Corp 論理回路合成装置
US6077315A (en) * 1995-04-17 2000-06-20 Ricoh Company Ltd. Compiling system and method for partially reconfigurable computing
US5764951A (en) * 1995-05-12 1998-06-09 Synopsys, Inc. Methods for automatically pipelining loops
US5854929A (en) * 1996-03-08 1998-12-29 Interuniversitair Micro-Elektronica Centrum (Imec Vzw) Method of generating code for programmable processors, code generator and application thereof
US5838583A (en) * 1996-04-12 1998-11-17 Cadence Design Systems, Inc. Optimized placement and routing of datapaths
US5974411A (en) * 1997-02-18 1999-10-26 Sand Technology Systems International, Inc. N-way processing of bit strings in a dataflow architecture
US6606588B1 (en) * 1997-03-14 2003-08-12 Interuniversitair Micro-Elecktronica Centrum (Imec Vzw) Design apparatus and a method for generating an implementable description of a digital system
US5966534A (en) * 1997-06-27 1999-10-12 Cooke; Laurence H. Method for compiling high level programming languages into an integrated processor with reconfigurable logic
US6075935A (en) * 1997-12-01 2000-06-13 Improv Systems, Inc. Method of generating application specific integrated circuits using a programmable hardware architecture
RU2148857C1 (ru) * 1998-02-20 2000-05-10 Бурцев Всеволод Сергеевич Вычислительная система
US6145073A (en) * 1998-10-16 2000-11-07 Quintessence Architectures, Inc. Data flow integrated circuit architecture
US6625797B1 (en) * 2000-02-10 2003-09-23 Xilinx, Inc. Means and method for compiling high level software languages into algorithmically equivalent hardware representations
JP3722351B2 (ja) * 2000-02-18 2005-11-30 シャープ株式会社 高位合成方法およびその実施に使用される記録媒体
KR100345009B1 (ko) * 2000-08-14 2002-07-20 주식회사 에이디칩스 비동기식 제어부의 생성 방법
US20020178432A1 (en) * 2000-08-17 2002-11-28 Hyungwon Kim Method and system for synthesizing a circuit representation into a new circuit representation having greater unateness
JP2002123563A (ja) * 2000-10-13 2002-04-26 Nec Corp コンパイル方法および合成装置ならびに記録媒体
WO2003032490A2 (en) * 2001-10-11 2003-04-17 California Institute Of Technology Method and apparatus for an asynchronous pulse logic circuit
JP4082653B2 (ja) * 2001-11-15 2008-04-30 松下電器産業株式会社 高位合成方法および高位合成装置
CN1659540A (zh) * 2002-06-03 2005-08-24 皇家飞利浦电子股份有限公司 可重配置集成电路
US7065665B2 (en) * 2002-10-02 2006-06-20 International Business Machines Corporation Interlocked synchronous pipeline clock gating
US6983456B2 (en) * 2002-10-31 2006-01-03 Src Computers, Inc. Process for converting programs in high-level programming languages to a unified executable for hybrid computing platforms
US8281297B2 (en) * 2003-02-05 2012-10-02 Arizona Board Of Regents Reconfigurable processing
WO2007046749A2 (en) * 2005-10-18 2007-04-26 Mitrionics Ab Method for avoiding deadlock in data flow machine

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11120210A (ja) * 1997-10-21 1999-04-30 Toshiba Corp 再構成可能な回路の設計装置、及び再構成可能な回路装置
JP2001306546A (ja) * 2000-04-27 2001-11-02 Sharp Corp データ駆動型情報処理装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022522177A (ja) * 2019-02-27 2022-04-14 コミッサリア ア レネルジー アトミーク エ オ ゼネルジ ザルタナテイヴ データフローシステムを検証するための方法
US12056507B2 (en) 2019-02-27 2024-08-06 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for validating a data flow system
JP7638879B2 (ja) 2019-02-27 2025-03-04 コミッサリア ア レネルジー アトミーク エ オ ゼネルジ ザルタナテイヴ データフローシステムを検証するための方法

Also Published As

Publication number Publication date
SE0300742D0 (sv) 2003-03-17
EP1609078A1 (en) 2005-12-28
US20060101237A1 (en) 2006-05-11
WO2004084086A1 (en) 2004-09-30
EP1609078B1 (en) 2016-06-01
CN1781092A (zh) 2006-05-31
WO2004084086A8 (en) 2005-02-24

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