JP2006517322A - パイプライン化ディジタルプロセッサにおけるハザード検出および管理のための方法および装置 - Google Patents

パイプライン化ディジタルプロセッサにおけるハザード検出および管理のための方法および装置 Download PDF

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JP2006517322A
JP2006517322A JP2006503481A JP2006503481A JP2006517322A JP 2006517322 A JP2006517322 A JP 2006517322A JP 2006503481 A JP2006503481 A JP 2006503481A JP 2006503481 A JP2006503481 A JP 2006503481A JP 2006517322 A JP2006517322 A JP 2006517322A
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instruction
write
read
resource
type
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JP2006503481A
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Japanese (ja)
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JP2006517322A5 (enExample
Inventor
トマジン，トーマス，ジェイ．
ウィット，デーヴィッド
チンナコンダ，ミューラリ
フーパー，ウィリアム，エイチ．
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アナログ・デバイシズ・インコーポレーテッド
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Publication of JP2006517322A publication Critical patent/JP2006517322A/ja
Publication of JP2006517322A5 publication Critical patent/JP2006517322A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
JP2006503481A 2003-02-10 2004-02-10 パイプライン化ディジタルプロセッサにおけるハザード検出および管理のための方法および装置 Pending JP2006517322A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/361,288 US20040158694A1 (en) 2003-02-10 2003-02-10 Method and apparatus for hazard detection and management in a pipelined digital processor
PCT/US2004/003963 WO2004072848A2 (en) 2003-02-10 2004-02-10 Method and apparatus for hazard detection and management in a pipelined digital processor

Publications (2)

Publication Number Publication Date
JP2006517322A true JP2006517322A (ja) 2006-07-20
JP2006517322A5 JP2006517322A5 (enExample) 2006-08-31

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ID=32824198

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006503481A Pending JP2006517322A (ja) 2003-02-10 2004-02-10 パイプライン化ディジタルプロセッサにおけるハザード検出および管理のための方法および装置

Country Status (4)

Country Link
US (1) US20040158694A1 (enExample)
EP (1) EP1609058A2 (enExample)
JP (1) JP2006517322A (enExample)
WO (1) WO2004072848A2 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010128582A1 (ja) * 2009-05-08 2010-11-11 パナソニック株式会社 プロセッサ
KR20200018233A (ko) * 2018-08-10 2020-02-19 베이징 바이두 넷컴 사이언스 앤 테크놀로지 코., 엘티디. 명령 실행 방법 및 장치

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7237065B2 (en) * 2005-05-24 2007-06-26 Texas Instruments Incorporated Configurable cache system depending on instruction type
WO2007068148A1 (en) * 2005-12-17 2007-06-21 Intel Corporation Method and apparatus for partitioning programs to balance memory latency
US20080005366A1 (en) * 2006-04-04 2008-01-03 Sreenidhi Raatni Apparatus and methods for handling requests over an interface
US20090260013A1 (en) * 2008-04-14 2009-10-15 International Business Machines Corporation Computer Processors With Plural, Pipelined Hardware Threads Of Execution
US9405548B2 (en) 2011-12-07 2016-08-02 International Business Machines Corporation Prioritizing instructions based on the number of delay cycles
US9323285B2 (en) 2013-08-13 2016-04-26 Altera Corporation Metastability prediction and avoidance in memory arbitration circuitry
US20150370564A1 (en) * 2014-06-24 2015-12-24 Eli Kupermann Apparatus and method for adding a programmable short delay
US10853077B2 (en) * 2015-08-26 2020-12-01 Huawei Technologies Co., Ltd. Handling Instruction Data and Shared resources in a Processor Having an Architecture Including a Pre-Execution Pipeline and a Resource and a Resource Tracker Circuit Based on Credit Availability
US11221853B2 (en) 2015-08-26 2022-01-11 Huawei Technologies Co., Ltd. Method of dispatching instruction data when a number of available resource credits meets a resource requirement
US11275590B2 (en) * 2015-08-26 2022-03-15 Huawei Technologies Co., Ltd. Device and processing architecture for resolving execution pipeline dependencies without requiring no operation instructions in the instruction memory
US10339063B2 (en) * 2016-07-19 2019-07-02 Advanced Micro Devices, Inc. Scheduling independent and dependent operations for processing
KR20190052441A (ko) * 2017-11-08 2019-05-16 에스케이하이닉스 주식회사 메모리 컨트롤러 및 그 동작 방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6035389A (en) * 1998-08-11 2000-03-07 Intel Corporation Scheduling instructions with different latencies
EP1004959B1 (en) * 1998-10-06 2018-08-08 Texas Instruments Incorporated Processor with pipeline protection
US6304955B1 (en) * 1998-12-30 2001-10-16 Intel Corporation Method and apparatus for performing latency based hazard detection
US6591360B1 (en) * 2000-01-18 2003-07-08 Hewlett-Packard Development Company Local stall/hazard detect in superscalar, pipelined microprocessor
US6708267B1 (en) * 2000-02-04 2004-03-16 International Business Machines Corporation System and method in a pipelined processor for generating a single cycle pipeline stall

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010128582A1 (ja) * 2009-05-08 2010-11-11 パナソニック株式会社 プロセッサ
JP2010262542A (ja) * 2009-05-08 2010-11-18 Panasonic Corp プロセッサ
KR20200018233A (ko) * 2018-08-10 2020-02-19 베이징 바이두 넷컴 사이언스 앤 테크놀로지 코., 엘티디. 명령 실행 방법 및 장치
KR102225768B1 (ko) 2018-08-10 2021-03-09 베이징 바이두 넷컴 사이언스 앤 테크놀로지 코., 엘티디. 명령 실행 방법 및 장치

Also Published As

Publication number Publication date
WO2004072848A3 (en) 2005-12-08
WO2004072848A8 (en) 2004-10-28
US20040158694A1 (en) 2004-08-12
WO2004072848A9 (en) 2005-08-18
WO2004072848A2 (en) 2004-08-26
EP1609058A2 (en) 2005-12-28

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