JP2006502507A5 - - Google Patents

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Publication number
JP2006502507A5
JP2006502507A5 JP2004543571A JP2004543571A JP2006502507A5 JP 2006502507 A5 JP2006502507 A5 JP 2006502507A5 JP 2004543571 A JP2004543571 A JP 2004543571A JP 2004543571 A JP2004543571 A JP 2004543571A JP 2006502507 A5 JP2006502507 A5 JP 2006502507A5
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JP
Japan
Prior art keywords
memory
thread
processor
thread identifier
selecting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2004543571A
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English (en)
Japanese (ja)
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JP2006502507A (ja
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Publication date
Priority claimed from US10/269,247 external-priority patent/US6925643B2/en
Application filed filed Critical
Publication of JP2006502507A publication Critical patent/JP2006502507A/ja
Publication of JP2006502507A5 publication Critical patent/JP2006502507A5/ja
Withdrawn legal-status Critical Current

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JP2004543571A 2002-10-11 2003-10-09 多重スレッド・プロセッサにおけるスレッドをベースにしたメモリ・アクセスの方法およびシステム Withdrawn JP2006502507A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/269,247 US6925643B2 (en) 2002-10-11 2002-10-11 Method and apparatus for thread-based memory access in a multithreaded processor
PCT/US2003/031961 WO2004034218A2 (en) 2002-10-11 2003-10-09 Method and apparatus for thread-based memory access in a multithreaded processor

Publications (2)

Publication Number Publication Date
JP2006502507A JP2006502507A (ja) 2006-01-19
JP2006502507A5 true JP2006502507A5 (enExample) 2006-12-07

Family

ID=32068735

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004543571A Withdrawn JP2006502507A (ja) 2002-10-11 2003-10-09 多重スレッド・プロセッサにおけるスレッドをベースにしたメモリ・アクセスの方法およびシステム

Country Status (9)

Country Link
US (1) US6925643B2 (enExample)
EP (1) EP1550032B1 (enExample)
JP (1) JP2006502507A (enExample)
KR (1) KR100980536B1 (enExample)
CN (1) CN1332303C (enExample)
AU (1) AU2003282511A1 (enExample)
ES (1) ES2758623T3 (enExample)
HU (1) HUE046355T2 (enExample)
WO (1) WO2004034218A2 (enExample)

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US7797363B2 (en) * 2004-04-07 2010-09-14 Sandbridge Technologies, Inc. Processor having parallel vector multiply and reduce operations with sequential semantics
US7475222B2 (en) * 2004-04-07 2009-01-06 Sandbridge Technologies, Inc. Multi-threaded processor having compound instruction and operation formats
US8074051B2 (en) * 2004-04-07 2011-12-06 Aspen Acquisition Corporation Multithreaded processor with multiple concurrent pipelines per thread
US7280428B2 (en) 2004-09-30 2007-10-09 Rambus Inc. Multi-column addressing mode memory system including an integrated circuit memory device
US7797728B2 (en) * 2004-10-27 2010-09-14 Intel Corporation Mechanism to generate restricted and unrestricted execution environments
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US8595459B2 (en) 2004-11-29 2013-11-26 Rambus Inc. Micro-threaded memory
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KR101279343B1 (ko) 2005-09-13 2013-07-04 프리스케일 세미컨덕터, 인크. 멀티-스레딩된 프로세서 구조
KR101305490B1 (ko) * 2005-10-01 2013-09-06 삼성전자주식회사 메모리 맵핑 방법 및 장치
US7788468B1 (en) 2005-12-15 2010-08-31 Nvidia Corporation Synchronization of threads in a cooperative thread array
US7861060B1 (en) * 2005-12-15 2010-12-28 Nvidia Corporation Parallel data processing systems and methods using cooperative thread arrays and thread identifier values to determine processing behavior
US7584342B1 (en) * 2005-12-15 2009-09-01 Nvidia Corporation Parallel data processing systems and methods using cooperative thread arrays and SIMD instruction issue
US20070260841A1 (en) * 2006-05-02 2007-11-08 Hampel Craig E Memory module with reduced access granularity
JP5076418B2 (ja) * 2006-09-19 2012-11-21 ソニー株式会社 共有メモリ装置
EP2069947A4 (en) * 2006-09-26 2013-10-09 Qualcomm Inc SOFTWARE IMPLEMENTATION OF A MATRIX INVERSION IN A WIRELESS COMMUNICATION SYSTEM
WO2008060948A2 (en) * 2006-11-10 2008-05-22 Sandbridge Technologies, Inc. Method and system for parallelization of pipelined computations
US7596668B2 (en) * 2007-02-20 2009-09-29 International Business Machines Corporation Method, system and program product for associating threads within non-related processes based on memory paging behaviors
US20100241834A1 (en) * 2007-11-05 2010-09-23 Sandbridge Technologies, Inc. Method of encoding using instruction field overloading
US8539188B2 (en) * 2008-01-30 2013-09-17 Qualcomm Incorporated Method for enabling multi-processor synchronization
US8762641B2 (en) * 2008-03-13 2014-06-24 Qualcomm Incorporated Method for achieving power savings by disabling a valid array
WO2010017263A1 (en) 2008-08-06 2010-02-11 Sandbridge Technologies, Inc. Haltable and restartable dma engine
CN101739242B (zh) * 2009-11-27 2013-07-31 深圳中微电科技有限公司 一种流数据处理方法及流处理器
CN102141905B (zh) * 2010-01-29 2015-02-25 上海芯豪微电子有限公司 一种处理器体系结构
US9268719B2 (en) 2011-08-05 2016-02-23 Rambus Inc. Memory signal buffers and modules supporting variable access granularity
GB2519813B (en) 2013-10-31 2016-03-30 Silicon Tailor Ltd Pipelined configurable processor
US9436501B2 (en) 2014-08-26 2016-09-06 International Business Machines Corporation Thread-based cache content saving for task switching
CN104461961B (zh) * 2014-11-20 2018-02-27 上海宝存信息科技有限公司 一种多核多线程的闪存装置及闪存控制方法
US11243880B1 (en) * 2017-09-15 2022-02-08 Groq, Inc. Processor architecture
CN114816529B (zh) * 2020-10-21 2025-07-18 上海壁仞科技股份有限公司 配置向量运算系统中的协作线程束的装置和方法

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