HUE046355T2 - Eljárás és berendezés szál alapú memória hozzáférésre egy többszálú processzorban - Google Patents

Eljárás és berendezés szál alapú memória hozzáférésre egy többszálú processzorban

Info

Publication number
HUE046355T2
HUE046355T2 HUE03774703A HUE03774703A HUE046355T2 HU E046355 T2 HUE046355 T2 HU E046355T2 HU E03774703 A HUE03774703 A HU E03774703A HU E03774703 A HUE03774703 A HU E03774703A HU E046355 T2 HUE046355 T2 HU E046355T2
Authority
HU
Hungary
Prior art keywords
based memory
multithreaded processor
accessing thread
accessing
thread
Prior art date
Application number
HUE03774703A
Other languages
English (en)
Hungarian (hu)
Inventor
Erdem Hokenek
Mayan Moudgill
John Glossner
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of HUE046355T2 publication Critical patent/HUE046355T2/hu

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3888—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple threads [SIMT] in parallel
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/342—Extension of operand address space
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Multimedia (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Power Sources (AREA)
HUE03774703A 2002-10-11 2003-10-09 Eljárás és berendezés szál alapú memória hozzáférésre egy többszálú processzorban HUE046355T2 (hu)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/269,247 US6925643B2 (en) 2002-10-11 2002-10-11 Method and apparatus for thread-based memory access in a multithreaded processor

Publications (1)

Publication Number Publication Date
HUE046355T2 true HUE046355T2 (hu) 2020-03-30

Family

ID=32068735

Family Applications (1)

Application Number Title Priority Date Filing Date
HUE03774703A HUE046355T2 (hu) 2002-10-11 2003-10-09 Eljárás és berendezés szál alapú memória hozzáférésre egy többszálú processzorban

Country Status (9)

Country Link
US (1) US6925643B2 (enExample)
EP (1) EP1550032B1 (enExample)
JP (1) JP2006502507A (enExample)
KR (1) KR100980536B1 (enExample)
CN (1) CN1332303C (enExample)
AU (1) AU2003282511A1 (enExample)
ES (1) ES2758623T3 (enExample)
HU (1) HUE046355T2 (enExample)
WO (1) WO2004034218A2 (enExample)

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US7475222B2 (en) * 2004-04-07 2009-01-06 Sandbridge Technologies, Inc. Multi-threaded processor having compound instruction and operation formats
US7280428B2 (en) 2004-09-30 2007-10-09 Rambus Inc. Multi-column addressing mode memory system including an integrated circuit memory device
US7797728B2 (en) * 2004-10-27 2010-09-14 Intel Corporation Mechanism to generate restricted and unrestricted execution environments
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US20060136681A1 (en) * 2004-12-21 2006-06-22 Sanjeev Jain Method and apparatus to support multiple memory banks with a memory block
WO2007014261A2 (en) * 2005-07-25 2007-02-01 Sysair, Inc. Cellular pc modem architecture and method of operation
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KR101305490B1 (ko) * 2005-10-01 2013-09-06 삼성전자주식회사 메모리 맵핑 방법 및 장치
US7584342B1 (en) * 2005-12-15 2009-09-01 Nvidia Corporation Parallel data processing systems and methods using cooperative thread arrays and SIMD instruction issue
US7788468B1 (en) 2005-12-15 2010-08-31 Nvidia Corporation Synchronization of threads in a cooperative thread array
US7861060B1 (en) * 2005-12-15 2010-12-28 Nvidia Corporation Parallel data processing systems and methods using cooperative thread arrays and thread identifier values to determine processing behavior
US20070260841A1 (en) 2006-05-02 2007-11-08 Hampel Craig E Memory module with reduced access granularity
JP5076418B2 (ja) * 2006-09-19 2012-11-21 ソニー株式会社 共有メモリ装置
US8819099B2 (en) * 2006-09-26 2014-08-26 Qualcomm Incorporated Software implementation of matrix inversion in a wireless communication system
WO2008060948A2 (en) * 2006-11-10 2008-05-22 Sandbridge Technologies, Inc. Method and system for parallelization of pipelined computations
US7596668B2 (en) * 2007-02-20 2009-09-29 International Business Machines Corporation Method, system and program product for associating threads within non-related processes based on memory paging behaviors
EP2210171A1 (en) * 2007-11-05 2010-07-28 Sandbridge Technologies, Inc. Method of encoding register instruction fields
US8539188B2 (en) * 2008-01-30 2013-09-17 Qualcomm Incorporated Method for enabling multi-processor synchronization
KR20100133964A (ko) * 2008-03-13 2010-12-22 아스펜 액퀴지션 코포레이션 유효 어레이를 비활성화함으로써 전력을 절약하기 위한 방법
WO2010017263A1 (en) 2008-08-06 2010-02-11 Sandbridge Technologies, Inc. Haltable and restartable dma engine
CN101739242B (zh) * 2009-11-27 2013-07-31 深圳中微电科技有限公司 一种流数据处理方法及流处理器
CN102141905B (zh) * 2010-01-29 2015-02-25 上海芯豪微电子有限公司 一种处理器体系结构
US9268719B2 (en) 2011-08-05 2016-02-23 Rambus Inc. Memory signal buffers and modules supporting variable access granularity
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CN104461961B (zh) * 2014-11-20 2018-02-27 上海宝存信息科技有限公司 一种多核多线程的闪存装置及闪存控制方法
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Also Published As

Publication number Publication date
KR20050046819A (ko) 2005-05-18
AU2003282511A8 (en) 2004-05-04
ES2758623T3 (es) 2020-05-06
WO2004034218A2 (en) 2004-04-22
JP2006502507A (ja) 2006-01-19
EP1550032B1 (en) 2019-09-11
US20040073772A1 (en) 2004-04-15
CN1708747A (zh) 2005-12-14
KR100980536B1 (ko) 2010-09-06
EP1550032A4 (en) 2008-03-12
US6925643B2 (en) 2005-08-02
WO2004034218A3 (en) 2004-06-03
CN1332303C (zh) 2007-08-15
EP1550032A2 (en) 2005-07-06
AU2003282511A1 (en) 2004-05-04

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