JP2006352169A - Solid-state imaging device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high image-quality solid-state imaging device in which the generation of a leakage current and noise during operation is reduced, and a method of manufacturing the same. <P>SOLUTION: A MOS imaging device 1 is constituted by forming an imaging region 10 and a driving circuit region 20 on a p-type silicon substrate (hereafter referred to as "Si substrate") 31. The imaging region 10 comprises six pixels 11-16 arranged in two rows by three columns. The driving circuit region 20 comprises a timing generation circuit 21, a vertical shift register 22, a horizontal shift register 23, a pixel selection circuit 24, and the like. All of the transistors in all pixels 11-16 in the imaging region 10 and in all circuits 21-24 of the driving circuit region 20 are of n-channel MOS types. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device used for a digital camera or the like and a manufacturing method thereof.

  Solid-state imaging devices, especially MOS (Metal Oxide Semiconductor) type imaging devices, generate a signal charge by photoelectrically converting the input light in each of the two-dimensionally arranged pixels on the substrate. In this device, the signal charge is amplified and read out by an amplifier circuit provided for each pixel. Such a MOS type imaging device can be driven with low voltage and low power consumption, and the so-called one-chip configuration in which the imaging region and the drive circuit region for driving the imaging region can be formed on one substrate. Since it is possible, it has attracted attention as an image input device for portable devices.

  A conventional MOS type imaging device is formed by forming an imaging region and a driving circuit region on a single silicon substrate (hereinafter referred to as “Si substrate”) based on a complementary metal oxide semiconductor (CMOS) process technology. Yes. In the CMOS process technology used for the MOS type imaging device, development and design of the device and the process are performed mainly for the purpose of increasing the driving speed.

  The imaging region is composed of a plurality of pixels arranged two-dimensionally (for example, in a matrix) on the Si substrate. Each pixel-corresponding region includes a photodiode portion that converts received light into signal charges, a MOS transistor portion that performs a switching function, a MOS transistor portion that amplifies a signal, and the like. Signal charges generated by photoelectric conversion in the photodiode section are amplified in each pixel and read out in units of pixels by a switching operation based on an instruction signal from a vertical shift register section and a horizontal shift register section in a drive circuit area described later. It is supposed to be.

  All the MOS type transistor portions in the imaging region are formed of an n-channel MOS type. On the other hand, the drive circuit region is roughly divided into four main circuit parts, a timing generation circuit part, a vertical shift register part, a horizontal shift register part, and a pixel selection circuit part, and includes an n-channel MOS transistor part and a p-channel part. The MOS type transistor part is formed with a CMOS type structure in which both the MOS type transistor part is combined.

The n-channel MOS transistor portion in the imaging region and the n-channel MOS transistor portion in the drive circuit region are normally formed with the same structure.
A circuit configuration of the horizontal shift register unit will be described with reference to FIG. In general, the horizontal shift register unit has a number of stages corresponding to the number of columns of pixels. In FIG. 10, only the first stage part is extracted and shown.

  As shown in FIG. 10, the first stage 50 of the horizontal shift register unit is composed of four switch parts 51, 54, 55, 58 and four inverter parts 52, 53, 56, 57. Each of the switch portions 51, 54, 55, 58 and the inverter portions 52, 53, 56, 57 is configured by combining one n-channel MOS type transistor portion and one p-channel MOS type transistor portion.

The inverter part 52 and the inverter part 53 are connected in series. The inverter parts 52 and 53 connected in series are connected in parallel with the switch part 54. The switch portion 51 is connected in series with the inverter portions 52 and 53 and the switch portion 54 having the above connection relationship.
The switch portions 55 and 58 and the inverter portions 56 and 57 also have the same connection relationship as described above.

  The first stage 50 of the horizontal shift register unit configured as described above is driven by the start pulse VST being applied to the switch unit 51, and the clock pulse CK1 and its inverted pulse CK2 are applied twice each time. The first-stage operation pulse is output to the pixel selection circuit unit. Thereafter, the second and third operation pulses are sequentially output from the horizontal shift register unit.

An element structure of a transistor portion (CMOS type) in the first stage 50 of the horizontal shift register portion will be described with reference to FIG. FIG. 11 is a cross-sectional view showing an element structure in the switch portions 51, 54, 55, 58 or the inverter portions 52, 53, 56, 57. As shown in FIG.
As shown in FIG. 11, an n-type well 62 and a p-type well 63 are formed from the surface of the Si substrate 61 to the inside in a state of being spaced apart from each other.

A gate insulating film 64 is formed on the surfaces of the n-type well 62, the p-type well 63 and the Si substrate 61. Gate electrodes 67 and 70 are formed at substantially central portions on the surface of the gate insulating film 64, respectively.
On the other hand, in each of the wells 62 and 63, source regions 65 and 68 and drain regions 66 and 69 are formed from the boundary with the gate insulating film 64 inward.

In this manner, in the Si substrate 61, a p-channel MOS type transistor portion is formed with three electrodes of the gate electrode 67, the source region 65, and the drain region 66, and the gate electrode 70, the source region 68, and the drain region are formed. An n-channel MOS transistor portion is formed with three poles 69.
The MOS type imaging device having the CMOS type structure is formed through the steps S1) to S15) for the Si substrate 61 as shown below.

S1) A resist for forming the n-type well 62 is formed.
S2) An n-type well 62 is formed.
S3) The resist for forming the n-type well 62 is removed.
S4) A resist for forming the p-type well 63 is formed.
S5) A p-type well 63 is formed.

S6) The resist for forming the p-type well 63 is removed.
S7) A gate insulating film 64 is formed.
S8) Gate electrodes 67 and 70 are formed.
S9) A resist for forming the source region 65 / drain region 66 for the n-channel MOS is formed.

S10) Source region 65 / drain region 66 for n-channel MOS are formed.
S11) The resist for forming the source region 65 / drain region 66 for the n-channel MOS is removed.
S12) A resist for forming the source region 68 / drain region 69 for the p-channel MOS is formed.

S13) Source region 68 / drain region 69 for p-channel MOS are formed.
S14) The resist for forming the source region 68 / drain region 69 for the p-channel MOS is removed.
S15) A photodiode portion is formed.

  However, the conventional MOS type imaging device manufactured on the basis of the CMOS process technology as described above causes a leakage current in the photodiode portion in the imaging region and deterioration of characteristics in the amplification portion during driving. In other words, noise may be generated. When noise occurs in the imaging region in this way, the noise is amplified together with the signal charge and output together with the problem that the image quality is degraded.

  It is an object of the present invention to provide a high-quality solid-state imaging device and a method for manufacturing the same that generate little leakage current during driving and reduce noise.

  In order to achieve the above object, a solid-state imaging device according to the present invention includes an imaging region having an amplification type unit pixel that amplifies a signal charge photoelectrically converted by a photodiode unit, and at least a vertical shift register and a horizontal shift. Solid-state imaging having a register, a drive circuit area for driving an element unit in each amplification type unit pixel in the imaging area on one semiconductor substrate, and having transistor function parts in both the imaging area and the driving circuit area The device is characterized in that all transistor function portions in both the imaging region and the drive circuit region are formed of the same conductivity type.

The amplifying unit pixel is a pixel formed by combining a photodiode portion that photoelectrically converts light input to the unit equivalent region and an amplifying portion that amplifies the photodiode portion.
Such a solid-state imaging device can be incorporated in a camera or the like as an image input sensor, and can obtain a high-quality image.
According to another aspect of the present invention, there is provided a method for manufacturing a solid-state imaging device, wherein a semiconductor substrate is formed with an imaging region including a photodiode unit that converts input light into signal electrification and an amplification unit that amplifies signal charge; Including at least a vertical shift register and a horizontal shift register on the same semiconductor substrate, and forming a drive circuit region for driving the imaging region. In both steps of forming the imaging region and the drive circuit region, The MOS transistor functional part is formed of the same conductivity type.

  In the solid-state imaging device according to the present invention, since all the transistor function units in both the imaging region and the drive circuit region are formed of the same conductivity type, the solid-state imaging device manufactured using the above-described conventional CMOS process technology As compared with the above, all the transistor function parts in both regions can be formed with the number of processes of about ½, and damage to the imaging region in the process of forming the transistor function parts can be reduced.

Therefore, in the solid-state imaging device according to the present invention, the noise generation in the amplifying unit and the leakage current in the photodiode unit due to the damage received in the imaging region are small, and the image quality caused by these is small. Have
In the solid-state imaging device according to the present invention, it is desirable that all transistor function units in both the imaging region and the drive circuit region are formed of an n-channel MOS type because the device can be driven at high speed.

The drive circuit region of the solid-state imaging device according to the present invention has a dynamic circuit portion including a capacitor function portion that accumulates charges and a transistor function portion that performs a switching function, thereby reducing power consumption. It is desirable because it can be planned.
Usually, in a solid-state imaging device, a plurality of amplification type unit pixels are formed in an imaging region, and as a method of reading signal charges from the plurality of amplification type unit pixels, a scan readout method, a random access method, an edge detection method, etc. There is. In particular, in the solid-state imaging device, a pixel selection circuit part for selecting one amplification type unit pixel from a plurality of amplification type unit pixels is provided in the drive circuit area, and the horizontal shift register selects the pixel selection circuit part It is desirable to employ a configuration in which an instruction signal is output from the viewpoint that scan reading can be performed at high speed.

In the imaging region of the solid-state imaging device according to the present invention, a transistor function unit that performs a switching function based on a signal from the drive circuit region is formed, and the signal charge photoelectrically converted when the transistor function unit is in an ON state It is desirable from the viewpoint of reducing power consumption.
In addition, in the case where the gate length in the transistor function portion is as small as 0.6 μm or less, the short channel effect due to the increase of the heat application process is accelerated when the conventional CMOS process technology is manufactured, and the amplification portion at the time of resist removal Alternatively, damage to the photodiode portion causes an increase in leakage current in the photodiode portion during driving and an increase in noise in the amplification portion.

  On the other hand, when all the transistor function parts in both the above regions are formed with the same conductivity type as in the solid-state imaging device of the present invention, the heat application process is reduced and the number of times of resist removal during the manufacturing process. The increase in leakage current at the time of driving is small due to the reduction of the above. Therefore, the solid-state imaging device of the present invention has an advantage even when a fine transistor function unit having a gate length of 0.6 μm or less (design rule of 0.6 μm or less) is provided.

  In a conventional solid-state imaging device, a gate electrode of a transistor function part is generally formed on a semiconductor substrate with an insulating film interposed therebetween. When the thickness of the gate insulating film is 20 (nm) or less In addition, the generation of leakage current between the gate insulating film and the semiconductor substrate increases rapidly. Even in the case of having such a thin gate insulating film, if the transistor portion is formed with the same conductivity type as in the solid-state imaging device of the present invention, the generation of leakage current is small.

A solid-state imaging device in which a transistor portion is formed with the same conductivity type even when an insulating film functioning as a capacitor has a thickness of 1 (nm) to 20 (nm) between the gate electrode and the semiconductor substrate. Then, the occurrence of leakage current can be reduced.
In the method for manufacturing a solid-state imaging device according to the present invention, all the transistor function portions in both the imaging region and the drive circuit region can be formed only through either the n-channel MOS type or the p-channel MOS type forming process. In addition, it is possible to reduce damage that the photodiode portion and the amplification portion in the imaging region receive during the manufacturing process. Therefore, the solid-state imaging device manufactured using this manufacturing method has little damage in the imaging region that is received during the manufacturing process, and causes a leakage current in the photodiode portion caused by this during driving and a characteristic in the amplification portion. Noise generation due to a decrease or the like can be suppressed.

Therefore, in the manufacturing method of the solid-state imaging device according to the present invention, it is possible to reduce damage to those that causes generation of leakage current in the photodiode portion during driving and deterioration of characteristics in the amplification portion. Sometimes a high-quality solid-state imaging device with little noise can be manufactured.
In the method for manufacturing a solid-state imaging device according to the present invention, it is desirable that the MOS transistor function portions in the imaging region and the drive circuit region are formed of an n-channel MOS type in order to drive the solid-state imaging device at high speed.

In the method for manufacturing a solid-state imaging device according to the present invention, even when the MOS transistor portion is formed with a fine structure with a gate length of 0.6 μm or less (design rule of 0.6 μm or less), Since generation of leakage current can be suppressed, noise can be reduced.
In the method of manufacturing a solid-state imaging device according to the present invention, the MOS transistor portion is formed with the same conductivity type even when the gate insulating film in the MOS transistor portion is formed with a thin film of 20 nm or less. By doing so, it is possible to suppress the occurrence of leakage current during driving, which is particularly effective.

  Furthermore, in the method for manufacturing a solid-state imaging device according to the present invention, the insulating film functioning as a capacitor is formed as a thin film having a thickness of 20 nm or less between the gate electrode of the MOS transistor and the semiconductor substrate. Also in this case, the generation of a leakage current during driving can be suppressed, and thus an effect is particularly obtained.

(Configuration of MOS imaging device 1)
A MOS type imaging device as the best mode for carrying out the present invention will be described with reference to FIGS. FIG. 1 is a plan (block) diagram showing the overall configuration of a MOS type imaging device 1 for image input of a digital camera according to this embodiment. FIG. 2 is a circuit diagram of a circuit (hereinafter simply referred to as “pixel”) 11 in an amplification unit pixel equivalent area in the MOS type imaging device 1, and FIG. 3 is a circuit diagram of the horizontal shift register unit 23.

  As shown in FIG. 1, the MOS imaging device 1 has an imaging region 10 and a drive circuit region 20 formed on a p-type silicon substrate (hereinafter referred to as “Si substrate”) 31. The circuits in each part of the imaging region 10 and the drive circuit region 20 are electrically connected by a wiring pattern formed on the Si substrate 31. In FIG. 1, the circuits of the regions 10 and 20 are shown as blocks. However, the actual Si substrate 31 is formed by densely forming the functional element portions provided in both the regions 10 and 20. Yes.

The imaging region 10 has six pixels 11 to 16 arranged in 2 rows × 3 columns, and the drive circuit region 20 includes a timing generation circuit unit 21, a vertical shift register unit 22, a horizontal shift register unit 23, and The pixel selection circuit unit 24 and the like are included.
Among them, the vertical shift register unit 22 and the horizontal shift register unit 23 are both dynamic circuit units, and are sequentially applied to the pixels 11 to 16 or the pixel selection circuit unit 24 in accordance with a signal from the timing generation circuit unit 21. A drive (switching) pulse is output.

In addition, the pixel selection circuit section 24 includes three switching element sections (not shown), one corresponding to the pixels 11 and 12, one corresponding to the pixels 13 and 14, and one corresponding to the pixels 15 and 16. And are sequentially turned on in response to a pulse from the horizontal shift register section 23.
Each of the six pixels 11 to 16 in the imaging region 10 is an amplifying unit pixel having an amplifying unit, and the photoelectric conversion signal charge is selected by the vertical shift register unit 22 and a pixel selecting circuit. The pixel 24 is read from the pixel intersecting with the column in which the unit 24 is in the ON state.

The timing generation circuit unit 21 is a circuit unit that applies a power supply voltage, a timing pulse, and the like to the vertical shift register unit 22 and the horizontal shift register unit 23.
(Circuit configuration of each pixel in the imaging region 10)
The six pixels 11 to 16 in the imaging region 10 are amplification type unit pixels and have the same circuit configuration in the corresponding region. Below, the pixel 11 is taken as an example, and a circuit configuration provided therein will be described with reference to FIG.

  As shown in FIG. 2, the pixel 11 includes a photodiode portion 111 and four transistor portions (a transfer transistor portion 112, a reset transistor portion 113, an amplification transistor portion 114, a selection transistor portion 115) and the like on a Si substrate. 31 is formed and configured. Of these, the four transistor portions 112 to 115 are all formed of an n-channel MOS type.

As shown in FIG. 2, the photodiode unit 111 is an element unit having a photoelectric conversion function that generates a signal charge proportional to the intensity of input light, one end of which is grounded and the other end is transferred. The transistor part 112 is connected to the source.
The transfer transistor unit 112 is an element unit for transferring the signal charge generated in the photodiode 111 to its own drain as a detection unit, and includes a gate of the amplification transistor unit 114 and a reset transistor unit 113 at the drain. Is connected to the source.

The reset transistor unit 113 is an element unit for resetting the signal charges accumulated in the drain of the transfer transistor unit 112 at predetermined time intervals, and the drain is electrically connected to the power supply voltage VDD. ing.
The amplification transistor unit 114 is an element that outputs the signal charge accumulated in the drain of the transfer transistor unit 112 when the selection transistor unit 115 is turned on according to a signal from the vertical shift register 22 or the like. The drain is connected to the power supply voltage VDD, and the source is connected to the drain of the selection transistor 115.

The source of the selection transistor unit 115 is connected to the pixel selection circuit unit 24.
The gates of the transfer transistor unit 112, the reset transistor unit 113, and the selection transistor unit 115 are connected to three signal lines from the vertical shift register unit 22, respectively.
Among the four transistor portions 112 to 115, the amplifying transistor portion 114 performs a signal amplifying function of signal charges in the pixel 11, and the other transistor portions 112, 113, and 115 perform a switching function.

  In the pixel 11 having the circuit configuration as described above, signal charges generated by photoelectric conversion in the photodiode unit 111 are accumulated in the photodiode unit 111. The accumulated signal charge is stored in the drain region of the transfer transistor unit 112 when the transfer transistor unit 112 is turned on based on the instruction signal from the vertical shift register unit 22. Then, the signal is transferred to (detection unit) and output to the gate of the amplification transistor unit 114.

The amplifying transistor unit 114 to which the signal charge is input to the gate amplifies the input signal charge.
The selection transistor unit 115 performs an ON / OFF operation based on an instruction signal from the vertical shift register unit 22.
The resetting transistor unit 113 discharges the signal charge accumulated in the detection unit at regular intervals, and resets the accumulation state of the signal charge in the detection unit.

In the imaging region 10 of the MOS type imaging device 1, the photoelectrically converted signal charges are accumulated for each of the pixels 11 to 16, and each pixel has an internal signal based on instruction signals from the vertical shift register unit 22 and the horizontal shift register unit 23. The signal charge is amplified in one pixel selected by the selection transistor portion and the pixel selection circuit portion 24, and the signal charge is output.
(Circuit configuration of the horizontal shift register unit 23)
Next, the circuit configuration of the horizontal shift register unit 23 among the circuits 21 to 24 in the drive circuit region 20 will be described with reference to FIG.

The horizontal shift register unit 23 shown in FIG. 3 is different from the conventional horizontal shift register unit (first stage) 50 shown in FIG. 10 in that all transistor units are formed of an n-channel MOS type.
As shown in FIG. 3, the horizontal shift register unit 23 includes three first-stage parts 231, second-stage parts 232, and third-stage parts 233 so as to correspond to the number of columns of the pixels 11 to 16 in the imaging region 10. It consists of two parts. Since the first stage portion 231, the second stage portion 232, and the third stage portion 233 have the same circuit configuration, only the circuit configuration of the first stage portion 231 will be described below as an example. As shown in FIG. 3, the first stage portion 231 of the horizontal shift register unit 23 includes four transistor units 2311, 2312, 2316, and 2317 and one boost trap capacitor unit 2313. Of these, the four transistor portions 2311, 2312, 2316, and 2317 are all formed of an n-channel MOS type similarly to the four transistor portions 112 to 115 in the imaging region 10.

  The charge transistor unit 2311 is an enhancement type n-channel MOS type device unit for charging the bootstrap capacitor unit 2313, the gate is connected to the signal line for the start pulse VST, and the drain is connected to the power supply voltage VDD. The source is connected to one end (plus side) of the bootstrap capacitor unit 2313. Here, the start pulse VST and the power supply voltage VDD are applied from the timing generation circuit unit 21. The same applies to a drive pulse V1 described later.

The source of the charging transistor portion 2311 is connected to the node 2315 connected to the gate of the output transistor portion 2312 and the drain of the discharging transistor portion 2316.
As described above, the output transistor portion 2312 has a gate connected to the source of the charging transistor portion 2311 through the node 2315, a drain connected to the signal line for the drive pulse V1, and a source connected to the other end of the boost trap capacitor portion 2313 ( It is connected to the negative side. The source of the output transistor portion 2312 is also connected to the drain of the discharge transistor portion 2317.

An output node 2314 is provided between the negative side of the bootstrap capacitor unit 2313 and the source of the output transistor unit 2312, and is connected to the imaging region 10.
The two discharge transistor portions 2316 and 2317 have their sources grounded and their gates connected to the output node 2324 of the second stage portion 232.

The drain of the output transistor portion 2322 in the second stage portion 232 is connected to the signal line for the drive pulse V2.
Other circuit configurations in the second stage portion 232 are the same as those in the first stage portion 231.
The third stage portion 233 is the same as the others except that the drain of the output transistor portion 2332 is connected to the signal line for the drive pulse V1.

  As described above, the horizontal shift register unit 23 in which the transistor unit is formed only by the n-channel MOS type includes four transistor units and one capacitor unit per stage. The horizontal shift register unit having the conventional CMOS structure shown in FIG. 11 includes 16 transistor units per stage, whereas the functional element unit (transistor unit and capacitor unit) included in the horizontal shift register unit 23. The number of is a total of five places and is very small.

Therefore, the horizontal shift register unit 23 is designed by designing a circuit so that the number of functional element units that need to be formed can be reduced as compared with the CMOS type structure of FIG. An equivalent or higher driving speed can be obtained.
(Driving of horizontal shift register unit 23)
The driving of the horizontal shift register unit 23 having the above circuit configuration will be described with reference to FIG. FIG. 4 is a drive timing chart of the horizontal shift register unit 23.

  As shown in FIG. 4, in the horizontal shift register unit 23, when a start pulse VST (voltage 5 (V)) is applied to the gate of the charging transistor unit 2311 at time t0, the charging transistor unit 2311 is turned on. It becomes. When the charging transistor portion 2311 is turned on, a voltage is applied to the gate of the output transistor portion 2312, and the output transistor portion 2312 is also turned on. At this time, the drive pulse V1 input to the drain of the output transistor portion 2312 is a ground potential, and the same potential difference as the power supply voltage VDD is generated at both ends of the boost trap capacitor portion 2313. Thereby, the bootstrap capacitor unit 2313 is charged until the voltage VDD (3 (V)) is reached.

  Next, at time t1, when the drive pulse V1 rises to 3 (V) and is input to the drain of the output transistor portion 2312, the voltage 3 (V) of the drive pulse V1 is boosted to the gate of the output transistor portion 2312. A high voltage HB1 (6 (V)) obtained by adding the voltage 3 (V) across the strap capacitor 2313 is applied as the pulse VN11. As a result, the operation pulse VN12 having an amplitude of 3 (V) is output from the output node 2314 to the switching element unit corresponding to the pixels 11 and 12 in the first column in the pixel selection circuit unit 24 as the output pulse Out1. Will be.

  At the same time, the pulse VN11 of the high voltage HB1 at the node 2315 is also applied to the gate of the charging transistor portion 2321 in the second stage 232, whereby the charging transistor portion 2321 is turned on. When the charging transistor portion 2321 of the second stage 232 is turned on, the output transistor portion 2322 is also turned on. At this time, since the drive pulse V2 is at the ground potential, the bootstrap capacitor unit 2323 is charged to the power supply voltage VDD (3 (V)).

  In the case of time t2, when the driving pulse V2 rises to 3 (V) and is input to the drain of the output transistor portion 2322, the voltage 3 (V) of the driving pulse V2 and the boost trap are applied to the gate of the output transistor portion 2322. A high voltage HB2 (6 (V)) obtained by adding the voltage 3 (V) across the capacitor portion 2323 is applied as the pulse VN21. As a result, the operation pulse VN22 having an amplitude of 3 (V) is output from the output node 2324 to the switching element unit corresponding to the pixels 13 and 14 in the second column in the pixel selection circuit unit 24 as the output pulse Out2. Will be.

At the same time, the pulse VN21 of the high voltage HB2 at the node 2315 is also applied to the gate of the charging transistor portion 2331 in the third stage 233, and the same driving as described above is performed, and at time t3, the output node 2334 receives 3 (V). An operation pulse VN32 having an amplitude is output as an output pulse Out3 to the switching element unit corresponding to the pixels 15 and 16 in the third column in the pixel selection circuit unit 24. Also, the operation from the output node 2324 in the second stage 232 At the same time, the pulse VN22 turns on the discharge transistor portions 2316 and 2317 in the first stage 231, and the charge capacity of the bootstrap capacitor portion 2313 is discharged.

Note that the discharge of the bootstrap capacitor unit 2313 may be performed using the drive pulse V2.
As described above, in the horizontal shift register unit 23 in which all the transistor units in the constituent elements are formed by the n-channel MOS type, the number of transistor units is smaller than that of the horizontal shift register unit 50 formed by the conventional CMOS process of FIG. It is possible to generate and sequentially output the output pulses Out1 to Out3 with no voltage drop.

Therefore, it can be said that the horizontal shift register unit 23 has the same performance including the driving speed as the horizontal shift register unit 50 manufactured using the CMOS process technology of FIG. 10 including the driving speed.
In addition to the horizontal shift register unit 23, the drive circuit region 20 includes a timing generation circuit unit 21, a vertical shift register unit 22, a pixel selection circuit unit 24, and the like. It is possible to achieve the same performance as each circuit unit designed and manufactured based on process technology.

(Element structure of transistor part in MOS type imaging device 1)
The MOS type imaging device 1 according to the embodiment of the present invention is characterized in that all transistor parts in both the imaging region 10 and the drive circuit region 20 are formed of an n-channel MOS type. The element structure of the transistor portion will be described with reference to FIG.
As shown in FIG. 5, a gate insulating film 32 made of insulating SiO ₂ is formed on the surface of the Si substrate 31. The film thickness of the gate insulating film 32 is set, for example, within a range of 1 (nm) to 20 (nm).

The Si substrate 31 has p-type characteristics.
In a region from the boundary between the Si substrate 31 and the gate insulating film 32 to the inside of the Si substrate 31, a source region 33 and a drain region 34 are formed in a state of being spaced apart from each other.
A gate electrode 35 made of polysilicon is formed in a portion corresponding to the gap between the source region 33 and the drain region 34 on the surface of the gate insulating film 32.

As shown in FIG. 5, in the Si substrate 31, the gate electrode 35, the source region 33, and the drain region 34 form three poles, and the surface layer of the Si substrate immediately below the gate electrode 35 forms a channel. The part is composed.
(Method for forming transistor portion)
A method for forming a transistor portion in the MOS imaging device 1 will be described with reference to FIGS.

By processing the Si substrate 31 shown in FIG. 6A in an oxidizing atmosphere, the gate insulating film 32 as an insulating film is made of SiO ₂ as shown in FIG. Thus, the Si substrate 31 formed in (1) is obtained.
Polysilicon (polycrystalline silicon) is deposited in a predetermined region on the surface of the gate insulating film 32 to form a gate electrode 35 as shown in FIG. For example, the LPCVD method can be used to form the gate electrode 35.

As shown in FIG. 6D, a resist film 400 is formed with a desired pattern on the surface of the gate insulating film 32 and at a predetermined interval from both sides of the gate electrode 35.
As shown in FIG. 7A, arsenic (As) and phosphorus (P) ions are implanted from the surface side of the gate insulating film 32 into the Si substrate 31 of FIG. By activation, the source region 33 and the drain region 34 are formed. At the time of ion implantation, a so-called self-alignment method in which the gate electrode 35 also serves as a resist is adopted, so that the positions of the source region 33 and the drain region 34 with respect to the gate electrode 35 are accurately determined.

Finally, the resist 400 is removed by ashing in oxygen plasma, and a transistor portion is formed on the Si substrate 31 as shown in FIG.
Note that the gate insulating film 32 between the gate electrode 35 and the Si substrate 31 in the transistor portion also has a function as a capacitor.
(Advantage of forming all transistor parts in n-channel MOS type)
As a result of studying the cause of the deterioration in image quality during driving, the present inventor has found that in the manufacturing method using the above-described CMOS process technology, the damage applied to the formation region or the planned region of the amplifying part and the photodiode during the process Has found out that it has an effect when driving. Specifically, in the above-described conventional manufacturing method, the surface portion of the Si substrate 61 where the transistor portion in the imaging region is to be formed is damaged by performing two steps of S3) and S6) for removing the resist. Receive. This damage may cause a defect below the gate electrodes 67 and 70 of the transistor portion, which may cause deterioration of characteristics such as an increase in 1 / f noise in the amplification portion.

  In addition, after the formation of the gate electrodes 67 and 70 in the imaging region, two resist removal steps S11) and S14) are performed, and the gate insulating films 64 on both sides of the gate electrodes 67 and 70 in the imaging region. May be damaged. In this case, at the time of driving, a leak current is easily generated between the gate electrodes 67 and 70, the source regions 65 and 68, and the drain regions 66 and 69, leading to an increase in noise in the amplifying unit. In particular, when the gate insulating film 32 is a thin film having a thickness of 20 (nm) or less, the generation of leakage current increases.

  Furthermore, since the surface of the Si substrate 61 in the region where the photodiode portion is to be formed is damaged through four steps of removing the resist in S3), S6), S11), and S14), This may cause leakage current during driving. This leakage current is added as noise to the signal generated by the photoelectric conversion, resulting in a decrease in image quality due to an increase in white scratches.

As described above, the MOS type imaging device manufactured by using the conventional manufacturing method causes the leakage current in the photodiode portion and the noise in the amplification portion due to the imaging region being damaged during the manufacturing process. The image quality deteriorates due to an increase in image quality.
On the other hand, in the method for manufacturing the MOS type imaging device 1 shown in FIGS. 6 and 7, the number of resist removal times during the process of the transistor portion is one. Compared with the conventional manufacturing method described above, in the manufacturing method of the MOS type imaging device 1, the p-type Si substrate 31 is used, so there is no resist removal process S3) and S6) related to well formation, and the source region The resist removal process relating to the formation of 33 and the drain region 34 may be performed only once in S11).

  Thus, in the manufacturing method according to the present embodiment, the 1 / f noise of the amplification unit due to the lower defect of the gate electrode 35 is increased, and the amplification unit due to damage of the gate insulating film 32 on both side portions of the gate electrode 35 is used. The generation of leakage current and the generation of leakage current in the photodiode portion due to defects in the Si substrate 31 below the photodiode portion are suppressed. In particular, even when the gate insulating film 32 is a thin film having a thickness of 20 (nm) or less, the generation of leakage current can be greatly suppressed, and the MOS type imaging in which all the transistor portions are formed of the n-channel MOS type. It can be confirmed that the device 1 has an advantage.

Therefore, in the manufacturing method according to the present embodiment in which all the transistor portions in both the imaging region 10 and the drive circuit region 20 are formed by the n-channel MOS type, damage to the imaging region 10 during the process can be reduced. A high-quality MOS imaging device 1 can be manufactured.
(Comparative experiment)
As described above, the MOS type imaging device 1 in which all the transistor portions in both the imaging region 10 and the drive circuit region 20 are formed of the n-channel MOS type, and the conventional CMOS type imaging manufactured using the CMOS process technology. Compare the performance with the equipment.

The number of leaked electrons in the photodiode portion is detected by reading electrons generated in the photodiode portion without reading light to the gate of the amplification transistor portion (reading by the transfer transistor portion), and the result is shown in FIG. .
As shown in FIG. 8, the number of leaked electrons in the photodiode portion is 0.82 in the n-channel MOS image pickup device when the conventional CMOS image pickup device is 1, which is reduced by 18%. Yes.

Next, the S / N ratio of the amplifying unit (amplifying transistor unit) was measured with a S / N measuring device of a camera manufactured using a solid-state imaging device, and the result is shown in FIG.
As shown in FIG. 9, the S / N ratio in the amplifying unit is 54 dB for the conventional MOS image pickup device, 57 dB for the n-channel MOS image pickup device, and is excellent at 3 dB.
As described above, in the MOS imaging device 1 in which all the transistor parts in the Si substrate 31 are formed of the n-channel MOS type, the photodiode part and the amplifying transistor part are damaged during the manufacturing process as described above. Therefore, both the characteristics of the number of leaked electrons in the photodiode portion and the S / N ratio of the amplifying portion are superior to the conventional CMOS type imaging device.

  Therefore, as can be seen from the above comparison results, the MOS imaging device 1 according to the present embodiment is formed by forming all the transistor portions in both the imaging region 10 and the drive circuit region 20 in the n-channel MOS type. Since there is little occurrence of leakage current in the photodiode portion during driving and little occurrence of noise in the amplification transistor portion, it has high image quality characteristics.

(Other matters)
The embodiment of the present invention is an example used for explaining the features and advantages of the present invention. Therefore, the present invention is not limited to this except for the essential part in which all transistor parts in the device are formed of an n-channel MOS type.
For example, the number of pixels in the imaging region and the arrangement thereof may be other than the above 2 rows × 3 columns, and the circuit unit provided in the drive circuit region may be provided in addition to the circuit units 21-24.
The circuit diagrams shown in FIGS. 2 and 3 are also examples, and a circuit configuration according to the purpose of use of the device other than this circuit configuration may be adopted.

Further, in the device, an element isolation portion made of a dispersed oxide film or the like may be formed in a portion between adjacent transistor portions. However, in the manufacturing process, it is necessary to prevent damage to the photodiode, the amplifying transistor, and the like in consideration of noise during driving.
In the above description, a Si substrate having p-type characteristics is used. However, a substrate in which a p-type well is formed in a necessary portion of the Si substrate may be used, or SOI (Silicon on Insulator) may be used. In this case, the isolation between the functional units and between the circuit units can be improved, which is effective.

It is a top view which shows the MOS type imaging device concerning embodiment of this invention. 2 is a circuit diagram of a pixel 11 in an imaging region 10. FIG. 3 is a circuit diagram of a horizontal shift register unit 23. FIG. 4 is an operation timing chart of the horizontal shift register unit 23. 3 is a cross-sectional view showing an element structure of a transistor portion in a horizontal shift register portion 23. FIG. It is a manufacturing process figure of an n channel MOS type transistor part. It is a manufacturing process figure of an n channel MOS type transistor part. It is a comparison characteristic figure which shows the relationship between the conductivity type of a transistor part, and the number of leak electrons in a photodiode. It is a comparison characteristic figure which shows the relationship between the conductivity type of a transistor part, and S / N ratio in the amplifier in a pixel. It is a circuit diagram of the conventional horizontal shift register part. It is sectional drawing which shows the element structure of the transistor part in the conventional horizontal shift register part.

Explanation of symbols

1. MOS type imaging device 10. Imaging region 11-16. Pixel 20. Drive circuit area 21. Timing generation circuit section 22. Vertical shift register section 23. Horizontal shift register section 24. Pixel selection circuit unit 31. Silicon substrate 32. Gate insulating film 33. Source region 34. Drain region 35. Gate electrode 111. Photodiode section 112. Transfer transistor portion 113. Reset transistor section 114. Amplifying transistor section 115. Selection transistor section 400. Resist films 2311, 2321, 2331. Charging transistor portion 2312, 2322, 2332. Output transistor portion 2316, 2317, 2326, 2327, 2336, 2337. Discharge transistor part 2313, 2323, 2333. Bootstrap capacitor part

Claims (6)

Forming on a semiconductor substrate an imaging region comprising a photodiode portion that converts input light into signal charge and an amplification portion that amplifies the signal charge;
Forming at least a vertical shift register and a horizontal shift register on the semiconductor substrate, and forming a drive circuit region for driving the imaging region;
In both steps of forming the imaging device and the drive circuit region, all the MOS transistor parts are formed only by the formation process of the same conductivity type,
The formation process of the same conductivity type includes a step of forming a gate insulating film on a surface of a first conductivity type semiconductor region, a step of forming a gate electrode on the gate insulating film, Forming a second conductivity type source region and drain region formed in a semiconductor region and positioned with respect to the gate electrode. A method of manufacturing a solid-state imaging device, comprising: . 2. The method of manufacturing a solid-state imaging device according to claim 1, wherein the formation process of the same conductivity type has a reduced number of times of resist removal during the manufacturing process as compared to a CMOS type formation process. The method for manufacturing a solid-state imaging device according to claim 2, wherein the number of resist removal times in the step of forming the source region and the drain region is one. The first conductivity type semiconductor region is either the first conductivity type semiconductor substrate or the first conductivity type well region formed in the second conductivity type semiconductor substrate. Item 3. A method for manufacturing a solid-state imaging device according to Item 2. The method of manufacturing a solid-state imaging device according to claim 2, wherein the step of forming the source region and the drain region is determined by a self-alignment method with respect to the gate electrode. An imaging region having an amplification unit pixel that amplifies the signal charge photoelectrically converted by the photodiode unit, and at least a vertical shift register and a horizontal shift register, and an element in each amplification unit pixel of the imaging region In a solid-state imaging device comprising a driving circuit region for driving the unit on one semiconductor substrate, and having a MOS type transistor unit in both the imaging region and the driving circuit region,
All the MOS transistor parts in both the imaging region and the drive circuit region are formed of the same conductivity type, and a gate insulating film formed on the surface of the first conductivity type semiconductor region; and the gate A gate electrode formed on the insulating film; and a second conductivity type source region and drain region formed in the first conductivity type semiconductor region and positioned with respect to the gate electrode. A solid-state imaging device characterized by being configured.

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