JP2004281436A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which no crystal defect caused by an STI stress layer exists and, in addition, the occurrence of leak currents in the reverse direction of a pn junction in the depletion layer of a semiconductor element can be reduced. <P>SOLUTION: A plurality of semiconductor elements are integrally formed on the main surface of a semiconductor substrate. An insulating film formed by partially oxidizing the semiconductor substrate insulates the semiconductor elements from each other, and the end of the insulating film in the direction of the main surface is positioned at a location which is farther depressed toward the semiconductor substrate side than the plane formed of the main surface of the semiconductor substrate in the cross section of the substrate perpendicular to the main surface. In addition, the semiconductor elements are formed so that the positions of their end sections in the direction of the main surface may roughly become coincident with the position of the end of the insulating film in the direction of the main surface in the cross section of the semiconductor substrate perpendicular to the main surface. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device in which a plurality of semiconductor elements are integrated.
[0002]
[Prior art]
In recent years, as one of solid-state imaging devices, a solid-state imaging device using an amplification type MOS sensor has attracted attention. The solid-state imaging device amplifies, using a transistor, a signal detected by a photodiode for each cell for each pixel, and has a feature of high sensitivity.
[0003]
Here, an example of the solid-state imaging device will be described with reference to the drawings. FIG. 7 is a diagram illustrating a circuit configuration of the solid-state imaging device. The solid-state imaging device includes photodiodes 31-1-1 to 31-mn, transfer transistors 32-1-1 to 32-mn, reset transistors 33-1 to 33-mn, and an amplification transistor 34. −1-1 to 34-mn, row selection transistors 35-1-1 to 35-mn, row signal lines 36-1 to 36-m, row signal storage unit 37, column selection unit 38, row selection Unit 39, transfer transistor control lines 40-1 to 40-n, reset transistor control lines 41-1 to 41-n, row selection transistor control lines 42-1 to 42-n, load transistor group 43, and pixel unit power supply 44. Prepare.
[0004]
The photodiodes 31-1-1 to 31-mn convert input light into an electric signal. The transfer transistors 32-1-1 to 32-mn transfer signals of the photodiodes 31-1-1 to 31-mn. The amplification transistors 34-1-1 to 34-mn amplify the transferred signal charges. The row selection transistors 35-1-1 to 35-mn select a line from which a signal is read. The reset transistors 33-1-1 to 33-mn reset signal charges. The photodiodes 31-1-1 to 31-mn, the transfer transistors 32-1-1 to 32-mn, the reset transistors 33-1 to 33-mn, and the amplification transistor 34-1-1. To 34-mn, and the row selection transistors 35-1-1 to 35-mn are two-dimensionally arranged in a unit cell having m stages in the vertical direction and n stages in the horizontal direction, as shown in FIG. Are located in
[0005]
The row selection unit 39 includes row selection transistor control lines 42-1 to 42-n connected to the gates of the row selection transistors 35-1-1 to 35-mn, which are wired in the horizontal direction. Determine the row to read. The reset transistor control lines 41-1 to 41-n are formed on the gates of the reset transistors 33-1-1 to 33-mn. The sources of the row selection transistors 35-1-1 to 35-mn are connected to row signal lines 36-1 to 36-m, and a load transistor group 43 is provided at one end. The other ends of the row signal lines 36-1 to 36-m are coupled to a row signal accumulation unit 37 including a switch transistor that takes in a signal for one row. The row signal accumulating unit 37 sequentially outputs the final output according to the column selection pulse supplied from the column selecting unit 38.
[0006]
The operation of the conventional solid-state imaging device configured as described above will be described with reference to the drawings. FIG. 8 is a timing chart of a pulse signal for driving the solid-state imaging device.
[0007]
First, the row selection unit 39 applies a row selection pulse 101-1 for setting the row selection transistor control line 42-1 to a high level. As a result, the row selection transistors 35-1-1 to 35-m-1 of the row on which the row selection transistor control line 42-1 is wired are turned on. Accordingly, a source follower circuit is configured by the amplification transistors 34-1-1 to 34-m-1 and the load transistor group 43 in the row to which the row selection transistor control line 42-1 is connected.
[0008]
Next, the row selection unit 39 applies the reset pulse 102-1 while the row selection transistor control line 42-1 is at the high level, and sets the reset transistor control line 41-1 to the high level. Thus, the gate regions of the amplification transistors 34-1-1 to 34-m-1 reset the potential of the connected floating diffusion layer.
[0009]
Next, the row selection unit 39 applies the transfer pulse 103-1 during a period in which the row selection transistor control line 42-1 is at the high level, and sets the transfer transistor control line 40-1 to the high level. Thereby, the signal charges accumulated in the photodiodes 31-1-31 to 1-m-1 are transferred to the floating diffusion layer. At this time, the gate voltages of the amplification transistors 34-1-1 to 34-m-1 connected to the floating diffusion layer become the same as the potential of the floating diffusion layer. Accordingly, a voltage substantially equivalent to the voltage appears on row signal lines 36-1 to 36-m. At this time, the signal is transferred to the row signal accumulation unit 37 including the switch transistor.
[0010]
Next, the column selection unit 38 outputs the column selection pulses 106-1-1 to 106-m-1 shown in FIG. Accordingly, the final output 107-1 in FIG. 8 is output as an output signal from the output terminal. Thereby, the signal of the first row is output. Note that the operations in the second and subsequent rows are the same as the operations in the first row, and a description thereof will be omitted. Through the above operation, the image data captured by the solid-state imaging device is output from the output terminal.
[0011]
Here, FIG. 9 is a schematic diagram showing the structure of the unit cell of the solid-state imaging device shown in FIG. Note that the schematic diagram shown in FIG. 9 is a diagram for representing an image of a unit cell of the solid-state imaging device, and its structure does not completely match that shown in FIG.
[0012]
The unit cells of the solid-state imaging device shown in FIG. 9 include photodiodes 51-1 and 51-2, source / drain sections 52-1 and 52-2, MOS transistor gate electrodes 53 and 54, contact section 55, and element isolation section 56. And 57. The contact portion 55 connects to an upper wiring layer. The element separating section 56 separates the adjacent photodiodes 51 from each other. The element separating section 57 separates the photodiode 51 from the transistor.
[0013]
FIG. 10 is a cross-sectional view of a unit cell of the solid-state imaging device configured as described above. FIG. 10 is a cross-sectional view of the unit cell of the solid-state imaging device taken along the line WXYZ of FIG. 9. Now, the cross-sectional view shown in FIG. 10 will be described.
[0014]
The sectional view shown in FIG. 10 includes a semiconductor substrate 50, photodiodes 51-1 and 51-2, source / drain portions 52-1 and 52-2, MOS transistor gate electrodes 53, element isolation portions 56 and 57, and gate insulation. A membrane 58 is described.
[0015]
Here, the structure of the element isolation portions 56 and 57 shown in the cross-sectional view of FIG. 10 employs a structure called STI (Shallow Trench Isolation) after the 0.25 μ rule. The STI has a structure in which the silicon substrate 50 is dug and an insulating film is embedded in the dug portion.
[0016]
In recent years, the size of elements such as transistors has been rapidly reduced due to miniaturization. Accordingly, the depths of the source / drain portions 52-1 and 52-2 and the like have rapidly become shallow, and the depth is now about 0.1 μm. Accordingly, the widths of the element isolation portions 56 and 57 have been rapidly reduced. STI has the advantage that such narrow device isolation can be performed.
[0017]
[Patent Document 1]
JP 2001-345439 A
[Problems to be solved by the invention]
However, a MOS type sensor to which the above-mentioned STI is applied has a problem that a crystal defect is easily generated, and as a result, the performance of the sensor is deteriorated. Now, the cause of the deterioration of the performance of the MOS type sensor to which the STI is applied will be described with reference to the drawings. FIG. 11 is a sectional view showing the structure of the STI. FIG. 12 is a diagram showing the distribution of the defect density in the XY direction of FIG.
[0019]
The STI structure shown in FIG. 11 includes a semiconductor substrate 90 whose center is cut off, and an insulating film 91 embedded in the cut-off portion. Then, as shown in FIG. 11, a crystal defect 92 occurs near the corner of the upper surface of the insulating film 91, and further, a crystal defect 93 occurs below the insulating film 91. I have. These defects occur so as to be distributed some inside the semiconductor substrate 90, and are large defects with a size of about 0.5 μm or more. Such crystal defects 92 and 93 cause white point defects on a reproduced screen in a MOS solid-state imaging device to which element isolation by STI is applied.
[0020]
Further, when the interface of the STI semiconductor substrate 90 is analyzed in detail along the cross section XY direction, as shown in FIG. 12, small defects increase from the X direction to the Y direction as approaching the interface. . Defects that increase as approaching the interface are referred to as an interface defect layer 94 and an STI stress defect layer 95. Among them, the interface defect layer 94 is a crystal defect generated near a boundary surface between the semiconductor substrate 90 and the insulating film 91. On the other hand, the STI stress defect layer 95 is a crystal defect generated by stress applied to the semiconductor substrate 90 when the STI insulating film 91 is formed. The STI stress defect layer 95 is generated up to 0.02 μ from the boundary surface in a direction away from the insulating film 91. Such an STI stress defect layer 95 causes non-uniform unevenness on a reproduction screen.
[0021]
With respect to the above-mentioned problems, recent advances in digital technology have made it possible to correct the former point defect. However, correction of the latter non-uniform unevenness requires a memory for storing the entire screen, and there is a problem that the cost of the entire MOS solid-state imaging device increases.
[0022]
To solve the above problem, application of LOCOS (abbreviation for Local Oxidation Silicon) adopted in the 0.35 μ rule before STI can be considered. FIG. 13 is a cross-sectional view showing a structure of a semiconductor device to which LOCOS isolation is applied. In the LOCOS isolation, a location where an element isolation portion is to be formed is locally oxidized on the semiconductor substrate 201, so that a LOCOS oxide film 202 serving as an insulating film is formed. Thereafter, a source / drain portion 207 is formed adjacent to the LOCOS oxide film 202.
[0023]
Here, in the LOCOS isolation, the semiconductor substrate 201 is not dug to form the LOCOS oxide film 202. Therefore, the semiconductor substrate 201 to which the LOCOS isolation is applied has an advantage that the number of crystal defects 206 is smaller than that of the semiconductor substrate 90 in which the element isolation by STI is performed.
[0024]
Further, as shown in FIG. 14, the defect density distribution in the XY direction of FIG. 13 shows that there is no equivalent to the STI stress defect layer 95, and only the LOCOS interface defect layer 300 which increases as approaching the boundary surface. Exists. FIG. 14 is a diagram showing the distribution of the defect density in the XY direction in FIG. As described above, it is considered that the reason why the STI stress defect layer 95 does not occur when the LOCOS isolation is applied is that there is no step of digging the semiconductor substrate like the STI in the LOCOS isolation. Thus, in the MOS solid-state imaging device to which the LOCOS isolation is applied, uneven unevenness on the reproduction screen due to the presence of the STI stress defect layer 95 is reduced.
[0025]
However, in the above-described conventional LOCOS element isolation, the depletion layer 210 sandwiched between the dotted lines 208 and 209 in FIG. 13 is located below the bird's beak 203 formed with the formation of the LOCOS oxide film 202. . It is known that many crystal defects exist below the bird's beak 203. The overlap between the layer having a large number of crystal defects and the depletion layer causes a pn junction reverse leakage current in a transistor or the like, which leads to a deterioration in the performance of the solid-state imaging device.
[0026]
In the conventional LOCOS element isolation, the thickness of the LOCOS oxide film 202 is 380 nm to 450 nm. And about half of them are exposed above the semiconductor substrate surface. Therefore, it is difficult to form a gate electrode and the like of the transistor finely on the LOCOS oxide film 202. Further, as compared with STI, the lateral width required for element isolation is also increased. As a result, miniaturization of the semiconductor device cannot be achieved.
[0027]
Therefore, an object of the present invention is to provide a semiconductor device in which no crystal defect due to an STI stress layer exists and which can reduce the occurrence of a pn junction reverse leakage current in a depletion layer of a semiconductor element.
[0028]
Another object of the present invention is to provide a semiconductor device which can be miniaturized.
[0029]
[Means for Solving the Problems]
According to a first aspect of the present invention, a semiconductor substrate is formed by partially oxidizing a semiconductor element to separate a plurality of semiconductor elements from each other. The semiconductor device includes an insulating film that is located at a position depressed toward the semiconductor substrate with respect to a plane formed by the main surface of the semiconductor substrate. Are formed so as to substantially coincide with the position of the end in the main surface direction of the insulating film.
[0030]
With this configuration, it is possible to provide a semiconductor device in which crystal defects due to the STI stress layer do not exist and in which the occurrence of a pn junction reverse leak current in a depletion layer of the semiconductor element can be reduced.
[0031]
BEST MODE FOR CARRYING OUT THE INVENTION
Now, a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view illustrating the main surface of the semiconductor device according to the present embodiment. The semiconductor device according to the present invention is preferably applied to a solid-state imaging device or a dynamic logic.
[0032]
The semiconductor device includes a semiconductor substrate 1, a LOCOS oxide film 2, and a source / drain layer 7. Further, a depletion layer 10 is generated in a region between the dotted line 8 and the dotted line 9. In the semiconductor device, the LOCOS oxide film 2 does not have a bird's beak, and its lower surface has a substantially elliptical shape. The end of the source / drain layer 7 is formed so as to contact the end of the lower surface of the LOCOS oxide film 2 in the major axis direction of the ellipse.
[0033]
Now, a method for manufacturing the semiconductor device will be described below with reference to the drawings. 2 and 3 are diagrams showing a procedure for manufacturing the semiconductor device.
[0034]
First, as shown in FIG. 2A, a silicon oxide film 21 is formed on a Si semiconductor substrate 1, and a silicon nitride film 22 is further formed thereon.
[0035]
Next, as shown in FIG. 2B, a resist 23 is formed on portions other than the portion where the LOCOS oxide film 2 is formed.
[0036]
Thereafter, as shown in FIG. 2C, the silicon nitride film 22 where the resist 23 is not formed is partially removed by dry etching. Then, as shown in FIG. 2D, the resist 23 is removed.
[0037]
Next, the semiconductor device shown in FIG. 2D is oxidized in an oxidation furnace. Thereby, as shown in FIG. 2E, the LOCOS oxide film 2 is formed in a portion where the silicon nitride film 22 is not formed. The thickness of the conventional LOCOS oxide film is about 400 nm, whereas the thickness of the LOCOS oxide film 2 according to the present invention is formed to be about 50 nm thinner than the conventional one.
[0038]
Next, as shown in FIG. 3F, the silicon nitride film 22 is removed by dry etching. Thereafter, the entire silicon oxide film 21 and a part of the LOCOS oxide film 2 are removed by spin etching. At this time, the amount by which the LOCOS oxide film 2 is scraped off by spin etching is preferably such that bird's beak is eliminated. Thereby, a LOCOS oxide film 2 as shown in FIG. 3G is formed.
[0039]
Thereafter, an active region such as the source / drain layer 7 is formed by ion implantation, and a semiconductor device as shown in FIG. Note that the source / drain layer 7 is formed such that the end thereof coincides with the end of the major axis of the ellipse on the lower surface of the LOCOS oxide film 2.
[0040]
Here, physical properties of the semiconductor device according to the present application will be described with reference to the drawings. FIG. 4 is a graph showing the distribution of defect density of SS′-T′-T in FIGS. 1 and 13. The vertical axis indicates the defect density, and the horizontal axis indicates the position.
[0041]
As shown in FIG. 4, the defect density has a low value between SS ′, that is, under the LOCOS oxide films 2 and 202. Then, between S′-T ′, that is, below the bird's beak 203 in FIG. 13, the defect density sharply increases and shows a high value. Thereafter, between T ′ and T, the defect density decreases.
[0042]
That is, in the conventional semiconductor device, the depletion layer 210 is located between S′-T ′ having the highest defect density, whereas in the semiconductor device according to the present embodiment, the bird's beak 203 of the LOCOS oxide film 2 is formed. Is removed, so that the depletion layer 10 can be located in SS ′ having a low defect density.
[0043]
As described above, according to the semiconductor device of the present embodiment, since the element isolation is performed by the LOCOS oxide film in which the semiconductor substrate is not dug, no crystal defect due to the STI stress layer is present. As a result, when the semiconductor device is applied to a solid-state imaging device, occurrence of unevenness on a reproduction screen is suppressed.
[0044]
Further, according to the semiconductor device according to the present embodiment, as shown in FIG. 4, the depletion layer is located at a position where the number of crystal defects is small, so that the pn junction reverse leakage current in the depletion layer of the semiconductor element is reduced. Can be reduced.
[0045]
Further, according to the semiconductor device of the present embodiment, the LOCOS oxide film is cut off to the extent that bird's beak is eliminated, so that the height h of the LOCOS oxide film in the cross section of FIG. The width w (minimum separation width) in the cross section can be reduced. As a result, the semiconductor device can be miniaturized.
[0046]
In addition, the height h of the portion where the LOCOS oxide film projects above the surface of the semiconductor substrate in FIG. 1 is preferably 0 nm to 50 nm. This is because the lithography focus margin can be handled in the 0.18 μ rule. Also, in the 0.18 μ rule, when h is 80 nm or more, the gate electrode cannot be processed due to unevenness of the surface of the semiconductor device.
[0047]
Further, the shape of the LOCOS oxide film is such that, in a cross section perpendicular to the main surface of the semiconductor substrate, the curvature of a portion in contact with the semiconductor substrate is larger than the curvature of a portion not in contact with the semiconductor substrate. It may be. This also provides the same effect as when the height h of the portion where the LOCOS oxide film is exposed above the semiconductor substrate surface is set to 0 nm to 50 nm.
[0048]
Further, the shape of the LOCOS oxide film is such that, in a cross section perpendicular to the main surface of the semiconductor substrate, the maximum value of the height protruding upward from the semiconductor substrate corresponds to the maximum value of the depth embedded in the semiconductor substrate. The shape may be such that the value of the ratio is ４ or less. This also provides the same effect as when the height h of the portion where the LOCOS oxide film is exposed above the semiconductor substrate surface is set to 0 nm to 50 nm.
[0049]
The crystal defect density distribution shown in FIG. 4 under the LOCOS oxide film showed the same tendency even when the conditions such as the oxidation temperature for manufacturing the LOCOS oxide film were changed.
[0050]
Also, when the actual reverse leakage current of the pn junction was measured, a value smaller than the value actually predicted was obtained in the structure of the present invention. Here, the measurement was performed after the bird's beak was removed. That is, it is considered that the removal of the bird's beak changes the state below the LOCOS oxide film, and as a result, the pn junction reverse leakage current has decreased from the predicted value.
[0051]
As shown in FIG. 5, the amount by which the LOCOS oxide film is removed by etching may be smaller than that in FIG. Similarly, as shown in FIG. 6, the amount by which the LOCOS oxide film is removed by etching may be larger than that in FIG. That is, in FIGS. 1, 5 and 6, the bird's beak may be removed such that both ends of the LOCOS oxide film in the left-right direction are located at least in locations recessed below the surface of the semiconductor substrate. In the case of FIG. 5, the source / drain layer 7 is formed such that the end of the major axis of the elliptical portion on the upper surface of the LOCOS oxide film 2 coincides with the end of the source / drain layer 7.
[0052]
In the above embodiment, when the bird's beak is removed, the upper part of the LOCOS oxide film is also partially removed. However, the upper part of the LOCOS oxide film does not necessarily need to be partially removed. That is, in this embodiment, as long as at least a part of the bird's beak has been removed, the other part may not be removed.
[0053]
In the present embodiment, the LOCOS oxide film has been described as having an elliptical shape, but the shape of the LOCOS oxide film is not limited to the elliptical shape. In the LOCOS oxide film, when there is a large spread in the main surface direction of the semiconductor substrate, the shape does not become elliptical but has a flat portion in part.
[0054]
Here, since CMOS logic has become mainstream in semiconductor devices in recent years, MOS solid-state imaging devices are often configured with CMOS logic.
[0055]
However, the manufacturing process of the CMOS logic is long and the manufacturing process is determined by miniaturization. Therefore, in the CMOS logic, it is very difficult to change the manufacturing process for the sensor. In the process of manufacturing a miniaturized transistor, it is difficult to form a p-channel transistor. This is because boron, which is a p-type impurity, has a low mass and is easy to move.
[0056]
Therefore, in the case described above, it is conceivable to configure the MOS type solid-state imaging device only with the NMOS. However, when a circuit including only NMOS is used, power consumption is generally larger than that of CMOS. Therefore, dynamic logic is applied to a MOS solid-state imaging device in order to measure reduction in power consumption.
[0057]
Here, in the dynamic logic, an operation called booting in which the voltage is raised by the capacitance of the MOS is performed. However, when the pn junction reverse leakage current increases in the MOS capacitor portion, the dynamic logic does not operate. Therefore, the problem that the dynamic logic does not operate is solved by applying the semiconductor device according to the present embodiment to element separation of the dynamic logic.
[0058]
Further, in the portion of the NMOS capacitor, the reverse leakage current of the pn junction is reduced, so that the dynamic logic can be operated slowly. As a result, for example, a mode in which the operation is performed very slowly, that is, long-time exposure, which is applied to an image sensor of a digital still camera in recent years, can be easily realized.
[0059]
As described above, in the solid-state imaging device, only the NMOS is used, and the dynamic logic in which the element isolation according to the present invention is performed is applied, so that the solid-state imaging device can be easily manufactured, miniaturized, reduced in power consumption, and reduced in power consumption. Leakage can be satisfied at the same time.
[0060]
The semiconductor device according to the present embodiment is effectively applied to a semiconductor device having an element isolation structure of STI (Shallow Trench Isolation) and a 0.25 μ rule or later in which a pn junction reverse leakage current increases. It is.
[0061]
【The invention's effect】
As described above, according to the semiconductor device of the present invention, there is no crystal defect due to the STI stress layer, and the occurrence of a pn junction reverse leakage current in the depletion layer of the semiconductor element can be reduced.
[Brief description of the drawings]
FIG. 1 is a sectional view of a semiconductor device according to the present invention.
FIG. 2 is a diagram showing a manufacturing process of the semiconductor device according to the present invention.
FIG. 3 is a view showing a manufacturing process of the semiconductor device according to the present invention.
FIG. 4 is a graph showing distribution of crystal defects between SS′-T′-T of the semiconductor device shown in FIG. 1;
FIG. 5 is a sectional view of another example of the semiconductor device according to the present invention.
FIG. 6 is a sectional view of another example of the semiconductor device according to the present invention.
FIG. 7 is a diagram illustrating a configuration of a conventional general solid-state imaging device.
FIG. 8 is a diagram illustrating operation timings of the solid-state imaging device in FIG. 7;
FIG. 9 is a schematic diagram illustrating a structure of a unit cell of the solid-state imaging device illustrated in FIG. 7;
FIG. 10 is a sectional view taken along the line WXYZ of FIG. 9;
FIG. 11 is a sectional view showing the structure of an STI.
FIG. 12 is a diagram showing a distribution of defect density in the XY direction of FIG. 11;
FIG. 13 is a cross-sectional view showing a structure of a semiconductor device to which LOCOS isolation is applied.
FIG. 14 is a diagram showing a distribution of defect density in the XY direction of FIG.
[Explanation of symbols]
Reference Signs List 1 semiconductor substrate 2 LOCOS oxide film 7 source / drain layer 10 depletion layer 21 silicon oxide film 22 silicon nitride film 23 resist

Claims (15)

A semiconductor substrate;
A plurality of semiconductor elements formed integrally on the main surface of the semiconductor substrate;
The semiconductor substrate is formed by being partially oxidized, and separates the plurality of semiconductor elements from each other. In a cross section perpendicular to a main surface of the semiconductor substrate, an end in a main surface direction is a main end of the semiconductor substrate. An insulating film located at a place depressed on the semiconductor substrate side relative to a plane formed by the surface,
The semiconductor device is formed such that, in a cross section perpendicular to a main surface of the semiconductor substrate, a position of an end in a main surface direction substantially coincides with a position of an end of the insulating film in a main surface direction. . 2. The semiconductor device according to claim 1, wherein an outer shape of an end of the insulating film in a direction of the main surface in a cross section perpendicular to a main surface of the semiconductor substrate is processed into a curve. 3. The insulating film is characterized in that, in a cross section perpendicular to a main surface of the semiconductor substrate, a curvature of a portion in contact with the semiconductor substrate is larger than a curvature of a portion not in contact with the semiconductor substrate. Item 2. The semiconductor device according to item 1. The insulating film has a ratio of a maximum value of a height protruding to the opposite side of the semiconductor substrate to a maximum value of a depth protruding to the semiconductor substrate side in a cross section perpendicular to the main surface of the semiconductor substrate. The semiconductor device according to claim 1, wherein is less than or equal to ４. 2. The insulating film according to claim 1, wherein in a cross section perpendicular to the main surface of the semiconductor substrate, a maximum value of a protruding height is 50 nm or less as viewed from a plane formed by the main surface. 3. Semiconductor device. The semiconductor device according to claim 1, wherein the semiconductor device is applied to a solid-state imaging device. The semiconductor device according to claim 1, wherein the semiconductor device is applied to a dynamic logic. 2. The semiconductor device according to claim 1, wherein the insulating film is an oxide film formed by a LOCOS (Local Oxidation Silicon) method. A method for manufacturing a semiconductor device in which a plurality of semiconductor elements are integrated and formed on a semiconductor substrate,
Forming an insulating film by oxidizing a part of the semiconductor substrate;
Removing at least a portion of a bird's beak generated at an end of the formed insulating film in a main surface direction in a cross section perpendicular to the main surface of the semiconductor substrate; and Forming a semiconductor element on the main surface of the semiconductor substrate such that an end of the semiconductor substrate in the main surface direction coincides with an end of the semiconductor element in the main surface direction. Production method. 10. The method according to claim 9, wherein the step of forming the insulating film is a step of forming an oxide film by a LOCOS (Local Oxidation Silicon) method. 10. The method according to claim 9, wherein in the step of removing at least a part of the bird's beak, a part of the insulating film is removed so that the film thickness of the insulating film is reduced. . In the step of removing at least a part of the bird's beak, at least a part of the bird's beak is removed so that an end of the insulating film in a main surface direction has a curved shape in a cross section perpendicular to the main surface of the semiconductor substrate. The method of manufacturing a semiconductor device according to claim 11, wherein: In the step of removing at least a part of the bird's beak, in a cross section perpendicular to a main surface of the semiconductor substrate, a curvature of a portion of the insulating film in contact with the semiconductor substrate is in contact with the semiconductor substrate of the insulating film. The method according to claim 11, wherein a part of the insulating film is removed so as to have a curvature larger than a curvature of a part which is not provided. In the step of removing at least a part of the bird's beak, in a cross section perpendicular to a main surface of the semiconductor substrate, a maximum value of a height of the insulating film protruding to the opposite side of the semiconductor substrate, the semiconductor of the insulating film is 12. The semiconductor device manufacturing method according to claim 11, wherein a part of the insulating film is removed so that a value of a ratio of a depth protruding toward the substrate side to a maximum value is 1/4 or less. Method. In the step of removing at least a part of the bird's beak, in a cross section perpendicular to the main surface of the semiconductor substrate, a maximum value of a height at which the insulating film protrudes becomes 50 nm or less as viewed from a plane formed by the main surface. The method of manufacturing a semiconductor device according to claim 11, wherein the semiconductor device is removed as described above.

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