JP2006350376A - Semiconductor device and light-emitting device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for driving a light-emitting device capable of preventing a luminance of a light-emitting element from being fluctuated by applying characteristics of TFTs for controlling current being fed to the light-emitting element, and also capable of generating the constant luminance without adversely being affected by a possible degradation of organic light emitting layers and variable temperature by way of preventing the luminance of light-emitting element from being lowered through a degradation of organic light emitting layers. <P>SOLUTION: Instead of controlling the luminance of the light-emitting element by a voltage applied to TFTs, by controlling current flowing into TFTs via a signal-line driving circuit, it is possible to hold on the current flowing into the light-emitting element at a desired value without adversely being affected by the characteristics of TFTs. Further, a voltage biasing in an inverse direction is fed to the light-emitting element at each predetermined period of time. The above-described two means multiply such practical effects to more securely prevent the luminance from being lowered by the possible degradation of organic light emitting layers, and make it possible to hold on such a current flowing into the light-emitting element at a desired value without being affected by electrical characteristics of TFTs. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a light emitting panel in which a light emitting element formed on a substrate is sealed between the substrate and a cover material. The present invention also relates to a light emitting module in which an IC including a controller is mounted on the light emitting panel. Note that in this specification, the light-emitting panel and the light-emitting module are collectively referred to as a light-emitting device. The present invention further relates to a driving method of the light emitting device and an electronic apparatus using the light emitting device.

  Since the light emitting element emits light by itself, the visibility is high, a backlight necessary for a liquid crystal display (LCD) is not necessary, and it is optimal for thinning, and the viewing angle is not limited. Therefore, in recent years, light emitting devices using light emitting elements have attracted attention as display devices that replace CRTs and LCDs.

  Note that in this specification, a light-emitting element means an element whose luminance is controlled by current or voltage, and an MIM type electron used in an OLED (Organic Light Emitting Diode) or an FED (Field Emission Display). Source elements (electron emitting elements) and the like are included.

  The OLED has a layer (hereinafter, referred to as an organic light emitting layer) containing an organic compound (organic light emitting material) capable of obtaining luminescence generated by applying an electric field, an anode layer, and a cathode layer. . Luminescence in organic compounds includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state. Any one of the above-described light emission may be used, or both light emission may be used.

  In this specification, all layers provided between the anode and the cathode of the OLED are defined as organic light emitting layers. Specifically, the organic light emitting layer includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer, an electron transport layer, and the like. Basically, the OLED has a structure in which an anode / light emitting layer / cathode is laminated in this order. In addition to this structure, the anode / hole injection layer / light emitting layer / cathode and the anode / hole injection layer / The light emitting layer / electron transport layer / cathode may be stacked in this order.

  FIG. 23 illustrates a pixel configuration of a general light-emitting device. The pixel shown in FIG. 23 includes TFTs 50 and 51, a storage capacitor 52, and a light emitting element 53.

  The TFT 50 has a gate connected to the scanning line 55, one of the source and drain connected to the signal line 54, and the other connected to the gate of the TFT 51. The TFT 51 has a source connected to the power source 56 and a drain connected to the anode of the light emitting element 53. The cathode of the light emitting element 53 is connected to the power source 57. The storage capacitor 52 is provided to hold the voltage between the gate and source of the TFT 51.

  When the TFT 50 is turned on by the voltage of the scanning line 55, the video signal input to the signal line 54 is input to the gate of the TFT 51. When a video signal is input, the gate voltage (voltage difference between the gate and the source) of the TFT 51 is determined according to the voltage of the input video signal. Then, the drain current of the TFT 51 flowing by the gate voltage is supplied to the light emitting element 53, and the light emitting element 53 emits light by the supplied current.

  By the way, a TFT formed of polysilicon has a higher field effect mobility and a higher on-current than a TFT formed of amorphous silicon, and thus is more suitable as a transistor of a light-emitting element panel.

  However, even if a TFT is formed using polysilicon, the electrical characteristics are not comparable to the characteristics of a MOS transistor formed on a single crystal silicon substrate. For example, the field effect mobility is 1/10 or less of single crystal silicon. In addition, TFTs using polysilicon have a problem that their characteristics are likely to vary due to defects formed at crystal grain boundaries.

  In the pixel shown in FIG. 23, when the characteristics of the TFT 51, such as the threshold value and the on-current, vary from pixel to pixel, the drain current of the TFT 51 differs between pixels even when the video signal voltage is the same. Variations in the brightness of the image.

  In addition, what has become a problem in putting light-emitting devices using OLEDs into practical use is the short lifetime of OLEDs due to deterioration of the organic light-emitting layer. Organic light-emitting materials are vulnerable to moisture, oxygen, light, and heat, and their deterioration is accelerated by these materials. Specifically, the speed of deterioration depends on the structure of the device that drives the light emitting device, the characteristics of the organic light emitting material, the electrode material, the conditions in the manufacturing process, the driving method of the light emitting device, and the like.

  Even if the voltage applied to the organic light emitting layer is constant, if the organic light emitting layer is deteriorated, the luminance of the OLED is lowered and the displayed image becomes unclear.

  In addition, the temperature of the organic light emitting layer depends on the outside air temperature, the heat generated by the OLED panel itself, etc., but in general, the value of the current flowing through the OLED varies depending on the temperature. Specifically, when the voltage is constant and the temperature of the organic light emitting layer increases, the current flowing through the OLED increases. Since the current flowing through the OLED and the luminance of the OLED are in a proportional relationship, the larger the current flowing through the OLED, the higher the luminance of the OLED. Thus, since the luminance of the OLED changes depending on the temperature of the organic light emitting layer, it is difficult to display a desired gradation, and the current consumption of the light emitting device increases as the temperature rises.

  Note that it has already been found that deterioration of current-voltage characteristics of a light emitting element can be improved by applying a driving voltage having a reverse polarity to the light emitting element at regular intervals (see, for example, Patent Document 1).

Dechun ZOU, Masayuki YAHIRO and Tetsuo TSUTSUI, "JPN. J. Appl. Phys.", 15 November 1998, Part 2 VOL.37, NO.11B pp. L1406-L1408 It has been introduced that deterioration of a light emitting element can be suppressed by applying a reverse bias voltage. However, there is no description regarding a specific configuration and driving method of the active matrix light-emitting device.

  In view of the above-described problems, the present invention can prevent the luminance of the light emitting element from varying due to the characteristics of the TFT that controls the current supplied to the light emitting element, and reduces the luminance of the light emitting element due to the deterioration of the organic light emitting layer. An object of the present invention is to provide a light-emitting device that can prevent and prevent the deterioration of the organic light-emitting layer or change in temperature and obtain a certain luminance.

  The present inventor has a smaller decrease in luminance of the OLED due to deterioration in the case where the voltage applied to the OLED is kept constant and the light is emitted while the current flowing in the OLED is kept constant. Focused on that. Note that in this specification, a current flowing through a light-emitting element is referred to as a drive current, and a voltage applied to the light-emitting element is referred to as a drive voltage.

  The luminance of the light emitting element is not controlled by the voltage applied to the TFT, but the current flowing through the TFT is controlled by the signal line driver circuit, so that the current flowing through the light emitting element is not affected by the characteristics of the TFT. It was thought that the value could be maintained, and the change in the luminance of the OLED due to the deterioration of the OLED could be prevented.

  Furthermore, as introduced in the above-mentioned document 1, it has been found that by applying a drive voltage having a reverse polarity to the light emitting element at regular intervals, the deterioration of the current-voltage characteristics of the light emitting element is improved. Yes. Utilizing this property, in addition to the above-described configuration, the present invention applies a reverse bias voltage to the light emitting element at regular intervals. Since the light emitting element is a diode, light is emitted when a forward bias voltage is applied, and the light emitting element does not emit light when a reverse bias voltage is applied.

  By using a driving method (AC driving) in which a reverse bias driving voltage is applied to the light emitting element at regular intervals as in the above configuration, the deterioration of the current-voltage characteristics of the light emitting element is improved, and the lifetime of the light emitting element is improved. Can be made longer than the conventional driving method.

  The above two configurations provide a synergistic effect, can further prevent a decrease in luminance due to deterioration of the organic light emitting layer, and can maintain a current flowing through the light emitting element at a desired value regardless of the characteristics of the TFT.

  Further, as described above, when displaying an image every frame period in AC driving, flickering may occur as flickering in the eyes of the observer. Therefore, in the case of AC driving, the light emitting device is driven at a frequency higher than the frequency at which flicker does not occur in the observer's eyes in DC driving in which only the forward bias voltage is applied so as to prevent the occurrence of flicker. It is preferable to do this.

  According to the present invention, even if the characteristics of the TFT for controlling the current supplied to the light emitting element vary from pixel to pixel, the pixel emits light between pixels compared to the general light emitting device shown in FIG. It is possible to prevent variation in luminance of the element. Further, as compared with the case where the TFT 51 of the voltage input type pixel shown in FIG. 23 is operated in a linear region, a reduction in luminance due to deterioration of the light emitting element can be suppressed. Even if the temperature of the organic light emitting layer depends on the outside air temperature, heat generated by the light emitting panel itself, etc., it is possible to suppress the luminance of the light emitting element from changing, and the current consumption increases as the temperature increases. Can be prevented.

  Note that in the light-emitting device of the present invention, a transistor used for a pixel may be a transistor formed using single crystal silicon, or a thin film transistor using polycrystalline silicon or amorphous silicon. Further, a transistor using an organic semiconductor may be used.

  Note that the transistor provided in the pixel of the light-emitting device of the present invention may have a single-gate structure, or a double-gate structure or a multi-gate structure having a gate electrode higher than that.

The light-emitting device of the present invention can prevent variation in luminance of light-emitting elements between pixels, as compared with a voltage-input light-emitting device, even if TFT characteristics vary from pixel to pixel. Further, as compared with the case where the TFT 51 of the voltage input type pixel shown in FIG. 23 is operated in a linear region, a reduction in luminance due to deterioration of the light emitting element can be suppressed.
Even if the temperature of the organic light emitting layer depends on the outside air temperature, heat generated by the light emitting panel itself, etc., it is possible to suppress the luminance of the light emitting element from changing, and the current consumption increases as the temperature increases. Can be prevented.

  FIG. 1 is a block diagram showing the structure of the light emitting device of the present invention. Reference numeral 100 denotes a pixel portion, and a plurality of pixels 101 are arranged in a matrix. Reference numeral 102 denotes a signal line driver circuit, and 103 denotes a scanning line driver circuit.

  In FIG. 1, the signal line driver circuit 102 and the scanning line driver circuit 103 are formed over the same substrate as the pixel portion 100; however, the present invention is not limited to this structure. The signal line driver circuit 102 and the scan line driver circuit 103 may be formed over a different substrate from the pixel unit 100 and connected to the pixel unit 100 via a connector such as an FPC. In FIG. 1, one signal line driver circuit 102 and one scanning line driver circuit 103 are provided, but the present invention is not limited to this structure. The number of the signal line driver circuits 102 and the scanning line driver circuits 103 can be arbitrarily set by a designer.

  In this specification, connection means an electrical connection unless otherwise specified. On the other hand, disconnecting means not connected.

  Although not shown in FIG. 1, the pixel portion 100 is provided with signal lines S1 to Sx, power supply lines V1 to Vx, and scanning lines G1 to Gy. Note that the number of signal lines and power supply lines is not necessarily the same. Further, it is not always necessary to have all of these wirings, and other different wirings may be provided in addition to these wirings.

  The signal line driver circuit 102 can supply a current having a magnitude corresponding to the voltage of the input video signal to each of the signal lines S1 to Sx, and when applying a reverse bias voltage to the light emitting element 104, Any circuit can be used as long as it can apply a voltage that turns on a TFT for controlling the magnitude of the current or voltage supplied to the light emitting element 104 to the gate of the TFT. Specifically, in this embodiment, the signal line driver circuit 102 includes a shift register 102a, a memory circuit A 102b that can store a digital video signal, a memory circuit B 102c, and a size corresponding to the voltage of the digital video signal. Of the current or voltage supplied to the light emitting element 104 only in a period in which the generated current is supplied to the signal line and a reverse bias is applied. A switching circuit 102e capable of applying a voltage that turns on the TFT to the gate of the TFT for controlling the size is provided. Note that the signal line driver circuit 102 of the light-emitting device of the present invention is not limited to the above structure. 1 shows a signal line driver circuit corresponding to a digital video signal (digital video signal). However, the signal line driver circuit of the present invention is not limited to this and corresponds to an analog video signal (analog video signal). You may do it.

  Note that the voltage in this specification means a potential difference from the ground unless otherwise specified.

  FIG. 2 shows a detailed configuration of the pixel 101 shown in FIG. 2 includes a signal line Si (one of S1 to Sx), a scanning line Gj (one of G1 to Gy), and a power supply line Vi (one of V1 to Vx). Have. The pixel 101 includes transistors Tr1, Tr2, Tr3, Tr4, a light emitting element 104, and a storage capacitor 105. The storage capacitor 105 is provided in order to hold the voltage (gate voltage) between the gate and source of the transistors Tr1 and Tr2 more reliably, but it is not always necessary to provide the storage capacitor 105.

  The gate of the transistor Tr3 is connected to the scanning line Gj. The transistor Tr3 has a source and a drain (one of which is a first terminal and the other a second terminal), one connected to the signal line Si and the other connected to the second terminal of the transistor Tr1. Yes.

  The gate of the transistor Tr4 is connected to the scanning line Gj. One of the first terminal and the second terminal of the transistor Tr4 is connected to the signal line Si, and the other is connected to the gates of the transistors Tr1 and Tr2.

  The gates of the transistors Tr1 and Tr2 are connected to each other. The first terminals of the transistors Tr1 and Tr2 are both connected to the power supply line Vi. The second terminal of the transistor Tr2 is connected to the pixel electrode of the light emitting element 104. One of the two electrodes of the storage capacitor 105 is connected to the gates of the transistors Tr1 and Tr2, and the other is connected to the power supply line Vi.

  The light emitting element 104 has an anode and a cathode. In this specification, when the anode is used as a pixel electrode, the cathode is called a counter electrode, and when the cathode is used as a pixel electrode, the anode is called a counter electrode. The voltage of the counter electrode is kept at a constant height.

  Note that the transistors Tr1 and Tr2 may be either n-channel transistors or p-channel transistors. However, the transistors Tr1 and Tr2 have the same polarity. When the anode is used as the pixel electrode and the cathode is used as the counter electrode, the transistors Tr1 and Tr2 are preferably p-channel transistors. Conversely, when the anode is used as the counter electrode and the cathode is used as the pixel electrode, the transistors Tr1 and Tr2 are preferably n-channel transistors.

  The transistors Tr3 and Tr4 may be either n-channel transistors or p-channel transistors, but both have the same polarity.

  Next, the operation of the light-emitting device of this embodiment will be described with reference to FIG. The operation of the light emitting device of the present invention can be described by dividing into a writing period Ta, a display period Td, and a reverse bias period Ti for each pixel of each line. FIG. 3 is a diagram simply showing the connection between the transistors Tr1 and Tr2 and the light-emitting element 104 in each period. Here, Tr1 and Tr2 are p-channel TFTs, and the anode of the light-emitting element 104 is used as a pixel electrode. Take as an example.

  First, when the writing period Ta is started in the pixels of each line, the voltages of the power supply lines V1 to Vx are kept high enough to allow a forward bias current to flow through the light emitting element when the transistor Tr2 is turned on. . Although FIG. 1 shows the configuration of a light emitting device that displays a monochrome image, the present invention may be a light emitting device that displays a color image. In that case, the voltage levels of the power supply lines V1 to Vx need not be kept all the same, and may be changed for each corresponding color.

  Then, the scanning line driving circuit 103 sequentially selects each scanning line, and the transistors Tr3 and Tr4 are turned on. Note that the selected periods of the scanning lines do not overlap each other. Based on the video signal input to the signal line driver circuit 102, currents corresponding to the video signals (hereinafter, signal current Ic) flow between the signal lines S1 to Sx and the power supply lines V1 to Vx, respectively.

  FIG. 3A is a schematic diagram of the pixel 101 when a signal current Ic corresponding to a video signal flows through the signal line Si in the writing period Ta. Reference numeral 106 denotes a terminal for connection with a power source for applying a voltage to the counter electrode. Reference numeral 107 denotes a constant current source included in the signal line driver circuit 102.

Since the transistor Tr3 is in the on state, when the signal current Ic corresponding to the video signal flows through the signal line Si, the signal current Ic flows between the drain and the source of the transistor Tr1. At this time, the transistor Tr1 operates in the saturation region because the gate and the drain are connected, and operates according to the following Equation 1. V _GS is the gate voltage, μ is the mobility, C ₀ is the gate capacitance per unit area, W / L is the ratio of the channel width W to the channel length L of the channel formation region, V _TH is the threshold value, and the drain current is I And

_{I = μC 0 W / L (} V GS -V TH) 2/2 ··· ( number 1)
In Equation 1, μ, C ₀ , W / L, and V _TH are all fixed values determined by individual transistors. From Equation 1, it can be seen that the gate voltage V _GS of the transistor Tr1 is determined by the current value Ic.

The gate of the transistor Tr2 is connected to the gate of the transistor Tr1. The source of the transistor Tr2 is connected to the source of the transistor Tr1. Therefore, the gate voltage of the transistor Tr1 becomes the gate voltage of the transistor Tr2 as it is. Therefore, the drain current of the transistor Tr2 is proportional to the drain current of the transistor Tr1. In particular, when μC ₀ W / L and V _TH are equal to each other, the drain currents of the transistors Tr1 and Tr2 are equal to each other, and I ₂ = Ic.

Then, the drain current I ₂ of the transistor Tr ₂ flows to the light emitting element 104.
The current flowing through the light emitting element has a magnitude corresponding to the signal current Ic determined by the constant current source 107, and the light emitting element 104 emits light with a luminance corresponding to the magnitude of the flowing current. The light emitting element 104 does not emit light when the current flowing through the light emitting element is as close as possible to zero or when the current flowing through the light emitting element flows in the direction of reverse bias.

When the writing period Ta ends, the selection of the scanning line for each line ends. When the writing period Ta ends in the pixels of each line, the display period Td starts in the pixels of each line. FIG. 3B is a schematic diagram of pixels in the display period Td. The transistors Tr3 and Tr4 are in an off state.
The source regions of the transistors Tr3 and Tr4 are connected to the power supply line Vi and are kept at a constant voltage (power supply voltage).

In the display period Td, the drain region of the transistor Tr1 is in a so-called floating state in which no potential is applied from another wiring, a power source, or the like. On the other hand, in the transistor Tr2, V _GS determined in the writing period Ta is maintained as it is. Therefore, the value of the drain current I ₂ of the transistor Tr2 is maintained at Ic. Therefore, in the display period Td, the OLED 104 emits light with a luminance corresponding to the magnitude of the current determined in the writing period Ta.

  Note that the display period Td always appears immediately after the writing period Ta. Immediately after the display period Td, the next writing period Ta appears or the reverse bias period Ti appears.

  When the reverse bias period starts, the voltages of the power supply lines V1 to Vx are kept high enough to apply a reverse bias voltage to the light emitting element when the transistor Tr2 is turned on. Then, the scanning line driving circuit 103 sequentially selects each scanning line, and the transistors Tr3 and Tr4 are turned on. Then, the signal line driving circuit 102 applies a voltage that turns on the transistor Tr2 to each of the signal lines S1 to Sx.

  FIG. 3C is a schematic diagram of the pixel 101 in the reverse bias period Ti. In the reverse bias period Ti, since Tr2 is turned on, the voltage of the power supply line Vi is applied to the pixel electrode of the light emitting element 104, and thus the reverse bias voltage is applied to the light emitting element 104. The light emitting element 104 does not emit light when a reverse bias voltage is applied.

  Note that the voltage of the power supply line only needs to be high enough to apply a reverse bias voltage to the light-emitting element when the transistor Tr2 is turned on. In addition, the length of the reverse bias period Ti can be appropriately set by the designer in consideration of the balance with the duty ratio (the ratio of the total length of the display periods in one frame period).

  In the case of a time grayscale driving method (digital driving method) using a digital video signal, a writing period Ta and a display period Td corresponding to the digital video signal of each bit repeatedly appear in one frame period. An image can be displayed. For example, when an image is displayed by an n-bit video signal, at least n writing periods and n display periods are provided in one frame period. The n writing periods (Ta1 to Tan) and the n display periods (Td1 to Tdn) correspond to each bit of the video signal.

  For example, next to the writing period Tam (m is an arbitrary number from 1 to n), a display period corresponding to the same number of bits, in this case, Tdm appears. The writing period Ta and the display period Td are collectively called a subframe period SF. A subframe period having a writing period Tam and a display period Tdm corresponding to the m-th bit is SFm.

  When the digital video signal is used, the reverse bias period Ti may be provided immediately after the display periods Td1 to Tdn, or may be provided immediately after the display period that appears at the end of one frame period among Td1 to Tdn. good. Further, it is not always necessary to provide the reverse bias period Ti for each frame period, and it may be caused to appear every several frame periods. It is possible for the designer to set as appropriate when the number of reverse bias periods Ti appears.

  In FIG. 4, when the reverse bias period Ti appears at the end of one frame period, the voltage applied to the scanning line in the pixel (i, j), the voltage applied to the power supply line, and the light emitting element are applied. The timing chart of the voltage to be performed is shown. FIG. 4 shows a case where Tr3 and Tr4 are both n-channel TFTs, and Tr1 and Tr2 are p-channel TFTs. In each writing period Ta1 to Tan and reverse bias period Ti, the scanning line Gj is selected and Tr3 and Tr4 are turned on. In each display period Td1 to Tdn, the scanning line Gj is not selected and Tr3 and Tr4 are selected. Is turned off. In addition, the voltage of the power supply line Vi is maintained at such a high level that a forward bias current flows through the light emitting element 104 when Tr2 is on in each of the writing periods Ta1 to Tan and each of the display periods Td1 to Tdn. . In the reverse bias period Ti, the voltage of the power supply line Vi is kept high enough to apply a reverse bias voltage to the light emitting element 104. The applied voltage of the light emitting element is maintained at the forward bias in each of the writing periods Ta1 to Tan and the display periods Td1 to Tdn, and is maintained at the reverse bias in the reverse bias period Ti.

The length of the subframe period SF1~SFn is, SF1: SF2: ...: SFn = 2 0: 2 1: ...: meet 2 ^n-1.

  Whether or not the light emitting element emits light in each subframe period is selected by each bit of the digital video signal. Then, the number of gradations can be controlled by controlling the sum of the lengths of the display periods during which light is emitted during one frame period.

  Note that a subframe period having a long display period may be divided into several parts in order to improve image quality on display. The specific division method is disclosed in Japanese Patent Application No. 2000-267164, and can be referred to.

  Further, gradation may be displayed in combination with area gradation.

  When displaying gradation using an analog video signal, one frame period ends when the writing period Ta and the display period Td end. One image is displayed in one frame period. Then, the next frame period is started, the writing period Ta is started again, and the above-described operation is repeated.

  When an analog video signal is used, the reverse bias period Ti is provided immediately after the display period Td. Further, it is not always necessary to provide the reverse bias period Ti for each frame period, and it may be caused to appear every several frame periods. The designer can appropriately set when the reverse bias period Ti appears.

  According to the present invention, even when the characteristics of the transistor Tr2 vary from pixel to pixel, it is possible to prevent the luminance of the light emitting element from varying between the pixels as compared with the general light emitting device shown in FIG. Further, as compared with the case where the TFT 51 of the voltage input type pixel shown in FIG. 23 is operated in a linear region, a reduction in luminance due to deterioration of the light emitting element can be suppressed. Even if the temperature of the organic light emitting layer depends on the outside air temperature, heat generated by the light emitting panel itself, etc., it is possible to suppress the luminance of the light emitting element from changing, and the current consumption increases as the temperature increases. Can be prevented.

  Note that in this embodiment, one of the first terminal and the second terminal of the transistor Tr4 is connected to the signal line Si, and the other is connected to the gate of the transistor Tr1 and the gate of the transistor Tr2. However, the present embodiment is not limited to this configuration. In the pixel of the present invention, the transistor Tr4 is connected to another element so that the gate of the transistor Tr1 and the second terminal can be connected in the writing period Ta and the gate of the transistor Tr1 and the second terminal can be disconnected in the display period Td. Or what is necessary is just to be connected with wiring. That is, Tr3 and Tr4 are connected as shown in FIG. 3A during the writing period Ta, connected as shown in FIG. 3B during the display period Td, and as shown in FIG. 3C during the reverse bias period Ti. It only has to be connected.

Note that the light-emitting element used in this embodiment is a material in which a hole injection layer, an electron injection layer, a hole transport layer, an electron transport layer, or the like is an inorganic compound alone or an organic compound is mixed with an inorganic compound. The formed form can also be taken. These layers may be partially mixed with each other.

Examples of the present invention will be described below.

In this embodiment, the case where the reverse bias period Ti appears at a timing different from that in FIG. 4 in the pixel shown in FIG. 2 will be described. The driving method of this embodiment will be described with reference to FIG.

  FIG. 5 shows a timing chart of the voltage applied to the scanning line, the voltage applied to the power supply line, and the voltage applied to the light emitting element in the pixel (i, j) of this embodiment. FIG. 5 shows a case where Tr3 and Tr4 are both n-channel TFTs and Tr1 and Tr2 are p-channel TFTs.

A length obtained by adding all of the writing periods Ta1 to Tan and the display periods Td1 to Tdn is T_1, and a voltage difference between the power supply line Vi and the counter electrode of the light emitting element in the period is V_1. The length of the reverse bias period Ti is T_2, and the voltage difference between the power supply line Vi and the counter electrode of the light emitting element in the period is V_2. In this embodiment, the voltage of the power supply line Vi is kept high enough to satisfy T_1 × V_1 = T_2 × V_2.
Further, the voltage of the power supply line Vi is kept high enough to apply a reverse bias voltage to the light emitting element 104.

An ionic impurity present in the organic light emitting layer is close to one of the electrodes, so that a part of the organic light emitting layer has a lower resistance than the other, and the part with a low resistance is positive. It is considered that the deterioration of the organic light emitting layer is promoted by the current flowing through In the present invention, by using inversion driving, it is possible to prevent ionic impurities from approaching one of the electrodes and to suppress deterioration of the organic light emitting layer. In particular, in this embodiment, with the above configuration, it is possible to prevent the bias of impurity ions to one of the electrodes, and to further suppress deterioration of the organic light emitting layer, rather than simply performing inversion driving.

  In this embodiment, the case where the reverse bias period Ti appears in the pixel shown in FIG. 2 at a timing different from those in FIGS. 4 and 5 will be described. The driving method of this embodiment will be described with reference to FIG.

  FIG. 6 shows a timing chart of the voltage applied to the scanning line, the voltage applied to the power supply line, and the voltage applied to the light emitting element in the pixel (i, j) of this embodiment. FIG. 6 shows a case where Tr3 and Tr4 are both n-channel TFTs, and Tr1 and Tr2 are p-channel TFTs.

  In this embodiment, the reverse bias periods Ti1 to Tin appear immediately after the display periods Td1 to Tdn, in other words, immediately after the subframe periods, respectively. For example, the display period Tdm appears immediately after the write period Tam in the m (m = 1 to n) arbitrary subframe period SFm, and the reverse bias period Tim appears immediately after the display period Tdm. become.

In this embodiment, the lengths of the reverse bias periods Ti1 to Tin are all the same, and the height of the power supply line Vi in each period is also the same. However, the present invention is not limited to this configuration. The length and voltage of each reverse bias period Ti1 to Tin can be set as appropriate by the designer.

  In this embodiment, the case where the reverse bias period Ti appears in the pixel shown in FIG. 2 at a timing different from that in FIGS. 4, 5, and 6 will be described. The driving method of this embodiment will be described with reference to FIG.

  FIG. 7 shows a timing chart of the voltage applied to the scanning line, the voltage applied to the power supply line, and the voltage applied to the light emitting element in the pixel (i, j) of this embodiment. FIG. 7 shows a case where Tr3 and Tr4 are both n-channel TFTs, and Tr1 and Tr2 are p-channel TFTs.

  In this embodiment, the reverse bias periods Ti1 to Tin appear immediately after the display periods Td1 to Tdn, in other words, immediately after the subframe periods, respectively. For example, the display period Tdm appears immediately after the write period Tam in the m (m = 1 to n) arbitrary subframe period SFm, and the reverse bias period Tim appears immediately after the display period Tdm. become.

  Furthermore, in this embodiment, the length of the reverse bias periods Ti1 to Tin is longer as the length of the display period that appears immediately before is longer. The height of the power supply line Vi in each period is also the same height. With the above configuration, it is possible to prevent the organic light emitting layer from being further deteriorated as compared with the driving methods shown in FIGS.

  In this embodiment, a case will be described in which the reverse bias period Ti appears in the pixel shown in FIG. 2 at a timing different from those in FIGS. The driving method of this embodiment will be described with reference to FIG.

  FIG. 8 shows a timing chart of the voltage applied to the scanning line, the voltage applied to the power supply line, and the voltage applied to the light emitting element in the pixel (i, j) of this embodiment. FIG. 8 shows a case where Tr3 and Tr4 are both n-channel TFTs and Tr1 and Tr2 are p-channel TFTs.

  In this embodiment, the reverse bias periods Ti1 to Tin appear immediately after the display periods Td1 to Tdn, in other words, immediately after the subframe periods, respectively. For example, the display period Tdm appears immediately after the write period Tam in the m (m = 1 to n) arbitrary subframe period SFm, and the reverse bias period Tim appears immediately after the display period Tdm. become.

  Furthermore, in this embodiment, the absolute value of the voltage difference between the voltage of the power supply line Vi and the counter electrode of the light emitting element in each reverse bias period becomes larger as the length of the display period appearing immediately before is longer. The lengths of the reverse bias periods Ti1 to Tin are all the same. With the above configuration, it is possible to prevent the organic light emitting layer from being further deteriorated compared to the pixels shown in FIGS. 4, 5, and 6.

  In this embodiment, a structure of a signal line driver circuit and a scan line driver circuit included in the light-emitting device of the present invention driven by a digital video signal will be described.

  FIG. 9 is a block diagram illustrating the configuration of the signal line driver circuit 102. 102a is a shift register, 102b is a storage circuit A, 102c is a storage circuit B, 102d is a current conversion circuit, and 102e is a switching circuit.

  A clock signal CLK and a start pulse signal SP are input to the shift register 102a. In addition, a digital video signal (Digital Video Signals) is input to the memory circuit A 102b, and a latch signal (Latch Signals) is input to the memory circuit B 102c. A switching signal (Select Signals) is input to the switching circuit 102e. Hereinafter, the operation of each circuit will be described in detail according to the signal flow.

  When the clock signal CLK and the start pulse signal SP are input to the shift register 102a from a predetermined wiring, a timing signal is generated. The timing signal is input to each of the plurality of latches A (LATA_1 to LATA_x) included in the memory circuit A102b. Note that at this time, the timing signal generated in the shift register 102a may be buffered and amplified by a buffer or the like and then input to each of the plurality of latches A (LATA_1 to LATA_x) included in the memory circuit A102b.

  When a timing signal is input to the memory circuit A 102b, a 1-bit digital video signal input to the video signal line 130 is sequentially input to each of the plurality of latches A (LATA_1 to LATA_x) in synchronization with the timing signal. Written and retained.

In this embodiment, digital video signals are sequentially written in the memory circuit A (LATA_1 to LATA_x) 102b. However, the present invention is not limited to this configuration.
A plurality of stages of latches included in the memory circuit A 102b may be divided into several groups, and so-called divided driving may be performed in which digital video signals are input simultaneously in parallel for each group. Note that the number of groups at this time is called the number of divisions. For example, when the latches are divided into groups for every four stages, it is said that the driving is divided into four.

  The time until the digital video signal is completely written to the latches of all the stages of the memory circuit A 102b is called a line period. Actually, the line period may include a period in which a horizontal blanking period is added to the line period.

When one line period ends, a latch signal (Latch Signal) is supplied to the plurality of latches B (LATB_1 to LATB_x) included in the memory circuit B102c through the latch signal line 131. At this moment, the digital video signals held in the plurality of latches A (LATA_1 to LATA_x) included in the memory circuit A102b are converted into the plurality of latches B (LATB_1 to LATB_x) included in the memory circuit B102c.
Are simultaneously written and retained.

  After the digital video signal has been sent to the storage circuit B 102c, the next 1-bit digital video signal is sequentially written in synchronization with the timing signal from the shift register 102a again. During the second line of one line period, the digital video signal written and held in the memory circuit B 102c is input to the current conversion circuit 102d.

  The current conversion circuit 102d has a plurality of current setting circuits (C1 to Cx). In each of the current setting circuits (C1 to Cx), the magnitude of the signal current Ic supplied to the subsequent switching circuit 102e is determined based on 1 or 0 information included in the input digital video signal. Specifically, the signal current Ic has such a magnitude that the light emitting element emits light or does not emit light.

  In the switching circuit 102e, according to the switching signal (Select Signals) input from the switching signal line 132, whether the signal current Ic is supplied to the signal line or a voltage that turns on the transistor Tr2 is supplied to the signal line. Selected.

  FIG. 10 shows an example of specific configurations of the current setting circuit C1 and the switching circuit D1. The current setting circuits C2 to Cx have the same configuration as the current setting circuit C1. The switching circuits D2 to Dx also have the same configuration as the switching circuit D1.

  The current setting circuit C1 includes a constant current source 631, four transmission gates SW1 to SW4, and two inverters Inb1 and Inb2. Note that the polarity of the transistor 650 included in the constant current source 631 is the same as the polarity of the transistors Tr1 and Tr2 included in the pixel.

  Switching of SW1 to SW4 is controlled by a digital video signal output from LATB_1 included in the memory circuit B102c. The digital video signal input to SW1 and SW3 and the digital video signal input to SW2 and SW4 are inverted by Inb1 and Inb2. Therefore, SW2 and SW4 are off when SW1 and SW3 are on, and SW2 and SW4 are on when SW1 and SW3 are off.

  When SW1 and SW3 are ON, a current Id having a predetermined value other than 0 is input from the constant current source 631 to the switching circuit D1 as the signal current Ic through SW1 and SW3.

  Conversely, when SW2 and SW4 are on, the current Id from the constant current source 631 is grounded through SW2. Further, the power supply voltages of the power supply lines V1 to Vx are supplied to the switching circuit D1 through SW4, and Ic≈0.

  The switching circuit D1 has two transmission gates SW5 and SW6 and one inverter Inb3. The switching of SW5 and SW6 is controlled by a switching signal. Since the polarity of the switching signal input to each of SW5 and SW6 is inverted by the inverter Inb3, SW6 is turned off when SW5 is on, and SW6 is turned on when SW5 is off. When SW5 is on, the signal current Ic is input to the signal line S1, and when SW6 is on, a voltage that turns on the transistor Tr2 is applied to the signal line S1.

  Referring to FIG. 9 again, the above operation is simultaneously performed in all the current setting circuits (C1 to Cx) included in current conversion circuit 102d within one line period. Therefore, the value of the signal current Ic input to all the signal lines is selected by the digital video signal.

  The drive circuit used in the present invention is not limited to the configuration shown in this embodiment. Further, the current conversion circuit shown in this embodiment is not limited to the configuration shown in FIG. The current conversion circuit used in the present invention can select any one of the binary values that can be taken by the signal current Ic by a digital video signal and supply a signal current having the selected value to the signal line. You may have the structure. Further, the switching circuit is not limited to the configuration shown in FIG. 10, and is a circuit that can select whether the signal current Ic is input to the signal line or a voltage that turns on the transistor Tr2 is input to the signal line. I need it.

  Instead of the shift register, another circuit capable of selecting a signal line such as a decoder circuit may be used.

  Next, the configuration of the scanning line driving circuit will be described.

  FIG. 11 is a block diagram showing a configuration of the scanning line driving circuit 641. The scanning line driver circuit 641 includes a shift register 642 and a buffer 643, respectively. In some cases, a level shifter may be provided.

  In the scan line driver circuit 641, when the clock CLK and the start pulse signal SP are input to the shift register 642, a timing signal is generated. The generated timing signal is buffered and amplified in the buffer 643 and supplied to the corresponding scanning line.

  The gate of the transistor of the pixel for one line is connected to the scanning line. Since the transistors of the pixels for one line must be turned on all at once, a buffer 643 that can flow a large current is used.

  Note that the scan line driver circuit included in the light-emitting device of the present invention is not limited to the structure shown in FIG. For example, instead of the shift register, another circuit capable of selecting a scanning line such as a decoder circuit may be used.

  The structure of a present Example can be implemented in combination freely with Examples 1-4.

  In this embodiment, a structure of a signal line driver circuit included in the light emitting device of the present invention driven by an analog driving method will be described. Note that the structure shown in Embodiment 5 can be used as the structure of the scanning line driver circuit, and thus the description thereof is omitted here.

  FIG. 12 is a block diagram of the signal line driver circuit 401 of this embodiment. Reference numeral 402 denotes a shift register, 403 denotes a buffer, 404 denotes a sampling circuit, 405 denotes a current conversion circuit, and 406 denotes a switching circuit 406.

  A clock signal (CLK) and a start pulse signal (SP) are input to the shift register 402. When a clock signal (CLK) and a start pulse signal (SP) are input to the shift register 402, a timing signal is generated.

  The generated timing signal is amplified or buffer amplified in the buffer 403 and input to the sampling circuit 404. Note that a level shifter may be provided instead of the buffer to amplify the timing signal. Further, both a buffer and a level shifter may be provided.

  In the sampling circuit 404, the analog video signal input from the video signal line 430 is input to the subsequent current conversion circuit 405 in synchronization with the timing signal.

  In the current conversion circuit, a signal current Ic having a magnitude corresponding to the voltage of the input analog video signal is generated and input to the subsequent switching circuit 406. The switching circuit 406 selects whether to input the signal current Ic to the signal line or to input a voltage that turns off the transistor Tr2 to the signal line.

  FIG. 13 shows specific configurations of the sampling circuit 404 and the current setting circuits (C1 to Cx) included in the current conversion circuit 405. Note that the sampling circuit 404 is connected to the buffer 403 at a terminal 410.

  The sampling circuit 404 is provided with a plurality of switches 411. An analog video signal is input from the video signal line 406 to the sampling circuit 404, and the switch 411 samples the analog video signal in synchronization with the timing signal and inputs the analog video signal to the subsequent current setting circuit C1. In FIG. 13, C1 which is one of the current setting circuits C1 to Cx shows only the current setting circuit C1 connected to one of the switches 411 included in the sampling circuit 404, but in the subsequent stage of each switch 411. Assume that a current setting circuit C1 as shown in FIG. 13 is connected.

  In this embodiment, only one transistor is used for the switch 411. However, the switch 411 may be any switch that can sample an analog video signal in synchronization with the timing signal, and is not limited to the configuration of this embodiment.

  The sampled analog video signal is input to the current output circuit 412 included in the current setting circuit C1. The current output circuit 412 outputs a current (signal current) having a value corresponding to the voltage of the input video signal. In FIG. 12, an amplifier and a transistor are used to form a current output circuit. However, the present invention is not limited to this configuration, and a circuit that can output a current having a value corresponding to the voltage of an input signal. I need it.

  The signal current is also input to the reset circuit 417 included in the current setting circuit C1. The reset circuit 417 includes two transmission gates 413 and 414 and an inverter 416.

  A reset signal (Res) is input to the transmission gate 414, and a reset signal (Res) inverted by the inverter 416 is input to the transmission gate 413. The transmission gate 413 and the transmission gate 414 operate in synchronization with the inverted reset signal and reset signal, respectively, and when one is on, one is off.

  When the transmission gate 413 is on, the signal current is input to the subsequent switching circuit D1. Conversely, when the transmission gate 414 is on, the voltage of the power source 415 is applied to the subsequent switching circuit D1. Note that the signal line is desirably reset during the return period. However, if it is outside the period during which the image is displayed, it can be reset to a period other than the blanking period as necessary.

  The switching circuit D1 has two transmission gates SW1 and SW2 and one inverter Inb. SW1 and SW2 are controlled by a switching signal. Since the polarity of the switching signal input to each of SW1 and SW2 is inverted by the inverter Inb, SW2 is off when SW1 is on, and SW2 is on when SW1 is off. A signal current Ic is input to the signal line S1 when SW1 is on, and a voltage is applied to the signal line S1 to turn on the transistor Tr2 when SW2 is on.

  Instead of the shift register, another circuit capable of selecting a signal line such as a decoder circuit may be used.

  The signal line driver circuit for driving the light-emitting device of the present invention is not limited to the structure shown in this embodiment. The configuration of the present embodiment can be implemented by freely combining the configurations shown in Embodiments 1 to 4.

  In the present invention, by using an organic light emitting material that can utilize phosphorescence from triplet excitons for light emission, the external light emission quantum efficiency can be dramatically improved. This makes it possible to reduce the power consumption, extend the life, and reduce the weight of the light emitting element.

Here, a report of using triplet excitons to improve the external emission quantum efficiency is shown.
(T. Tsutsui, C. Adachi, S. Saito, Photochemical Processes in Organized Molecular Systems, ed. K. Honda, (Elsevier Sci. Pub., Tokyo, 1991) p.437.)
The molecular formula of the organic light-emitting material (coumarin dye) reported by the above paper is shown below.

(MABaldo, DFO'Brien, Y.You, A.Shoustikov, S.Sibley, METhompson, SRForrest, Nature 395 (1998) p.151.)
The molecular formula of the organic light-emitting material (Pt complex) reported by the above paper is shown below.

  (MABaldo, S. Lamansky, PEBurrrows, METhompson, SRForrest, Appl.Phys.Lett., 75 (1999) p.4.) (T.Tsutsui, M.-J.Yang, M.Yahiro, K .Nakamura, T.Watanabe, T.tsuji, Y.Fukuda, T.Wakimoto, S.Mayaguchi, Jpn.Appl.Phys., 38 (12B) (1999) L1502.)

The molecular formula of the organic light-emitting material (Ir complex) reported by the above paper is shown below.

  As described above, if phosphorescence emission from triplet excitons can be used, in principle, it is possible to realize an external emission quantum efficiency that is 3 to 4 times higher than that in the case of using fluorescence emission from singlet excitons.

  In addition, the structure of a present Example can be implemented in combination freely with any structure of Example 1- Example 6. FIG.

  Organic light-emitting materials used for OLEDs are roughly classified into low molecular weight systems and high molecular weight systems. The light emitting device of the present invention can be used with either a low molecular weight organic light emitting material or a high molecular weight organic light emitting material.

  The low molecular weight organic light emitting material is formed by a vapor deposition method. Therefore, it is easy to take a laminated structure, and it is easy to increase efficiency by laminating films having different functions such as a hole transport layer and an electron transport layer.

Examples of the low molecular weight organic light emitting material include an aluminum complex Alq ₃ having quinolinol as a ligand, a triphenylamine derivative (TPD), and the like.

  On the other hand, a high molecular organic light emitting material has higher physical strength and higher device durability than a low molecular material. In addition, since the film can be formed by coating, the device can be manufactured relatively easily.

  The structure of a light emitting element using a high molecular weight organic light emitting material is basically the same as that when a low molecular weight organic light emitting material is used, and is a cathode / organic light emitting layer / anode. However, when forming an organic light emitting layer using a high molecular weight organic light emitting material, it is difficult to form a laminated structure as in the case of using a low molecular weight organic light emitting material. The two-layer structure is famous. Specifically, the structure is cathode / light-emitting layer / hole transport layer / anode. In the case of a light emitting element using a polymer organic light emitting material, Ca can also be used as a cathode material.

  Note that since the color of light emitted from the element is determined by the material for forming the light-emitting layer, a light-emitting element exhibiting desired light emission can be formed by selecting them. Examples of the polymer organic light emitting material that can be used for forming the light emitting layer include polyparaphenylene vinylene, polyparaphenylene, polythiophene, and polyfluorene.

  The polyparaphenylene vinylene system includes derivatives of poly (paraphenylene vinylene) [PPV], poly (2,5-dialkoxy-1,4-phenylene vinylene) [RO-PPV], poly (2- (2′- Ethyl-hexoxy) -5-methoxy-1,4-phenylenevinylene) [MEH-PPV], poly (2- (dialkoxyphenyl) -1,4-phenylenevinylene) [ROPh-PPV] and the like.

  The polyparaphenylene series includes derivatives of polyparaphenylene [PPP], poly (2,5-dialkoxy-1,4-phenylene) [RO-PPP], poly (2,5-dihexoxy-1,4-phenylene). ) And the like.

The polythiophene series includes polythiophene [PT] derivatives, poly (3-alkylthiophene) [PAT], poly (3-hexylthiophene) [PHT], poly (3-cyclohexylthiophene) [PCHT], poly (3-cyclohexyl). -4-methylthiophene) [PCHMT], poly (3,4-dicyclohexylthiophene) [PDCHT], poly [3- (4-octylphenyl) -thiophene]
[POPT], poly [3- (4-octylphenyl) -2,2bithiophene] [PTOPT] and the like.

  Examples of the polyfluorene series include polyfluorene [PF] derivatives, poly (9,9-dialkylfluorene) [PDAF], poly (9,9-dioctylfluorene) [PDOF], and the like.

  Note that when a hole-transporting polymer-based organic light-emitting material is sandwiched between an anode and a light-emitting polymer-based organic light-emitting material, hole injection properties from the anode can be improved. In general, an acceptor material dissolved in water is applied by spin coating or the like. In addition, since it is insoluble in an organic solvent, it can be stacked with the above-described light-emitting organic light-emitting material.

  Examples of the hole-transporting polymer organic light emitting material include a mixture of PEDOT and camphor sulfonic acid (CSA) as an acceptor material, a mixture of polyaniline [PANI] and polystyrene sulfonic acid [PSS] as an acceptor material, and the like. It is done.

  In addition, the structure of a present Example can be implemented in combination with Example 1-7.

  In this example, a method for manufacturing a light-emitting device of the present invention will be described. Note that in this embodiment, a method for manufacturing the pixel illustrated in FIGS. Further, in this embodiment, only a cross-sectional view of the transistors Tr2 and Tr3 included in the pixel is shown, but the transistors Tr1 and Tr4 can be formed by referring to the manufacturing method of this embodiment. In this embodiment, an example in which a TFT included in a driver circuit (a signal line driver circuit or a scanning line driver circuit) provided around the pixel portion is formed over the same substrate as the TFT in the pixel portion is shown.

First, as shown in FIG. 14A, a silicon oxide film is formed on a substrate 301 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass, or aluminoborosilicate glass. A base film 302 made of an insulating film such as a silicon nitride film or a silicon oxynitride film is formed. For example, a silicon oxynitride film 302a made of SiH ₄ , NH ₃ , and N ₂ O is formed by plasma CVD method to a thickness of 10 to 200 nm (preferably 50 to 100 nm), and similarly, made of SiH ₄ and N ₂ O. A silicon oxynitride silicon film 302b is stacked to a thickness of 50 to 200 nm (preferably 100 to 150 nm). Although the base film 302 is shown as a two-layer structure in this embodiment, it may be formed as a single layer film of the insulating film or a structure in which two or more layers are stacked.

The island-shaped semiconductor layers 303 to 306 are formed using a crystalline semiconductor film in which a semiconductor film having an amorphous structure is formed using a laser crystallization method or a known thermal crystallization method. The thickness of the island-like semiconductor layers 303 to 306 is 25 to 80 nm (preferably 30 to 60 nm).
The thickness is formed. There is no limitation on the material of the crystalline semiconductor film, but the crystalline semiconductor film is preferably formed of silicon or a silicon germanium (SiGe) alloy.

In the case of manufacturing a crystalline semiconductor film by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, YAG laser, or YVO ₄ laser is used. In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor film. The conditions for crystallization are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 300 Hz and the laser energy density is 100 to 400 mJ / cm ² (typically 200 to 300 mJ / cm ^2). ). When a YAG laser is used, the second harmonic is used and the pulse oscillation frequency is 30 to 300 kHz, and the laser energy density is 300 to 600 mJ / cm ² (typically 350 to 500 mJ / cm ² ). Then, laser light condensed linearly with a width of 100 to 1000 μm, for example, 400 μm, is irradiated over the entire surface of the substrate, and the superposition ratio (overlap ratio) of the linear laser light at this time is 50 to 90%.

As the laser, a continuous wave or pulsed gas laser or solid-state laser can be used. Examples of gas lasers include excimer laser, Ar laser, and Kr laser. Examples of solid-state lasers include YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, alexandride laser, and Ti: sapphire laser. Can be mentioned. As a solid-state laser, a laser using a crystal such as YAG, YVO ₄ , YLF, YAlO ₃ doped with Cr, Nd, Er, Ho, Ce, Co, Ti, or Tm can be used. The fundamental wave of the laser differs depending on the material to be doped, and laser light having a fundamental wave of around 1 μm can be obtained. The harmonic with respect to the fundamental wave can be obtained by using a nonlinear optical element.

  Furthermore, after converting infrared laser light emitted from a solid-state laser into green laser light using a nonlinear optical element, ultraviolet laser light obtained by another nonlinear optical element can also be used.

In crystallization of the amorphous semiconductor film, in order to obtain a crystal with a large grain size, it is preferable to apply a second to fourth harmonic of the fundamental wave using a solid-state laser capable of continuous oscillation. Typically, it is desirable to apply the second harmonic (532 nm) or the third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm). Specifically, laser light emitted from a continuous wave YVO ₄ laser having an output of 10 W is converted into a harmonic by a non-linear optical element. There is also a method of emitting harmonics by putting a YVO ₄ crystal and a nonlinear optical element in a resonator. Then, it is preferably formed into a rectangular or elliptical laser beam on the irradiation surface by an optical system, and irradiated to the object to be processed. At this time, the energy density of approximately 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed by moving the semiconductor film relative to the laser light at a speed of about 10 to 2000 cm / s.

Next, a gate insulating film 307 covering the island-shaped semiconductor layers 303 to 306 is formed.
The gate insulating film 307 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film is formed with a thickness of 120 nm. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O ₂ are mixed by a plasma CVD method to obtain a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (13.56 MHz).
It can be formed by discharging at a power density of 0.5 to 0.8 W / cm ² . The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by thermal annealing at 400 to 500 ° C. thereafter.

  Then, a first conductive film 308 and a second conductive film 309 for forming a gate electrode are formed over the gate insulating film 307. In this embodiment, the first conductive film 308 is formed with Ta to a thickness of 50 to 100 nm, and the second conductive film 309 is formed with W to a thickness of 100 to 300 nm.

  The Ta film is formed by sputtering, and a Ta target is sputtered with Ar. In this case, when an appropriate amount of Xe or Kr is added to Ar, the internal stress of the Ta film can be relieved and peeling of the film can be prevented. The resistivity of the α-phase Ta film is about 20 μΩcm and can be used as a gate electrode, but the resistivity of the β-phase Ta film is about 180 μΩcm and is not suitable for a gate electrode. In order to form an α-phase Ta film, tantalum nitride having a crystal structure close to Ta's α-phase is formed on a Ta base with a thickness of about 10 to 50 nm, so that an α-phase Ta film is easily obtained. I can do it.

When forming a W film, it is formed by sputtering using W as a target. In addition, it can also be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and the resistivity of the W film is desirably 20 μΩcm or less. Although the resistivity of the W film can be reduced by increasing the crystal grains, if the impurity element such as oxygen is large in W, the crystallization is hindered and the resistance is increased. Therefore, in the case of sputtering, a W film having a purity of 99.9999% or 99.99% is used, and a W film is formed with sufficient consideration so that impurities are not mixed in the gas phase during film formation. By doing so, a resistivity of 9 to 20 μΩcm can be realized.

  In this embodiment, the first conductive film 308 is Ta and the second conductive film 309 is W. However, the present invention is not particularly limited, and any of them is selected from Ta, W, Ti, Mo, Al, Cu, and the like. Or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. As another example of a combination other than the present embodiment, a combination in which the first conductive film 308 is formed of tantalum nitride (TaN) and the second conductive film 309 is W is used. Is made of tantalum nitride (TaN), the second conductive film 309 is made of Al, the first conductive film 308 is made of tantalum nitride (TaN), and the second conductive film 309 is made of Cu. Can be mentioned. (Fig. 14 (A))

Next, a resist mask 310 is formed, and a first etching process is performed to form electrodes and wirings. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used, CF ₄ and Cl ₂ are mixed in an etching gas, and 500 W RF (13.56 MHz) is applied to a coil type electrode at a pressure of 1 Pa. Power is applied to generate plasma. 100 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. When CF ₄ and Cl ₂ are mixed, the W film and the Ta film are etched to the same extent.

Under the above etching conditions, by making the shape of the resist mask suitable, the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is 15 to 45 °.
In order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%. Since the selection ratio of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the surface where the silicon oxynitride film is exposed is etched by about 20 to 50 nm by the overetching process. Thus, the first shape conductive layers 311 to 314 (the first conductive layers 311a to 314a and the second conductive layers 311b to 314b) formed of the first conductive layer and the second conductive layer by the first etching process. Form. At this time, in the gate insulating film 307, a region which is not covered with the first shape conductive layers 311 to 314 is etched and thinned by about 20 to 50 nm. The surface of the mask 310 was also etched by the above etching.

Then, an impurity element imparting n-type is added by performing a first doping process.
As a doping method, an ion doping method or an ion implantation method may be used. The conditions of the ion doping method are a dose amount of 1 × 10 ^{13 to} 5 × 10 ¹⁴ atoms / cm ² and an acceleration voltage of 60 to 100 keV. As an impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As), is used here, but phosphorus (P) is used. In this case, the conductive layers 311 to 314 serve as a mask for the impurity element imparting n-type, and the first impurity regions 317 to 320 are formed in a self-aligning manner. An impurity element imparting n-type conductivity is added to the first impurity regions 317 to 320 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ . (Fig. 14B)

Next, as shown in FIG. 14C, a second etching process is performed without removing the resist mask 310. The W film is selectively etched using CF ₄ , Cl ₂ and O _{2 as an} etching gas. At this time, second shape conductive layers 325 to 328 (first conductive layers 325a to 328a and second conductive layers 325b to 328b) are formed by the second etching process. At this time, in the gate insulating film 307, a region that is not covered with the second shape conductive layers 325 to 328 is further etched and thinned by about 20 to 50 nm.

The etching reaction of the W film or Ta film with the mixed gas of CF ₄ and Cl ₂ can be estimated from the generated radicals or ion species and the vapor pressure of the reaction product. When the vapor pressures of W and Ta fluorides and chlorides are compared, WF ₆ which is a fluoride of W is extremely high, and other WCl ₅ , TaF ₅ and TaCl ₅ are similar. Therefore, both the W film and the Ta film are etched with a mixed gas of CF ₄ and Cl ₂ . However, when an appropriate amount of O ₂ is added to this mixed gas, CF ₄ and O ₂ react to form CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure is increased. On the other hand, the increase in etching rate of Ta is relatively small even when F increases. Further, since Ta is more easily oxidized than W, the surface of Ta is oxidized by adding O ₂ . Since the Ta oxide does not react with fluorine or chlorine, the etching rate of the Ta film further decreases. Therefore, it is possible to make a difference in the etching rate between the W film and the Ta film, and the etching rate of the W film can be made larger than that of the Ta film.

Then, a second doping process is performed as shown in FIG. In this case, an impurity element imparting n-type conductivity is doped as a condition of a high acceleration voltage by lowering the dose than in the first doping process. For example, the acceleration voltage is set to 70 to 120 keV and the dose is 1 × 10 ¹³ atoms / cm ^2. A new impurity region is formed inside the first impurity region formed in the island-shaped semiconductor layer in FIG. 14B. Form. Doping is performed using the second shape conductive layers 325 to 328 as masks against the impurity elements so that the impurity elements are also added to regions below the first conductive layers 325 a to 328 a. Thus, third impurity regions 332 to 335 are formed. The concentration of phosphorus (P) added to the third impurity regions 332 to 335 has a gradual concentration gradient according to the film thickness of the tapered portions of the first conductive layers 325a to 328a. Note that, in the semiconductor layer overlapping the tapered portions of the first conductive layers 325a to 328a, although the impurity concentration slightly decreases inward from the end portions of the tapered portions of the first conductive layers 325a to 328a, The concentration is similar.

A third etching process is performed as shown in FIG. CHF ₆ is used as an etching gas and a reactive ion etching method (RIE method) is used. By the third etching treatment, the tapered portions of the first conductive layers 325a to 328a are partially etched, so that a region where the first conductive layer overlaps with the semiconductor layer is reduced. By the third etching treatment, third-shaped conductive layers 336 to 339 (first conductive layers 336a to 339a and second conductive layers 336b to 339b) are formed. At this time, in the gate insulating film 307, a region that is not covered with the third shape conductive layers 336 to 339 is further etched and thinned by about 20 to 50 nm.

  By the third etching process, in the third impurity regions 332 to 335, the third impurity regions 332 a to 335 a overlapping with the first conductive layers 336 a to 339 a, the first impurity region, the third impurity region, Second impurity regions 332b to 335b are formed.

Then, as shown in FIG. 15C, fourth impurity regions 343 to 348 having a conductivity type opposite to the first conductivity type are formed in the island-like semiconductor layers 303 and 306 forming the p-channel TFT. . Impurity regions are formed in a self-aligning manner using the third shape conductive layers 336b and 339b as masks against the impurity element. At this time, the entire surface of the island-like semiconductor layers 304 and 305 forming the n-channel TFT is covered with a resist mask 350. Phosphorus is added to the impurity regions 343 to 348 at different concentrations, but the impurity regions 343 to 348 are formed by ion doping using diborane (B ₂ H ₆ ), and the impurity concentration is 2 × 10 ²⁰ to 2 × 10 ²¹ atoms / cm ³ .

  Through the above steps, impurity regions are formed in each island-like semiconductor layer. The third shape conductive layers 336 to 339 overlapping with the island-shaped semiconductor layers function as gate electrodes.

  After removing the resist mask 350, a process of activating the impurity element added to each island-like semiconductor layer is performed for the purpose of controlling the conductivity type. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. The thermal annealing method is performed in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less, at 400 to 700 ° C., typically 500 to 600 ° C. In this embodiment, the temperature is 500 ° C. for 4 hours. Heat treatment is performed. However, if the wiring material used for the third shape conductive layers 336 to 339 is weak against heat, activation is performed after an interlayer insulating film (mainly composed of silicon) is formed to protect the wiring and the like. Preferably it is done.

When the laser annealing method is used, it is possible to use a laser used for crystallization. For activation, the moving speed is required energy density of the same west and crystallization, 0.01 to 100 MW / cm ² about (preferably 0.01~10MW / cm ^2).

  Further, a heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the island-shaped semiconductor layer. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

  Next, as shown in FIG. 16A, a first interlayer insulating film 355 is formed with a thickness of 100 to 200 nm from a silicon oxynitride film. A second interlayer insulating film 356 made of an organic insulating material is formed thereon, and then contact holes are formed in the first interlayer insulating film 355, the second interlayer insulating film 356, and the gate insulating film 307. The connection wirings 357 to 362 and 380 are formed by patterning. Reference numeral 380 denotes a power line, and 360 denotes a signal line.

  As the second interlayer insulating film 356, a film made of an organic resin is used. As the organic resin, polyimide, polyamide, acrylic, BCB (benzocyclobutene), or the like can be used. In particular, since the second interlayer insulating film 356 has a strong meaning of flattening, acrylic having excellent flatness is preferable. In this embodiment, the acrylic film is formed with a film thickness that can sufficiently flatten the step formed by the TFT. The thickness is preferably 1 to 5 μm (more preferably 2 to 4 μm).

  The contact holes are formed by dry etching or wet etching, and contact holes reaching n-type impurity regions 318 and 319 or p-type impurity regions 345 and 348 and contact holes reaching a capacitor wiring (not shown) (not shown). Each).

  In addition, as the connection wirings 357 to 362 and 380, a laminated film having a three-layer structure in which a Ti film is continuously formed by sputtering, a Ti film having a thickness of 300 nm, and a Ti film having a thickness of 150 nm is formed into a desired shape is used. . Of course, other conductive films may be used.

  Next, the pixel electrode 365 in contact with the connection wiring (connection wiring) 362 is formed by patterning. The connection wiring includes connection wiring and connection wiring. The connection wiring is a wiring connected to the source region of the active layer, and the connection wiring means a wiring connected to the drain region.

  Further, in this embodiment, an ITO film having a thickness of 110 nm is formed as the pixel electrode 365 and patterned. The pixel electrode 365 is placed in contact with the connection wiring 362 to make contact. Alternatively, a transparent conductive film in which 2 to 20% zinc oxide (ZnO) is mixed with indium oxide may be used. This pixel electrode 365 becomes the anode of the OLED. (FIG. 16 (A))

FIG. 17 shows a top view of the pixel at the time when the process up to the step of FIG.
Note that the insulating film and the interlayer insulating film are omitted in order to clarify the position of the wiring and the position of the semiconductor layer. A cross-sectional view taken along the line AA ′ in FIG. 17 corresponds to the portion indicated by AA ′ in FIG. A cross-sectional view taken along the line BB ′ in FIG. 17 corresponds to the part indicated by BB ′ in FIG.

  The transistor Tr3 includes a gate electrode 338 that is a part of the scanning line 574, and the gate electrode 338 is also connected to the gate electrode 520 of the transistor Tr4. One of the impurity regions 317 in the semiconductor layer of the transistor Tr3 is connected to the connection wiring 360 functioning as the signal line Si, and the other is connected to the connection wiring 361.

  The transistor Tr2 includes a gate electrode 339 that is part of the capacitor wiring 573, and the gate electrode 339 is also connected to the gate electrode 576 of the transistor Tr1. One of the impurity regions 348 in the semiconductor layer of the transistor Tr2 is connected to the connection wiring 362 and the other is connected to the connection wiring 361 functioning as the power supply line Vi.

  The connection wiring 361 is also connected to an impurity region (not shown) of the transistor Tr1. Reference numeral 570 denotes a storage capacitor, which includes a semiconductor layer 572, a gate insulating film 307, and a capacitor wiring 573. An impurity region (not shown) included in the semiconductor layer 572 is connected to the connection wiring 361.

  Next, as shown in FIG. 16B, an insulating film containing silicon (silicon oxide film in this embodiment) is formed to a thickness of 500 nm, and an opening is formed at a position corresponding to the pixel electrode 365. Then, a third interlayer insulating film 366 functioning as a bank is formed. When the opening is formed, a tapered sidewall can be easily formed by using a wet etching method. If the side wall of the opening is not sufficiently gentle, the deterioration of the organic light emitting layer due to the step becomes a significant problem, so care must be taken.

  Next, the organic light emitting layer 367 and the cathode (MgAg electrode) 368 are continuously formed by using a vacuum deposition method without being released to the atmosphere. Note that the thickness of the organic light emitting layer 367 may be 80 to 200 nm (typically 100 to 120 nm), and the thickness of the cathode 368 may be 180 to 300 nm (typically 200 to 250 nm).

  In this step, an organic light emitting layer and a cathode are sequentially formed for a pixel corresponding to red, a pixel corresponding to green, and a pixel corresponding to blue. However, since the organic light emitting layer has poor resistance to a solution, it must be formed for each color individually without using a photolithography technique. Therefore, it is preferable to use a metal mask to hide other than the desired pixels and to selectively form the organic light emitting layer only at necessary portions.

  That is, first, a mask that hides all pixels other than those corresponding to red is set, and an organic light emitting layer that emits red light is selectively formed using the mask. Next, a mask that hides all but the pixels corresponding to green is set, and an organic light emitting layer that emits green light is selectively formed using the mask. Next, similarly, a mask for hiding all but the pixels corresponding to blue is set, and a blue light emitting organic light emitting layer is selectively formed using the mask. Note that although all the different masks are described here, the same mask may be used.

  Here, a method of forming three types of OLEDs corresponding to RGB is used, but a method of combining a white light emitting OLED and a color filter, a blue or blue green light emitting OLED and a phosphor (fluorescent color conversion layer: CCM). ), A method of superimposing OLEDs corresponding to RGB using a transparent electrode as a cathode (counter electrode), or the like may be used.

  Note that a known material can be used for the organic light emitting layer 367. As the known material, it is preferable to use an organic material in consideration of the driving voltage. For example, a four-layer structure including a hole injection layer, a hole transport layer, a light emitting layer, and an electron injection layer may be used as the organic light emitting layer.

  Next, the cathode 368 is formed. In this embodiment, MgAg is used as the cathode 368, but the present invention is not limited to this. Other known materials may be used for the cathode 368.

  A portion where the pixel electrode 365, the organic light emitting layer 367, and the cathode 368 overlap corresponds to the OLED 375.

Next, a protective electrode 369 is formed by vapor deposition. The protective electrode 369 may be formed continuously with the cathode 368 without opening to the atmosphere. The protective electrode 369 is effective for protecting the organic light emitting layer 367 from moisture and oxygen.
The protective electrode 369 is provided in order to prevent the cathode 368 from being deteriorated, and a metal film mainly composed of aluminum is typically used. Of course, other materials may be used. Further, since the organic light emitting layer 367 and the cathode 368 are very sensitive to moisture, it is desirable that the protective electrode 369 is continuously formed without being released to the atmosphere to protect the organic light emitting layer from the outside air.

  Finally, a passivation film 370 made of a silicon nitride film is formed to a thickness of 300 nm. By forming the passivation film 370, the organic light emitting layer 367 can be protected from moisture and the like, and the reliability of the OLED can be further improved. Note that the passivation film 370 is not necessarily provided.

  Thus, a light emitting device having a structure as shown in FIG. 16B is completed. Reference numeral 371 denotes a p-channel TFT in the driver circuit portion, reference numeral 372 denotes an n-channel TFT in the driver circuit portion, reference numeral 373 denotes a transistor Tr3, and reference numeral 374 corresponds to a transistor Tr2.

  By the way, the light emitting device of this embodiment can exhibit extremely high reliability and improve the operation characteristics by arranging TFTs having an optimal structure not only in the pixel portion but also in the driving circuit. In addition, it is possible to increase the crystallinity by adding a metal catalyst such as Ni in the crystallization step. Accordingly, the driving frequency of the signal line driver circuit can be 10 MHz or more.

  Actually, when the state shown in FIG. 16B is completed, a protective film (laminate film, ultraviolet curable resin film, etc.) or a light-transmitting material having high hermeticity and low degassing so as not to be exposed to the outside air. It is preferable to package (enclose) with a sealing material. At that time, if the inside of the sealing material is made an inert atmosphere or a hygroscopic material (for example, barium oxide) is arranged inside, the reliability of the OLED is improved.

  In addition, when the airtightness is improved by processing such as packaging, a connector for connecting a terminal routed from an element or circuit formed on the substrate and an external signal terminal is attached.

  Further, according to the steps shown in this embodiment, the number of photomasks necessary for manufacturing a light-emitting device can be suppressed. As a result, the process can be shortened, and the manufacturing cost can be reduced and the yield can be improved.

  This embodiment can be implemented in combination with Embodiments 1-8.

  In this embodiment, a structure different from that in Embodiment 9 of a pixel of a light emitting device which is one of the semiconductor devices of the present invention will be described. FIG. 18 is a cross-sectional view of a pixel of the light emitting device of this example. In the present embodiment, Tr1 and Tr4 are not shown for simplicity of explanation, but the same configuration as that of Tr3 and Tr2 can be used.

  Reference numeral 751 denotes an n-channel TFT, which corresponds to Tr3 in FIG. Reference numeral 752 denotes a p-channel TFT, which corresponds to Tr2 in FIG. The n-channel TFT 751 includes a semiconductor film 753, a first insulating film 770, first electrodes 754 and 755, a second insulating film 771, and second electrodes 756 and 757. The semiconductor film 753 includes a first-concentration one-conductivity type impurity region 758, a second-concentration one-conductivity type impurity region 759, and channel formation regions 760 and 761.

  In this embodiment, the first insulating film 770 has a structure in which two insulating films 770a and 770b are stacked. However, the first insulating film 770 may be a single-layer insulating film, It may have a structure in which three or more insulating films are stacked.

  The first electrodes 754 and 755 and the channel formation regions 760 and 761 overlap with each other with the first insulating film 770 interposed therebetween. In addition, the second electrodes 756 and 757 and the channel formation regions 760 and 761 overlap with the second insulating film 771 interposed therebetween.

The p-channel TFT 752 includes a semiconductor film 780, a first insulating film 770, a first electrode 782, a second insulating film 771, and a second electrode 781.
The semiconductor film 780 includes a first conductivity type impurity region 783 having a third concentration and a channel formation region 784.

  The first electrode 782 and the channel formation region 784 overlap with each other with the first insulating film 770 interposed therebetween. The second electrode 781 and the channel formation region 784 overlap with each other with the second insulating film 771 interposed therebetween.

  In this embodiment, although not shown, the first electrodes 754 and 755 and the second electrodes 756 and 757 are electrically connected. In addition, the first electrode 782 and the second electrode 781 are electrically connected. Note that the present invention is not limited to this structure, and the first electrodes 754 and 755 and the second electrodes 756 and 757 are electrically disconnected, and a constant voltage is applied to the first electrodes 754 and 755. It may be applied. Alternatively, the first electrode 782 and the second electrode 781 may be electrically disconnected, and a voltage may be applied to the first electrode 782 at a constant level.

  By applying a constant voltage to the first electrode, variation in threshold value can be suppressed as compared with the case where there is one electrode, and off-state current can be suppressed. In addition, by applying the same voltage to the first electrode and the second electrode, the depletion layer spreads quickly in the same way as the thickness of the semiconductor film is substantially reduced, so the subthreshold coefficient is reduced. And field effect mobility can be further improved. Therefore, the on-current can be increased as compared with the case of one electrode. Therefore, the driving voltage can be lowered by using the TFT having this structure in the driving circuit. In addition, since the on-current can be increased, the TFT size (especially the channel width) can be reduced. Therefore, the integration density can be improved.

  In addition, a present Example can be implemented in combination with any one of Example 1- Example 8.

  In this embodiment, a structure different from those in Embodiments 9 and 10 of a pixel of a light-emitting device which is one of the semiconductor devices of the present invention will be described. FIG. 19 is a cross-sectional view of a pixel of the light emitting device of this example. In the present embodiment, Tr1 and Tr4 are not shown for simplicity of explanation, but the same configuration as that of Tr3 and Tr2 can be used.

  In FIG. 19, reference numeral 911 denotes a substrate, and 912 denotes an insulating film to be a base (hereinafter referred to as a base film). As the substrate 911, a light-transmitting substrate, typically a glass substrate, a quartz substrate, a glass ceramic substrate, or a crystallized glass substrate can be used. However, it must withstand the maximum processing temperature during the fabrication process.

  8201 is Tr3 and 8202 is Tr2, which are formed of an n-channel TFT and a p-channel TFT, respectively. When the light emitting direction of the organic light emitting layer is the lower surface of the substrate (the surface on which the TFT and the organic light emitting layer are not provided), the above configuration is preferable. However, Tr3 and Tr2 may be either n-channel TFTs or p-channel TFTs.

  Tr3 8201 includes an active layer including a source region 913, a drain region 914, LDD regions 915a to 915d, an isolation region 916, and channel formation regions 917a and 917b, a gate insulating film 918, gate electrodes 919a and 919b, and a first interlayer. An insulating film 920, a signal line 921, and a connection wiring 922 are included. Note that the gate insulating film 918 or the first interlayer insulating film 920 may be common to all TFTs on the substrate, or may be different depending on a circuit or an element.

  Further, Tr3 8201 shown in FIG. 19 has a so-called double gate structure in which gate electrodes 917a and 917b are electrically connected. Needless to say, not only a double gate structure but also a so-called multi-gate structure (a structure including an active layer having two or more channel formation regions connected in series) such as a triple gate structure may be used.

  The multi-gate structure is extremely effective in reducing the off-state current. If the off-state current of Tr3 is made sufficiently low, the minimum capacitance required by the capacitor connected to the gate electrode of Tr2 8202 can be suppressed. it can. That is, since the area of the capacitor can be reduced, the multi-gate structure is also effective in increasing the effective light emitting area of the light emitting element.

  Further, in Tr3 8201, the LDD regions 915a to 915d are provided so as not to overlap with the gate electrodes 919a and 919b with the gate insulating film 918 interposed therebetween. Such a structure is very effective in reducing off current. The length (width) of the LDD regions 915a to 915d may be set to 0.5 to 3.5 μm, typically 2.0 to 2.5 μm. Note that in the case of a multi-gate structure having two or more gate electrodes, an isolation region 916 (a region to which the same impurity element is added at the same concentration as the source region or the drain region) provided between the channel formation regions is provided. It is effective for reducing the off current.

  Next, Tr2 8202 includes an active layer including a source region 926, a drain region 927, and a channel formation region 929, a gate insulating film 918, a gate electrode 930, a first interlayer insulating film 920, a connection wiring 931, and a connection wiring. 932. In this embodiment, Tr2 8202 is a p-channel TFT.

  Note that the gate electrode 930 has a single gate structure, but may have a multi-gate structure. Further, the connection wiring 931 of the Tr2 8202 corresponds to a power supply line (not shown).

  Although the above has described the structure of the TFT provided in the pixel, a driving circuit is also formed at this time. FIG. 19 shows a CMOS circuit as a basic unit for forming a driving circuit.

  In FIG. 19, a TFT having a structure that reduces hot carrier injection while reducing the operating speed as much as possible is used as the n-channel TFT 8204 of the CMOS circuit. Note that the driver circuit here refers to a source signal side driver circuit and a gate signal side driver circuit. Of course, other logic circuits (level shifter, A / D converter, signal dividing circuit, etc.) can be formed.

  The active layer of the n-channel TFT 8204 in the CMOS circuit includes a source region 935, a drain region 936, an LDD region 937, and a channel formation region 938, and the LDD region 937 overlaps with the gate electrode 939 with a gate insulating film 918 interposed therebetween.

The reason why the LDD region 937 is formed only on the drain region 936 side is to prevent the operation speed from being lowered. In addition, the n-channel TFT 8204 does not need to worry about the off-current value so much, and it is better to focus on the operation speed than that.
Therefore, it is desirable that the LDD region 937 is completely overlapped with the gate electrode to reduce the resistance component as much as possible. That is, it is better to eliminate the so-called offset.

  Further, the p-channel TFT 8205 of the CMOS circuit is hardly concerned with deterioration due to hot carrier injection, so that it is not particularly necessary to provide an LDD region. Therefore, the active layer includes a source region 940, a drain region 941, and a channel formation region 942, on which a gate insulating film 918 and a gate electrode 943 are provided. Needless to say, it is possible to provide an LDD region as in the case of the n-channel TFT 8204 and take measures against hot carriers.

  Reference numerals 961 to 965 denote masks for forming channel formation regions 942, 938, 917a, 917b, and 929.

  Each of the n-channel TFT 8204 and the p-channel TFT 8205 has connection wirings 944 and 945 over the source region with a first interlayer insulating film 920 interposed therebetween. In addition, the drain region of the n-channel TFT 8204 and the p-channel TFT 8205 is electrically connected to each other by the connection wiring 946.

  In addition, the structure of a present Example can be implemented in combination freely with Examples 1-8.

  In this embodiment, a configuration of a pixel using a cathode as a pixel electrode will be described.

  A cross-sectional view of the pixel of this example is shown in FIG. In FIG. 20, Tr3 3502 provided over a substrate 3501 is manufactured using a known method. In this embodiment, a double gate structure is used. In this embodiment, a double gate structure is used, but a single gate structure may be used, and a triple gate structure or a multi-gate structure having more gate electrodes may be used. In the present embodiment, Tr1 and Tr4 are not shown for simplicity of explanation, but the same configuration as that of Tr3 and Tr2 can be used.

  Tr2 3503 is an n-channel TFT and is manufactured using a known method. A wiring indicated by 38 is a scanning line for electrically connecting the gate electrodes 39a and 39b of Tr3 3502.

  In this embodiment, Tr2 3503 is illustrated with a single gate structure, but a multi-gate structure in which a plurality of TFTs are connected in series may be used. Further, a structure may be employed in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of portions so that heat can be emitted with high efficiency. Such a structure is effective as a countermeasure against deterioration due to heat.

  The connection wiring 40 is connected to a power supply line (not shown), and a constant voltage is always applied.

  A first interlayer insulating film 41 is provided on Tr3 3502 and Tr2 3503, and a second interlayer insulating film 42 made of a resin insulating film is formed thereon. It is very important to flatten the step due to the TFT using the second interlayer insulating film 42. Since the organic light emitting layer formed later is very thin, the presence of a step may cause a light emission failure. Therefore, it is desirable that the organic light emitting layer be planarized before forming the pixel electrode so that the organic light emitting layer can be formed as flat as possible.

  Reference numeral 43 denotes a pixel electrode (a cathode of a light emitting element) made of a highly reflective conductive film, which is electrically connected to the drain region of Tr2 3503. As the pixel electrode 43, it is preferable to use a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a laminated film thereof. Of course, a laminated structure with another conductive film may be used.

  A light emitting layer 45 is formed in a groove (corresponding to a pixel) formed by banks 44a and 44b formed of an insulating film (preferably resin). Although only one pixel is shown here, a light emitting layer corresponding to each color of R (red), G (green), and B (blue) may be formed separately. A π-conjugated polymer material is used as the organic organic light emitting material for the light emitting layer. Typical polymer materials include polyparaphenylene vinylene (PPV), polyvinyl carbazole (PVK), and polyfluorene.

  There are various types of PPV organic light-emitting materials. For example, “H. Shenk, H. Becker, O. Gelsen, E. Kluge, W. Kreuder, and H. Spreitzer,“ Polymers for Light Emitting ”. Materials such as those described in “Diodes”, Euro Display, Proceedings, 1999, p. 33-37 ”and Japanese Patent Laid-Open No. 10-92576 may be used.

  As a specific light emitting layer, cyanopolyphenylene vinylene may be used for a light emitting layer that emits red light, polyphenylene vinylene may be used for a light emitting layer that emits green light, and polyphenylene vinylene or polyalkylphenylene may be used for a light emitting layer that emits blue light. The film thickness may be 30 to 150 nm (preferably 40 to 100 nm).

  However, the above example is an example of an organic light emitting material that can be used as a light emitting layer, and it is not absolutely necessary to limit to this. An organic light emitting layer (a layer for emitting light and moving carriers therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer.

  For example, in this embodiment, an example in which a polymer material is used as the light emitting layer is shown, but a low molecular weight organic light emitting material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer or the charge injection layer. Known materials can be used for these organic light emitting materials and inorganic materials.

In this embodiment, an organic light emitting layer having a laminated structure in which a hole injection layer 46 made of PEDOT (polythiophene) or PAni (polyaniline) is provided on the light emitting layer 45 is used. An anode 47 made of a transparent conductive film is provided on the hole injection layer 46.
In the case of the present embodiment, since the light generated in the light emitting layer 45 is emitted toward the upper surface side (upward of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used, but it is possible to form after forming a light-emitting layer or hole injection layer with low heat resistance. What can form into a film at low temperature as much as possible is preferable.

  When the anode 47 is formed, the light emitting element 3505 is completed. Note that the light-emitting element 3505 here is formed of a pixel electrode (cathode) 43, a light-emitting layer 45, a hole injection layer 46, and an anode 47. Since the pixel electrode 43 substantially matches the area of the pixel, the entire pixel functions as a light emitting element. Therefore, the use efficiency of light emission is very high, and a bright image display is possible.

  By the way, in the present embodiment, a second passivation film 48 is further provided on the anode 47. The second passivation film 48 is preferably a silicon nitride film or a silicon nitride oxide film. This purpose is to shut off the light emitting element from the outside, and has both the meaning of preventing deterioration due to oxidation of the organic light emitting material and the meaning of suppressing degassing from the organic light emitting material. This increases the reliability of the light emitting device.

  As described above, the light-emitting device of the present invention includes a pixel portion including pixels having a structure as shown in FIG. 20, and includes Tr3 having a sufficiently low off-state current value and Tr2 that is strong against hot carrier injection. Therefore, a light emitting device having high reliability and capable of displaying a good image can be obtained.

  In addition, the structure of a present Example can be implemented in combination freely with Examples 1-8 structure.

  In this example, the structure of the light-emitting device of the present invention will be described with reference to FIG.

  21 is a top view of a light-emitting device formed by sealing an element substrate over which a transistor is formed with a sealing material, and FIG. 21B is a cross-sectional view taken along line AA ′ in FIG. FIG. 21C is a cross-sectional view taken along line BB ′ of FIG.

  A sealant 4009 is provided so as to surround the pixel portion 4002 provided over the substrate 4001, the signal line driver circuit 4003, and the first and second scan line driver circuits 4004a and 4004b. In addition, a sealing material 4008 is provided over the pixel portion 4002, the signal line driver circuit 4003, and the first and second scan line driver circuits 4004a and 4004b. Therefore, the pixel portion 4002, the signal line driver circuit 4003, and the first and second scan line driver circuits 4004 a and 400 b are sealed with the filler 4210 by the substrate 4001, the sealant 4009, and the sealant 4008. .

  The pixel portion 4002, the signal line driver circuit 4003, and the first and second scan line driver circuits 4004a and 4004b provided over the substrate 4001 include a plurality of TFTs. In FIG. 21B, typically, a driver TFT (here, an n-channel TFT and a p-channel TFT are illustrated) 4201 and a pixel included in the signal line driver circuit 4003 formed over the base film 4010. The transistor Tr2 4202 included in the portion 4002 is illustrated.

  In this embodiment, a p-channel TFT or an n-channel TFT manufactured by a known method is used for the driving TFT 4201, and a p-channel TFT manufactured by a known method is used for the transistor Tr2 4202.

  An interlayer insulating film (planarization film) 4301 is formed over the driving TFT 4201 and the transistor Tr2 4202, and a pixel electrode (anode) 4203 electrically connected to the drain of the transistor Tr2 4202 is formed thereon. As the pixel electrode 4203, a transparent conductive film having a large work function is used. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Moreover, you may use what added the gallium to the said transparent conductive film.

  An insulating film 4302 is formed over the pixel electrode 4203, and an opening is formed over the pixel electrode 4203 in the insulating film 4302. In this opening, an organic light emitting layer 4204 is formed on the pixel electrode 4203. A known organic light emitting material or inorganic light emitting material can be used for the organic light emitting layer 4204. The organic light emitting material includes a low molecular (monomer) material and a high molecular (polymer) material, either of which may be used.

  As a method for forming the organic light emitting layer 4204, a known vapor deposition technique or coating technique may be used. The structure of the organic light emitting layer may be a laminated structure or a single layer structure by freely combining a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, or an electron injection layer.

  On the organic light emitting layer 4204, a cathode 4205 made of a light-shielding conductive film (typically a conductive film containing aluminum, copper or silver as a main component or a laminated film of these with another conductive film) is formed. The In addition, it is desirable to remove moisture and oxygen present at the interface between the cathode 4205 and the organic light emitting layer 4204 as much as possible. Therefore, it is necessary to devise a method in which the organic light emitting layer 4204 is formed in a nitrogen or rare gas atmosphere and the cathode 4205 is formed without being exposed to oxygen or moisture. In this embodiment, the above-described film formation is possible by using a multi-chamber type (cluster tool type) film formation apparatus. The cathode 4205 is given a predetermined voltage.

  As described above, the light emitting element 4303 including the pixel electrode (anode) 4203, the organic light emitting layer 4204, and the cathode 4205 is formed. A protective film 4209 is formed over the insulating film 4302 so as to cover the light emitting element 4303. The protective film 4209 is effective in preventing oxygen, moisture, and the like from entering the light emitting element 4303.

  Reference numeral 4005a denotes a lead wiring connected to the power supply line, which is electrically connected to the source of the transistor Tr2 4202. The lead wiring 4005 a passes between the sealant 4009 and the substrate 4001 and is electrically connected to the FPC wiring 4301 included in the FPC 4006 through the anisotropic conductive film 4300.

As the sealing material 4008, a glass material, a metal material (typically a stainless steel material), a ceramic material, or a plastic material (including a plastic film) can be used. Plastic materials include FRP (Fiberglass-Reinforced Plastics) plate, PVF (polyvinyl fluoride)
A film, mylar film, polyester film or acrylic resin film can be used. A sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can also be used.

  However, when the light emission direction from the light emitting element is directed toward the cover material, the cover material must be transparent. In that case, a transparent material such as a glass plate, a plastic plate, a polyester film or an acrylic film is used.

  As the filler 4210, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used. PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (Polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. In this example, nitrogen was used as the filler.

  In order to expose the filler 4210 to a hygroscopic substance (preferably barium oxide) or a substance capable of adsorbing oxygen, a recess 4007 is provided on the surface of the sealing material 4008 on the substrate 4001 side to adsorb the hygroscopic substance or oxygen. A possible substance 4207 is arranged. In order to prevent the hygroscopic substance or the substance 4207 capable of adsorbing oxygen from scattering, the concave part cover material 4208 holds the hygroscopic substance or the substance 4207 capable of adsorbing oxygen in the concave part 4007. Note that the concave cover material 4208 has a fine mesh shape, and is configured to allow air and moisture to pass therethrough but not a hygroscopic substance or a substance 4207 capable of adsorbing oxygen. By providing the hygroscopic substance or the substance 4207 capable of adsorbing oxygen, deterioration of the light-emitting element 4303 can be suppressed.

  As shown in FIG. 21C, the conductive film 4203a is formed so as to be in contact with the lead wiring 4005a at the same time as the pixel electrode 4203 is formed.

  The anisotropic conductive film 4300 has a conductive filler 4300a. By thermally pressing the substrate 4001 and the FPC 4006, the conductive film 4203a on the substrate 4001 and the FPC wiring 4301 on the FPC 4006 are electrically connected by the conductive filler 4300a.

  The configuration of the present embodiment can be implemented by freely combining the configurations shown in Embodiments 1 to 12.

(Example 14)
Since a light-emitting device using a light-emitting element is a self-luminous type, it has excellent visibility in a bright place and a wide viewing angle compared to a liquid crystal display. Therefore, it can be used for display portions of various electronic devices.

  As an electronic device using the light emitting device of the present invention, a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproduction device (car audio, audio component, etc.), a notebook type personal computer, a game device, Play back a recording medium such as a portable information terminal (mobile computer, mobile phone, portable game machine, electronic book, etc.) or recording medium (specifically, Digital Versatile Disc (DVD)) A device having a display capable of displaying). In particular, it is desirable to use a light-emitting device for a portable information terminal that often has an opportunity to see a screen from an oblique direction because the wide viewing angle is important. Specific examples of these electronic devices are shown in FIGS.

  FIG. 22A illustrates a light-emitting element display device including a housing 2001, a support base 2002, a display portion 2003, a speaker portion 2004, a video input terminal 2005, and the like. The light emitting device of the present invention can be used for the display portion 2003. Since the light-emitting device is a self-luminous type, a backlight is not necessary and a display portion thinner than a liquid crystal display can be obtained. The light emitting element display device includes all information display devices such as a personal computer, a TV broadcast receiver, and an advertisement display.

  FIG. 22B illustrates a digital still camera, which includes a main body 2101, a display portion 2102, an image receiving portion 2103, operation keys 2104, an external connection port 2105, a shutter 2106, and the like. The light emitting device of the present invention can be used for the display portion 2102.

  FIG. 22C illustrates a laptop personal computer, which includes a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. The light-emitting device of the present invention can be used for the display portion 2203.

  FIG. 22D illustrates a mobile computer, which includes a main body 2301, a display portion 2302, a switch 2303, operation keys 2304, an infrared port 2305, and the like. The light emitting device of the present invention can be used for the display portion 2302.

  FIG. 22E shows a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2401, a housing 2402, a display portion A2403, a display portion B2404, a recording medium (DVD, etc.). A reading unit 2405, operation keys 2406, a speaker unit 2407, and the like are included. Although the display portion A 2403 mainly displays image information and the display portion B 2404 mainly displays character information, the light-emitting device of the present invention can be used for the display portions A, B 2403, and 2404. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.

  FIG. 22F illustrates a goggle type display (head mounted display), which includes a main body 2501, a display portion 2502, and an arm portion 2503. The light emitting device of the present invention can be used for the display portion 2502.

  FIG. 22G illustrates a video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control receiving portion 2605, an image receiving portion 2606, a battery 2607, an audio input portion 2608, operation keys 2609, and an eyepiece. Part 2610 and the like. The light-emitting device of the present invention can be used for the display portion 2602.

  Here, FIG. 22H shows a mobile phone, which includes a main body 2701, a housing 2702, a display portion 2703, an audio input portion 2704, an audio output portion 2705, operation keys 2706, an external connection port 2707, an antenna 2708, and the like. The light emitting device of the present invention can be used for the display portion 2703. Note that the display portion 2703 can suppress current consumption of the mobile phone by displaying white characters on a black background.

  If the light emission luminance of the organic light emitting material is increased in the future, the light including the output image information can be enlarged and projected by a lens or the like and used in a front type or rear type projector.

  In addition, the electronic devices often display information distributed through electronic communication lines such as the Internet and CATV (cable television), and in particular, opportunities to display moving image information are increasing. Since the organic light emitting material has a very high response speed, the light emitting device is preferable for displaying moving images.

  In addition, since the light emitting device consumes power in the light emitting portion, it is desirable to display information so that the light emitting portion is minimized. Therefore, when a light emitting device is used for a display unit mainly including character information, such as a portable information terminal, particularly a mobile phone or a sound reproduction device, it is driven so that character information is formed by the light emitting part with the non-light emitting part as the background. It is desirable to do.

  As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields. In addition, the electronic apparatus of this embodiment may use the light emitting device having any configuration shown in Embodiments 1 to 9.

  In addition, by using a drive method (AC drive) that applies a reverse bias drive voltage to a light emitting element at regular intervals, the current-voltage characteristics of the light emitting element are improved and the lifetime of the light emitting element is improved over conventional driving. It becomes possible to make it longer than the method.

1 is a block diagram of a light emitting device of the present invention. 1 is a pixel circuit diagram of a light emitting device of the present invention. Schematic of a pixel in driving. 6 is a timing chart of voltages applied to scanning lines and power supply lines. 6 is a timing chart of voltages applied to scanning lines and power supply lines. 6 is a timing chart of voltages applied to scanning lines and power supply lines. 6 is a timing chart of voltages applied to scanning lines and power supply lines. 6 is a timing chart of voltages applied to scanning lines and power supply lines. 1 is a block diagram of a signal line driver circuit of the present invention. The circuit diagram of a current setting circuit and a switching circuit. FIG. 11 is a block diagram of a scan line driver circuit. 1 is a block diagram of a signal line driver circuit of the present invention. The circuit diagram of a current setting circuit and a switching circuit. 4A and 4B illustrate a method for manufacturing a light-emitting device of the present invention. 4A and 4B illustrate a method for manufacturing a light-emitting device of the present invention. 4A and 4B illustrate a method for manufacturing a light-emitting device of the present invention. FIG. 6 is a top view of a pixel of a light-emitting device of the present invention. 4 is a cross-sectional view of a pixel of a light-emitting device of the present invention. 4 is a cross-sectional view of a pixel of a light-emitting device of the present invention. 4 is a cross-sectional view of a pixel of a light-emitting device of the present invention. The external view and sectional drawing of the light-emitting device of this invention. FIG. 14 is a diagram of an electronic device using the light-emitting device of the present invention. The circuit diagram of a general pixel.

Claims (12)

A first transistor, a second transistor, a third transistor, and a fourth transistor;
One of a source and a drain of the first transistor is electrically connected to the first wiring;
One of a source and a drain of the second transistor is electrically connected to the first wiring;
The gate of the first transistor and the gate of the second transistor are electrically connected,
One of a source and a drain of the third transistor is electrically connected to the second wiring;
One of a source and a drain of the fourth transistor is electrically connected to the second wiring;
The other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor;
The other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor;
The other of the source and the drain of the second transistor is electrically connected to the pixel electrode. A first transistor, a second transistor, a third transistor, and a fourth transistor;
One of a source and a drain of the first transistor is electrically connected to the first wiring;
One of a source and a drain of the second transistor is electrically connected to the first wiring;
The gate of the first transistor and the gate of the second transistor are electrically connected,
One of a source and a drain of the third transistor is electrically connected to the second wiring;
One of a source and a drain of the fourth transistor is electrically connected to the second wiring;
The other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor;
The other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor;
The other of the source and the drain of the second transistor is electrically connected to the pixel electrode,
A semiconductor device comprising means for controlling supply of current or voltage to the second wiring. A first transistor, a second transistor, a third transistor, and a fourth transistor;
One of a source and a drain of the first transistor is electrically connected to the first wiring;
One of a source and a drain of the second transistor is electrically connected to the first wiring;
The gate of the first transistor and the gate of the second transistor are electrically connected,
One of a source and a drain of the third transistor is electrically connected to the second wiring;
One of a source and a drain of the fourth transistor is electrically connected to the second wiring;
The other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor;
The other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor;
The other of the source and the drain of the second transistor is electrically connected to the pixel electrode,
In the first period, a current is supplied to the second wiring,
The semiconductor device is characterized in that a voltage is supplied to the second wiring in the second period. In claim 3,
The first period is a writing period;
2. The semiconductor device according to claim 1, wherein the second period is a reverse bias period. A first transistor, a second transistor, a third transistor, and a fourth transistor;
One of a source and a drain of the first transistor is electrically connected to the first wiring;
One of a source and a drain of the second transistor is electrically connected to the first wiring;
The gate of the first transistor and the gate of the second transistor are electrically connected,
One of a source and a drain of the third transistor is electrically connected to the second wiring;
One of a source and a drain of the fourth transistor is electrically connected to the second wiring;
The other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor;
The other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor;
The other of the source and the drain of the second transistor is electrically connected to the pixel electrode,
A semiconductor device comprising a circuit for switching supply of current or voltage to the second wiring. In any one of Claims 1 thru | or 5,
It further has a capacitive element,
One electrode of the capacitor is electrically connected to a gate of the second transistor. A first transistor, a second transistor, a third transistor, a fourth transistor, and a light-emitting element;
One of a source and a drain of the first transistor is electrically connected to the first wiring;
One of a source and a drain of the second transistor is electrically connected to the first wiring;
The gate of the first transistor and the gate of the second transistor are electrically connected,
One of a source and a drain of the third transistor is electrically connected to the second wiring;
One of a source and a drain of the fourth transistor is electrically connected to the second wiring;
The other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor;
The other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor;
The other of the source and the drain of the second transistor is electrically connected to a pixel electrode of the light emitting element. A first transistor, a second transistor, a third transistor, a fourth transistor, and a light-emitting element;
One of a source and a drain of the first transistor is electrically connected to the first wiring;
One of a source and a drain of the second transistor is electrically connected to the first wiring;
The gate of the first transistor and the gate of the second transistor are electrically connected,
One of a source and a drain of the third transistor is electrically connected to the second wiring;
One of a source and a drain of the fourth transistor is electrically connected to the second wiring;
The other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor;
The other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor;
The other of the source and the drain of the second transistor is electrically connected to the pixel electrode of the light emitting element,
A light-emitting device comprising means for controlling supply of current or voltage to the second wiring. A first transistor, a second transistor, a third transistor, a fourth transistor, and a light-emitting element;
One of a source and a drain of the first transistor is electrically connected to the first wiring;
One of a source and a drain of the second transistor is electrically connected to the first wiring;
The gate of the first transistor and the gate of the second transistor are electrically connected,
One of a source and a drain of the third transistor is electrically connected to the second wiring;
One of a source and a drain of the fourth transistor is electrically connected to the second wiring;
The other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor;
The other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor;
The other of the source and the drain of the second transistor is electrically connected to the pixel electrode of the light emitting element,
In the first period, a current is supplied to the second wiring,
In the second period, a voltage is supplied to the second wiring. In claim 9,
The first period is a writing period;
The light emitting device according to claim 2, wherein the second period is a reverse bias period. A first transistor, a second transistor, a third transistor, a fourth transistor, and a light-emitting element;
One of a source and a drain of the first transistor is electrically connected to the first wiring;
One of a source and a drain of the second transistor is electrically connected to the first wiring;
The gate of the first transistor and the gate of the second transistor are electrically connected,
One of a source and a drain of the third transistor is electrically connected to the second wiring;
One of a source and a drain of the fourth transistor is electrically connected to the second wiring;
The other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor;
The other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor;
The other of the source and the drain of the second transistor is electrically connected to the pixel electrode of the light emitting element,
A light emitting device comprising a circuit for switching supply of current or voltage to the second wiring. In any one of Claims 7 to 11,
It further has a capacitive element,
One electrode of the capacitor is electrically connected to a gate of the second transistor.

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