JP2000268957A - Electroluminescence display device - Google Patents

Electroluminescence display device

Info

Publication number
JP2000268957A
JP2000268957A JP11073927A JP7392799A JP2000268957A JP 2000268957 A JP2000268957 A JP 2000268957A JP 11073927 A JP11073927 A JP 11073927A JP 7392799 A JP7392799 A JP 7392799A JP 2000268957 A JP2000268957 A JP 2000268957A
Authority
JP
Japan
Prior art keywords
anode
cathode
voltage
supplying
display device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11073927A
Other languages
Japanese (ja)
Inventor
Naoaki Furumiya
直明 古宮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP11073927A priority Critical patent/JP2000268957A/en
Priority to TW089104464A priority patent/TW488187B/en
Priority to KR1020000013554A priority patent/KR20010014601A/en
Publication of JP2000268957A publication Critical patent/JP2000268957A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

PROBLEM TO BE SOLVED: To substantially prevent shortage of the life of an EL element caused by accumulation of space charges in the EL element generating by repeating current driving. SOLUTION: In this EL display device having at least a hole transport layer and a luminescent layer between an anode and a cathode and emitting light by supplying a specified bias, a selecting circuit 2 for supplying voltage VBS higher than power source voltage supplying to the anode during driving and either one voltage of earthing voltage and negative voltage Vcd to the cathode is installed, and space charges accumulating in the element are periodically removed by applying reverse bias between the anode and the cathode during a non-display period.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、陽極と陰極の間
に、少なくともホール輸送層及び発光層を有し、所定の
バイアスを供給することにより発光を行うエレクトロル
ミネッセンス表示装置に関する。
The present invention relates to an electroluminescent display device having at least a hole transport layer and a light emitting layer between an anode and a cathode and emitting light by supplying a predetermined bias.

【0002】[0002]

【従来の技術】有機EL素子は、自ら発光するため液晶表
示装置で必要なバックライトが要らず薄型化に最適であ
ると共に、視野角にも制限が無いため、次世代の表示装
置としてその実用化が大きく期待されている。
2. Description of the Related Art An organic EL element emits light by itself, so it is not necessary for a backlight necessary for a liquid crystal display device, and is optimal for thinning. In addition, since there is no restriction on a viewing angle, it is practically used as a next-generation display device. It is greatly expected to be used.

【0003】このような有機EL素子は、図7に示すよう
に、ITO等の透明電極から成る陽極51とMgIn合金から
成る陰極55との間に、MTDATAから成るホール輸送層5
2,TPDとRubreneから成る発光層53,Alq3から成る電
子輸送層54を順に積層して形成されている。そして、
陽極51から注入されたホールと陰極55から注入され
た電子とが発光層53の内部で再結合することにより光
が放たれ、図中の矢印で示すように光は透明な陽極側か
ら外部へ放射される。
As shown in FIG. 7, such an organic EL device has a hole transport layer 5 made of MTDATA between an anode 51 made of a transparent electrode such as ITO and a cathode 55 made of an MgIn alloy.
2, a light emitting layer 53 composed of TPD and Rubrene and an electron transport layer 54 composed of Alq3 are sequentially laminated. And
Light is emitted when the holes injected from the anode 51 and the electrons injected from the cathode 55 are recombined inside the light-emitting layer 53, and light is transmitted from the transparent anode side to the outside as shown by arrows in the drawing. Radiated.

【0004】この有機ELを駆動する表示装置には、単純
マトリクス構造のパッシブ型と、TFTを用いるアクティ
ブ型の2種類があり、アクティブ型においては、従来、
図6に示す駆動回路が用いられていた。
[0004] There are two types of display devices for driving the organic EL, a passive type having a simple matrix structure and an active type using a TFT.
The driving circuit shown in FIG. 6 was used.

【0005】図6において70が有機EL素子であり、1
画素分の駆動回路は、表示信号ライン75からの表示信
号DATAがドレインに印加され、選択信号ライン76から
の選択信号SCANがゲートに印加され、選択信号SCANによ
りオンオフするスイッチング用TFT71と、TFT71のソ
ースと所定の直流電圧Vsc 間に接続され、TFT71のオ
ン時に供給される表示信号により充電され、TFT71の
オフ時には充電電圧VGを保持するコンデンサ72と、ド
レインが駆動電源電圧Vddを供給する電源ライン77に
接続され、ソースが有機EL素子70の陽極に接続される
と共に、ゲートにコンデンサ72からの保持電圧VGが供
給されることにより有機EL素子70を電流駆動する駆動
用TFT74によって構成されている。また、通常、有機E
L素子の陰極は接地(GND)電位に接続されており、駆動
電源電圧Vddは例えば10Vといった正電位である。ま
た、電圧Vscは例えば、Vddと同一電位あるいは接地(GN
D)電位である。
In FIG. 6, reference numeral 70 denotes an organic EL element,
The driving circuit for the pixels includes a switching TFT 71 that is turned on / off by the selection signal SCAN when the display signal DATA from the display signal line 75 is applied to the drain and the selection signal SCAN from the selection signal line 76 is applied to the gate. A power supply line connected between the source and a predetermined DC voltage Vsc, charged by a display signal supplied when the TFT 71 is turned on, and holding a charging voltage VG when the TFT 71 is turned off; 77, a source is connected to the anode of the organic EL element 70, and a driving TFT 74 that current-drives the organic EL element 70 by supplying a holding voltage VG from the capacitor 72 to the gate. . Also, usually, organic E
The cathode of the L element is connected to a ground (GND) potential, and the drive power supply voltage Vdd is a positive potential, for example, 10V. The voltage Vsc is, for example, the same potential as Vdd or ground (GN
D) potential.

【0006】この駆動用のTFT74は、図7に示すよう
に、ガラス基板60上に、ゲート電極61,ゲート絶縁
膜62,ドレイン領域63,チャネル領域及びソース領
域64を有するポリシリコン薄膜65,層間絶縁膜6
6,平坦化膜67を順に積層して形成されており、ドレ
イン領域63は電源ライン67(図6参照)を構成する
ドレイン電極68に、そして、ソース領域64は有機EL
素子の陽極である透明電極51に接続されている。
As shown in FIG. 7, the driving TFT 74 is formed on a glass substrate 60 by forming a polysilicon thin film 65 having a gate electrode 61, a gate insulating film 62, a drain region 63, a channel region and a source region 64, Insulating film 6
6, a planarizing film 67 is sequentially laminated, the drain region 63 is a drain electrode 68 constituting a power supply line 67 (see FIG. 6), and the source region 64 is an organic EL.
It is connected to a transparent electrode 51 which is the anode of the device.

【0007】[0007]

【発明が解決しようとする課題】EL素子は上述したよう
に電流駆動により発光し、駆動時には陽極から陰極に向
かって電流が流れ、非駆動時には電流は流れない。つま
り、常に一方向にしか電流が流れないため駆動を繰り返
すと、ホール輸送層と発光層の間、あるいは電子輸送層
と発光層の間等EL素子内に空間電荷が溜まり、これがE
L素子の寿命を短くする原因になっている。特に、素子
内のうちでも、ホール輸送層と発光層の間に空間電荷が
溜まりやすいと考えられている。このような課題は、駆
動方式がパッシブ型であってアクティブ型であっても同
様である。
As described above, the EL element emits light by current driving. When driven, current flows from the anode to the cathode, and when not driven, no current flows. That is, since current always flows in only one direction, when driving is repeated, space charges accumulate in the EL element such as between the hole transport layer and the light emitting layer, or between the electron transport layer and the light emitting layer, and this is the E
This causes the life of the L element to be shortened. In particular, it is considered that space charges easily accumulate between the hole transport layer and the light emitting layer even within the device. Such a problem is the same even when the driving method is a passive type and an active type.

【0008】そこで、本発明は、寿命を極力長くできる
ようにEL素子を電流駆動することを目的とする。
Accordingly, it is an object of the present invention to drive an EL element with current so as to extend the life as much as possible.

【0009】[0009]

【課題を解決するための手段】本発明は、陽極と陰極の
間に、少なくともホール輸送層及び発光層を有し、所定
のバイアスを供給することにより発光を行うエレクトロ
ルミネッセンス表示装置において、非表示期間に前記陽
極と陰極の間に逆バイアスをかけるようにしたことを特
徴とする。
According to the present invention, there is provided an electroluminescent display device having at least a hole transport layer and a light emitting layer between an anode and a cathode and emitting light by supplying a predetermined bias. A reverse bias is applied between the anode and the cathode during the period.

【0010】また、本発明は、非表示期間に発生するパ
ルス信号を入力し、該パルス信号が第1レベルのとき、
前記陽極と陰極の間に前記所定のバイアスを供給するた
めの第1の電位を前記陰極又は陽極に印加し、前記パル
ス信号が第2レベルのとき、前記陽極と陰極の間に前記
逆バイアスを供給するための第2の電位を前記陰極又は
陽極に印加する選択回路を有することを特徴とする。
Further, according to the present invention, when a pulse signal generated during a non-display period is input, and when the pulse signal is at a first level,
A first potential for supplying the predetermined bias between the anode and the cathode is applied to the cathode or the anode, and when the pulse signal is at a second level, the reverse bias is applied between the anode and the cathode. A selection circuit for applying a second potential to be supplied to the cathode or the anode;

【0011】また、本発明では、前記パルス信号は、非
表示期間に発生するブランキングパルス信号もしくはク
ランプパルス信号であることを特徴とする。
In the present invention, the pulse signal is a blanking pulse signal or a clamp pulse signal generated during a non-display period.

【0012】[0012]

【発明の実施の形態】図3は、本発明によるEL表示装置
に用いるEL表示パネルの回路構成を示しており、基本的
には従来と同一構成である。
FIG. 3 shows a circuit configuration of an EL display panel used in an EL display device according to the present invention, which is basically the same as the conventional one.

【0013】即ち、この構成は複数の画素を有するアク
ティブ型であって、有機EL素子20を駆動する1画素分
の駆動回路は、表示信号ライン25からの表示信号DATA
がドレインに印加され、選択信号ライン26からの選択
信号SCANがゲートに印加され、選択信号SCANによりオン
オフするスイッチング用TFT21と、TFT21のソースと
所定の直流電圧Vsc 間に接続され、TFT21のオン時に
供給される表示信号により充電され、TFT21のオフ時
には充電電圧VGを保持するコンデンサ22と、ドレイン
が駆動電源電圧Vddを供給する電源ライン27に接続さ
れ、ソースが有機EL素子20の陽極201に接続される
と共に、ゲートにコンデンサ22からの保持電圧VGが供
給されることにより有機EL素子20を電流駆動する駆動
用TFT24によって構成されている。
That is, this configuration is an active type having a plurality of pixels, and a driving circuit for one pixel for driving the organic EL element 20 is provided with a display signal DATA from a display signal line 25.
Is applied to the drain, the selection signal SCAN from the selection signal line 26 is applied to the gate, and the switching TFT 21 is turned on and off by the selection signal SCAN, and is connected between the source of the TFT 21 and a predetermined DC voltage Vsc. When the TFT 21 is turned off, it is charged by the supplied display signal, the capacitor 22 holding the charging voltage VG, the drain is connected to the power supply line 27 for supplying the drive power supply voltage Vdd, and the source is connected to the anode 201 of the organic EL element 20. The driving TFT 24 drives the organic EL element 20 by supplying a holding voltage VG from the capacitor 22 to the gate.

【0014】そして、従来同様、駆動電源電圧Vddは例
えば10Vといった正電位であり、電圧Vscは例えばVdd
と同一電位あるいは接地(GND)電位であるが、本実施
形態では、有機EL素子20の陰極202は、従来と異な
り、接地(GND)電位等の固定電位ではなく、可変電位
を供給する端子Tに接続されている。
As in the prior art, the drive power supply voltage Vdd is a positive potential, for example, 10 V, and the voltage Vsc is, for example, Vdd
In this embodiment, the cathode 202 of the organic EL element 20 is not a fixed potential such as a ground (GND) potential, but is a terminal T that supplies a variable potential. It is connected to the.

【0015】図4は、複数の画素について、図3に示す
EL素子20及び駆動用TFT24の構造を示す断面図で
あり、31は表示信号DATAを供給するアルミニウムより
成るドレインライン、32は電源電圧Vddを供給するア
ルミニウムより成る電源電圧ライン、33は選択信号Sc
anを供給するクロムより成るゲートラインであり、36
が図3の駆動用TFT24、そして、37がITOより成り画
素電極を構成するEL素子20の陽極201を表してい
る。
FIG. 4 shows a plurality of pixels shown in FIG.
It is a sectional view showing the structure of the EL element 20 and the driving TFT 24, 31 is a drain line made of aluminum for supplying a display signal DATA, 32 is a power supply voltage line made of aluminum for supplying a power supply voltage Vdd, and 33 is a selection signal Sc.
a gate line of chromium that supplies an
3 represents the driving TFT 24 shown in FIG. 3, and 37 represents the anode 201 of the EL element 20 made of ITO and constituting the pixel electrode.

【0016】この駆動用TFT36は以下のようにして形
成する。まず、透明なガラス基板38上にクロムのゲー
ト電極39を形成し、その上にゲート絶縁膜40を成膜
する。次にゲート絶縁膜40の上にポリシリコン薄膜4
1を成膜し、これを層間絶縁膜42で覆った上にドレイ
ンライン31及び電源ライン32を形成する。更に、平
坦化絶縁膜43を積層し、その上にITOにて成る陽極3
7を形成する。そして、ポリシリコン薄膜41のドレイ
ン領域を電源ライン32にコンタクトし、ソース領域を
陽極37にコンタクトする。また、図3に示すスイッチ
ングTFT21の構造も駆動用TFT36と同一であり、TFT
21に接続されるコンデンサ22はゲート絶縁膜を挟ん
だクロム電極とポリシリコン薄膜から構成されている。
The driving TFT 36 is formed as follows. First, a chromium gate electrode 39 is formed on a transparent glass substrate 38, and a gate insulating film 40 is formed thereon. Next, the polysilicon thin film 4 is formed on the gate insulating film 40.
Then, a drain line 31 and a power supply line 32 are formed on the substrate 1 covered with an interlayer insulating film 42. Further, a flattening insulating film 43 is laminated, and an anode 3 made of ITO is formed thereon.
7 is formed. Then, the drain region of the polysilicon thin film 41 is contacted with the power supply line 32, and the source region is contacted with the anode 37. Also, the structure of the switching TFT 21 shown in FIG.
A capacitor 22 connected to 21 is composed of a chrome electrode and a polysilicon thin film with a gate insulating film interposed therebetween.

【0017】また、陽極37は平坦化絶縁膜43上に各
画素毎に分離して形成されており、その上にホール輸送
層44,発光層45,電子輸送層46,陰極47が順に
積層されることにより、EL素子が形成されている。そし
て、陽極37から注入されたホールと陰極47から注入
された電子とが発光層45の内部で再結合することによ
り光が放たれ、この光が矢印で示すように透明な陽極側
から外部へ放射される。また、発光層45は陽極37と
ほぼ同様の形状に画素毎に分離して形成され、更にRG
B毎に異なる発光材料を使用することにより、RGBの
各光が各EL素子から発光される。
The anode 37 is formed separately for each pixel on the flattening insulating film 43, and a hole transport layer 44, a light emitting layer 45, an electron transport layer 46, and a cathode 47 are sequentially laminated thereon. As a result, an EL element is formed. Then, the holes injected from the anode 37 and the electrons injected from the cathode 47 are recombined inside the light emitting layer 45 to emit light, and this light is emitted from the transparent anode side to the outside as shown by the arrow. Radiated. The light-emitting layer 45 is formed in the same shape as the anode 37 separately for each pixel.
By using a different light emitting material for each B, each light of RGB is emitted from each EL element.

【0018】ここで、ホール輸送層44,電子輸送層4
6,陰極47の材料として、例えば、、MTDATA,Alq3,
MgIn合金が用いられ、また、R,G,Bの各々の発光層
45としては、DCM系をドーパントとして含むAlq、キナ
クリドンをドーパントとして含むAlq、ジスチリルアリ
ーレン系をドーパントとして含むDPVBi系を使用してい
る。
Here, the hole transport layer 44 and the electron transport layer 4
6, as a material of the cathode 47, for example, MTDATA, Alq3,
An MgIn alloy is used, and as each light emitting layer 45 of R, G, and B, Alq containing DCM as a dopant, Alq containing quinacridone as a dopant, and DPVBi containing distyrylarylene as a dopant are used. ing.

【0019】ところで、EL素子の陽極37は上述したよ
うに画素毎に独立して形成されているのに対し、陰極4
7は図4に示すように全画素に対して共通して形成され
ている。図5に示す平面図により更に明らかなように、
陰極47は連続して一面に形成されており、その陰極材
料をそのまま引き延ばして外部回路との接続端子Tが形
成されている。接続端子Tは、TABやFPC等の信号基板4
8の裏面に形成された銅等でなる接続端子49に連結さ
れて、外部回路と接続される。
Incidentally, the anode 37 of the EL element is formed independently for each pixel as described above, while the cathode 4 is formed.
7 is formed in common for all pixels as shown in FIG. As is further clear from the plan view shown in FIG.
The cathode 47 is continuously formed on one surface, and the cathode material is stretched as it is to form a connection terminal T with an external circuit. The connection terminal T is a signal board 4 such as TAB or FPC.
8 is connected to a connection terminal 49 made of copper or the like formed on the back surface of the device 8 and connected to an external circuit.

【0020】次に、信号基板48を介して接続される外
部回路について、図1及び2を参照しながら説明する。
Next, an external circuit connected via the signal board 48 will be described with reference to FIGS.

【0021】図1は、外部回路の構成を示す回路図であ
り、表示コントローラ1と選択回路2から成る。表示コ
ントローラ1は、ビデオ入力信号をデコードしてR,
G,Bの3原色のビデオ信号を出力するデコーダ3と、
デコーダ3からのビデオ信号を電流増幅するビデオバッ
ファ4と、ビデオ入力信号から同期信号を分離する同期
分離回路5と、分離された同期信号に基づいてブランキ
ングパルスBLP及びクランプパルスCLPを各々発生するブ
ランキングパルス発生回路6及びクランプパルス発生回
路7と、同期分離回路5の出力に基づき有機EL表示パネ
ルで使用する各種のタイミング信号を発生するタイミン
グコントローラ8とより成る。
FIG. 1 is a circuit diagram showing the configuration of an external circuit, which comprises a display controller 1 and a selection circuit 2. The display controller 1 decodes the video input signal to
A decoder 3 for outputting video signals of three primary colors of G and B;
A video buffer 4 for current-amplifying a video signal from the decoder 3, a synchronization separation circuit 5 for separating a synchronization signal from a video input signal, and a blanking pulse BLP and a clamp pulse CLP based on the separated synchronization signal. It comprises a blanking pulse generating circuit 6 and a clamp pulse generating circuit 7, and a timing controller 8 which generates various timing signals used in the organic EL display panel based on the output of the synchronization separating circuit 5.

【0022】選択回路2は、nチャンネルのTFT9と
10が直列に接続されて構成され、TFT9の一端は逆
バイアス電圧VBSに接続され、TFT10の一端は接地
電位もしくは負電位の電圧Vcdに接続され、TFT9及
び10の他端は、図3に示すEL素子20の陰極202
(図4,5の47)に繋がる接続端子Tに接続されてい
る。TFT9のゲートにはクランプパルスBLPがそのま
ま入力され、TFT10のゲートにはインバータ11を介
してクランプパルスBLPの反転信号が入力されている。
ここで、逆バイアス電圧VBSは、図3に示す電源電圧Vdd
より高い電圧、例えば20Vに設定されている。
The selection circuit 2 is configured by connecting n-channel TFTs 9 and 10 in series. One end of the TFT 9 is connected to a reverse bias voltage VBS, and one end of the TFT 10 is connected to a ground potential or a negative potential voltage Vcd. , TFTs 9 and 10 are connected to cathode 202 of EL element 20 shown in FIG.
(47 in FIGS. 4 and 5). The gate of the TFT 9 receives the clamp pulse BLP as it is, and the gate of the TFT 10 receives an inverted signal of the clamp pulse BLP via the inverter 11.
Here, the reverse bias voltage VBS is equal to the power supply voltage Vdd shown in FIG.
It is set to a higher voltage, for example, 20V.

【0023】表示コントローラ1に入力されるビデオ入
力信号は、図2aに示すように、表示期間と非表示期間
が明確に分離されており、ブランキングパルスBLPは図
2bに示すように非表示期間に出力される。また、クラ
ンプパルスCLPは図2cに示すように出力され、これまた
非表示期間に出力される。尚、図2dは同期分離された
水平同期信号Hsyncである。
As shown in FIG. 2A, the video input signal input to the display controller 1 has a display period and a non-display period which are clearly separated from each other, and the blanking pulse BLP has a non-display period as shown in FIG. 2B. Is output to Further, the clamp pulse CLP is output as shown in FIG. 2C and is also output during the non-display period. FIG. 2D shows the horizontal synchronization signal Hsync separated from the synchronization.

【0024】図2bに示すようにクランプパルスBLPは、
表示期間にLレベルになり、このLレベル信号がTFT
9のゲートに入力され、Lレベル信号を反転したHレベ
ル信号がTFT10のゲートに入力されるので、TFT
9がオフしTFT10がオンする。よって、選択回路2
では、表示期間に接地電位もしくは負電位の電圧Vcdが
接続端子Tに出力され、この電圧Vcdが端子Tを通して
全EL素子20の陰極202に供給される。全EL素子20
の陽極201は、上述したように駆動用TFT24を介
して正の電源電圧Vddに接続されているので、EL素子は
順方向にバイアスされ、従来と同様の電流駆動が実現さ
れる。
As shown in FIG. 2B, the clamp pulse BLP is
It becomes L level during the display period, and this L level signal
9 is input to the gate of the TFT 10, and an H level signal obtained by inverting the L level signal is input to the gate of the TFT 10.
9 turns off and the TFT 10 turns on. Therefore, the selection circuit 2
In this case, the voltage Vcd of the ground potential or the negative potential is output to the connection terminal T during the display period, and this voltage Vcd is supplied to the cathodes 202 of all the EL elements 20 through the terminal T. All EL elements 20
Since the anode 201 is connected to the positive power supply voltage Vdd via the driving TFT 24 as described above, the EL element is biased in the forward direction, and current driving similar to the conventional one is realized.

【0025】一方、クランプパルスBLPは、非表示期間
にHレベルになり、このHレベル信号がTFT9のゲー
トに入力され、Hレベル信号を反転したLレベル信号が
TFT10のゲートに入力されるので、TFT9がオン
しTFT10がオフする。よって、選択回路2では、非
表示期間に逆バイアス電圧VBSが接続端子Tに出力さ
れ、この電圧VBSが端子Tを通して全EL素子20の陰極
202に供給される。そして、電圧VBSは、上述したよ
うに電源電圧Vddより高い電圧に設定されているので、E
L素子20の陰極202に陽極201より高い電圧が加
わり、 EL素子20には逆バイアスがかかる。
On the other hand, the clamp pulse BLP goes to the H level during the non-display period, and the H level signal is input to the gate of the TFT 9 and the L level signal obtained by inverting the H level signal is input to the gate of the TFT 10. The TFT 9 turns on and the TFT 10 turns off. Therefore, in the selection circuit 2, the reverse bias voltage VBS is output to the connection terminal T during the non-display period, and this voltage VBS is supplied to the cathodes 202 of all the EL elements 20 through the terminal T. Since the voltage VBS is set to a voltage higher than the power supply voltage Vdd as described above,
A voltage higher than that of the anode 201 is applied to the cathode 202 of the L element 20, and a reverse bias is applied to the EL element 20.

【0026】EL素子20は、表示期間に電流駆動を繰り
返すと、ホール輸送層44と発光層45との間や電子輸
送層46と発光層45との間に空間電荷が溜まり、これ
が寿命を短くする原因になる。しかし、本実施形態で
は、非表示期間にEL素子20に逆バイアスがかかるた
め、ホール輸送層44と発光層45との間や電子輸送層
46と発光層45との間に溜まった空間電荷は放電され
てしまう。特に、ブランキングパルスBLPは、非表示期
間において1水平期間毎に定期的に出力されるため、電
荷の放電が頻繁に行われ、電荷が溜まることを極力防止
できる。よって、EL素子20の寿命を長くできる。
In the EL element 20, when current driving is repeated during the display period, space charges accumulate between the hole transport layer 44 and the light emitting layer 45 and between the electron transport layer 46 and the light emitting layer 45, which shortens the life. Cause you to However, in the present embodiment, since a reverse bias is applied to the EL element 20 during the non-display period, space charges accumulated between the hole transport layer 44 and the light emitting layer 45 and between the electron transport layer 46 and the light emitting layer 45 are reduced. It is discharged. In particular, since the blanking pulse BLP is periodically output every one horizontal period in the non-display period, electric charges are frequently discharged, and accumulation of electric charges can be prevented as much as possible. Therefore, the life of the EL element 20 can be extended.

【0027】尚、本実施形態では、選択回路2に表示コ
ントローラ1からのブランキングパルスBLPを入力する
ようにしたが、その代わりにクランプパルスCLPあるい
は非表示期間でのみ出力される他のパルスを入力するよ
うにしてもよい。
In the present embodiment, the blanking pulse BLP from the display controller 1 is input to the selection circuit 2. Instead, the clamp pulse CLP or another pulse output only during the non-display period is used instead. You may make it input.

【0028】また、本実施形態では、陽極を固定電位と
し陰極へ供給する電圧を選択回路によって変化させるよ
うにしたが、逆に、陰極を固定電位とし陽極へ供給する
電圧を選択回路によって変化させるようにしてもよく、
更には、陽極と陰極の双方に供給する電圧を選択回路に
よって変化させても良い。
Further, in this embodiment, the voltage supplied to the cathode is changed by the selection circuit while the anode is fixed, but the voltage supplied to the anode is changed by the selection circuit by setting the cathode to the fixed potential. You may do
Further, the voltage supplied to both the anode and the cathode may be changed by a selection circuit.

【0029】[0029]

【発明の効果】本発明によれば、電流駆動を繰り返すこ
とによってEL素子内に溜まる空間電荷を非表示期間に放
電するようにしたので、表示期間での駆動に何ら影響を
与えることなく、EL素子の寿命を長くすることが実現で
きる。
According to the present invention, the space charge accumulated in the EL element is discharged in the non-display period by repeating the current driving, so that the EL in the display period is not affected at all. The life of the element can be extended.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施形態における外部回路構成を示す
回路図である。
FIG. 1 is a circuit diagram showing an external circuit configuration according to an embodiment of the present invention.

【図2】図1に示す回路の動作を説明するためのタイミ
ングチャートである。
FIG. 2 is a timing chart for explaining the operation of the circuit shown in FIG.

【図3】本発明の実施形態におけるEL表示パネルの構成
を示す回路図である。
FIG. 3 is a circuit diagram illustrating a configuration of an EL display panel according to an embodiment of the present invention.

【図4】本発明の実施形態におけるEL表示パネルの構造
を示す断面図である。
FIG. 4 is a cross-sectional view illustrating a structure of an EL display panel according to the embodiment of the present invention.

【図5】本発明の実施形態におけるEL表示パネルの構造
を示す平面図である。
FIG. 5 is a plan view showing a structure of an EL display panel according to the embodiment of the present invention.

【図6】従来のEL表示装置の構成を示す回路図である。FIG. 6 is a circuit diagram showing a configuration of a conventional EL display device.

【図7】従来のEL表示装置の構造を示す断面図である。FIG. 7 is a cross-sectional view illustrating a structure of a conventional EL display device.

【符号の説明】[Explanation of symbols]

1 表示コントローラ 2 選択回路 6 ブランキングパルス発生回路 7 クランプパルス発生回路 20 EL素子 21 スイッチング用TFT 24 駆動用TFT 201、37 陽極 202,47 陰極 44 ホール輸送層 45 発光層 46 電子輸送層 Reference Signs List 1 display controller 2 selection circuit 6 blanking pulse generation circuit 7 clamp pulse generation circuit 20 EL element 21 switching TFT 24 driving TFT 201, 37 anode 202, 47 cathode 44 hole transport layer 45 light emitting layer 46 electron transport layer

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 陽極と陰極の間に、少なくともホール輸
送層及び発光層を有し、所定のバイアスを供給すること
により発光を行うエレクトロルミネッセンス表示装置に
おいて、非表示期間に前記陽極と陰極の間に逆バイアス
をかけるようにしたことを特徴とするエレクトロルミネ
ッセンス表示装置。
1. An electroluminescent display device having at least a hole transport layer and a light emitting layer between an anode and a cathode, and emitting light by supplying a predetermined bias, wherein a light is applied between the anode and the cathode during a non-display period. An electroluminescent display device, wherein a reverse bias is applied to the display.
【請求項2】 非表示期間に発生するパルス信号を入力
し、該パルス信号が第1レベルのとき、前記陽極と陰極
の間に前記所定のバイアスを供給するための第1の電位
を前記陰極又は陽極に印加し、前記パルス信号が第2レ
ベルのとき、前記陽極と陰極の間に前記逆バイアスを供
給するための第2の電位を前記陰極又は陽極に印加する
選択回路を有することを特徴とする請求項1記載のエレ
クトロルミネッセンス表示装置。
2. A pulse signal generated during a non-display period is input, and when the pulse signal is at a first level, a first potential for supplying the predetermined bias between the anode and the cathode is applied to the cathode. Or a selection circuit for applying a second electric potential for supplying the reverse bias between the anode and the cathode when the pulse signal is applied to the anode and the pulse signal is at a second level. The electroluminescent display device according to claim 1, wherein
【請求項3】 前記パルス信号は、非表示期間に発生す
るブランキングパルス信号もしくはクランプパルス信号
であることを特徴とする請求項1又は2記載のエレクト
ロルミネッセンス表示装置。
3. The electroluminescent display device according to claim 1, wherein the pulse signal is a blanking pulse signal or a clamp pulse signal generated during a non-display period.
JP11073927A 1999-03-18 1999-03-18 Electroluminescence display device Pending JP2000268957A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP11073927A JP2000268957A (en) 1999-03-18 1999-03-18 Electroluminescence display device
TW089104464A TW488187B (en) 1999-03-18 2000-03-13 Electro luminescence display device
KR1020000013554A KR20010014601A (en) 1999-03-18 2000-03-17 Electroluminescence display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11073927A JP2000268957A (en) 1999-03-18 1999-03-18 Electroluminescence display device

Publications (1)

Publication Number Publication Date
JP2000268957A true JP2000268957A (en) 2000-09-29

Family

ID=13532274

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Application Number Title Priority Date Filing Date
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Country Status (3)

Country Link
JP (1) JP2000268957A (en)
KR (1) KR20010014601A (en)
TW (1) TW488187B (en)

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