JP2006344777A - Chip resistor - Google Patents

Chip resistor Download PDF

Info

Publication number
JP2006344777A
JP2006344777A JP2005169272A JP2005169272A JP2006344777A JP 2006344777 A JP2006344777 A JP 2006344777A JP 2005169272 A JP2005169272 A JP 2005169272A JP 2005169272 A JP2005169272 A JP 2005169272A JP 2006344777 A JP2006344777 A JP 2006344777A
Authority
JP
Japan
Prior art keywords
resistor
film
electrode layer
external electrode
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2005169272A
Other languages
Japanese (ja)
Other versions
JP4799916B2 (en
Inventor
Makio Sato
牧夫 佐藤
Makoto Abe
阿部  誠
Kimisuke Shindo
公介 進藤
Akira Oishi
明 大石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alpha Electronics Corp
Original Assignee
Alpha Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alpha Electronics Corp filed Critical Alpha Electronics Corp
Priority to JP2005169272A priority Critical patent/JP4799916B2/en
Publication of JP2006344777A publication Critical patent/JP2006344777A/en
Application granted granted Critical
Publication of JP4799916B2 publication Critical patent/JP4799916B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Non-Adjustable Resistors (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To give a resistance higher than before when the overall dimensions are identical. <P>SOLUTION: In the chip resistor where a filmlike resistor 2 is formed on the insulating surface of a substrate 1 and coated with a protective film 5 and an external electrode layer 6 is formed at the opposite ends of the substrate 1, the resistor film 2 is extended below the external electrode layer 6 while sandwiching an insulator film 4 between the resistor film 2 and the external electrode layer 6. Opposing face of the resistor film 2 and the external electrode layer 6 is lacking partially from the insulator film 4 and the lacking portion can serve as a portion for connecting the external electrode layer 6 and the resistor film 2 electrically (i. e. an internal electrode). The portion becoming the internal electrode may be not longer than one half of the short side of the substrate 1 where the external electrode layer 6 is formed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、基板の絶縁性の表面に抵抗体膜が形成され、この基板の両端に外部電極が設けられたチップ抵抗器に関するものである。   The present invention relates to a chip resistor in which a resistor film is formed on an insulating surface of a substrate and external electrodes are provided on both ends of the substrate.

図1は従来の一般的なチップ抵抗器の外観図、図4はその内部構造を製造工程順に説明するための斜視図である。これらによって従来のチップ抵抗器の構造を説明する。なおこのようなチップ抵抗器は、特許文献1にも示されている。   FIG. 1 is an external view of a conventional general chip resistor, and FIG. 4 is a perspective view for explaining the internal structure in the order of manufacturing steps. The structure of the conventional chip resistor will be described with these. Such a chip resistor is also shown in Patent Document 1.

特開2002−208502JP2002-208502

最初に絶縁性セラミック基板1の両端に内部電極層3と呼ばれる導電性膜が形成され、その内部電極層3に一部分が重なるように抵抗体膜2が形成される(図4の(A))。この抵抗体膜2は必要な場合はフォトリソグラフィ等の手法で細線パターンを形成してもよく、あるいは後の工程でレーザ等で切り込みを入れることにより抵抗値を調整することが行なわれる。   First, conductive films called internal electrode layers 3 are formed on both ends of the insulating ceramic substrate 1, and the resistor film 2 is formed so as to partially overlap the internal electrode layers 3 ((A) in FIG. 4). . If necessary, the resistor film 2 may be formed with a fine line pattern by a technique such as photolithography, or the resistance value is adjusted by cutting with a laser or the like in a later step.

この抵抗体膜2の保護の目的で、絶縁体膜を用いた抵抗体保護層4を形成する場合もある。この抵抗体保護層4は抵抗体膜2を覆いつつ内部電極層3の大部分が露出するように形成される。その後、保護膜5と外部電極層6が形成される。   For the purpose of protecting the resistor film 2, the resistor protective layer 4 using an insulator film may be formed. The resistor protective layer 4 is formed so as to cover most of the internal electrode layer 3 while covering the resistor film 2. Thereafter, the protective film 5 and the external electrode layer 6 are formed.

従来のチップ抵抗器の構造では、内部電極層3が大きな面積を占めておりチップ面積の60%程度にしか抵抗体膜2を配置できない。また、抵抗体膜2は内部電極層3の上に一部分を重ねており、この重なり部分で生ずる段差のため、フォトリソグラフィのレジストパターン形成工程で10μm幅以下のレジストパターン形成が困難となり、抵抗体膜の細線パターンを形成することが困難である。これらのことにより、外形寸法を同一とした場合には従来のチップ抵抗器では高い抵抗値を持たせることが困難であった。   In the structure of the conventional chip resistor, the internal electrode layer 3 occupies a large area, and the resistor film 2 can be disposed only in about 60% of the chip area. Further, the resistor film 2 is partially overlapped on the internal electrode layer 3, and because of the step formed at the overlapped portion, it is difficult to form a resist pattern having a width of 10 μm or less in the photolithography resist pattern forming step. It is difficult to form a fine line pattern of the film. For these reasons, when the external dimensions are the same, it is difficult to provide a high resistance value with the conventional chip resistor.

本発明は、このような事情に鑑みなされたものであり、外形寸法を同一にした場合に従来よりも高い抵抗値を持たせることができるチップ抵抗器を提供することを目的とする。   The present invention has been made in view of such circumstances, and an object of the present invention is to provide a chip resistor that can have a higher resistance value than before when the external dimensions are the same.

本発明によればこの目的は、基板の絶縁性の表面上に膜状の抵抗体を形成し、この抵抗体膜を保護膜で被覆し、前記基板の両端に外部電極層を形成したチップ抵抗器において、前記抵抗体膜を前記外部電極層との間に絶縁体膜を挟んで前記外部電極層の下方に延在させたことを特徴とするチップ抵抗器、により達成される。   According to the present invention, this object is to provide a chip resistor in which a film-like resistor is formed on the insulating surface of the substrate, the resistor film is covered with a protective film, and external electrode layers are formed on both ends of the substrate. The chip resistor is characterized in that the resistor film extends below the external electrode layer with an insulator film interposed between the resistor film and the external electrode layer.

本発明のチップ抵抗器の構成によれば、外形寸法と同一とした場合に抵抗体膜が配置される面積が従来のチップ抵抗器の構造に比して大幅に増大でき、なおかつ抵抗体膜の細線加工が容易になるので、限られたチップ面積で大きい抵抗値を得ることができる。   According to the configuration of the chip resistor of the present invention, the area in which the resistor film is disposed can be significantly increased as compared with the structure of the conventional chip resistor when the outer dimensions are the same, and the resistor film Since thin wire processing becomes easy, a large resistance value can be obtained with a limited chip area.

絶縁体膜は抵抗体膜と外部電極層との対向面の一部が欠如され、この欠如部分を外部電極層と抵抗体膜が電気的に接続する部分(すなわち内部電極)とすることができる。この内部電極となる部分は、基板の外部電極層を形成した短辺の長さの半分以下とすることができる。この場合には抵抗体膜の面積を十分に増大させる一方、外部電極層と内部電極の接触面積を小さくできるので、はんだや外部電極を伝わって侵入する水分が抵抗体膜に与える影響を小さくすることができ、チップ抵抗器の信頼性が向上する。また抵抗体膜が外部電極の下方へ延出した部分には抵抗パターンを形成しておくことが可能である。   In the insulator film, a part of the opposing surface of the resistor film and the external electrode layer is missing, and this lacking part can be a part where the external electrode layer and the resistor film are electrically connected (that is, the internal electrode). . The portion to be the internal electrode can be made to be half or less of the length of the short side on which the external electrode layer of the substrate is formed. In this case, the area of the resistor film is sufficiently increased, while the contact area between the external electrode layer and the internal electrode can be reduced, thereby reducing the influence of moisture entering through the solder and the external electrode on the resistor film. This improves the reliability of the chip resistor. In addition, it is possible to form a resistance pattern in the portion where the resistor film extends below the external electrode.

本発明のチップ抵抗器の製造にあたっては、最初に絶縁性基板の上面全面に抵抗体膜を形成した後フォトリソグラフィによる細線加工を行ない抵抗パターンを形成する。このようにすれば抵抗体膜の全領域において段差が無く、フォトリソグラフィによる細線加工が容易である。その後、内部電極層を抵抗体膜上に必要最小限の面積で形成し、抵抗体膜上に絶縁体膜を形成し、絶縁体膜上に外部電極層を形成する。このようにすれば、外部電極層の直下にも抵抗体膜を配置でき、内部電極の部分を除いて基板のほぼ全面に抵抗体膜従って抵抗パターンを配置できることになる。   In manufacturing the chip resistor of the present invention, a resistor film is first formed on the entire upper surface of an insulating substrate, and then a fine pattern is formed by photolithography to form a resistance pattern. In this way, there is no step in the entire region of the resistor film, and thin line processing by photolithography is easy. Thereafter, the internal electrode layer is formed on the resistor film with a necessary minimum area, the insulator film is formed on the resistor film, and the external electrode layer is formed on the insulator film. In this way, the resistor film can be disposed immediately below the external electrode layer, and the resistor film and thus the resistor pattern can be disposed on almost the entire surface of the substrate except for the internal electrode portion.

以下に本発明の一実施例を図2、3に基づいて説明する。図2は一実施例の構造を製造工程順に示す斜視図、図3の(A)、(B)、(C)はそれぞれ図1におけるA−A線、B−B線、C−C線における断面図である。まずセラミック基板1の上面全面に抵抗体膜2を真空成膜法によって形成した(図2の(A))。抵抗体膜の材質はニッケルクロム系合金とし、厚みは0.1μmとした。次にフォトリソグラフィを用いて抵抗体膜2をエッチングし2μm幅の細線パターン(抵抗パターン)を形成した(図2の(B))。   An embodiment of the present invention will be described below with reference to FIGS. 2 is a perspective view showing the structure of one embodiment in the order of the manufacturing process, and FIGS. 3A, 3B, and 3C are taken along lines AA, BB, and CC in FIG. 1, respectively. It is sectional drawing. First, the resistor film 2 was formed on the entire upper surface of the ceramic substrate 1 by a vacuum film forming method ((A) in FIG. 2). The material of the resistor film was a nickel chromium alloy, and the thickness was 0.1 μm. Next, the resistor film 2 was etched using photolithography to form a thin line pattern (resistance pattern) having a width of 2 μm ((B) in FIG. 2).

この抵抗体膜2は全面にわたって段差が無いためフォトリソグラフィを用いると微細加工が容易であるが、所望の抵抗値が比較的低く微細な加工が必要でない場合は、レーザ加工や人手で抵抗体膜に切れ込みを入れて所望の抵抗値になるように加工してもよい。次に抵抗体膜2の表面の一部に内部電極層3を形成した。この内部電極層3はめっき法により形成し、抵抗体膜側からNi、Auの二層を積層した。この内部電極層3は基板1の短辺の長さの半分以下(約1/4)である。   Since the resistor film 2 has no step over the entire surface, it is easy to perform fine processing using photolithography. However, when the desired resistance value is relatively low and fine processing is not required, the resistor film is formed by laser processing or by hand. You may process so that it may make a notch and may become desired resistance value. Next, the internal electrode layer 3 was formed on a part of the surface of the resistor film 2. The internal electrode layer 3 was formed by plating, and two layers of Ni and Au were laminated from the resistor film side. The internal electrode layer 3 is not more than half the length of the short side of the substrate 1 (about ¼).

次に感光性のポリイミド膜を用いて、基板1の上面の内部電極層3以外の部分に絶縁体膜である抵抗体保護層4を形成した(図2の(C))。次にエポキシ系樹脂を用いて基板1の短辺に沿った一定幅を除いた部分を被覆することにより保護膜5を形成した(図2の(D))。その後基板1の短辺に沿って一定幅の外部電極層6を、内部電極層3に重ねて形成した。外部電極層6はAg−エポキシペーストを塗布して下地とし、その上にNiめっき層とハンダめっき層を形成して作製した。   Next, using a photosensitive polyimide film, a resistor protective layer 4 as an insulator film was formed on a portion other than the internal electrode layer 3 on the upper surface of the substrate 1 ((C) in FIG. 2). Next, a protective film 5 was formed by covering a portion excluding a certain width along the short side of the substrate 1 using an epoxy resin ((D) of FIG. 2). Thereafter, an external electrode layer 6 having a constant width was formed on the internal electrode layer 3 along the short side of the substrate 1. The external electrode layer 6 was prepared by applying an Ag-epoxy paste as a base, and forming a Ni plating layer and a solder plating layer thereon.

以上の構成によれば、図3のように外部電極層6の直下に抵抗体膜2を配置できる。このとき内部電極層3の面積を必要最小限にすると、抵抗体膜2を配置できる面積が最大となる。この実施例ではこの面積を図4に示す従来のものに比べて約1.4倍程度にすることができる。   According to the above configuration, the resistor film 2 can be disposed directly under the external electrode layer 6 as shown in FIG. At this time, if the area of the internal electrode layer 3 is minimized, the area where the resistor film 2 can be disposed is maximized. In this embodiment, this area can be about 1.4 times that of the conventional one shown in FIG.

この実施例では2.0mm×1.2mm×0.55mmの外形のチップ抵抗器を作製したが、抵抗体膜として抵抗率が比較的低いニッケルクロム系合金を用いたのにかかわらず、抵抗値は2MΩを取得することができた。この抵抗値は同一外形寸法の従来のものに比べて約2倍の大きさである。   In this example, a chip resistor having an outer shape of 2.0 mm × 1.2 mm × 0.55 mm was manufactured, but the resistance value was not limited regardless of using a nickel chrome alloy having a relatively low resistivity as the resistor film. Was able to obtain 2 MΩ. This resistance value is about twice as large as that of a conventional one having the same outer dimensions.

基板はセラミックの他にガラス等の絶縁体や、導電性の基板の表面に絶縁体層を形成したものを使用してもよい。この実施例では抵抗体膜2は真空成膜法(蒸着法、スパッタリング法、イオンプレーティング法、化学蒸着法など)で形成した薄膜を用いているが、この発明ではめっき法印刷法などで形成した膜を用いてもよい。   In addition to ceramic, the substrate may be an insulator such as glass, or a substrate having an insulator layer formed on the surface of a conductive substrate. In this embodiment, the resistor film 2 is a thin film formed by a vacuum film formation method (evaporation method, sputtering method, ion plating method, chemical vapor deposition method, etc.), but in this invention, it is formed by a plating method printing method or the like. You may use the film | membrane which carried out.

内部電極層3の材質や層構成は、抵抗体膜2と外部電極層6の材質を考慮して決定されるが、はんだのバリア層となりうるNiやPdの層を含むことが望ましい。外部電極層6は、はんだのバリア層となる金属を真空成膜法で形成してめっきの下地とし、その上にはんだめっきによってはんだ層を形成してもよい。   The material and the layer structure of the internal electrode layer 3 are determined in consideration of the material of the resistor film 2 and the external electrode layer 6, and it is desirable to include a layer of Ni or Pd that can be a solder barrier layer. The external electrode layer 6 may be formed by forming a metal serving as a solder barrier layer by a vacuum film forming method as a base for plating, and forming a solder layer thereon by solder plating.

抵抗体保護層4は、ポリイミド等の樹脂の他に、ガラスペーストを塗布して形成することもでき、SiO2等の絶縁性膜を真空成膜法を用いて形成してもよい。抵抗体保護層4と保護膜5の間に、外部から抵抗体膜に加わるストレスを緩和させる目的の層を形成することもできる。   The resistor protective layer 4 can be formed by applying a glass paste in addition to a resin such as polyimide, and an insulating film such as SiO 2 may be formed by using a vacuum film forming method. Between the resistor protective layer 4 and the protective film 5, a layer intended to relieve stress applied to the resistor film from the outside can be formed.

チップ抵抗器の外観図External view of chip resistor 本発明のチップ抵抗器の構成を製造工程順に示す斜視図The perspective view which shows the structure of the chip resistor of this invention in order of a manufacturing process. (A)本発明のチップ抵抗器の図1におけるA−A線断面図 (B)本発明のチップ抵抗器の図1におけるB−B線断面図 (C)本発明のチップ抵抗器の図1におけるC−C線断面図(A) Cross-sectional view of the chip resistor of the present invention taken along line AA in FIG. 1 (B) Cross-sectional view of the chip resistor of the present invention taken along line BB in FIG. 1 (C) FIG. 1 of the chip resistor of the present invention CC sectional view taken on the line 従来例のチップ抵抗器の内部構造を製造工程順に示す斜視図The perspective view which shows the internal structure of the chip resistor of a prior art example in order of a manufacturing process.

符号の説明Explanation of symbols

1 セラミック基板
2 抵抗体膜
3 内部電極層
4 抵抗体保護層(絶縁体膜)
5 保護膜
6 外部電極層
DESCRIPTION OF SYMBOLS 1 Ceramic substrate 2 Resistor film 3 Internal electrode layer 4 Resistor protective layer (insulator film)
5 Protective film 6 External electrode layer

Claims (4)

基板の絶縁性の表面上に膜状の抵抗体を形成し、この抵抗体膜を保護膜で被覆し、前記基板の両端に外部電極層を形成したチップ抵抗器において、
前記抵抗体膜を前記外部電極層との間に絶縁体膜を挟んで前記外部電極層の下方に延在させたことを特徴とするチップ抵抗器。
In a chip resistor in which a film-like resistor is formed on an insulating surface of a substrate, this resistor film is covered with a protective film, and external electrode layers are formed on both ends of the substrate.
A chip resistor characterized in that the resistor film extends below the external electrode layer with an insulator film interposed between the resistor film and the external electrode layer.
絶縁体膜は抵抗体膜と外部電極層との対向面の一部が欠如され、この欠如部分に抵抗体膜を外部電極層に電気接続する内部電極を形成した請求項1のチップ抵抗器。   2. The chip resistor according to claim 1, wherein a part of the opposing surface of the resistor film and the external electrode layer is lacked in the insulator film, and an internal electrode for electrically connecting the resistor film to the external electrode layer is formed in the lacked part. 請求項2において、抵抗体膜が外部電極層に電気的に接続される内部電極となる部分は、基板の外部電極層を形成した短辺の長さの半分以下であることを特徴とするチップ抵抗器。   3. The chip according to claim 2, wherein the portion of the resistor film serving as the internal electrode electrically connected to the external electrode layer is not more than half the length of the short side of the substrate on which the external electrode layer is formed. Resistor. 抵抗体膜が外部電極の下方に延在する部分に抵抗パターンが形成されている請求項1のチップ抵抗器。   2. The chip resistor according to claim 1, wherein a resistor pattern is formed in a portion where the resistor film extends below the external electrode.
JP2005169272A 2005-06-09 2005-06-09 Chip resistor Expired - Fee Related JP4799916B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005169272A JP4799916B2 (en) 2005-06-09 2005-06-09 Chip resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005169272A JP4799916B2 (en) 2005-06-09 2005-06-09 Chip resistor

Publications (2)

Publication Number Publication Date
JP2006344777A true JP2006344777A (en) 2006-12-21
JP4799916B2 JP4799916B2 (en) 2011-10-26

Family

ID=37641510

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005169272A Expired - Fee Related JP4799916B2 (en) 2005-06-09 2005-06-09 Chip resistor

Country Status (1)

Country Link
JP (1) JP4799916B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3813631A (en) * 1972-08-09 1974-05-28 Hitachi Ltd High resistance resistor device for dc high voltage circuits
JP2006019694A (en) * 2004-06-03 2006-01-19 Taiyosha Electric Co Ltd Chip resistor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3813631A (en) * 1972-08-09 1974-05-28 Hitachi Ltd High resistance resistor device for dc high voltage circuits
JP2006019694A (en) * 2004-06-03 2006-01-19 Taiyosha Electric Co Ltd Chip resistor

Also Published As

Publication number Publication date
JP4799916B2 (en) 2011-10-26

Similar Documents

Publication Publication Date Title
US8035476B2 (en) Chip resistor and method for making the same
JP7385358B2 (en) chip resistor
JP4916715B2 (en) Electronic components
JPH03165501A (en) Chip type electric resistor and its manufacture
JP2011040571A (en) Dielectric thin film element
JP6788847B2 (en) Capacitor
JP2006310277A (en) Chip type fuse
JP4799916B2 (en) Chip resistor
JP2008251974A (en) Thin-film component and manufacturing method thereof
JP2002231502A (en) Fillet-less chip resistor and method for manufacturing the same
US9806145B2 (en) Passive chip device and method of making the same
JP2005191406A (en) Chip resistor, and manufacturing method thereof
JP6954517B2 (en) Electronic components and their manufacturing methods
WO2020170750A1 (en) Resistor
JP2006080322A (en) Chip type compound electronic part
JP2019067956A (en) Chip resistor
JP6819894B2 (en) Electronic components
US20210020738A1 (en) Capacitor and method for manufacturing the same
JP5135745B2 (en) Chip component and manufacturing method thereof
JP2654655B2 (en) Manufacturing method of resistor
JP2720442B2 (en) Method of manufacturing magnetoresistive element
JPH02198141A (en) Manufacture of bump electrode of semiconductor device
JP2000331590A (en) Circuit protection element and its manufacture
JP2008294350A (en) Semiconductor device and method of manufacturing the same
JPH01204763A (en) Thermal head

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080606

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20101102

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101222

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110726

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110803

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140812

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 4799916

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees